Indication device

Abstract

To provide a display device with reduced manufacturing processes and costs. [Solution] The display device includes a first substrate including a plurality of upper pads, a first substrate including a plurality of lower pads, and a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads. Each of the plurality of lower pads includes a first lower pad electrode located below the second substrate, a first insulating layer located below the first lower pad electrode, a second lower pad electrode located below the first insulating layer, a third lower pad electrode located below the second lower pad electrode, and a second insulating layer located below the third lower pad electrode. The third lower pad electrode is made of a transparent conductive material. Therefore, the manufacturing process and manufacturing cost of the display device can be reduced.

Description

Technical Field

[0001] This specification relates to a display device, and more particularly to a display device using LEDs (Light Emitting Diodes).

Background Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display devices (OLEDs) that emit light by themselves, and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The application range of display devices is diverse, not only including computer monitors and TVs, but also personal mobile devices. Research is underway on display devices that have a reduced volume and weight while having a large display area.

[0004] In recent years, display devices including LEDs (Light Emitting Diodes) have attracted attention as next-generation display devices. Since LEDs are made of inorganic materials rather than organic materials, they have excellent reliability and a longer lifespan compared to liquid crystal display devices and organic light emitting display devices. In addition, LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by this specification is to provide a display device with reduced manufacturing processes and manufacturing costs.

[0006] Another problem to be solved by this specification is to provide a display device with reduced disconnection paths and reduced defect problems.

[0007] Another problem that this specification seeks to solve is to provide a display device in which the generation of parasitic capacitors is reduced.

[0008] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A display device according to one embodiment of this specification includes a first substrate including a plurality of upper pads, a first substrate including a plurality of lower pads, and a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads, wherein each of the plurality of lower pads includes a first lower pad electrode disposed at the bottom of a second substrate, a first insulating layer disposed at the bottom of the first lower pad electrode, a second lower pad electrode disposed at the bottom of the first insulating layer, a third lower pad electrode disposed at the bottom of the second lower pad electrode, and a second insulating layer disposed at the bottom of the third lower pad electrode, the third lower pad electrode may be made of a transparent conductive material.

[0010] Specific details of other embodiments are included in the detailed description and drawings.

[0011] This specification shows that the manufacturing cost of a display device can be reduced by reducing the masking process.

[0012] This specification describes how to improve the structure of the pad portion to prevent problems with defects.

[0013] This specification describes how to prevent corrosion of the pad portion and improve the reliability of the pad portion.

[0014] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0015] [Figure 1]This is a schematic diagram of a display device according to one embodiment of this specification. [Figure 2a] This is a partial cross-sectional view of a display device according to one embodiment of this specification. [Figure 2b] This is a perspective view of a tiling display device according to one embodiment of this specification. [Figure 3] This is an enlarged plan view of the first substrate of a display device according to one embodiment of this specification. [Figure 4] This is an enlarged plan view of the second substrate of a display device according to one embodiment of this specification. [Figure 5] This is a cross-sectional view of a subpixel of a display device according to one embodiment of this specification. [Figure 6] This is a cross-sectional view of the pad area of ​​a display device according to one embodiment of this specification. [Figure 7a] This is a cross-sectional view of the upper pad of a display device according to one embodiment of this specification. [Figure 7b] This is a cross-sectional view of the lower pad of a display device according to one embodiment of this specification. [Figure 8] This is a cross-sectional view of the second substrate relative to A-A' in Figure 4. [Figure 9] This is a cross-sectional view of the second substrate relative to B-B' in Figure 4. [Modes for carrying out the invention]

[0016] The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the examples described below in detail with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms, and these examples are provided merely to make the disclosure of this specification complete and to fully inform a person with ordinary skill in the art to which this specification belongs.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, and this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, in the description of this specification, when it is determined that a specific description of related known technologies may muddy the gist of this specification, the detailed description thereof is omitted. When terms such as "comprising", "having", "being made" are used in this specification, other parts may be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0018] When interpreting a component, it is interpreted to include an error range even without a separate explicit description.

[0019] In the case of an explanation of a positional relationship, for example, when the positional relationship between two parts is described such as "on", "above", "below", "next to", etc., one or more other parts may be located between the two parts as long as "immediately" or "directly" is not used.

[0020] An element or layer referred to as "on" another element or layer includes both the case where it is immediately above the other element and the case where another layer or another element is interposed in the middle.

[0021] Also, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0022] Throughout the specification, the same reference numerals refer to the same components.

[0023] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0024] The features of each of the various embodiments described herein can be combined or linked together, either partially or entirely, allowing for a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0025] In the following, this specification will be described with reference to the drawings.

[0026] Figure 1 is a schematic diagram of a display device according to one embodiment of this specification. In Figure 1, for the sake of explanation, only the display panel PN, gate drive unit GD, data drive unit DD, and timing controller TC are shown among the various components of the display device 100.

[0027] Referring to Figure 1, the display device 100 includes a display panel PN containing a plurality of subpixels SP, a gate drive unit GD and a data drive unit DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate drive unit GD and the data drive unit DD.

[0028] The gate drive unit GD supplies multiple scan signals to multiple scan wirings SL based on multiple gate control signals provided by the timing controller TC. In Figure 1, one gate drive unit GD is shown spaced apart on one side of the display panel PN, but the number and arrangement of gate drive units GD are not limited to this.

[0029] The data drive unit DD converts video data input from the timing controller TC into data voltage using a reference gamma voltage, based on multiple data control signals provided by the timing controller TC. The data drive unit DD can then supply the converted data voltage to multiple data wirings DL.

[0030] The timing controller TC aligns the video data input from an external source and supplies it to the data drive unit DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals input from an external source, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then control the gate drive unit GD and the data drive unit DD by supplying the generated gate control signals and data control signals to the gate drive unit GD and the data drive unit DD, respectively.

[0031] The display panel PN is configured to display images to the user and includes multiple sub-pixels SP. Multiple scan lines SL and multiple data lines DL intersect within the display panel PN, and each of the multiple sub-pixels SP is connected to the scan lines SL and data lines DL. In addition, although not shown in the drawing, each of the multiple sub-pixels SP may be connected to high-potential power lines, low-potential power lines, reference lines, etc.

[0032] The display panel PN may define a display area AA and a non-display area NA that surrounds the display area AA.

[0033] Display area AA is the area where the image is displayed on the display device 100. Display area AA may contain multiple subpixels SP that constitute multiple pixels PX, and circuits for driving the multiple subpixels SP. Multiple subpixels SP are the smallest units that constitute display area AA, and n subpixels SP can form one pixel PX. Each of the multiple subpixels SP may contain a light-emitting element and a thin-film transistor or the like for driving the light-emitting element. Multiple light-emitting elements may be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting elements may be LEDs (Light-emitting Diodes) or micro-LEDs (Micro Light-emitting Diodes).

[0034] Multiple signal lines are arranged in the display area AA to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL that supply data voltage to each of the multiple sub-pixels SP, and multiple scan lines SL that supply gate voltage to each of the multiple sub-pixels SP. Multiple scan lines SL may extend from the display area AA in one direction and be connected to the multiple sub-pixels SP, and multiple data lines DL may extend from the display area AA in directions other than one direction and be connected to the multiple sub-pixels SP. In addition, low-potential power supply lines, high-potential power supply lines, etc., may be further arranged in the display area AA, but are not limited to these.

[0035] The non-display area NA is an area where no image is displayed and can be defined as an area extending from the display area AA. The non-display area NA may contain link wiring and pad electrodes for transmitting signals to the subpixels SP of the display area AA, as well as drive ICs such as gate driver ICs and data driver ICs. The non-display area NA may be located on the back of the display panel PN, i.e., the side without subpixels SP, or it may be omitted, and is not limited to what is shown in the drawing.

[0036] On the other hand, drive units such as the gate drive unit GD, data drive unit DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate drive unit GD may be implemented in the non-display area NA using the GIP (Gate In Panel) method, or it may be implemented in the display area AA between multiple sub-pixels SP using the GIA (Gate In Active Area) method. For example, the data drive unit DD and timing controller TC may be formed on a separate flexible film and printed circuit board, and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. If the gate drive unit GD is implemented using the GIP method, and the data drive unit DD and timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, it is necessary to secure an area in the non-display area NA to accommodate the gate drive unit GD and the pad electrodes, which may increase the bezel size.

[0037] In contrast, when the gate drive unit GD is implemented inside the display area AA using the GIA method, and side wiring SRL is formed to connect the signal wiring on the front of the display panel PN to the pad electrodes on the back of the display panel PN, and a flexible film and printed circuit board are bonded to the back of the display panel PN, the non-display area NA on the front of the display panel PN can be minimized. That is, when the gate drive unit GD, data drive unit DD, and timing controller TC are connected to the display panel PN in the manner described above, it may be possible to realize a zero-bezel system where there is virtually no bezel, and for a more detailed explanation, please refer to Figures 2a and 2b.

[0038] Figure 2a is a partial cross-sectional view of a display device according to one embodiment of this specification. Figure 2b is a perspective view of a tiling display device according to one embodiment of this specification.

[0039] Multiple pad electrodes are arranged in the non-display area NA of the display panel PN to transmit various signals to multiple sub-pixels SP. For example, the upper pad TPAD, which transmits signals to multiple sub-pixels SP, is arranged in the non-display area NA on the front of the display panel PN, and the lower pad BPAD, which is electrically connected to drive components such as flexible film and printed circuit boards, is arranged in the non-display area NA on the back of the display panel PN.

[0040] In this case, although not shown in the drawing, various signal wirings connected to multiple sub-pixels SP, such as scan wiring SL and data wiring DL, can extend from the display area AA to the non-display area NA and be electrically connected to the upper pad TPAD.

[0041] Then, a side wiring SRL is positioned along the side of the display panel PN. The side wiring SRL can electrically connect the upper pad TPAD on the front of the display panel PN and the lower pad BPAD on the back of the display panel PN. Thus, signals from the drive components on the back of the display panel PN can be transmitted to multiple subpixels SP through the lower pad BPAD, the side wiring SRL, and the upper pad TPAD. In this way, a signal transmission path can be formed from the front to the sides and back of the display panel PN, minimizing the area of ​​the non-display region NA of the display panel PN.

[0042] Referring to Figure 2b, a tiling display device TD with a large screen can be realized by connecting multiple display devices 100. In this case, as shown in Figure 2a, when the tiling display device TD is realized using display devices 100 with minimized bezels, the seam area between the display devices 100 where images are not displayed can be minimized, which can improve display quality.

[0043] For example, multiple subpixels SP can form a single pixel PX, and the spacing D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 can be made identical to the spacing D1 between pixels PX within one display device 100. Therefore, the spacing between pixels PX can be configured to be constant between display devices 100, thereby minimizing the seam area.

[0044] However, Figures 2a and 2b are illustrative examples, and the display device 100 according to one embodiment of this specification may be a general display device with a bezel, and is not limited thereto.

[0045] On the other hand, the display panel PN may include a first substrate and a second substrate.

[0046] In the following sections, the first and second substrates will be described in detail with reference to Figures 3 and 4.

[0047] Figure 3 is an enlarged plan view of the first substrate of a display device according to one embodiment of this specification.

[0048] First, the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components placed on top of the display device 100, and may be an insulating substrate. Multiple pixels PX are formed on the first substrate 110 so that an image can be displayed. For example, the first substrate 110 may be made of glass or resin. The first substrate 110 may also contain a polymer or plastic. In some embodiments, the first substrate 110 may be made of a flexible plastic material.

[0049] Referring to Figure 3, the first substrate 110 has multiple pixel regions UPA, multiple gate drive regions GA, and multiple upper pad regions. Of these, the multiple pixel regions UPA and the multiple gate drive regions GA may be included in the display region AA of the display panel PN.

[0050] First, multiple pixel regions UPA are regions where multiple pixels PX are arranged. Multiple pixel regions UPA can be arranged in multiple rows and multiple columns. Each of the multiple pixels PX arranged in the multiple pixel regions UPA contains multiple sub-pixels SP. Each of the multiple sub-pixels SP contains a light-emitting element LED and a pixel circuit and can emit light independently.

[0051] The display panel PN includes multiple pixels PX, each consisting of multiple subpixels SP. Each of the multiple subpixels SP includes a light-emitting element LED and a pixel circuit and can emit light independently. A single pixel may include one or more first subpixels, one or more second subpixels, and one or more third subpixels. For example, a single pixel may consist of two first subpixels, two second subpixels, and two third subpixels. In this case, the first subpixels may be red subpixels, the second subpixels may be green subpixels, and the third subpixels may be blue subpixels, but this is not limited to them.

[0052] Multiple gate drive regions GA are areas where gate drive units GD are located. The gate drive units GD can be implemented in the display region AA using a GIA (Gate In Active Area) method. For example, gate drive regions GA can be formed along the row and / or column directions between multiple pixel regions UPA. The gate drive units GD formed in the gate drive regions GA can provide scan signals to multiple scan wirings SL.

[0053] The gate drive unit GD located in the gate drive region GA may include a circuit for outputting a scan signal. In this case, the gate drive unit GD may include, for example, multiple transistors and / or capacitors. Here, the active layers of the multiple transistors may, but are not limited to, semiconductor materials such as oxide semiconductors, amorphous silicon, or polysilicon. In this case, the active layers of the multiple transistors may be made of the same material or different materials. Furthermore, the active layers of the transistors in the gate drive unit may be made of the same material as the active layers of the various transistors in the pixel circuit or different materials.

[0054] The multiple upper pad areas include a first upper pad area TPA1 located at the first edge EG1 of the display panel PN, and a second upper pad area TPA2 located at the second edge EG2 of the display panel PN.

[0055] The first upper pad area TPA1 and the second upper pad area TPA2 are areas on which a plurality of upper pads TPAD are arranged on the first substrate 110. The plurality of upper pads TPAD can transmit various signals to various wirings that extend in the column direction in the display area AA.

[0056] Multiple first upper pads TPAD1 may be arranged in the first upper pad region TPA1. The multiple first upper pads TPAD1 may include upper pads TPAD to which different signals are applied. For example, the first upper pad TPAD1 may include an upper data pad TDP that transmits data voltage to the upper data wiring TDL, an upper gate pad TGP that transmits clock signals, start signals, gate low voltage, gate high voltage, etc. to the gate drive unit GD for driving the gate drive unit GD, and an upper high-potential power supply pad TVP1 that transmits high-potential power supply voltage to the upper high-potential power supply wiring TVL1.

[0057] In the second upper pad region TPA2, multiple second upper pads TPAD2 may be arranged. In this case, the multiple second upper pads TPAD2 may be different upper pads from the multiple first upper pads TPAD1. For example, the multiple second upper pads TPAD2 may include upper low-potential power supply pads TVP2 that transmit low-potential power supply voltage to multiple upper low-potential power supply wiring TVL2.

[0058] In this case, each of the multiple upper pads TPAD can be formed to be of a different size from one another. For example, among the multiple first upper pads TPAD1, the multiple upper data pads TDP that are connected one-to-one with the multiple upper data wiring TDLs may have a relatively narrow width, while the upper high-potential power pad TVP1 and upper gate pad TGP may have a relatively wide width. Similarly, the multiple second upper pads TPAD2, which are upper low-potential power pads TVP2, may also have a relatively wider width than the multiple upper data pads TDP, and each of the upper low-potential power pads TVP2 may have a different width from one another. However, the widths of the upper data pad TDP, upper gate pad TGP, upper high-potential power pad TVP1, and upper low-potential power pad TVP2 shown in Figure 3 are illustrative, and the size of the upper pads TPAD can be configured in a variety of ways and is not limited thereto.

[0059] On the other hand, to reduce the bezel of the display panel PN, the edges of the display panel PN can be cut and removed. Multiple pixels PX, multiple wirings, and multiple upper pads TPAD can be formed on the initial first substrate 110i, and the bezel area can be reduced by grinding the edges of the initial first substrate 110i. In the grinding process, a portion of the initial first substrate 110i may be removed, forming a first substrate 110 of a smaller size. At this time, a portion of the multiple upper pads TPAD and wirings located on the edges of the first substrate 110 may be removed. Therefore, only a portion of the multiple upper pads TPAD may remain on the first substrate 110.

[0060] On the first substrate 110 of the display panel PN, multiple upper data wirings TDL are arranged in multiple pixel regions UPA, extending in the column direction from multiple upper pads TPAD. The multiple upper data wirings TDL may extend from multiple upper data pads TDP of the first upper pad region TPA1 toward the multiple pixel regions UPA. The multiple upper data wirings TDL may be arranged to extend in the column direction and overlap the multiple pixel regions UPA. Thus, the multiple upper data wirings TDL can transmit data voltages to the pixel circuits of each of the multiple sub-pixels SP.

[0061] Multiple upper high-potential power supply wirings TVL1 are arranged on the first substrate 110 of the display panel PN, extending in the column direction to multiple pixel regions UPA. Some of the multiple upper high-potential power supply wirings TVL1 extend from the upper high-potential power supply pad TVP1 of the first upper pad region TPA1 towards the multiple pixel regions UPA, and can transmit a high-potential power supply voltage to the light-emitting element LED of each of the multiple sub-pixels SP. Other parts of the multiple upper high-potential power supply wirings TVL1 can be electrically connected to other upper high-potential power supply wirings TVL1 through the upper auxiliary high-potential power supply wiring TAVL1, which will be described later. In Figure 3, for the sake of explanation, it is shown that one upper high-potential power supply wiring TVL1 and one upper high-potential power supply pad TVP1 are arranged, but multiple upper high-potential power supply wirings TVL1 and upper high-potential power supply pad TVP1 can be arranged.

[0062] Multiple upper low-potential power supply wirings TVL2 are arranged on the first substrate 110 of the display panel PN, extending in the column direction to multiple pixel regions UPA. At least a portion of the multiple upper low-potential power supply wirings TVL2 extend from the upper low-potential power supply pad TVP2 of the second upper pad region TPA2 towards the multiple pixel regions UPA, and can transmit a low-potential power supply voltage to the pixel circuit of each of the multiple sub-pixels SP. Another portion of the multiple upper low-potential power supply wirings TVL2 can be electrically connected to other upper low-potential power supply wirings TVL2 through upper auxiliary low-potential power supply wiring TAVL2, which will be described later.

[0063] Multiple upper scan wirings TSLs extending in the row direction are arranged on the first substrate 110 of the display panel PN. The multiple upper scan wirings TSLs may extend in the row direction and be arranged across multiple pixel regions UPA and multiple gate drive regions GA. The multiple upper scan wirings TSLs can transmit scan signals from the gate drive unit GD to the pixel circuits of multiple sub-pixels SP.

[0064] Multiple upper auxiliary high-potential power supply wirings TAVL1 extending in the row direction are arranged on the first substrate 110 of the display panel PN in multiple pixel regions UPA. Multiple upper auxiliary high-potential power supply wirings TAVL1 may be arranged in the regions between the multiple pixel regions UPA. Multiple upper auxiliary high-potential power supply wirings TAVL1 extending in the row direction can be electrically connected to multiple upper high-potential power supply wirings TVL1 extending in the column direction through contact holes to form a mesh structure. Thus, multiple upper auxiliary high-potential power supply wirings TAVL1 and multiple upper high-potential power supply wirings TVL1 are configured to form a mesh structure, minimizing voltage drop and voltage deviation.

[0065] Multiple upper auxiliary low-potential power supply wirings TAVL2 extending in the row direction are arranged on the first substrate 110 of the display panel PN in multiple pixel regions UPA. Multiple upper auxiliary low-potential power supply wirings TAVL2 may be arranged in the regions between the multiple pixel regions UPA. Multiple upper auxiliary low-potential power supply wirings TAVL2 extending in the row direction can be electrically connected to multiple upper low-potential power supply wirings TVL2 extending in the column direction through contact holes to form a mesh structure. Thus, multiple upper auxiliary low-potential power supply wirings TAVL2 and multiple upper low-potential power supply wirings TVL2 are configured to form a mesh structure, which can reduce the resistance of the wiring and minimize voltage deviation.

[0066] Referring to Figure 3, multiple upper gate drive wirings TGVL are arranged on the first substrate 110 of the display panel PN, extending in the row and column directions to multiple pixel regions UPA. Some of the multiple upper gate drive wirings TGVL extend from the upper gate pad TGP of the first upper pad region TPA1 to the gate drive region GA, and can transmit signals to the gate drive unit GD. Other parts of the multiple upper gate drive wirings TGVL extend in the row direction and can transmit signals to the gate drive units GD of the multiple gate drive regions GA. Thus, various signals are transmitted from the upper gate drive wirings TGVL to the gate drive units GD, and the gate drive units GD can be driven.

[0067] Multiple upper gate drive wirings TGVL may include wiring that transmits clock signals, start signals, gate high voltage, gate low voltage, etc., to the gate drive unit GD. Thus, various signals can be transmitted from the upper gate drive wirings TGVL to the gate drive unit GD, and the gate drive unit GD can be driven.

[0068] For example, multiple upper gate drive wirings TGVL may include gate power wiring that transmits a power supply voltage to the gate drive unit GD of the gate drive region GA. Multiple gate power wirings may include a first gate power wiring that transmits a gate high voltage to the gate drive unit GD, and a second gate power wiring that transmits a gate low voltage to the gate drive unit GD.

[0069] Multiple alignment keys AK1 and AK2 are positioned in the region between multiple pixel regions UPA in the display panel PN. The multiple alignment keys AK1 and AK2 are used for alignment during the manufacturing process of the display panel PN. The multiple alignment keys AK1 and AK2 include a first alignment key AK1 and a second alignment key AK2.

[0070] The first alignment key AK1 may be positioned in the gate drive region GA, which is a region between multiple pixel regions UPA. The first alignment key AK1 may be used to check the alignment position of multiple light-emitting elements LEDs. For example, the first alignment key AK1 may be cross-shaped, but is not limited to this.

[0071] The second alignment key AK2 may be positioned to overlap the upper high-potential power supply wiring TVL1 in the region between multiple pixel regions UPA. A hole is formed in the upper high-potential power supply wiring TVL1 that overlaps with the second alignment key AK2, thereby separating the second alignment key AK2 from the upper high-potential power supply wiring TVL1. The second alignment key AK2 may be used when aligning the display panel PN and the donor. By using the second alignment key AK2 to align the display panel PN and the donor, multiple light-emitting LEDs of the donor can be transferred to the display panel PN. For example, the second alignment key AK2 may be made in the shape of a circular ring.

[0072] Figure 4 is an enlarged plan view of the second substrate of a display device according to one embodiment of this specification.

[0073] First, the display panel PN includes a second substrate 130. The second substrate 130 is a substrate that supports components located at the bottom of the display device 100, and may be an insulating substrate. For example, multiple flexible films COF and a printed circuit board PCB that transmit signals to multiple subpixels SP may be located at the bottom of the second substrate 130.

[0074] The second substrate 130 may be made of glass or resin, etc. The second substrate 130 may also contain polymers or plastics. The second substrate 130 may be made of the same material as the first substrate 110. In some embodiments, the second substrate 130 may be made of a flexible plastic material.

[0075] Referring to Figure 4, the second substrate 130 can include a plurality of lower pad regions, a COF pad region BPA3, and a plurality of wiring regions.

[0076] The multiple lower pad regions are areas on the lower part of the second substrate 130 where multiple lower pads BPAD are located. For example, the multiple lower pad regions may include a first lower pad region BPA1 located at the first edge EG1 of the display panel PN, and a second lower pad region BPA2 located at the second edge EG2. The multiple lower pads BPAD can transmit various signals to various wirings located in the multiple lower wiring regions.

[0077] Referring to Figure 4, the first lower pad region BPA1 may contain multiple first lower pads BPAD1. The multiple first lower pads BPAD1 may include multiple lower pads BPAD to which different signals are applied. For example, the multiple first lower pads BPAD1 may include a lower data pad BDP, a lower gate pad BGP, and a lower high-potential power pad BVP1.

[0078] On the other hand, each of the multiple lower pads BPAD can be formed to be of a different size from one another. For example, each of the multiple first lower pads BPAD1 can have a different size from one another. Specifically, the multiple lower data pads BDP, which are connected one-to-one with the multiple lower data wiring BDLs, may have a relatively narrow width, while the lower high-potential power pad BVP1 and lower gate pad BGP may have a relatively wide width. However, the widths of the lower data pads BDP, lower gate pad BGP, and lower high-potential power pad BVP1 shown in Figure 4 are illustrative, and the size of the lower pads BPAD can be configured in a variety of ways and is not limited thereto.

[0079] Multiple second lower pads BPAD2 may be arranged in the second lower pad region BPA2. In this case, the multiple second lower pads BPAD2 may be different lower pads BPAD from the multiple first lower pads BPAD1. For example, the multiple second lower pads BPAD2 may include a lower low-potential power supply pad BVP2 that transmits a low-potential power supply voltage to the lower low-potential power supply wiring BVL2.

[0080] On the other hand, each of the multiple second lower pads BPAD2 may have a different size from the others. For example, each of the multiple second lower pads BPAD2 may have a width that is relatively narrower than the multiple lower data pads BDP of the multiple first lower pads BPAD1, but is not limited to this. Also, the width of the lower low-potential power pad BVP2 shown in Figure 4 is illustrative, and the size of the lower pads BPAD can be configured in a variety of ways and is not limited thereto.

[0081] On the other hand, to reduce the bezel of the display panel PN, the edge of the display panel PN can be cut and removed. Multiple pixels PX, multiple wirings, and multiple lower pads BPAD can be formed on the initial second substrate 130i, and the bezel area can be reduced by grinding the edge portion of the initial second substrate 130i together with the initial first substrate 110i. In the grinding process, a portion of the initial second substrate 130i may be removed, forming a smaller second substrate 130. At this time, a portion of the multiple lower pads BPAD and wirings located on the edge of the second substrate 130 may be removed. Therefore, only a portion of the multiple lower pads BPAD may remain on the second substrate 130.

[0082] The COF pad area BPA3 is positioned between the first lower pad area BPA1 and the second lower pad area BPA2. For example, the COF pad area BPA3 may be positioned adjacent to the first lower pad area BPA1 among the first lower pad area BPA1 and the second lower pad area BPA2, but is not limited to this.

[0083] Multiple COF pads BPAD3 are placed in the COF pad area BPA3.

[0084] Multiple COF pads BPAD3 are connected to multiple underwires located in multiple underwire regions, enabling electrical connection between multiple underwires and multiple flexible film COF and printed circuit boards (PCBs).

[0085] For example, multiple lower data link wirings BDL can be connected to multiple COF pads BPAD3, and multiple COF pads BPAD3 can be electrically connected to multiple flexible film COF. Thus, multiple COF pads BPAD3 can electrically connect multiple flexible film COF and multiple lower data link wirings BDL.

[0086] Detailed information about the multiple COF pads BPAD3 will be described later, referring to Figure 8.

[0087] On the other hand, multiple flexible film COFs and printed circuit boards (PCBs) can be arranged in the COF pad area BPA3.

[0088] Multiple flexible film COFs can be electrically connected to multiple COF pads BPAD3. The flexible film COF is a film in which various components are arranged on a ductile base film and supplies signals to sub-pixels SP and drive components, and can be electrically connected to the display panel PN.

[0089] Multiple flexible film COFs may contain drive ICs such as gate driver ICs and data driver ICs. The drive ICs are components that process data for displaying the image and the drive signals required to process it. Depending on the mounting method, the drive ICs may be mounted in chip-on-glass (COG), chip-on-film (COF), or tape carrier package (TCP). However, for the sake of explanation, it has been described as a chip-on-film configuration where the drive ICs are mounted on multiple flexible film COFs, but the explanation is not limited to this configuration.

[0090] The printed circuit board (PCB) is electrically connected to multiple flexible film (COF) components. The PCB is a component that supplies signals to the drive IC. Various components can be arranged on the PCB to supply diverse signals to the drive IC.

[0091] On the other hand, while Figure 4 shows three flexible film COFs and one printed circuit board (PCB), the number of flexible film COFs and printed circuit boards (PCBs) can be varied depending on the design and is not limited thereto.

[0092] Multiple lower wiring areas are areas where multiple wires connected to multiple lower pads BPAD are located. Multiple lower wiring areas may include a first lower wiring area BLA1 and a second lower wiring area BLA2.

[0093] Referring to Figure 4, the first lower wiring area BLA1 and the second lower wiring area BLA2 are arranged between the first lower pad area BPA1 and the second lower pad area BPA2. The first lower wiring area BLA1 and the second lower wiring area BLA2 may be arranged separated by the COF pad area BPA3. For example, the first lower wiring area BLA1 may be arranged between the first lower pad area BPA1 and the COF pad area BPA3, and the second lower wiring area BLA2 may be arranged between the second lower pad area BPA2 and the COF pad area BPA3. Thus, the first lower pad area BPA1, the first lower wiring area BLA1, the COF pad area BPA3, the second lower wiring area BLA2, and the second lower pad area BPA2 may be arranged sequentially from the first edge EG1 to the second edge EG2 of the display panel PN.

[0094] The first lower wiring area BLA1 may contain lower data link wiring BDL, lower gate link wiring, lower high-potential power supply wiring BVL1, and a plurality of lower auxiliary high-potential power supply wiring BAVL1.

[0095] For example, in the first lower wiring area BLA1 on the back of the second substrate 130, multiple lower data link wirings BDL extending in the column direction from the lower data pad BDP are arranged. The multiple lower data link wirings BDL can extend toward the COF pad area BPA3 and be connected to multiple flexible film COF and printed circuit board PCB. In addition, the multiple lower data link wirings BDL can be arranged to overlap with the lower high-potential power supply wiring BVL1.

[0096] Multiple lower gate link wires are arranged in the first lower wiring area BLA1 on the back of the second substrate 130, extending in the column direction from the lower gate pad BGP. These multiple lower gate link wires can extend toward the COF pad area BPA3 and be connected to multiple COF pads BPAD3.

[0097] Multiple lower high-potential power link wirings extending in a row direction from multiple lower high-potential power pads BVP1 are arranged in the first lower wiring area BLA1 on the back of the second substrate 130.

[0098] Each of the multiple lower high-potential power link wires can extend in the column direction and be connected to the lower high-potential power wire BVL1.

[0099] The lower high-potential power supply wiring BVL1 may have a long axis in the row direction. For example, the width of the lower high-potential power supply wiring BVL1 may correspond to the width of the first lower pad area BPA1. For example, the width of the lower high-potential power supply wiring BVL1 may correspond to the distance between the outermost first lower pads BPAD1 among a plurality of first lower pads BPAD1. Thus, the lower high-potential power supply wiring BVL1 can contact each of the plurality of lower high-potential power supply link wirings that extend in the row direction.

[0100] Multiple lower auxiliary high-potential power supply wirings BAVL1 may be arranged in the first lower wiring region BLA1. Multiple lower auxiliary high-potential power supply wirings BAVL1 may be arranged superimposed on the lower high-potential power supply wiring BVL1.

[0101] On the other hand, the width of each of the multiple lower auxiliary high-potential power supply wirings BAVL1 can increase as they become adjacent to the lower low-potential power supply wiring BVL2. For example, the planar shape of the multiple lower auxiliary high-potential power supply wirings BAVL1 may be triangular.

[0102] Each of the multiple lower auxiliary high-potential power supply wirings BAVL1 may be spaced apart from the flexible film COF and arranged alternately with the flexible film COF along the row direction.

[0103] Detailed information regarding the multiple lower auxiliary high-potential power supply wirings BAVL1 and the multiple lower data link wirings BDL will be described later with reference to Figure 9.

[0104] Multiple lower low-potential power link wirings extending in the column direction from multiple second lower pads BPAD2 are arranged in the second lower wiring area BLA2 on the back of the second substrate 130.

[0105] Each of the multiple lower low-potential link wirings can extend in the column direction and be connected to the lower low-potential power wiring BVL2.

[0106] The lower low-potential power supply wiring BVL2 may have a long axis in the row direction. For example, the width of the lower low-potential power supply wiring BVL2 may correspond to the width of the second lower pad area BPA2. For example, the width of the lower low-potential power supply wiring BVL2 may correspond to the distance between the outermost second lower pads BPAD2 among a plurality of second lower pads BPAD2. Thus, the lower low-potential power supply wiring BVL2 can contact each of the plurality of lower low-potential power supply link wirings that extend in the row direction.

[0107] On the other hand, the lower data link wiring BDL, lower gate link wiring, and lower high-potential power link wiring, each located in the first lower wiring region BLA1 of the second substrate 130, can extend to a plurality of first lower pads BPAD1 and be connected to a plurality of first upper pads TPAD1 located on the first substrate 110 via first side wiring, which will be described later.

[0108] Furthermore, each of the lower low-potential power link wirings located in the second lower wiring region BLA2 of the second substrate 130 can extend to a plurality of second lower pads BPAD2 and be connected to a plurality of second upper pads TPAD2 located on the first substrate 110 via second side wiring, which will be described later.

[0109] Detailed information about the side wiring SRL will be provided later, referring to Figure 6.

[0110] In the following sections, we will refer to Figure 5 to provide a more detailed explanation of the multiple subpixels SP within the pixel region UPA.

[0111] Figure 5 is a cross-sectional view of a subpixel of a display device according to one embodiment of this specification. Each of the multiple subpixels SP of the display panel PN of the display device 100 according to one embodiment of this specification is provided with a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, an adhesive layer 116, a second planarization layer 117, a third planarization layer 118, a passivation layer 119, a drive transistor DT, a light-emitting element LED, multiple reflective electrodes RE1 and RE2, multiple connecting electrodes CE1 and CE2, a light-shielding layer LS, and an auxiliary electrode LE.

[0112] First, the first substrate 110 is a structure for supporting the various components included in the display device 100, and may be made of an insulating material. For example, the first substrate 110 may be made of glass or resin. Furthermore, the first substrate 110 may contain polymers or plastics, and may be made of a flexible material.

[0113] A light-shielding layer LS is placed on each of the multiple subpixels SP on the first substrate 110. The light-shielding layer LS blocks the light incident on the active layer ACT of the drive transistor DT, which will be described later, at the bottom of the first substrate 110. By blocking the light incident on the active layer ACT of the drive transistor DT with the light-shielding layer LS, leakage current can be minimized. For example, the light-shielding layer LS may be made of molybdenum (Mo), but is not limited to this.

[0114] A buffer layer 111 is placed on the first substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 110. The buffer layer 111 may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may, but is not limited to, be omitted depending on the type of first substrate 110 or the type of transistor.

[0115] A drive transistor DT is placed on the buffer layer 111. The drive transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0116] An active layer ACT is placed on the buffer layer 111. The active layer ACT may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0117] A gate insulating layer 112 is placed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE, and may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0118] A gate electrode GE is placed on the gate insulating layer 112. The gate electrode GE may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0119] A first interlayer insulating layer 113 is placed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 for the source electrode SE and the drain electrode DE to connect to the active layer ACT, respectively. The first interlayer insulating layer 113 is an insulating layer that protects the first interlayer insulating layer 113 and the underlying structure, and may, but is not limited to, a single or multilayer structure of silicon oxide (SiOx) or silicon nitride (SiNx).

[0120] A capacitor electrode C2 is placed on the first interlayer insulating layer 113. The capacitor electrode C2 may be placed so as to overlap the gate electrode GE with the first interlayer insulating layer 113 in between.

[0121] A second interlayer insulating layer 114 is placed on the capacitor electrode C2. Contact holes are formed in the second interlayer insulating layer 114 for the source electrode SE and the drain electrode DE to connect to the active layer ACT, respectively. The second interlayer insulating layer 114 is an insulating layer for protecting the structure below it and may, but is not limited to, a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0122] A source electrode SE and a drain electrode DE are arranged on the second interlayer insulating layer 114, electrically connected to the active layer ACT. The source electrode SE and drain electrode DE may, but are not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0123] On the other hand, although this specification has described a configuration in which a first interlayer insulating layer 113 and a second interlayer insulating layer 114, i.e., multiple insulating layers, are arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE, the specification is not limited to this configuration, and may also describe a configuration in which only one insulating layer is arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE.

[0124] Furthermore, as shown in the drawing, if multiple insulating layers such as a first interlayer insulating layer 113 and a second interlayer insulating layer 114 are arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE, then electrodes can be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and these further formed electrodes can form a capacitor with other components arranged below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0125] An auxiliary electrode LE is placed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to either the source electrode SE or the drain electrode DE through the auxiliary electrode LE and ceases to operate as a floating gate, thereby minimizing the threshold voltage fluctuation of the drive transistor DT caused by the floating light-shielding layer LS. In the drawing, the light-shielding layer LS is shown to be connected to the source electrode SE, but the light-shielding layer LS may also be connected to the drain electrode DE, and is not limited to this.

[0126] A first planarization layer 115 is placed on the drive transistor DT. The first planarization layer 115 can planarize the upper part of the first substrate 110 on which the drive transistor DT is placed. The first planarization layer 115 may be composed of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0127] Multiple reflective electrodes RE1 and RE2 are arranged on the first planarization layer 115, spaced apart from each other. The multiple reflective electrodes RE1 and RE2 electrically connect the light-emitting element LED to the power supply wiring and the drive transistor DT, and at the same time function as reflectors that reflect the light emitted by the light-emitting element LED towards the top of the light-emitting element LED. The multiple reflective electrodes RE1 and RE2 are formed of a conductive material with excellent reflective properties, and can reflect the light emitted by the light-emitting element LED towards the top of the light-emitting element LED.

[0128] For example, the multiple reflective electrodes RE1 and RE2 may, but are not limited to, a conductive material, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0129] The multiple reflective electrodes RE1 and RE2 include a first reflective electrode RE1 and a second reflective electrode RE2. The second reflective electrode RE2 can electrically connect the drive transistor DT and the light-emitting element LED. The second reflective electrode RE2 can be connected to the source electrode SE or drain electrode DE of the drive transistor DT through a contact hole formed in the first planarization layer 115. Furthermore, the second reflective electrode RE2 can be electrically connected to the first electrode 124 of the light-emitting element LED through a second connecting electrode CE2, which will be described later.

[0130] The first reflective electrode RE1 can electrically connect the power supply wiring and the light-emitting element LED. The first reflective electrode RE1 is connected to the power supply wiring and can be electrically connected to the second electrode 125 of the light-emitting element LED through the first connecting electrode CE1, which will be described later.

[0131] A passivation layer 119 is placed on multiple reflective electrodes RE1 and RE2. The passivation layer 119 has contact holes for connecting each of the multiple reflective electrodes RE1 and RE2 to the first connecting electrode CE1 and the second connecting electrode CE2. The passivation layer 119 is an insulating layer for protecting the underlying structure and may, but is not limited to, a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0132] An adhesive layer 116 is placed on multiple reflective electrodes RE1 and RE2. The adhesive layer 116 is coated on the front surface of the first substrate 110, and can fix the light-emitting element LED placed on the adhesive layer 116. The adhesive layer 116 can be selected from, but is not limited to, one of the following: adhesive polymer, epoxy resist, UV resin, polyimide series, acrylate series, urethane series, or polydimethylsiloxane (PDMS).

[0133] Multiple light-emitting LEDs are arranged on each of the multiple subpixels SP on the adhesive layer 116. The multiple light-emitting LEDs are elements that emit light when an electric current is applied, and may include light-emitting LEDs that emit red light, green light, blue light, etc., and various hues of light, including white, can be realized by combinations of these. For example, the multiple light-emitting LEDs may be LEDs (Light Emitting Diodes) or microLEDs, but are not limited to these.

[0134] Multiple light-emitting LEDs may include a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element may be placed in the first subpixel, the second light-emitting element in the second subpixel SP2, and the third light-emitting element in the third subpixel SP3. For example, the first light-emitting element may be a red light-emitting element, the second light-emitting element may be a green light-emitting element, and the third light-emitting element may be a blue light-emitting element.

[0135] Each of the multiple light-emitting LEDs includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a sealing film 126.

[0136] A first semiconductor layer 121 is placed on the adhesive layer 116, and a second semiconductor layer 123 is placed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping specific materials with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be layers doped with n-type and p-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited to these.

[0137] A light-emitting layer 122 is disposed between a first semiconductor layer 121 and a second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can be a single layer or a multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0138] A first electrode 124 is placed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the drive transistor DT and the first semiconductor layer 121. The first electrode 124 may be placed on the upper surface of the first semiconductor layer 121 that is exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0139] A second electrode 125 is placed on the second semiconductor layer 123. The second electrode 125 may be placed on the upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the power supply wiring and the second semiconductor layer 123. The second electrode 125 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0140] Next, a sealing film 126 is placed surrounding the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The sealing film 126 is made of an insulating material and can protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Contact holes are formed in the sealing film 126 to expose the first electrode 124 and the second electrode 125, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be electrically connected to the first electrode 124 and the second electrode 125.

[0141] A second planarization layer 117 and a third planarization layer 118 are arranged on the adhesive layer 116. The second planarization layer 117 can be superimposed on a portion of the side surfaces of the multiple light-emitting element LEDs to fix and protect them. Specifically, in Figure 5, the sealing film 126 is shown to surround the entire side surface of the first semiconductor layer 121, but a portion of the side surface of the first semiconductor layer 121 may be exposed from the sealing film 126. The light-emitting element LEDs manufactured on the wafer can be separated from the wafer and transferred to the display panel PN. However, a portion of the sealing film 126 may be peeled off during the process of separating the light-emitting element LEDs from the wafer. For example, a portion of the sealing film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting element LED may be peeled off during the separation process of the light-emitting element LED from the wafer, exposing a portion of the lower side surface of the first semiconductor layer 121 to the outside. However, even if the lower portion of the light-emitting element LED is exposed from the sealing film 126, the first connecting electrode CE1 and the second connecting electrode CE2 are formed after the second planarization layer 117 that covers the side surface of the first semiconductor layer 121 is formed, so short-circuit defects can be minimized.

[0142] Furthermore, the third planarization layer 118 is formed to cover the second planarization layer 117 and the upper portion of the light-emitting LED, and contact holes may be formed that expose the first electrode 124 and the second electrode 125 of the light-emitting LED. The first electrode 124 and the second electrode 125 of the light-emitting LED are exposed from the third planarization layer 118, and the third planarization layer 118 is partially positioned in the region between the first electrode 124 and the second electrode 125, thereby minimizing short-circuit defects.

[0143] The second planarization layer 117 and the third planarization layer 118 may be single or multilayered, and may, for example, be made of photoresist or acrylic organic material, but are not limited thereto. On the other hand, although this specification has described the arrangement of the second planarization layer 117 and the third planarization layer 118, the planarization layer may be a single layer, and is not limited thereto.

[0144] Multiple connecting electrodes CE1 and CE2 are arranged on the third planarization layer 118. The multiple connecting electrodes CE1 and CE2 include multiple first connecting electrodes CE1 and second connecting electrodes CE2.

[0145] The second connecting electrode CE2 is positioned in each of the multiple sub-pixels SP and is an electrode for electrically connecting the light-emitting element LED and the drive transistor DT. The second connecting electrode CE2 can be connected to the second reflective electrode RE2 through contact holes formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Thus, the second connecting electrode CE2 can be electrically connected to either the source electrode SE or the drain electrode DE of the drive transistor DT through the second reflective electrode RE2. Furthermore, the second connecting electrode CE2 can be connected to the first electrode 124 of each of the multiple light-emitting elements LED through contact holes formed in the third planarization layer 118. Thus, the second connecting electrode CE2 can electrically connect the drive transistor DT and the first electrode 124 of the multiple light-emitting elements LED.

[0146] The first connecting electrode CE1 is an electrode for electrically connecting the light-emitting element LED and the power supply wiring. The first connecting electrode CE1 can be connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. The first connecting electrode CE1 can also be electrically connected to the power supply wiring through the first reflective electrode RE1. Furthermore, the first connecting electrode CE1 can be connected to the second electrode 125 of each of the multiple light-emitting element LEDs through contact holes formed in the third planarization layer 118. Thus, the first connecting electrode CE1 can electrically connect the power supply wiring to the second electrode 125 of the multiple light-emitting element LEDs.

[0147] Bank BB is positioned on the first connecting electrode CE1 and the second connecting electrode CE2. Bank BB may be positioned at a certain distance from the light-emitting element LED.

[0148] The bank BB may consist of an opaque material to reduce color mixing between multiple subpixels SP, for example, black resin, but is not limited to this.

[0149] A protective layer 190 is placed on the first connecting electrode CE1, the second connecting electrode CE2, and the bank BB. The protective layer 190 is a layer for protecting the components beneath it, and may, for example, cover at least a portion of the light-emitting element LED. It may, but is not limited to, consist of a single or multiple layer of translucent epoxy, silicon oxide (SiOx), or silicon nitride (SiNx).

[0150] On the other hand, the second connecting electrode CE2, which connects the drive transistor DT and the light-emitting element LED, each of the multiple subpixels SP, can be individually arranged for each of the multiple subpixels SP.

[0151] In the following sections, the multiple upper pads (TPAD) and the multiple lower pads (BPAD) will be described in detail with reference to Figures 6 through 7b.

[0152] Figure 6 is a cross-sectional view of the pad area of ​​a display device according to one embodiment of this specification. Figure 7a is a cross-sectional view of the upper pad of a display device according to one embodiment of this specification. Figure 7b is a cross-sectional view of the lower pad of a display device according to one embodiment of this specification. In Figure 7b, for illustrative purposes, the positions of the second substrate 130 and the lower components of the second substrate 130 are reversed so that the second substrate 130 is located at the bottom.

[0153] Referring to Figures 6 and 7a, each of the multiple upper pads TPAD can consist of multiple conductive layers. For example, each of the multiple upper pads TPAD can include a first upper pad electrode TPEa, a second upper pad electrode TPEb, and a third upper pad electrode TPEc. That is, each of the multiple first upper pads TPAD1 and the multiple second upper pads TPAD2 can include a first upper pad electrode TPEa, a second upper pad electrode TPEb, and a third upper pad electrode TPEc.

[0154] First, a first upper pad electrode TPEa is placed on the second interlayer insulating layer 114. The first upper pad electrode TPEa may be made of the same conductive material as the source electrode SE and the drain electrode DE, and may be, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0155] A second upper pad electrode TPEb is positioned on a first upper pad electrode TPEa. The second upper pad electrode TPEb may consist of the same conductive material as the plurality of reflective electrodes RE1 and RE2. The second upper pad electrode TPEb may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0156] A third upper pad electrode TPEc is placed on the second upper pad electrode TPEb. The third upper pad electrode TPEc may be made of the same conductive material as the first connecting electrode CE1 and the second connecting electrode CE2, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0157] Although not shown in the drawing, some of the multiple upper pad electrodes of the upper pad TPAD are electrically connected to multiple wirings on the first substrate 110, and can supply various signals to multiple wirings and multiple sub-pixels SP. For example, the first upper pad electrode TPEa and / or the second upper pad electrode TPEb of the upper pad TPAD are connected to the upper data wiring TDL, upper high-potential power wiring TVL1, upper low-potential power wiring TVL2, etc., located in the display area AA, and can transmit signals to each of them.

[0158] Furthermore, a first metal layer ML1, a second metal layer ML2, and multiple insulating layers may be arranged together below the upper pad TPAD. The step height of the upper pad TPAD can be adjusted by arranging the first metal layer ML1, the second metal layer ML2, and multiple insulating layers below the upper pad TPAD. For example, a buffer layer 111, a gate insulating layer 112, a first metal layer ML1, a first interlayer insulating layer 113, and a second metal layer ML2 may be arranged sequentially between the upper pad TPAD and the first substrate 110. The first metal layer ML1 may be made of the same conductive material as the gate electrode GE, and the second metal layer ML2 may be made of the same conductive material as the capacitor electrode C2. However, the multiple insulating layers below the upper pad TPAD, as well as the first metal layer ML1 and the second metal layer ML2, may be omitted depending on the design, and are not limited thereto.

[0159] A second substrate 130 is placed below the first substrate 110. The second substrate 130 is a substrate that supports components placed at the bottom of the display device 100, and may be an insulating substrate. For example, the second substrate 130 may be made of glass or resin. The second substrate 130 may also contain polymers or plastics. The second substrate 130 may be made of the same material as the first substrate 110. In some embodiments, the second substrate 130 may be made of a flexible plastic material.

[0160] A bonding layer BL is placed between the first substrate 110 and the second substrate 130. The bonding layer BL can be made of a material that can be cured through various curing methods and bond the first substrate 110 and the second substrate 130 together. The bonding layer BL may be placed in only a portion of the area between the first substrate 110 and the second substrate 130, or it may be placed over the entire area.

[0161] Multiple lower pads BPAD are arranged on the back of the second substrate 130. The multiple lower pads BPAD are electrodes for transmitting signals from drive components located on the back side of the second substrate 130 to multiple side wirings SRL, multiple upper pads TPAD on the first substrate 110, and multiple wirings. The multiple lower pads BPAD are located at the edge of the second substrate 130 in a non-display area NA and can be electrically connected to the side wirings SRL that cover the edge of the second substrate 130.

[0162] In this case, multiple lower pads BPAD may also be arranged corresponding to multiple lower pad areas. Each of the multiple upper pads TPAD may be arranged corresponding to each of the multiple lower pads BPAD, and thereafter, the upper pads TPAD and lower pads BPAD that overlap each other may be electrically connected via side wiring SRL.

[0163] Each of the multiple lower pads BPAD includes multiple pad electrodes. For example, each of the multiple lower pads BPAD includes a first lower pad electrode BPEa, a second lower pad electrode BPEb, and a third lower pad electrode BPEc. That is, each of the multiple first lower pads BPAD1 and the multiple second lower pads BPAD2 includes a first lower pad electrode BPEa, a second lower pad electrode BPEb, and a third lower pad electrode BPEc.

[0164] In Figure 7b, for illustrative purposes, the lower pad BPAD is shown to be placed on the second substrate 130, and the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc are sequentially placed on the upper part of the second substrate 130.

[0165] However, the second substrate 130 shown in Figure 7b is inverted vertically and bonded to the first substrate 110. In this state, when the second substrate 130 and the first substrate 110 are bonded together, as shown in Figure 6, a plurality of lower pads BPAD may be placed below the second substrate 130, and the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc may be placed sequentially below the second substrate 130.

[0166] In the following explanation, we will use the time when the second substrate 130 is bonded to the first substrate 110 as a reference point, and explain that the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc are sequentially placed beneath the second substrate 130.

[0167] First, a first lower pad electrode BPEa is placed beneath the second substrate 130. The first lower pad electrode BPEa may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0168] A first insulating layer 131 is positioned beneath the first lower pad electrode BPEa. Referring to Figure 7b, the first insulating layer 131 may cover the side portion of the first lower pad electrode BPEa. On the other hand, the first insulating layer 131 may include an open portion that exposes a portion of one side of the first lower pad electrode BPEa.

[0169] The first insulating layer 131 may be an inorganic insulating layer. For example, the first insulating layer 131 may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0170] The second lower pad electrode BPEb is positioned beneath the first insulating layer 131. Referring to Figure 7b, the second lower pad electrode BPEb can contact one surface of the first lower pad electrode BPEa that is exposed by the opening in the first insulating layer 131.

[0171] The second lower pad electrode BPEb may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0172] The third lower pad electrode BPEc is positioned below the second lower pad electrode BPEb. Referring to Figure 7b, the third lower pad electrode BPEc can contact one surface of the second lower pad electrode BPEb.

[0173] On the other hand, referring to Figure 7b, the third lower pad electrode BPEc and the second lower pad electrode BPEb can completely overlap. For example, the area where the third lower pad electrode BPEc and the second substrate 130 overlap may be the same as the area where the second lower pad electrode BPEb and the second substrate 130 overlap.

[0174] The third lower pad electrode BPEc may be made of a material that does not corrode well even when in contact with air or moisture, in order to prevent corrosion of the second lower pad electrode BPEb. For example, the third lower pad electrode BPEc may be made of a conductive material, such as a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0175] A second insulating layer 132 is positioned below the third lower pad electrode BPEc. The second insulating layer 132 may be an inorganic insulating layer. For example, the second insulating layer 132 may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0176] On the other hand, the second insulating layer 132 may leave a portion of the third lower pad electrode BPEc open, or it may cover a portion of the edge of the third lower pad electrode BPEc.

[0177] The third lower pad electrode BPEc, exposed by the second insulating layer 132, can come into contact with the side wiring SRL, which will be described later.

[0178] On the other hand, the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc of the multiple lower pads BPAD can extend to the multiple flexible film COF located on the back side of the second substrate 130 and be electrically connected to the multiple flexible film COF, and the multiple flexible film COF can supply various signals to the multiple side wiring SRL, the multiple upper pads TPAD, the multiple wirings, and the multiple sub-pixels SP through the multiple lower pads BPAD. Thus, signals from the drive components can be transmitted to the signal wiring on the front of the first substrate 110 and the multiple sub-pixels SP through the multiple lower pads BPAD of the second substrate 130, the side wiring SRL, and the multiple upper pads TPAD of the first substrate 110.

[0179] Referring again to Figure 6, a plurality of side wiring SRLs are arranged on the sides of the first substrate 110 and the second substrate 130. The plurality of side wiring SRLs can electrically connect a plurality of upper pads TPAD formed on the upper surface of the first substrate 110 and a plurality of lower pads BPAD formed on the back surface of the second substrate 130. For example, the plurality of side wiring SRLs may be arranged to contact the third upper pad electrode TPEc and the third lower pad electrode BPEc, respectively, and surround the side of the display device 100. Each of the plurality of side wiring SRLs may cover a plurality of upper pads TPAD at the edge of the first substrate 110, the side of the first substrate 110, the side of the second substrate 130, and a plurality of lower pads BPAD at the edge of the second substrate 130. For example, the plurality of side wiring SRLs may be formed by a pad printing method using conductive ink, for example, conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

[0180] Multiple side traces (SRLs) may include multiple first side traces arranged corresponding to the first edge EG1 of the first substrate 110 and the first edge EG1 of the second substrate 130, and multiple second side traces arranged corresponding to the second edge EG2 of the first substrate 110 and the second edge EG2 of the second substrate 130.

[0181] Therefore, among the multiple side wirings SRL, multiple first side wirings can connect multiple first upper pads TPAD1 and multiple first lower pads BPAD1, and multiple second side wirings can connect multiple second upper pads TPAD2 and multiple second lower pads BPAD2.

[0182] Referring to Figure 6, a side insulating layer 150 is arranged to cover multiple side wiring SRLs. The side insulating layer 150 may be formed to cover the side wiring SRLs on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 130, and the back surface of the second substrate 130. The side insulating layer 150 can protect multiple side wiring SRLs.

[0183] On the other hand, if multiple side wiring SRLs are made of metallic material, a problem may arise where ambient light is reflected by the multiple side wiring SRLs, or light emitted by the light-emitting element LED is reflected by the multiple side wiring SRLs and becomes visible to the user. Therefore, the side insulating layer 150 is configured to include a black material to suppress ambient light reflection. For example, the side insulating layer 150 can be formed by an insulating material containing a black material, for example, by a pad printing method using black ink.

[0184] A sealing member 160 is positioned to cover the side insulating layer 150. The sealing member 160 is positioned to surround the side of the display device 100, protecting the display device 100 from external impacts, moisture, oxygen, etc. For example, the sealing member 160 may be made of, but is not limited to, polyimide (PI), polyurethane (Poly Urethane), epoxy (Epoxy), or acrylic (Acryl) series insulating materials.

[0185] An optical film MF is placed on the sealing member 160, the side insulating layer 150, and the protective layer 190. The optical film MF may be a functional film that provides higher quality images while protecting the display device 100. For example, the optical film MF may include, but is not limited to, a shatterproof film, an anti-glare film, an anti-reflective film, a low-reflecting film, an oled transmittance controllable film, or a polarizing plate.

[0186] On the other hand, an adhesive layer may be further arranged between the optical film MF, the sealing member 160, the side insulating layer 150, and the protective layer 190, but for convenience of illustration, the adhesive layer is omitted in Figures 5 and 6. Alternatively, the optical film MF may be defined as including an adhesive layer arranged at the bottom.

[0187] The edges of the sealing member 160 and the optical film MF can be aligned on the same line. During the manufacturing process of the display device 100, a larger optical film MF can be attached to the top of the first substrate 110 to form a sealing member 160 that covers the side insulating layer 150. After this, a laser can be irradiated onto the sealing member 160 and the optical film MF to cut a portion of the sealing member 160 and the optical film MF to correspond to the edges of the display device 100. Thus, the size of the display device 100 can be adjusted and the edges of the display device 100 can be formed flat through the cutting process of the outer casings of the sealing member 160 and the optical film MF.

[0188] In the following, with reference to Figure 8, the COF pad area BPA3 of the display device according to one embodiment of this specification will be described in detail.

[0189] Figure 8 is a cross-sectional view of the second substrate along A-A' in Figure 4. Figure 8 is a cross-sectional view of the COF pad region BPA3. In Figure 8, for illustrative purposes only, only the COF pad BPAD3 is shown, without the flexible film COF. In Figure 8, for illustrative purposes only, the positions of the second substrate 130 and the COF pad BPAD3 are reversed, and the second substrate 130 is shown as being positioned at the bottom of the drawing.

[0190] Referring to Figure 8, multiple COF pads BPAD3 are arranged in the COF pad area BPA3.

[0191] Each of the multiple COF pads BPAD3 may consist of multiple conductive layers. For example, each of the multiple COF pads BPAD3 may include a first COF pad electrode BPE3a, a second COF pad electrode BPE3b, and a third COF pad electrode BPE3c.

[0192] In Figure 8, for illustrative purposes, the COF pad BPAD3 is shown to be placed on the second substrate 130, and the first COF pad electrode BPE3a, the second COF pad electrode BPE3b, and the third COF pad electrode BPE3c are shown to be sequentially placed on the upper part of the second substrate 130.

[0193] However, the second substrate 130 shown in Figure 8 is inverted vertically and bonded to the first substrate 110. In this state, when the second substrate 130 and the first substrate 110 are bonded together, multiple COF pads BPAD3 may be placed beneath the second substrate 130, and the first COF pad electrode BPE3a, the second COF pad electrode BPE3b, and the third COF pad electrode BPE3c may be placed sequentially beneath the second substrate 130.

[0194] In the following explanation, we will use the time when the second substrate 130 is bonded to the first substrate 110 as a reference point, and explain that the first COF pad electrode BPE3a, the second COF pad electrode BPE3b, and the third COF pad electrode BPE3c are sequentially placed beneath the second substrate 130.

[0195] The first COF pad electrode BPE3a is positioned at the bottom of the second substrate 130.

[0196] The first COF pad electrode BPE3a may be made of the same material as the first lower pad electrode BPEa. For example, the first COF pad electrode BPE3a may be, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0197] A second COF pad electrode BPE3b is positioned below the first COF pad electrode BPE3a. The second COF pad electrode BPE3b can contact one surface of the first COF pad electrode BPE3a that is exposed by the first insulating layer 131.

[0198] The second COF pad electrode BPE3b may be made of the same material as the second lower pad electrode BPEb. For example, the second COF pad electrode BPE3b may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0199] The third COF pad electrode BPE3c is positioned below the second COF pad electrode BPE3b. The third COF pad electrode BPE3c can contact one surface of the second COF pad electrode BPE3b.

[0200] The third COF pad electrode BPE3c and the second COF pad electrode BPE3b can completely overlap. For example, the area where the third COF pad electrode BPE3c and the second substrate 130 overlap may be the same as the area where the second COF pad electrode BPE3b and the second substrate 130 overlap.

[0201] The third COF pad electrode BPE3c may be made of the same material as the third lower pad electrode BPEc. For example, the third COF pad electrode BPE3c may be made of a material that does not corrode well even when in contact with air or moisture, in order to prevent corrosion of the second COF pad electrode BPE3b. For example, the third COF pad electrode BPE3c may be made of a conductive material, such as a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0202] Multiple COF pads BPAD3 can be electrically connected to multiple flexible film COF through the third COF pad electrode BPE3c, which is one of the multiple conductive layers constituting each of the multiple COF pads BPAD3. That is, they can be electrically connected to an external module through the third COF pad electrode BPE3c.

[0203] For example, multiple COF pads BPAD3 can be electrically connected to multiple flexible film COF through a third COF pad electrode BPE3c exposed by a second insulating layer 132.

[0204] Although not shown in Figure 8, each of the multiple COF pads BPAD3 can be electrically connected to multiple flexible film COFs through the third COF pad electrode BPE3c, which is one of the multiple conductive layers constituting each COF pad BPAD3.

[0205] Multiple COF pads BPAD3 can be connected to multiple flexible film COF through an adhesive layer. For example, the adhesive layer may be an anisotropic conductive film (ACF) or a conductive paste. Alternatively, for example, multiple flexible film COF can be electrically connected to the multiple COF pads BPAD3 of the second substrate 130 by heat and pressure.

[0206] In the following section, the lower power supply wiring will be explained in detail with reference to Figure 9.

[0207] Figure 9 is a cross-sectional view of the second substrate along B-B' in Figure 4. Figure 9 is a cross-sectional view of the first lower wiring region BLA1 and the second lower wiring region BLA2. In Figure 9, for illustrative purposes, the positions of the second substrate 130 and its lower components are reversed so that the second substrate 130 is located at the bottom.

[0208] Referring to Figure 9, the lower high-potential power supply wiring BVL1, the lower auxiliary high-potential power supply wiring BAVL1, and multiple lower data link wirings BDL are arranged in the first lower wiring area BLA1.

[0209] In Figure 9, for illustrative purposes, it is shown that the lower high-potential power supply wiring BVL1, the lower auxiliary high-potential power supply wiring BAVL1, and multiple lower data link wirings BDL are arranged on the second substrate 130.

[0210] However, the second substrate 130 shown in Figure 9 is inverted vertically and bonded to the first substrate 110. Therefore, in the state where the second substrate 130 and the first substrate 110 are bonded together, the lower high-potential power supply wiring BVL1, the lower auxiliary high-potential power supply wiring BAVL1, and multiple lower data link wirings BDL can be placed below the second substrate 130.

[0211] In the following explanation, we will use the time when the second substrate 130 is bonded to the first substrate 110 as a reference point, and explain that the lower high-potential power supply wiring BVL1, the lower auxiliary high-potential power supply wiring BAVL1, and multiple lower data link wirings BDL are arranged below the second substrate 130.

[0212] The lower high-potential power supply wiring BVL1 is located at the bottom of the second board 130.

[0213] The lower high-potential power supply wiring BVL1 may be made of the same material as the first lower pad electrode BPEa and the first COF pad electrode BPE3a. For example, the lower high-potential power supply wiring BVL1 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0214] A first insulating layer 131 is positioned below the lower high-potential power supply wiring BVL1. The first insulating layer 131 may include multiple open portions positioned to overlap with the multiple lower auxiliary high-potential power supply wirings BAVL1, which will be described later. On the other hand, the first insulating layer 131 is positioned to overlap with the multiple lower data link wirings BDL, thereby insulating the lower high-potential power supply wiring BVL1 from the multiple lower data link wirings BDL.

[0215] Multiple lower auxiliary high-potential power supply wirings BAVL1 and multiple lower data link wirings BDL are arranged below the first insulating layer 131.

[0216] First, multiple lower auxiliary high-potential power supply wirings BAVL1 are placed below the first insulating layer 131.

[0217] Multiple lower auxiliary high-potential power wirings BAVL1 can contact the front surface of the lower high-potential power wiring BVL1 exposed by the first insulating layer 131. For example, the first insulating layer 131 and multiple lower auxiliary high-potential power wirings BAVL1 may be arranged below the lower high-potential power wiring BVL1, and the first insulating layer 131 may be arranged in a region excluding the space between the flexible film COF. Thus, multiple lower auxiliary high-potential power wirings BAVL1 can contact the lower high-potential power wiring BVL1 in the region between the flexible film COF where the first insulating layer 131 is open.

[0218] Therefore, multiple lower auxiliary high-potential power supply wirings BAVL1 can contact the lower high-potential power supply wiring BVL1 to minimize voltage drop and voltage deviation.

[0219] Each of the multiple lower auxiliary high-potential power supply wirings BAVL1 includes a first lower auxiliary high-potential power supply wiring BAVL1a and a second lower auxiliary high-potential power supply wiring BAVL1b.

[0220] A first insulating layer 131 is placed below the second substrate 130, and a first lower auxiliary high-potential power supply wiring BAVL1a is placed below the first insulating layer 131.

[0221] The first lower auxiliary high-potential power supply wiring BAVL1a may be made of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b. For example, the first lower auxiliary high-potential power supply wiring BAVL1a may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0222] The second lower auxiliary high-potential power supply wiring BAVL1b is positioned below the first lower auxiliary high-potential power supply wiring BAVL1a.

[0223] The second lower auxiliary high-potential power supply wiring BAVL1b may be made of the same material as the third lower pad electrode BPEc and the third COF pad electrode BPE3c. For example, the second lower auxiliary high-potential power supply wiring BAVL1b may be made of a material that does not corrode well even when in contact with air or moisture, in order to prevent corrosion of the first lower auxiliary high-potential power supply wiring BAVL1a. For example, the second lower auxiliary high-potential power supply wiring BAVL1b may be made of a conductive material, such as a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0224] The second lower auxiliary high-potential power supply wiring BAVL1b can come into contact with the front surface of the first lower auxiliary high-potential power supply wiring BAVL1a. On the other hand, the second lower auxiliary high-potential power supply wiring BAVL1b can completely overlap with the first lower auxiliary high-potential power supply wiring BAVL1a. For example, the area where the second lower auxiliary high-potential power supply wiring BAVL1b and the second substrate 130 overlap may be the same as the area where the first lower auxiliary high-potential power supply wiring BAVL1a and the second substrate 130 overlap.

[0225] Multiple lower auxiliary high-potential power supply wirings BAVL1 may be made of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b.

[0226] For example, the multiple lower auxiliary high-potential power supply wiring BAVL1 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0227] Multiple lower data link wiring BDLs are arranged below the first insulating layer 131.

[0228] Multiple lower data link wirings (BDL) may be located on the same layer as multiple lower auxiliary high-potential power supply wirings (BAVL1).

[0229] Multiple lower data link wirings BDL can be arranged superimposed on the lower high-potential power supply wiring BVL1. For example, multiple lower data link wirings BDL can be arranged superimposed on the lower high-potential power supply wiring BVL1 with the first insulating layer 131 in between.

[0230] Each of the multiple lower data link wirings BDL includes a first lower data link wiring BDLa and a second lower data link wiring BDLb.

[0231] A first insulating layer 131 is placed below the second substrate 130, and a first lower data link wiring BDLa is placed below the first insulating layer 131.

[0232] The first lower data link wiring BDLa may consist of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b. For example, the first lower data link wiring BDLa may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0233] The second lower data link wiring BDLb is located below the first lower data link wiring BDLa.

[0234] The second lower data link wiring BDLb may be made of the same material as the third lower pad electrode BPEc and the third COF pad electrode BPE3c. For example, the second lower data link wiring BDLb may be made of a material that does not corrode well even when in contact with air or moisture, in order to prevent corrosion of the first lower data link wiring BDLa. For example, the second lower data link wiring BDLb may be made of a conductive material, such as a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0235] The second lower data link wiring BDLb can be in contact with the front surface of the first lower data link wiring BDLa. On the other hand, the second lower data link wiring BDLb can completely overlap the first lower data link wiring BDLa. For example, the area where the second lower data link wiring BDLb and the second substrate 130 overlap may be the same as the area where the first lower data link wiring BDLa and the second substrate 130 overlap.

[0236] The lower low-potential power supply wiring BVL2 is located in the second lower wiring area BLA2.

[0237] In Figure 9, for illustrative purposes, the lower low-potential power supply wiring BVL2 is shown as being placed on the second substrate 130. However, the second substrate 130 shown in Figure 9 is inverted vertically and bonded to the first substrate 110. Therefore, in the state where the second substrate 130 and the first substrate 110 are bonded together, the lower low-potential power supply wiring BVL2 can be placed below the second substrate 130.

[0238] In the following explanation, we will use the time when the second substrate 130 is bonded to the first substrate 110 as a reference point, and will explain that the lower low-potential power supply wiring BVL2 is placed below the second substrate 130.

[0239] The lower low-potential power supply wiring BVL2 includes the first lower low-potential power supply wiring BVL2a, the second lower low-potential power supply wiring BVL2b, and the third lower low-potential power supply wiring BVL2c.

[0240] The first lower low-potential power supply wiring BVL2a is located at the bottom of the second substrate 130.

[0241] The first lower low-potential power supply wiring BVL2a may be made of the same material as the first lower pad electrode BPEa and the first COF pad electrode BPE3a. For example, the first lower low-potential power supply wiring BVL2a may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0242] A first insulating layer 131 may be placed below the first lower low-potential power supply wiring BVL2a, and a second lower low-potential power supply wiring BVL2b may be placed below the first insulating layer 131.

[0243] The second lower low-potential power supply wiring BVL2b can contact the front surface of the first lower low-potential power supply wiring BVL2a, which is exposed by the first insulating layer 131. For example, the first insulating layer 131 and the second lower low-potential power supply wiring BVL2b may be located below the first lower low-potential power supply wiring BVL2a, and the first insulating layer 131 may be located in an area excluding the second lower wiring region BLA2. In this case, the second lower low-potential power supply wiring BVL2b can contact the first lower low-potential power supply wiring BVL2a in the second lower wiring region BLA2.

[0244] The second lower low-potential power wiring BVL2b may be made of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b. For example, the second lower low-potential power wiring BVL2b may be made of a conductive material, and may, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0245] A third lower low-potential power supply wiring BVL2c may be placed below the second lower low-potential power supply wiring BVL2b.

[0246] The third lower low-potential power supply wiring BVL2c can make contact with the front surface of the second lower low-potential power supply wiring BVL2b.

[0247] The third lower low-potential power supply wiring BVL2c may be made of the same material as the third lower pad electrode BPEc and the third COF pad electrode BPE3c. For example, the third lower low-potential power supply wiring BVL2c may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0248] On the other hand, the third lower low-potential power supply wiring BVL2c can completely overlap with the second lower low-potential power supply wiring BVL2b. For example, the area where the third lower low-potential power supply wiring BVL2c and the second substrate 130 overlap may be the same as the area where the second lower low-potential power supply wiring BVL2b and the second substrate 130 overlap.

[0249] When multiple metal layers arranged on a display panel are exposed to the outside, these metal layers can corrode in reaction with air or moisture. For example, multiple upper pads arranged on a first substrate and multiple lower pads arranged on the bottom of a second substrate can corrode in reaction with air or moisture. Therefore, to prevent corrosion of the multiple upper pads and multiple lower pads, a transparent conductive layer is used as the multiple pad electrodes that make up the multiple upper pads and multiple lower pads. In this case, multiple power lines or multiple data lines can also be arranged on the same layer as the transparent conductive layer of the multiple upper pads and multiple lower pads. However, when multiple power lines or multiple data lines are formed with a transparent conductive layer, a separate masking process is carried out to pattern the transparent conductive layer. For example, a process of forming an insulating layer, such as an organic insulating layer, on the top or bottom of the transparent conductive layer may be added. This leads to an increase in the number of masks, resulting in increased manufacturing costs and time.

[0250] On the other hand, wiring made of a transparent conductive layer can be arranged in superimposition with metal layer wiring having different loads. For example, low-potential power wiring formed of a transparent conductive layer on the back surface of a second substrate can be arranged in superimposition with data wiring and high-potential power wiring. In this case, potential differences may occur between the low-potential power wiring and the data wiring, between the low-potential power wiring and the high-potential power wiring, and between the data wiring and the high-potential power wiring. Therefore, there is a problem of parasitic capacitance occurring between the low-potential power wiring, data wiring and high-potential power wiring, and short-circuit failures may occur between the high-potential power wiring, low-potential power wiring and data wiring depending on the external environment. In particular, in the case of the back surface of the second substrate, it comes into contact with a support part that supports the second substrate during the manufacturing process of the display device. In this case, cuts may occur on the back surface of the second substrate due to contact with the support part. Specifically, when an optical film is attached to the first substrate, pressure is applied from the top of the first substrate toward the bottom of the second substrate, and the pressure may cause cuts on the back surface of the second substrate, resulting in damage such as scratches. Therefore, there is a problem in that external shocks can create a break in the connection between the low-potential power supply wiring and the data wiring, and between the low-potential power supply wiring itself.

[0251] Therefore, in the display device 100 according to one embodiment of this specification, the transparent conductive layer disposed on the back surface of the second substrate 130 can be formed with the same mask as the metal layer. For example, the third lower pad electrode BPEc, which is the lowest of the multiple pad electrodes constituting the multiple lower pads BPAD and is made of a transparent conductive layer, can be formed in the same process as the second lower pad electrode BPEb, which is made of a metal layer. Thus, the masking process can be reduced. Furthermore, multiple wirings disposed in the same layer as the second lower pad electrode BPEb can be formed using the same mask as multiple wirings disposed in the same layer as the second lower pad electrode BPEb. For example, the second lower data link wiring BDLb, disposed in the same layer as the third lower pad electrode BPEc, can be formed in the same process as the first lower data link wiring BDLa, disposed in the same layer as the second lower pad electrode BPEb. Also, the second lower auxiliary high-potential power supply wiring BAVL1b, disposed in the same layer as the third lower pad electrode BPEc, can be formed in the same process as the first lower auxiliary high-potential power supply wiring BAVL1a, disposed in the same layer as the second lower pad electrode BPEb. Therefore, the number of masks can be reduced, and manufacturing costs and time can be reduced.

[0252] Furthermore, in the display device 100 according to one embodiment of this specification, by forming the transparent conductive layer disposed on the back of the second substrate 130 with the same mask as the metal layer, only the second insulating layer 132 can be disposed below the lower data link wiring BDL. For example, the lower data link wiring BDL can include a first lower data link wiring BDLa made of a metal layer and a second lower data link wiring BDLb made of a transparent conductive layer. Therefore, the second lower data link wiring BDLb, which has the same potential as the first lower data link wiring BDLa, is disposed below the first lower data link wiring BDLa, and is cut into the back surface of the second substrate 130. This prevents the problem of short-circuit failures occurring between wirings with different loads when damage such as scratches occurs. Thus, the reliability of the display device 100 can be improved by reducing the short-circuit paths that may occur on the back surface of the second substrate 130.

[0253] The various embodiments of this specification may be described as follows.

[0254] A display device according to one embodiment of this specification includes a first substrate including a plurality of upper pads, a first substrate including a plurality of lower pads, and a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads, wherein each of the plurality of lower pads includes a first lower pad electrode disposed at the bottom of a second substrate, a first insulating layer disposed at the bottom of the first lower pad electrode, a second lower pad electrode disposed at the bottom of the first insulating layer, a third lower pad electrode disposed at the bottom of the second lower pad electrode, and a second insulating layer disposed at the bottom of the third lower pad electrode, the third lower pad electrode may be made of a transparent conductive material.

[0255] According to other features of this specification, the invention further includes a plurality of side ground wirings arranged on the sides of the first substrate and the second substrate, and each of the plurality of ground pads includes an upper ground pad arranged on the first substrate and having the same structure as the plurality of upper pads, and a lower ground pad arranged below the second substrate and having the same structure as the plurality of lower pads, and the plurality of side ground wirings can connect the upper ground pad and the lower ground pad.

[0256] According to other features of this specification, the third lower pad electrode and the second lower pad electrode can be completely superimposed.

[0257] According to other features of this specification, the first insulating layer and the second insulating layer are inorganic insulating layers, and the second insulating layer can leave a portion of the second lower pad electrode open.

[0258] According to other features of this specification, the third lower pad electrode can contact multiple side wirings.

[0259] According to other features of this specification, the second substrate includes a plurality of first lower pads located on the first edge of the second substrate and a plurality of second lower pads located on the second edge of the second substrate, wherein a high potential power supply voltage may be applied to the plurality of first lower pads and a low potential power supply voltage may be applied to the plurality of second lower pads.

[0260] According to other features of this specification, the plurality of upper pads may include a plurality of first upper pads and a plurality of second upper pads, and the plurality of side wiring may include a plurality of first side wiring connecting the plurality of first upper pads and a plurality of first lower pads, and a plurality of second side wiring connecting the plurality of second upper pads and a plurality of second lower pads.

[0261] According to other features of this specification, the second substrate further includes low-potential power supply wiring, high-potential power supply wiring, and a plurality of data wirings, the plurality of data wirings may overlap with a portion of the high-potential power supply wiring.

[0262] According to other features of this specification, the invention further includes a plurality of flexible films arranged between a high-potential power supply wiring and a low-potential power supply wiring, and a plurality of auxiliary high-potential power supply wirings arranged above the high-potential power supply wiring and in contact with the high-potential power supply wiring, each of the plurality of auxiliary high-potential power supply wirings may be arranged alternately with the plurality of flexible films.

[0263] According to other features of this specification, the high-potential power supply wiring may be made of the same material as the first lower pad electrode, and the multiple auxiliary high-potential power supply wirings may be made of the same material as the second lower pad electrode.

[0264] According to other features of this specification, the width of each of the multiple auxiliary high-potential power supply wires may increase as they are adjacent to low-potential power supply wires.

[0265] According to other features of this specification, the invention further includes a plurality of COF pads arranged on a second substrate and to which a flexible film is attached, wherein the plurality of COF pads include a first COF pad electrode, a second COF pad electrode, and a third COF pad electrode made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode, respectively, and the second COF pad electrode and the third COF pad electrode can be completely superimposed.

[0266] According to other features of this specification, the second substrate includes a plurality of first lower pads located on the first edge of the second substrate and a plurality of second lower pads located on the second edge of the second substrate, wherein high-potential power supply wiring may be located on the first edge of the second substrate and connected to the plurality of first lower pads, and low-potential power supply wiring may be located on the second edge of the second substrate and connected to the plurality of second lower pads.

[0267] According to other features of this specification, the width of the high-potential power wiring may correspond to the distance between the outermost first lower pads of a plurality of first lower pads, and the width of the low-potential power wiring may correspond to the distance between the outermost second lower pads of a plurality of second lower pads.

[0268] According to other features of this specification, the low-potential power supply wiring may consist of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode.

[0269] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. First substrate including multiple upper pads, A second substrate including multiple lower pads, and Includes a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads, Each of the aforementioned lower pads is The first lower pad electrode is located at the bottom of the second substrate. A first insulating layer disposed below the first lower pad electrode, A second lower pad electrode positioned below the first insulating layer, A third lower pad electrode positioned below the second lower pad electrode, and Includes a second insulating layer disposed below the third lower pad electrode, The third lower pad electrode is a display device made of a transparent conductive material.

2. The display device according to claim 1, wherein the third lower pad electrode and the second lower pad electrode are completely superimposed.

3. The first insulating layer and the second insulating layer are inorganic insulating layers. The display device according to claim 1, wherein the second insulating layer leaves a portion of the third lower pad electrode open.

4. The display device according to claim 3, wherein the third lower pad electrode is in contact with the plurality of side wirings.

5. The aforementioned multiple lower pads are A plurality of first lower pads arranged on the first edge of the second substrate, and The second substrate includes a plurality of second lower pads arranged on the second edge, A high-potential power supply voltage is applied to the plurality of first lower pads. The display device according to claim 1, wherein a low potential power supply voltage is applied to the plurality of second lower pads.

6. The plurality of upper pads include a plurality of first upper pads and a plurality of second upper pads, The aforementioned multiple side wirings are Multiple first side wirings connecting the multiple first upper pads and the multiple first lower pads, and The display device according to claim 5, further comprising a plurality of second side wirings connecting the plurality of second upper pads and the plurality of second lower pads.

7. The second substrate further includes low-potential power supply wiring, high-potential power supply wiring, and a plurality of data wirings, The display device according to claim 1, wherein the plurality of data lines overlap with a portion of the high-potential power supply lines.

8. A plurality of flexible films disposed between the high-potential power wiring and the low-potential power wiring, The present invention further includes a plurality of auxiliary high-potential power wirings positioned above the aforementioned high-potential power wiring and in contact with the aforementioned high-potential power wiring, The display device according to claim 7, wherein each of the plurality of auxiliary high-potential power supply wirings is arranged alternately with each of the plurality of flexible films.

9. The high-potential power supply wiring is made of the same material as the first lower pad electrode. The display device according to claim 8, wherein the plurality of auxiliary high-potential power supply wirings are made of the same material as the second lower pad electrode and the third lower pad electrode.

10. The display device according to claim 8, wherein the width of each of the plurality of auxiliary high-potential power supply wirings increases as it is adjacent to the low-potential power supply wiring.

11. The second substrate further includes a plurality of COF pads on which the flexible film is attached, The aforementioned multiple COF pads are The first COF pad electrode, the second COF pad electrode, and the third COF pad electrode are made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode, respectively. The display device according to claim 8, wherein the second COF pad electrode and the third COF pad electrode are completely superimposed.

12. The aforementioned multiple lower pads are A plurality of first lower pads arranged on the first edge of the second substrate, and Includes a plurality of second lower pads disposed on the second edge of the second substrate, The high-potential power supply wiring is arranged on the first edge of the second substrate and connected to the plurality of first lower pads. The display device according to claim 7, wherein the low-potential power supply wiring is arranged on the second edge of the second substrate and connected to the plurality of second lower pads.

13. The width of the high-potential power supply wiring corresponds to the distance between the first lower pads located on the outermost edge of the plurality of first lower pads. The display device according to claim 12, wherein the width of the low-potential power supply wiring corresponds to the distance between the second lower pads located on the outermost edge of the plurality of second lower pads.

14. The display device according to claim 13, wherein the low-potential power supply wiring is made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode.

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