Display device and method for manufacturing a display device

Abstract

It helps to suppress the decline in reliability. [Solution] According to one embodiment, a method for manufacturing a display device involves preparing a processing substrate on which a first lower electrode, a second lower electrode, and a third lower electrode are formed and an overhang-shaped partition wall is formed; using the partition wall as a mask, a first laminated film including a first organic layer, a first upper electrode, and a first cap layer is formed on the first laminated film; a first sealing layer is formed on the first laminated film, and the partition wall is covered with the first sealing layer; a first resist patterned into a predetermined shape is formed on the first sealing layer; using the first resist as a mask, the first sealing layer is patterned, a part of the partition wall surrounding the second lower electrode and the third lower electrode is exposed, a water plasma treatment is performed on the processing substrate, the first laminated film is patterned using the first resist as a mask, the second lower electrode and the third lower electrode are exposed, and the first resist is removed.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. Such a display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to the light-emitting layer. In the process of manufacturing such a display element, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0004] One of the objectives of this invention is to provide a display device and a method for manufacturing a display device that can suppress a decrease in reliability. [Means for solving the problem]

[0005] According to the embodiment, the method for manufacturing the display device is: A processing substrate is prepared in which a first lower electrode, a second lower electrode, and a third lower electrode are formed on the upper part of the substrate, and overhang-shaped partition walls are formed to surround the first lower electrode, the second lower electrode, and the third lower electrode, respectively. Using the partition walls as a mask, a first laminated film including a first organic layer, a first upper electrode, and a first cap layer is formed on the first laminated film, a first sealing layer is formed on the first laminated film, and the partition walls are covered with the first sealing layer. A first resist patterned into a predetermined shape is formed on the first sealing layer, the first resist is used as a mask to pattern the first sealing layer, a part of the partition walls surrounding the second and third lower electrodes is exposed, water plasma treatment is performed on the processing substrate, the first resist is used as a mask to pattern the first laminated film, the second and third lower electrodes are exposed, and the first resist is removed.

[0006] According to the embodiment, the display device is The device comprises a substrate, an inorganic insulating layer disposed above the substrate, a first display element configured to display a first color, a second display element configured to display a second color different from the first color, a third display element configured to display a third color different from the first and second colors, a partition wall disposed on the inorganic insulating layer, having conductivity, surrounding the first display element, the second display element, and the third display element, respectively, and formed in an overhanging manner, a first sealing layer covering the first display element, a second sealing layer covering the second display element, and a third sealing layer covering the third display element, wherein the partition wall comprises a bottom layer disposed on the inorganic insulating layer, an axial layer disposed on the bottom layer, and a top layer disposed on the axial layer, the ends of the bottom layer and the top layer each protrude from the side surface of the axial layer, and the axial layer has a cavity recessed from the side surface surrounding the second and third display elements, respectively, exposing the bottom layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX. [Figure 3] Figure 3 is a diagram illustrating an example of pixel PX. [Figure 4] Figure 4 is a schematic cross-sectional view of the DSP display device along line AB in Figure 2. [Figure 5A] Figure 5A is a diagram illustrating the manufacturing method of a display device DSP. [Figure 5B] Figure 5B is a diagram illustrating the manufacturing method of a display device DSP. [Figure 5C] Figure 5C is a diagram illustrating the manufacturing method of a display device DSP. [Figure 5D] Figure 5D is a diagram illustrating the manufacturing method of a display device DSP. [Figure 5E] Figure 5E is a diagram illustrating the manufacturing method of a display device DSP. [Figure 5F] FIG. 5F is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5G] FIG. 5G is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5H] FIG. 5H is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5I] FIG. 5I is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5J] FIG. 5J is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5K] FIG. 5K is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5L] FIG. 5L is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining the main steps of forming the display elements DE1, DE2, and DE3 on the processing substrate SUB. [Figure 7A] FIG. 7A is a diagram for explaining another manufacturing method. [Figure 7B] FIG. 7B is a diagram for explaining another manufacturing method. [Figure 7C] FIG. 7C is a diagram for explaining another manufacturing method. [Figure 7D] FIG. 7D is a diagram for explaining another manufacturing method. [Figure 7E] FIG. 7E is a diagram for explaining another manufacturing method. [Figure 8] FIG. 8 is a diagram for explaining another manufacturing method.

Embodiments for Carrying Out the Invention

[0008] Embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing various elements parallel to the third direction Z is called a plan view. In addition, terms such as "up," "above," "between," and "opposite" refer to the positional relationship between two or more constituent elements, and include not only cases where the two or more constituent elements of an object are in direct contact, but also cases where they are separated from each other by gaps or other constituent elements. The positive direction of the Z axis will be referred to as "up" or "above."

[0010] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] Figure 1 shows an example of a display device DSP.

[0012] The display device DSP includes a display panel 100. The display panel 100 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0013] At least a portion of the outer edge of the display area DA includes a rounded portion RD. In the illustrated example, the shape of the display area DA is circular in plan view. However, the shape of the display area DA in plan view is not limited to the illustrated example. For example, the outer edge of the display area DA may be a combination of a rounded portion RD and a straight portion.

[0014] The display area DA comprises a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors from each other. In one example, a pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first, second, and third colors are all different from each other. Note that a pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] Note that the rounded portion RD of the display area DA is a shape that is visible macroscopically, while microscopically it is a shape formed by the arrangement of multiple pixels PX in a stepped pattern.

[0016] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. In the illustrated example, the scan line GL and power line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0020] The display device DSP further includes a terminal section T located in the peripheral region SA. The terminal section T has multiple terminals and is electrically connected to, for example, an IC chip for driving a display element DE or a flexible circuit board.

[0021] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX.

[0022] In the illustrated example, sub-pixels SP2 and SP3 are aligned in the second direction Y, sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0023] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown.

[0024] The display area DA has an inorganic insulating layer 5 and a partition wall 6. The inorganic insulating layer 5 has apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. These inorganic insulating layers 5 with apertures AP1, AP2, and AP3 are sometimes referred to as ribs.

[0025] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a grid pattern surrounding the apertures AP1, AP2, and AP3. Similar to the inorganic insulating layer 5, the partition wall 6 can also be said to have apertures OP1, OP2, and OP3 in the sub-pixels SP1, SP2, and SP3, respectively. Aperture OP1 overlaps with aperture AP1, aperture OP2 overlaps with aperture AP2, and aperture OP3 overlaps with aperture AP3. The partition wall 6 is conductive and is electrically connected to the common voltage terminal at the terminal section T shown in Figure 1.

[0026] The sub-pixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3, respectively.

[0027] The display element DE1 of the sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, organic layer OR1, and upper electrode UE1 constituting the display element DE1 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view.

[0028] The display element DE2 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, organic layer OR2, and upper electrode UE2 constituting the display element DE2 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view.

[0029] The sub-pixel SP3 display element DE3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, organic layer OR3, and upper electrode UE3 constituting the display element DE3 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view.

[0030] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are shown with dashed lines, and the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown with dotted lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown may not accurately reflect their actual shapes.

[0031] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode and are in contact with the partition wall 6.

[0032] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0033] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different from each other. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. Note that the relative sizes of the areas of opening AP1, opening AP2, and opening AP3 are not limited to the illustrated example.

[0034] Figure 3 is a diagram illustrating an example of pixel PX.

[0035] In the sub-pixel SP1, the display element DE1 comprises a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, which includes the light-emitting layer EM1, is positioned between the lower electrode LE1 and the upper electrode UE1. The cap layer CP1 is positioned on top of the upper electrode UE1. The sealing layer SE11 is positioned on top of the cap layer CP1 and covers the display element DE1.

[0036] In the sub-pixel SP2, the display element DE2 comprises a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a cap layer CP2. The organic layer OR2, which includes the light-emitting layer EM2, is positioned between the lower electrode LE2 and the upper electrode UE2. The cap layer CP2 is positioned on top of the upper electrode UE2. The sealing layer SE12 is positioned on top of the cap layer CP2 and covers the display element DE2.

[0037] In the sub-pixel SP3, the display element DE3 comprises a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a cap layer CP3. The organic layer OR3, which includes the light-emitting layer EM3, is positioned between the lower electrode LE3 and the upper electrode UE3. The cap layer CP3 is positioned on top of the upper electrode UE3. The sealing layer SE13 is positioned on top of the cap layer CP3 and covers the display element DE3.

[0038] In the following explanation, a multilayer including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 may be referred to as multilayer film FL1, a multilayer including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 may be referred to as multilayer film FL2, and a multilayer including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 may be referred to as multilayer film FL3.

[0039] The light-emitting layers EM1, EM2, and EM3 are made of different materials. In one example, light-emitting layer EM1 is made of a material that emits light in the blue wavelength range, light-emitting layer EM2 is made of a material that emits light in the green wavelength range, and light-emitting layer EM3 is made of a material that emits light in the red wavelength range. In other words, display element DE1 is configured to display blue as the first color, display element DE2 is configured to display green as the second color, and display element DE3 is configured to display red as the third color.

[0040] Furthermore, the light-emitting layer EM1 may be formed from a material that emits light in the green wavelength range, and the light-emitting layer EM2 may be formed from a material that emits light in the blue wavelength range. In other words, the display element DE1 may be configured to display green as the first color, and the display element DE2 may be configured to display blue as the second color.

[0041] Figure 4 is a schematic cross-sectional view of the DSP display device along line AB in Figure 2.

[0042] The circuit layer 11 is placed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, various wirings such as scan lines GL, signal lines SL, and power lines PL, and various insulating layers.

[0043] The organic insulating layer 12 is placed on top of the circuit layer 11. The organic insulating layer 12 is formed, for example, to flatten the irregularities caused by the circuit layer 11.

[0044] The lower electrode LE1 of sub-pixel SP1, LE2 of sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 are arranged on the organic insulating layer 12 and spaced apart from each other.

[0045] The inorganic insulating layer 5 is placed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The aperture AP1 of the inorganic insulating layer 5 overlaps the lower electrode LE1, the aperture AP2 overlaps the lower electrode LE2, and the aperture AP3 overlaps the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the organic insulating layer 12. Note that the contact holes of the organic insulating layer 12 are not shown in the illustration.

[0046] The partition wall 6 is formed in an overhang shape and comprises a conductive lower part 61 placed on the inorganic insulating layer 5 and an upper part 62 placed on the lower part 61.

[0047] In the illustrated example, the lower part 61 comprises a bottom layer 63 placed on top of the inorganic insulating layer 5, and an axial layer 64 placed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a greater width than the axial layer 64. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0048] The upper part 62 comprises a top layer 65 positioned on the axial layer 64 and a cover layer 66 positioned on the top layer 65. The top layer 65 and the cover layer 66 have a greater width than the axial layer 64. Both ends of the top layer 65 and the cover layer 66 protrude from the sides of the axial layer 64. In this specification, the side of the axial layer 64 refers to the surface of the axial layer 64 that extends between the bottom layer 63 and the top layer 65. In the illustrated example, the upper part 62 has a greater width than the bottom layer 63. The bottom layer 63 may also have a greater width than the upper part 62.

[0049] In the display element DE1, the organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0050] In the display element DE2, the organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0051] In the display element DE3, the organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0052] Furthermore, contact between each of the upper electrodes UE1, UE2, and UE3 and the lower part 61 includes the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63, and the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper part 62.

[0053] Cap layer CP1 is placed on top of upper electrode UE1. Cap layer CP2 is placed on top of upper electrode UE2. Cap layer CP3 is placed on top of upper electrode UE3. Cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the efficiency of light extraction from organic layers OR1, OR2, and OR3, respectively. Note that cap layers CP1, CP2, and CP3 may be omitted.

[0054] The sealing layer SE11 is positioned on top of the cap layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE11 is in contact with the axial layer 64 and upper layer 62 of the partition wall 6 surrounding the display element DE1.

[0055] The sealing layer SE12 is positioned on top of the cap layer CP2, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE12 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE2.

[0056] The sealing layer SE13 is positioned on top of the cap layer CP3, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP3. The sealing layer SE13 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE3.

[0057] The sealing layers SE11, S12, and SE13 each extend above the partition wall 6. Furthermore, the edges of the sealing layers SE11, SE12, and SE13 are located above the partition wall 6.

[0058] None of the laminated films FL1, FL2, and FL3 are located on the partition wall 6. Cavities GP are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6, respectively.

[0059] The transparent resin layer RS1 covers the partition wall 6 and the sealing layers SE11, SE12, and SE13. The resin layer RS1 also fills the cavities GP formed between sealing layer SE11 and partition wall 6, between sealing layer SE12 and partition wall 6, and between sealing layer SE13 and partition wall 6.

[0060] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 is placed on top of the sealing layer SE2.

[0061] The inorganic insulating layer 5, sealing layers SE11, SE12, SE13, and sealing layer SE2 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). In one example, the inorganic insulating layer 5 is formed from silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride.

[0062] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is made of a titanium-based material, such as titanium or a titanium compound. The bottom layer 63 may also be made of an oxide conductive material, such as indium tin oxide (ITO). The axial layer 64 is made of a different material from the bottom layer 63 and the top layer 65, and is made of an aluminum-based material, such as aluminum or an aluminum compound.

[0063] The upper part 62 of the partition wall 6 is formed of a conductive material, for example, but may also be formed of an insulating material. In the illustrated example, the upper part 62 is formed as a multilayer of a top layer 65 and a cover layer 66, both of which are made of conductive material. The top layer 65 is made of a titanium-based material, such as titanium or a titanium compound. The cover layer 66 is made of a different material from the top layer 65, such as an oxide conductive material like ITO.

[0064] The lower electrodes LE1, LE2, and LE3 are multilayer structures, for example, comprising an oxide conductive layer and a metal layer. The oxide conductive layer is formed from an oxide conductive material such as ITO. The metal layer is formed from a metallic material such as silver and functions as a reflective layer. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures containing a metal layer between a pair of oxide conductive layers.

[0065] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Furthermore, each of organic layers OR1, OR2, and OR3 includes multiple functional layers such as hole injection layers, hole transport layers, electron blocking layers, hole blocking layers, electron transport layers, and electron injection layers.

[0066] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0067] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0068] The illustrated circuit layer 11, organic insulating layer 12, inorganic insulating layer 5, and partition wall 6 are arranged across the display area DA and the surrounding area SA.

[0069] Next, the manufacturing method of the display device DSP will be described. Figures 5A to 5L are cross-sectional views of the processing substrate SUB along the AB line in Figure 2, with elements below the organic insulating layer 12 omitted.

[0070] First, a processing substrate SUB is prepared as shown in Figure 5A. The process of preparing the processing substrate SUB includes the steps of forming the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 on the organic insulating layer 12, forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap the lower electrodes LE1, LE2, and LE3, respectively, and forming overhang-shaped partition walls 6 that surround the lower electrodes LE1, LE2, and LE3 and are located on the inorganic insulating layer 5. Note that the partition walls 6 may be formed after the inorganic insulating layer 5 having openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed on the inorganic insulating layer 5 after the partition walls 6 is formed.

[0071] The process of forming the lower electrodes LE1, LE2, and LE3 includes the steps of forming an oxide conductive layer LEa located on the organic insulating layer 12, forming a metal layer LEb located on the oxide conductive layer LEa, and forming the respective LEc of the lower electrodes LE1, LE2, and LE3. For example, the lower electrodes LE1, LE2, and LE3 are formed by first forming a laminate of the oxide conductive layer LEa, the metal layer LEb, and the oxide conductive layer LEc, and then patterning them all together.

[0072] The process of forming the partition wall 6 includes the steps of forming a bottom layer 63 located on the inorganic insulating layer 5 from a conductive material, forming an axial layer 64 located on the bottom layer 63 from an aluminum-based material, forming a top layer 65 located on the axial layer 64 from a titanium-based material, and forming a cover layer 66 located on the top layer 65 from an oxide conductive material. The bottom layer 63 is formed from, for example, a titanium-based material, but may also be formed from an oxide conductive material. According to this process of forming the partition wall 6, the bottom layer 63, the top layer 65, and the cover layer 66 are all formed to protrude from the side surface of the axial layer 64.

[0073] Next, the display element DE1 is formed.

[0074] First, as shown in Figure 5B, deposition is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. The laminated film FL1 is formed on the lower electrodes LE1, LE2, and LE3, as well as on the partition wall 6. The laminated film FL1 includes an organic layer OR1 containing an emissive layer EM1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed continuously in a vacuum environment in the deposition apparatus.

[0075] The multilayer film FL1 is divided by an overhanging partition wall 6. In other words, in the multilayer film FL1, the portions located above the lower electrodes LE1, LE2, and LE3 are separated from the portions located above the partition wall 6.

[0076] Next, as shown in Figure 5C, a sealing layer SE11 is formed on the laminated film FL1. The sealing layer SE11 is formed to continuously cover the laminated film FL1 and the partition wall 6. The sealing layer SE11 is formed by depositing an inorganic insulating material (e.g., silicon nitride) on the processing substrate SUB in a CVD (Chemical Vapor Deposition) apparatus.

[0077] The laminated film FL1 and the sealing layer SE11 are formed over almost the entire surface of the processing substrate SUB, and in the display area DA, they are located not only on the sub-pixel SP1 but also on the sub-pixels SP2 and SP3.

[0078] Next, as shown in Figure 5D, a resist R1 patterned to a predetermined shape is formed on the sealing layer SE11. The resist R1 overlaps the subpixel SP1 and a portion of the surrounding partition wall 6.

[0079] Next, as shown in Figure 5E, the sealing layer SE11 is patterned using the resist R1 as a mask. For example, by performing dry etching, the sealing layer SE11 exposed from the resist R1 is removed. As a result, the laminated film FL1 overlapping the lower electrode LE2 and the laminated film FL1 overlapping the lower electrode LE3 are exposed, as well as a portion of the laminated film FL1 on the partition wall 6. Furthermore, a portion of the partition wall 6 surrounding the lower electrode LE2 and a portion of the partition wall 6 surrounding the lower electrode LE3 are also exposed.

[0080] Here, the multilayer film FL1 covers the bottom layer 63 at the partition wall 6 and covers the first portion 641 of the side surface of the axial layer 64 that connects to the bottom layer 63. In the illustrated example, the first portion 641 is covered by the upper electrode UE1 of the multilayer film FL1. The multilayer film FL1 also exposes the second portion 642 of the side surface of the axial layer 64 that connects to the top layer 65, and the lower surface 651 of the top layer 65 that protrudes from the axial layer 64. The second portion 642 and the lower surface 651 are covered by the sealing layer SE11 before the dry etching shown in Figure 5E.

[0081] Next, as shown in Figure 5F, the substrate SUB is subjected to water plasma treatment. This type of water plasma treatment has a high ability to remove organic matter and a high ability to oxidize conductive materials. Therefore, the reaction products and resist R1 fragments that adhere to the substrate SUB in the dry etching shown in Figure 5E are decomposed and removed by the water plasma treatment. As a result, the entire surface of the substrate SUB is cleaned. In addition, by performing the water plasma treatment, a portion of the axial layer 64, which is made of a metallic material, is oxidized, and an aluminum oxide film 64A is formed as an oxide film on the side surface of the axial layer 64. Furthermore, by performing the water plasma treatment, a portion of the top layer 65, which is made of a metallic material, is oxidized, and a titanium oxide film 65A is formed as an oxide film on the underside of the top layer 65.

[0082] In the illustrated example, an aluminum oxide film 64A is formed on the entire side surface of the axial layer 64 of the partition wall 6 surrounding the lower electrodes LE2 and LE3, i.e., the entire region between the bottom layer 63 and the top layer 65. In other words, both the first portion 641 and the second portion 642, as explained with reference to Figure 5E, are oxidized, and an aluminum oxide film 64A is formed on the first portion 641 and the second portion 642. At this time, the portion of the bottom layer 63 that protrudes from the side surface of the axial layer 64 is covered with the laminated film FL1 and is not oxidized during the water plasma treatment.

[0083] Next, as shown in Figure 5G, the cap layer CP1 of the multilayer film FL1 is patterned using the resist R1 as a mask. This removes the cap layer CP1 exposed from the resist R1, exposing the upper electrode UE1. If the cap layer CP1 includes an organic layer, at least a portion of the cap layer CP1 may be removed by the water plasma treatment shown in Figure 5F.

[0084] Next, as shown in Figure 5H, the upper electrode UE1 of the multilayer film FL1 is patterned using the resist R1 as a mask. This removes the upper electrode UE1 exposed from the resist R1, exposing the organic layer OR1. In the wet etching process to remove the upper electrode UE1, the aluminum oxide film 64A acts as an etching stopper, suppressing erosion of the axial layer 64 by the etching solution. Similarly, the titanium oxide film 65A also acts as an etching stopper, suppressing erosion of the top layer 65 by the etching solution.

[0085] Next, as shown in Figure 5I, the organic layer OR1 of the multilayer film FL1 is patterned using the resist R1 as a mask. This removes the organic layer OR1 that has been exposed from the resist R1. As a result, a portion of the partition wall 6, the lower electrode LE2, and the lower electrode LE3 are exposed.

[0086] Next, as shown in Figure 5J, the resist R1 is removed. The step of removing the resist R1 includes, for example, a step of removing the resist R1 with a stripping solution and a step of washing the processed substrate SUB with water. As a result, the display element DE1 is formed on the sub-pixel SP1. In addition, the laminated film FL1 remaining between the partition wall 6 and the sealing layer SE11 is removed during the process from patterning the laminated film FL1 to the removal of the resist R1. Therefore, a cavity GP is formed between the partition wall 6 and the sealing layer SE11. Furthermore, the aluminum oxide film 64A and the titanium oxide film 65A function as etching stoppers against the alkaline solution generated in the resist R1 removal step, protecting the axial layer 64 and the top layer 65.

[0087] Next, as shown in Figure 5K, the display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1, and therefore, detailed illustrations are omitted. Specifically, a multilayer film FL2 is formed on the lower electrode LE2. The multilayer film FL2 includes an organic layer OR2 containing an emissive layer EM2, an upper electrode UE2, and a cap layer CP2. Then, a sealing layer SE12 is formed on the multilayer film FL2. Then, a resist R2 is formed on the sealing layer SE12. Then, the sealing layer SE12 and the multilayer film FL2 are patterned using this resist R2 as a mask. As a result, after the sealing layer SE12 exposed from the resist R2 is removed, the cap layer CP2, upper electrode UE2, and organic layer OR2 of the multilayer film FL2 are sequentially removed. Finally, the resist R2 is removed.

[0088] As a result, the display element DE2 is formed on the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed. In addition, the laminated film FL2 formed between the partition wall 6 and the sealing layer SE12 is removed during the process from patterning of the laminated film FL2 to removal of the resist R2. Therefore, a cavity GP is formed between the partition wall 6 and the sealing layer SE12.

[0089] In the display element DE2, an aluminum oxide film 64A is formed on the side surface of the axial layer 64, and a titanium oxide film 65A is formed on the lower surface of the top layer 65 that protrudes from the side surface of the axial layer 64. The sealing layer SE12 is in contact with the aluminum oxide film 64A and also in contact with the titanium oxide film 65A.

[0090] Next, as shown in Figure 5L, the display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1, and detailed illustrations are omitted. Specifically, a multilayer film FL3 is formed on the lower electrode LE3. The multilayer film FL3 includes an organic layer OR3 containing an emissive layer EM3, an upper electrode UE3, and a cap layer CP3. Then, a sealing layer SE13 is formed on the multilayer film FL3. Next, a resist R3 is formed on the sealing layer SE13. Then, the sealing layer SE12 and the multilayer film FL2 are patterned using this resist R3 as a mask. As a result, after the sealing layer SE13 exposed from the resist R3 is removed, the cap layer CP3, upper electrode UE3, and organic layer OR3 of the multilayer film FL3 are sequentially removed. Finally, the resist R3 is removed.

[0091] As a result, the display element DE3 is formed on the sub-pixel SP3. In addition, the laminated film FL3 formed between the partition wall 6 and the sealing layer SE13 is removed during the process from patterning the laminated film FL3 to removing the resist R3. Therefore, a cavity GP is formed between the partition wall 6 and the sealing layer SE13.

[0092] In the display element DE3, an aluminum oxide film 64A is formed on the side surface of the axial layer 64, and a titanium oxide film 65A is formed on the lower surface of the top layer 65 that protrudes from the side surface of the axial layer 64. The sealing layer SE13 is in contact with the aluminum oxide film 64A and also in contact with the titanium oxide film 65A.

[0093] In the above manufacturing process, we assumed that the display element DE1 is formed first, then the display element DE2, and finally the display element DE3. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0094] Figure 6 is a diagram illustrating the main steps for forming the display elements DE1, DE2, and DE3 on the processing substrate SUB.

[0095] First, a multilayer film FL1 is formed on the lower electrodes LE1, LE2, LE3 and the partition wall 6 by vapor deposition using the partition wall 6 as a mask (step ST11). Then, a sealing layer SE11 is formed on the multilayer film FL1 (step ST12). Next, a resist R1 is formed on the sealing layer SE11 (step ST13). Finally, the sealing layer SE11 is patterned using the resist R1 as a mask (step ST14).

[0096] Subsequently, the processing substrate SUB is subjected to water plasma treatment (step ST15).

[0097] Next, the patterning of the multilayer film FL1 is performed using the resist R1 as a mask. First, the cap layer CP1 is patterned (step ST16). Then, the upper electrode UE1 is patterned (step ST17). After that, the organic layer OR1 is patterned (step ST18). Finally, the resist R1 is removed (step ST19). This forms the display element DE1.

[0098] Next, the sealing layer SE11 of the display element DE1, the lower electrodes LE2 and LE3, and the multilayer film FL2 on the sealing layer SE11, lower electrodes LE2 and LE3, and the sealing layer FL2 are formed on the sealing layer SE12 by vapor deposition using the partition wall 6 as a mask (step ST21). Subsequently, the sealing layer SE12 is formed on the multilayer film FL2 (step ST22). Then, the resist R2 is formed on the sealing layer SE12 (step ST23). Finally, the sealing layer SE12 is patterned using the resist R2 as a mask (step ST24).

[0099] Subsequently, the processed substrate SUB is subjected to water plasma treatment (step ST25). However, if oxide films 64A and 65A of sufficient thickness have been formed by the water plasma treatment performed in step ST15, the water plasma treatment in step ST25 may be omitted.

[0100] Next, the patterning of the multilayer film FL2 is performed using the resist R2 as a mask. First, the cap layer CP2 is patterned (step ST26). Then, the upper electrode UE2 is patterned (step ST27). After that, the organic layer OR2 is patterned (step ST28). Finally, the resist R2 is removed (step ST29). This forms the display element DE2.

[0101] Next, the sealing layer SE11 for the display element DE1, the sealing layer SE21 for the display element DE2, the lower electrode LE3, and the multilayer film FL3 are formed on the partition wall 6 by vapor deposition using the partition wall 6 as a mask (step ST31). Subsequently, the sealing layer SE13 is formed on the multilayer film FL3 (step ST32). Then, the resist R3 is formed on the sealing layer SE13 (step ST33). Finally, the sealing layer SE13 is patterned using the resist R3 as a mask (step ST34).

[0102] Subsequently, without performing water plasma treatment on the processing substrate SUB, the patterning of the multilayer film FL3 is carried out using the resist R3 as a mask. First, the cap layer CP3 is patterned (step ST35). Then, the upper electrode UE3 is patterned (step ST36). After that, the organic layer OR3 is patterned (step ST37). Finally, the resist R3 is removed (step ST38). This forms the display element DE3.

[0103] Subsequently, an organic insulating material is applied to the sealing layers SE11, SE12, and SE13, and the organic insulating material is cured to form the resin layer RS1 shown in Figure 4. At this time, the applied organic insulating material fills the cavities GP formed between the partition wall 6 and the sealing layer SE11, between the partition wall 6 and the sealing layer SE12, and between the partition wall 6 and the sealing layer SE13, respectively.

[0104] Next, an inorganic insulating material (e.g., silicon nitride) is deposited to form a sealing layer SE2. Then, an organic insulating material is applied and cured to form a resin layer RS2.

[0105] After the above steps, the DSP display device is completed.

[0106] As described above, in the process of forming the display element DE1, water plasma treatment is performed after patterning the sealing layer SE11 but before patterning the upper electrode UE1. This removes unwanted reaction products adhering to the side surface of the axial layer 64 and forms an oxide film on the side surface of the axial layer 64. As a result, in subsequent patterning and resist removal processes, the oxide film suppresses erosion of the axial layer 64, and the partition wall 6 can be maintained in the desired shape. Therefore, it is possible to prevent light emission defects of the display element caused by instability in the shape of the partition wall 6, and a decrease in reliability is suppressed.

[0107] Furthermore, the sealing layers SE11, SE12, and SE13 securely seal the display elements DE1, DE2, and DE3, respectively. This prevents moisture from entering the display elements.

[0108] Furthermore, during the formation of the oxide film by water plasma treatment, oxidation of the bottom layer 63 is suppressed, and the bottom layer 63 and the upper electrodes UE2 and UE3 can be reliably electrically connected.

[0109] Next, other manufacturing methods will be described. Note that in the manufacturing methods described below, steps that overlap with the manufacturing methods described above may be omitted.

[0110] First, a processing substrate SUB is prepared as shown in Figure 5A. Then, a multilayer film FL1 is formed as shown in Figure 5B. Next, a sealing layer SE11 is formed as shown in Figure 5C. Then, a resist R1 is formed as shown in Figure 5D. Finally, the sealing layer SE11 is patterned as shown in Figure 5E. At this time, the multilayer film FL1 covers the bottom layer 63 and the first portion 641 of the axial layer 64. The multilayer film FL1 also exposes the second portion 642 of the axial layer 64 and the lower surface 651 of the top layer 65 that protrudes from the axial layer 64.

[0111] Next, as shown in Figure 7A, the processing substrate SUB is subjected to water plasma treatment. This water plasma treatment causes an aluminum oxide film 64A to form as an oxide film on the second portion 642 of the axial layer 64 of the partition wall 6 surrounding the lower electrodes LE2 and LE3, respectively. In addition, a titanium oxide film 65A is formed as an oxide film on the lower surface protruding from the side of the axial layer 64 in the top layer 65.

[0112] On the other hand, the first portion 641 covered with the multilayer film FL1 is not oxidized. In the water plasma treatment shown here, the area in which the axial layer 64 is oxidized is smaller compared to the water plasma treatment shown in Figure 5F. The area in which the axial layer 64 is oxidized can be controlled by adjusting the treatment conditions such as treatment time and pulse power.

[0113] Next, as shown in Figure 7B, using the resist R1 as a mask, the patterning of the cap layer CP1 of the multilayer film FL1 is performed, followed by the patterning of the upper electrode UE1. The upper electrode UE1 exposed from the resist R1 is removed, and the first portion 641 of the partition wall 6 surrounding the lower electrodes LE2 and LE3 is removed, forming a cavity 64B in the axial layer 64. Furthermore, the bottom layer 63 is exposed in the cavity 64B. The aluminum oxide film 64A and the titanium oxide film 65A remain.

[0114] Next, as shown in Figure 7C, the organic layer OR1 of the multilayer film FL1 is patterned using the resist R1 as a mask. This removes the organic layer OR1 that is exposed from the resist R1. As a result, a portion of the partition wall 6, the lower electrode LE2, and the lower electrode LE3 are exposed.

[0115] Next, as shown in Figure 7D, the resist R1 is removed. This forms the display element DE1 on the sub-pixel SP1. The laminated film FL1 remaining between the partition wall 6 and the sealing layer SE11 is removed during the process from patterning the laminated film FL1 to removing the resist R1. As a result, a cavity GP is formed between the partition wall 6 and the sealing layer SE11. In addition, the portion of the axial layer 64 not covered by the aluminum oxide film 64A is dissolved by the alkaline solution generated during the resist R1 removal process. As a result, the cavity 64B is expanded.

[0116] Next, as shown in Figure 7E, after forming the display element DE2, the display element DE3 is formed.

[0117] In the display element DE2, the aluminum oxide film 64A formed on the side surface of the axial layer 64 and the titanium oxide film 65A formed on the lower surface of the top layer 65 are in contact with the sealing layer SE12.

[0118] Focusing on the partition wall 6 located between display element DE1 and display element DE2, the axial layer 64 has a cavity 64B that is recessed relative to the side surface surrounding display element DE2. In the cavity 64B, the bottom layer 63 is exposed. On the other hand, the axial layer 64 does not have a recessed cavity relative to the side surface surrounding display element DE1.

[0119] The upper electrode UE2 extends into the cavity 64B and is in contact with the bottom layer 63. The upper electrode UE2 is not in contact with the side surface of the axial layer 64. On the other hand, the upper electrode UE1 is in contact with the bottom layer 63, which protrudes from the axial layer 64. The contact area between the upper electrode UE2 and the bottom layer 63 is larger than the contact area between the upper electrode UE1 and the bottom layer 63.

[0120] In the display element DE3, the aluminum oxide film 64A formed on the side surface of the axial layer 64 and the titanium oxide film 65A formed on the lower surface of the top layer 65 are in contact with the sealing layer SE13.

[0121] Focusing on the partition wall 6 located between display element DE1 and display element DE3, the axial layer 64 has a cavity 64B that is recessed relative to the side surface surrounding display element DE3. In the cavity 64B, the bottom layer 63 is exposed. On the other hand, the axial layer 64 does not have a recessed cavity relative to the side surface surrounding display element DE1.

[0122] The upper electrode UE3 extends into the cavity 64B and is in contact with the bottom layer 63. The upper electrode UE3 is not in contact with the side surface of the axial layer 64. On the other hand, the upper electrode UE1 is in contact with the bottom layer 63, which protrudes from the axial layer 64. The contact area between the upper electrode UE3 and the bottom layer 63 is larger than the contact area between the upper electrode UE1 and the bottom layer 63.

[0123] This reduces the connection resistance between the upper electrode UE2 of the display element DE2, which is formed after the display element DE1, and the partition wall 6, and also reduces the connection resistance between the upper electrode UE3 of the display element DE3 and the partition wall 6.

[0124] Furthermore, in order to reduce damage to the bottom layer 63 that is exposed between the patterning of the multilayer film FL1 and the removal of the resist R1, the bottom layer 63 may be formed of an oxide conductive material such as ITO.

[0125] In the manufacturing methods described with reference to Figures 5A to 5L and Figures 7A to 7E, water plasma treatment may be added after patterning the upper electrode UE1 but before patterning the organic layer OR1. Alternatively, water plasma treatment may be added after patterning the organic layer OR1 but before forming the laminated film FL2.

[0126] In the example shown in Figure 8, water plasma treatment is added after patterning the organic layer OR1 (i.e., after patterning the multilayer film FL1) and before removing the resist R1. This water plasma treatment oxidizes the oxide conductive layer located on the surface of the lower electrodes LE2 and LE3, and the cover layer (oxide conductive layer) 66 of the partition wall 6, and also promotes crystallization. As a result, the hole injection efficiency from the lower electrodes LE2 and LE3 is improved in the display elements DE2 and DE3. In addition, the strength of the upper part 62 of the partition wall 6 can be improved.

[0127] In the above embodiment, for example, display element DE1 corresponds to the first display element, display element DE2 corresponds to the second display element, and display element DE3 corresponds to the third display element.

[0128] Lower electrode LE1 corresponds to the first lower electrode, lower electrode LE2 corresponds to the second lower electrode, and lower electrode LE3 corresponds to the third lower electrode. Organic layer OR1 corresponds to the first organic layer, organic layer OR2 corresponds to the second organic layer, organic layer OR3 corresponds to the third organic layer, light-emitting layer EM1 corresponds to the first light-emitting layer, light-emitting layer EM2 corresponds to the second light-emitting layer, and light-emitting layer EM3 corresponds to the third light-emitting layer. Upper electrode UE1 corresponds to the first upper electrode, upper electrode UE2 corresponds to the second upper electrode, and upper electrode UE3 corresponds to the third upper electrode. Cap layer CP1 corresponds to the first cap layer, cap layer CP2 corresponds to the second cap layer, and cap layer CP3 corresponds to the third cap layer.

[0129] The multilayer film FL1 corresponds to the first multilayer film, the multilayer film FL2 corresponds to the second multilayer film, and the multilayer film FL3 corresponds to the third multilayer film. The encapsulation layer SE11 corresponds to the first encapsulation layer, the encapsulation layer SE12 corresponds to the second encapsulation layer, and the encapsulation layer SE13 corresponds to the third encapsulation layer. The resist R1 corresponds to the first resist, the resist R2 corresponds to the second resist, and the resist R3 corresponds to the third resist.

[0130] As described above, according to this embodiment, it is possible to provide a display device and a method for manufacturing a display device that can suppress a decrease in reliability.

[0131] All display devices and manufacturing methods thereof that a person skilled in the art can implement by appropriately modifying the design based on the display devices and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0132] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0133] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0134] DSP…display device DA…display area DE1, DE2, DE3... Display elements LE1, LE2, LE3…lower electrode OR1, OR2, OR3…Organic layer UE1, UE2, UE3...upper electrode CP1, CP2, CP3...cap layers SE11, SE12, SE13, SE2...Sealing layer RS1, RS2…Resin layer 5…Inorganic insulating layer 12…Organic insulating layer 6...Battal 61...Lower part 62...Upper part 63...Bottom layer 64...Axial layer 65...Top layer 66...Cover layer FL1, FL2, FL3… Multilayer film

Claims

1. A processing substrate is prepared in which a first lower electrode, a second lower electrode, and a third lower electrode are formed on the upper part of the substrate, and overhang-shaped partition walls are formed to surround the first lower electrode, the second lower electrode, and the third lower electrode, respectively. Using the partition wall as a mask, a first laminated film including a first organic layer, a first upper electrode, and a first cap layer is formed on the first lower electrode, the second lower electrode, and the third lower electrode. A first sealing layer is formed on the first laminated film, and the partition wall is covered with the first sealing layer. A first resist patterned in a predetermined shape is formed on the first sealing layer. Using the first resist as a mask, the first sealing layer is patterned, and a portion of the partition wall surrounding the second lower electrode and the third lower electrode is exposed. The aforementioned processing substrate is subjected to water plasma treatment. Using the first resist as a mask, the first multilayer film is patterned to expose the second and third lower electrodes. Remove the first resist, A method for manufacturing a display device.

2. The step of forming the partition wall includes the step of forming an axial layer with an aluminum-based material. The water plasma treatment forms an aluminum oxide film on the side surface of the axial layer. A method for manufacturing a display device according to claim 1.

3. The step of forming the partition wall includes the step of forming a top layer with a titanium-based material. The top layer is located above the axial layer and has a lower surface that protrudes from the side surface of the axial layer. The water plasma treatment forms a titanium oxide film on the lower surface. A method for manufacturing a display device according to claim 2.

4. The step of preparing the processing substrate includes forming the first lower electrode, the second lower electrode, and the third lower electrode, and then forming an inorganic insulating layer having openings that overlap the first lower electrode, the second lower electrode, and the third lower electrode, respectively. The step of forming the partition wall includes the steps of forming a bottom layer located on the inorganic insulating layer, forming an axial layer located on the bottom layer, and forming a top layer located on the axial layer, wherein the bottom layer and the top layer are formed to protrude from the side surface of the axial layer. A method for manufacturing a display device according to claim 1.

5. The water plasma treatment forms an oxide film on the entire surface of the side surfaces of the partition walls surrounding the second and third lower electrodes, respectively. A method for manufacturing a display device according to claim 4.

6. The first laminated film covers the bottom layer and covers the first portion of the side surface of the axial layer that is connected to the bottom layer, while exposing the second portion of the side surface of the axial layer that is connected to the top layer. The water plasma treatment forms an oxide film on the second portion of the partition wall surrounding the second lower electrode and the third lower electrode, respectively. A method for manufacturing a display device according to claim 4.

7. The step of patterning the first multilayer film includes the step of removing the first upper electrode exposed from the first resist, In the step of removing the first upper electrode, the first portion of the partition wall surrounding the second lower electrode and the third lower electrode is removed, a cavity is formed in the axial layer, and the bottom layer is exposed in the cavity. A method for manufacturing a display device according to claim 6.

8. In the step of removing the first resist, the cavity is expanded. A method for manufacturing a display device according to claim 7.

9. The bottom layer is formed of an oxide conductive material. A method for manufacturing a display device according to claim 4.

10. The steps for forming the first lower electrode, the second lower electrode, and the third lower electrode include the step of forming an oxide conductive layer located on each of their surfaces. Furthermore, the process includes a step of performing water plasma treatment after patterning the first laminated film, A method for manufacturing a display device according to claim 1.

11. Furthermore, the process includes forming a second laminated film located on the second lower electrode, comprising a second organic layer, a second upper electrode, and a second cap layer, and a second sealing layer located on the second laminated film. After patterning the second sealing layer, the processed substrate is subjected to a water plasma treatment. A method for manufacturing a display device according to claim 1.

12. Furthermore, the process includes forming a third multilayer film located on the third lower electrode, which includes a third organic layer, a third upper electrode, and a third cap layer, and a third sealing layer located on the third multilayer film. After patterning the third sealing layer, the third laminated film is patterned without performing a water plasma treatment on the processing substrate. A method for manufacturing a display device according to claim 11.

13. circuit board and An inorganic insulating layer disposed above the substrate, A first display element configured to display a first color, A second display element configured to display a second color different from the first color, A third display element configured to display a third color different from the first and second colors, Displaced on the inorganic insulating layer, conductive, and surrounding the first display element, the second display element, and the third display element, respectively, a partition wall formed in an overhanging manner, A first sealing layer covering the first display element, A second sealing layer covering the second display element, The device comprises a third sealing layer covering the third display element, The partition wall comprises a bottom layer disposed on the inorganic insulating layer, an axial layer disposed on the bottom layer, and a top layer disposed on the axial layer. Both ends of the bottom layer and the top layer protrude from the side surface of the axial layer, The axial layer has a cavity that is recessed in the side surface surrounding the second and third display elements, respectively, exposing the bottom layer. Display device.

14. The axial layer does not have a recessed cavity relative to the side surface surrounding the first display element. The display device according to claim 13.

15. The second display element includes a second upper electrode electrically connected to the partition wall, The third display element comprises a third upper electrode electrically connected to the partition wall, Each of the second upper electrode and the third upper electrode extends into the cavity. The display device according to claim 13.

16. The first display element includes a first upper electrode electrically connected to the partition wall, The second display element includes a second upper electrode electrically connected to the partition wall, The contact area between the second upper electrode and the bottom layer is larger than the contact area between the first upper electrode and the bottom layer. The display device according to claim 13.

17. The third display element comprises a third upper electrode electrically connected to the partition wall, The contact area between the third upper electrode and the bottom layer is larger than the contact area between the first upper electrode and the bottom layer. The display device according to claim 16.

18. The axial layer is formed of an aluminum-based material and has an aluminum oxide film on the side surfaces surrounding the second display element and the third display element, respectively. The display device according to claim 13.

19. The top layer is formed of a titanium-based material and has a titanium oxide film on the lower surface protruding from the side surface of the axial layer. The display device according to claim 18.

20. Each of the second sealing layer and the third sealing layer is in contact with the aluminum oxide film and the titanium oxide film. The display device according to claim 19.

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