Information processing device and control method

Abstract

Reduce power consumption. [Solution] The information processing device comprises a memory drive device for storing data used for information processing, a main control unit for executing the information processing, which is connected to the memory drive device by a first interface for sending and receiving the data used for the information processing, and a sub-control unit which operates independently of the main control unit and is connected to the memory drive device by a second interface for managing the state of the memory drive device, the memory drive device comprises a drive control unit that can change the first interface and the second interface from a communicable active state to a non-communicable inactive state, and a release processing unit that, in response to a request from the main control unit or the sub-control unit, releases the inactive state of the first interface and the inactive state of the second interface and changes them back to the active state.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus and a control method.

Background Art

[0002] In recent years, information processing apparatuses such as personal computers (PCs) equipped with solid state drives (SSDs) have become widespread. Among such information processing apparatuses, those using a PCIe (Peripheral Component Interconnect-Express) bus for connecting an SSD are known in order to speed up data transfer (see, for example, Patent Document 1). In addition, among such information processing apparatuses, in addition to the PCIe bus, for example, an interface for system management such as an SMBus (System Management Bus) is connected to the SSD in some cases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional information processing apparatuses as described above, for example, since two interfaces, namely, a PCIe bus and an SMBus, are used to control the SSD, there is a problem that power consumption increases.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide an information processing apparatus and a control method capable of reducing power consumption.

Means for Solving the Problems

[0006] To solve the above problems, one aspect of the present invention is an information processing device comprising: a memory drive device for storing data used for information processing; a main control unit for executing the information processing, the main control unit being connected to the memory drive device by a first interface for sending and receiving the data used for the information processing; and a sub-control unit operating independently of the main control unit and connected to the memory drive device by a second interface for managing the state of the memory drive device, wherein the memory drive device is an information processing device comprising: a drive control unit capable of changing the first interface and the second interface from a communicable active state to a non-communicable inactive state; and a release processing unit that, in response to a request from the main control unit or the sub-control unit, releases the inactive state of the first interface and the inactive state of the second interface and changes them back to the active state.

[0007] Furthermore, in one aspect of the present invention, in the above-described information processing apparatus, the first interface is a PCI-Express bus interface, the CLKREQ# signal line of the PCI-Express bus interface is connected between the main control unit, the sub-control unit, and the memory drive device, and the release processing unit may release the inactive state of the first interface and the inactive state of the second interface and change them to the active state in response to a change in the CLKREQ# signal line from the main control unit or the sub-control unit to the active state.

[0008] Furthermore, in one aspect of the present invention, in the above-mentioned information processing apparatus, the memory drive device includes a PLL circuit (Phase Locked Loop circuit) that generates a multiplier synchronous clock signal used for transmitting and receiving data on the PCI-Express bus interface from a basic clock signal, and in the inactive state of the first interface, the PLL circuit is stopped. The release processing unit may, in response to the change in the CLKREQ# signal line to an active state, initiate the operation of the PLL circuit to release the inactive state of the first interface.

[0009] Furthermore, in one aspect of the present invention, in the above-described information processing device, the second interface may be any of the SMBus (System Management Bus) interface, the I2C bus interface, and the I3C bus interface.

[0010] Furthermore, one aspect of the present invention is a control method for an information processing apparatus comprising: a memory drive device for storing data used for information processing; a main control unit for executing the information processing, the main control unit being connected to the memory drive device by a first interface for sending and receiving the data used for the information processing; and a sub-control unit operating independently of the main control unit and connected to the memory drive device by a second interface for managing the state of the memory drive device, the control method comprising: a step of the drive control unit changing the first interface and the second interface in the memory drive device from a communicable active state to a communication-disabled inactive state; and a step of the release processing unit releasing the inactive state of the first interface and the inactive state of the second interface and changing them to the active state in response to a request from the main control unit or the sub-control unit.

[0011] Furthermore, one aspect of the present invention is an information communication device for communicating data used for information processing, a main control unit for executing the information processing, the main control unit being connected to the information communication device by a first interface for sending and receiving the data used for the information processing, and a sub-control unit operating independently of the main control unit and connected to the information communication device by a second interface for managing the state of the information communication device, wherein the information communication device is an information processing device comprising a control unit capable of changing the first interface and the second interface from a communication-enabled active state to a communication-disabled inactive state, and a release processing unit that, in response to a request from the main control unit or the sub-control unit, releases the inactive state of the first interface and the inactive state of the second interface and changes them back to the active state.

[0012] Furthermore, one aspect of the present invention is a control method for an information processing apparatus comprising: an information communication device for communicating data used for information processing; a main control unit for executing the information processing, the main control unit being connected to the information communication device by a first interface for sending and receiving the data used for the information processing; and a sub-control unit operating independently of the main control unit and connected to the information communication device by a second interface for managing the state of the information communication device, the control method comprising the steps of: the control unit changing the first interface and the second interface in the information communication device from a communication-enabled active state to a communication-disabled inactive state; and the release processing unit releasing the inactive state of the first interface and the inactive state of the second interface and changing them to the active state in response to a request from the main control unit or the sub-control unit. [Effects of the Invention]

[0013] According to the above-described embodiment of the present invention, power consumption can be reduced. [Brief explanation of the drawing]

[0014] [Figure 1] This figure shows an example of the main hardware configuration of a notebook PC and SSD according to this embodiment. [Figure 2] This is a functional block diagram showing an example of the functional configuration of a notebook PC according to this embodiment. [Figure 3] This figure shows an example of the SSD state in this embodiment. [Figure 4] This figure shows an example of the state transitions of the SSD in this embodiment. [Figure 5] This flowchart shows an example of how a notebook PC operates according to this embodiment. [Modes for carrying out the invention]

[0015] Hereinafter, an information processing device and a control method according to one embodiment of the present invention will be described with reference to the drawings.

[0016] FIG. 1 is a diagram showing an example of the main hardware configuration of the notebook PC 1 and the SSD 40 according to the first embodiment. As shown in FIG. 1, the notebook PC 1 (notebook personal computer) includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40. In the present embodiment, as an example of the information processing apparatus, a case where the information processing apparatus is the notebook PC 1 will be described.

[0017] The CPU (Central Processing Unit) 11 executes various arithmetic processes under program control and controls the entire notebook PC 1.

[0018] The main memory 12 is a writable memory that is used as a read area for the execution program of the CPU 11 or as a work area for writing the processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. This execution program includes an OS (Operating System), various drivers for hardware operation of peripheral devices, various services / utilities, application programs, and the like.

[0019] The video subsystem 13 is a subsystem for realizing functions related to image display and includes a video controller. This video controller processes the drawing command from the CPU 11, writes the processed drawing information to the video memory, reads the drawing information from the video memory, and outputs it to the display unit 14 as drawing data (display data).

[0020] The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on the drawing data (display data) output from the video subsystem 13.

[0021] The chipset 21 includes controllers such as a USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus (PCIe bus), and LPC (Low Pin Count) bus, to which a plurality of devices are connected. In FIG. 1, as an example of devices, a BIOS memory 22 and an SSD 40 are connected to the chipset 21. In this embodiment, the CPU 11 and the chipset 21 correspond to the main control unit 10.

[0022] The BIOS (Basic Input Output System) memory 22 is composed of an electrically rewritable non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory), for example. The BIOS memory 22 stores system firmware such as BIOS and an embedded controller 31 for controlling the same. <000010​​​​​The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touchpad.

[0025] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, and an AC / DC adapter, and converts, for example, a DC voltage supplied from an external power source via an AC / DC adapter or from a battery into multiple voltages necessary to operate the notebook PC 1. The power supply circuit 33 also supplies power to various parts of the notebook PC 1 based on control from the embedded controller 31.

[0026] The SSD (Solid State Drive) 40 is a memory drive device with rewritable non-volatile memory, which stores the OS, various drivers, various services / utilities, application programs, and various data. The notebook PC 1 uses the data stored in the SSD 40 to perform various information processing tasks. The SSD 40 is connected to the chipset 21, for example, via a PCI-Express bus (hereinafter sometimes referred to as a PCIe bus).

[0027] In addition to the PCIe bus interface (first interface), the SSD40 can communicate via the SMBus (System Management Bus) interface (second interface) through the embedded controller 31. Communication using these two interfaces, the PCIe bus interface and the SMBus interface, will be described later. The SSD 40 also includes multiple flash memory devices 41 and a memory controller 42.

[0028] The flash memory 41 is, for example, a NAND flash memory. The flash memory 41 includes, for example, a floating-gate type memory cell, a charge-trap type memory cell that stores data by trapping electrons in a charge-trap layer without a floating gate, and so on.

[0029] The memory controller 42 is a processor that includes, for example, a CPU, ROM, RAM, etc. (not shown), and comprehensively controls the SSD 40. The memory controller 42 performs processes such as controlling the host interface (host I / F) between the chipset 21 and the embedded controller 31, controlling the memory interface (memory I / F) between the flash memory 41 and the SSD 40, and managing the data of the flash memory 41.

[0030] Next, with reference to Figure 2, the functional configuration of the notebook PC 1 according to this embodiment will be described. Figure 2 is a functional block diagram showing an example of the functional configuration of the notebook PC 1 according to this embodiment.

[0031] As shown in Figure 2, the notebook PC 1 comprises a main control unit 10, an embedded controller 31, and an SSD 40. The main control unit 10 and the SSD 40 are connected by two interfaces: a PCIe bus interface (first interface) and an SMBus interface (second interface) via the embedded controller 31.

[0032] The main control unit 10 is a functional unit realized by the CPU 11 and chipset 21 executing programs stored in the main memory 12, and performs various processes (information processing) based on the OS. For example, the main control unit 10 performs various processes based on data stored in the SSD 40 and management processes for managing the SSD 40. The main control unit 10 includes a first communication unit 101, a release processing unit 102, a PLL circuit 103, and a third communication unit 104.

[0033] The first communication unit 101 is a functional unit implemented, for example, using a PCIe bus interface device (not shown) of the chipset 21, and performs communication with the SSD 40 via the PCIe bus. The first communication unit 101 sends and receives data used for information processing performed by the main control unit 10.

[0034] When the first communication unit 101 is in an inactive state (operational stop state) and has stopped operating, the release processing unit 102 responds to an activation request (startup request) from the PCIe bus CLKREQ# signal line to release the inactive state (operational stop state) of the first communication unit 101 and changes the first communication unit 101 to an active state (operational state) that is capable of communication.

[0035] The release processing unit 102, in response to the activation request (startup request) via the CLKREQ# signal line, activates the PLL circuit 103 (described later) and changes the first communication unit 101 to a communication-enabled activated state (operating state).

[0036] The PLL circuit 103 (Phase Locked Loop circuit) is used by the first communication unit 101 to generate a clock signal (for example, a multiplier synchronous clock signal) for data communication via the PCIe bus interface.

[0037] The third communication unit 104 is a functional unit implemented, for example, using an interface device (not shown) of the eSPI (Enhanced Serial Peripheral Interface) bus of the chipset 21, and performs communication with the embedded controller 31 via the eSPI bus. The third communication unit 104 sends and receives data used for various device management and system management using the embedded controller 31.

[0038] The embedded controller 31 (an example of a sub-control unit) operates independently of the main control unit 10 and is connected to the SSD 40 via an SMBus interface for managing the SSD 40's status. The embedded controller 31 communicates with the main control unit 10 via the eSPI bus interface and with the SSD 40 via the SMBus interface.

[0039] The embedded controller 31 is connected to the CLKREQ# signal line. When the SSD 40's SMBus interface (the second communication unit 424, described later) is inactive (operationally disabled), the embedded controller 31 can change the SSD 40's SMBus interface to an active state (operational state) by changing the CLKREQ# signal line to an asserted state (enabled state). Changing the CLKREQ# signal line to an asserted state (enabled state) corresponds to a request from the main control unit 10 or the embedded controller 31 (a request to release the deactivated state).

[0040] Furthermore, the PCIe bus interface's CLKREQ# signal line connects the main control unit 10, the embedded controller 31, and the SSD 40. The CLKREQ# signal line is a single signal line connected to three locations: the main control unit 10, the embedded controller 31, and the SSD 40, and is connected to a pull-up resistor (not shown). When the main control unit 10, the embedded controller 31, and the SSD 40 are all in the release state, the CLKREQ# signal line remains high due to the pull-up resistor.

[0041] The CLKREQ# signal line outputs a Low state as an asserted state (enabled state) from either the main control unit 10, the embedded controller 31, or the SSD 40, thereby releasing the PCIe bus interface and the SSD 40's SMBus interface from the inactive state (stopped state).

[0042] SSD40 includes a drive control unit 420. The drive control unit 420 is a functional unit implemented by the memory controller 42, and can change the PCIe bus interface and SMBus interface from an active state where communication is possible to an inactive state where communication is impossible. The drive control unit 420 includes a first communication unit 421, a release processing unit 422, a PLL circuit 423, and a second communication unit 424.

[0043] The first communication unit 421 is a functional unit implemented using an interface device (not shown) for the PCIe bus of the memory controller 42, and performs communication between the SSD 40 and the main control unit 10 via the PCIe bus. The first communication unit 421 can be deactivated to transition to a power-down state with reduced power consumption. Furthermore, when the first communication unit 421 is inactive, it can be deactivated via the release processing unit 422 and transition to an active state.

[0044] The release processing unit 422 releases the inactive state (operational stop state) of the PCIe bus interface and the SMBus interface and changes them to the active state (operational state) in response to a request from the main control unit 10 or the embedded controller 31 (for example, an activation request (startup request)). The release processing unit 422 releases the inactive state of the PCIe bus interface and the SMBus interface and changes them to the active state in response to a change in the valid state (for example, a Low state) of the CLKREQ# signal line from the main control unit 10 or the embedded controller 31.

[0045] In other words, the release processing unit 422 detects when the CLKREQ# signal line goes low, and when the CLKREQ# signal line goes low, it changes the first communication unit 421, the PLL circuit 423, and the second communication unit 424 to an active state.

[0046] The release processing unit 422, for example, in response to a change in the CLKREQ# signal line to an enabled state (change to a Low state), starts the operation of the PLL circuit 423 to release the inactive state of the PCIe bus interface.

[0047] The PLL circuit 423 generates a clock signal (e.g., a multiplier synchronous clock signal) for data communication via the PCIe bus interface, which is performed by the first communication unit 421. It generates a multiplier synchronous clock signal used for sending and receiving data on the PCI-Express bus interface from the basic clock signal.

[0048] Furthermore, the PLL circuit 423 can be stopped when the PCIe bus interface (first communication unit 421) is deactivated. The PLL circuit 423 can significantly reduce the power consumption of the SSD 40 by stopping the generation of the multiplier synchronous clock signal. When the PLL circuit 423 is operating at reduced capacity, it can transition from a stopped state to an operating state via the release processing unit 422.

[0049] In this embodiment, a configuration example is described in which the PLL circuit 423 is included in the first communication unit 421. However, the drive control unit 420 may also be configured to include the PLL circuit 423 separately from the first communication unit 421.

[0050] Alternatively, in this embodiment, when transmitting data from the SSD 40 to the main control unit 10 via the PCIe bus interface, the PLL circuit 423 may be omitted, and the data may be transmitted in synchronization with the clock signal generated by the PLL circuit 103 of the main control unit 10.

[0051] The second communication unit 424 is a functional unit implemented using the SMBus interface device (not shown) of the memory controller 42, and performs communication between the SSD 40 and the embedded controller 31 via SMBus. The second communication unit 424 can be deactivated to transition to a power-down state with reduced power consumption. Furthermore, when the second communication unit 424 is inactive, it can be deactivated via the release processing unit 422 and transition to an active state.

[0052] Next, with reference to Figure 3, the state of the SSD 40 in this embodiment will be described. Figure 3 shows an example of the state of the SSD40 in this embodiment. As shown in Figure 3, the SSD40 can be switched between L0, L1.0, L1.2, and L1.3 states.

[0053] The L0 state is the normal operating state in which communication is possible on both the PCIe bus and SMBus. In the L0 state, the CLKREQ# signal line is asserted (low state) by at least one of the main control unit 10, embedded controller 31, and SSD 40.

[0054] Furthermore, in the L0 state, the PLL circuit 423, PCIe bus, and SMBus are all operational. In other words, in the L0 state, the PLL circuit 423, the first communication unit 421, and the second communication unit 424 are all operational (active). The power consumption of SSD40 in the L0 state is PW1, which is approximately several hundred mW (milliwatts).

[0055] Furthermore, the L1.0 state is a state in which the PCIe bus is inactive (stopped) among the PLL circuit 423, PCIe bus, and SMBus. In other words, in the L1.0 state, the PLL circuit 423 and the second communication unit 424 are in operation (active), while the first communication unit 421 is inactive (stopped). Note that the power consumption of SSD40 in the L1.0 state is PW2, which is smaller than the power consumption PW1 in the L0 state mentioned above (PW1 > PW2).

[0056] Furthermore, the L1.2 state is a state in which the PLL circuit 423 and PCIe bus are inactive (stopped) among the PLL circuit 423, PCIe bus, and SMBus. In other words, in the L1.2 state, the second communication unit 424 is in operation (active), while the PLL circuit 423 and the first communication unit 421 are inactive (stopped). Note that the power consumption of SSD40 in the L1.2 state is PW3, which is smaller than the power consumption PW2 in the L1.0 state mentioned above (PW2 > PW3).

[0057] Furthermore, state L1.3 is a state in which the PLL circuit 423, PCIe bus, and SMBus are all inactive (stopped). In other words, in state L1.3, the PLL circuit 423, the first communication unit 421, and the second communication unit 424 are all inactive (stopped). In state L1.3, the CLKREQ# signal line is released (high due to the pull-up resistor in an unconnected state) by the main control unit 10, the embedded controller 31, and the SSD 40.

[0058] Note that the power consumption in state L1.3 is PW4, which is smaller than the power consumption PW3 in state L1.2 (PW3 > PW4). The power consumption PW4 of SSD40 in state L1.3 is, for example, a few mW.

[0059] Next, the operation of the notebook PC 1 according to this embodiment will be described with reference to the drawings. First, with reference to Figure 4, the state transitions of the SSD40 in this embodiment will be described. Figure 4 shows an example of the state transitions of the SSD40 in this embodiment.

[0060] As shown in Figure 4, state S11 is the L0 state described above. For example, when the SSD 40's drive control unit 420 receives a PCIe bus stop request from the main control unit 10, it transitions to the L1.0 state of state S12.

[0061] Furthermore, when the drive control unit 420 receives a request to release the L1.0 state in state S12, it transitions to the L0 state in state S11. Here, a request to release the L1.0 state may be, for example, a change to the asserted state of the CLKREQ# signal line from the main control unit 10, or a request to release the L1.0 state from the embedded controller 31 using SMBus.

[0062] Furthermore, when the drive control unit 420 receives a request to change to the L1.2 state while in the L0 state of state S11, it transitions to the L1.2 state of state S13. Here, a request to change to the L1.2 state may be, for example, a request to change to the L1.2 state from the main control unit 10 using the PCIe bus, or a request to change to the L1.2 state from the embedded controller 31 using SMBus.

[0063] Furthermore, in the L1.2 state of state S13, for example, if the drive control unit 420 receives a Low state from the CLKREQ# signal line of the main control unit 10, the drive control unit 420 transitions to the L0 state of state S11.

[0064] Furthermore, if a stop request for the SMBus is received in state S13 (L1.2 state), the drive control unit 420 transitions to state S14 (L1.3 state). Here, the stop request for the SMBus is, for example, a stop request for the SMBus from the embedded controller 31 using the SMBus.

[0065] Furthermore, when the drive control unit 420 receives a request to change to the L1.3 state while in the L0 state of state S11, it transitions to the L1.3 state of state S14. Here, a request to change to the L1.3 state may be, for example, a request to change to the L1.3 state from the main control unit 10 using the PCIe bus, or a request to change to the L1.3 state from the embedded controller 31 using SMBus.

[0066] Furthermore, in the L1.3 state of state S14, if the drive control unit 420 receives a Low state from the CLKREQ# signal line from the main control unit 10 or the embedded controller 31, for example, the drive control unit 420 transitions to the L0 state of state S11.

[0067] Next, with reference to Figure 5, the operation of the SSD 40 of the notebook PC 1 according to this embodiment will be described. Figure 5 is a flowchart showing an example of the operation of the notebook PC 1 according to this embodiment. Here, the initial state of the SSD 40 is the L0 state described above.

[0068] As shown in Figure 5, the SSD 40 of the notebook PC 1 determines whether or not it has received a request to change to the L1.3 state (step S101). The drive control unit 420 of the SSD 40 determines whether or not it has received a request to change to the L1.3 state via the first communication unit 421 or the second communication unit 424 while in the L0 state. If the drive control unit 420 has received a request to change to the L1.3 state (step S101: YES), it proceeds to step S102. If the drive control unit 420 has not received a request to change to the L1.3 state (step S101: NO), it returns to step S101.

[0069] In step S102, the drive control unit 420 stops the operation of the PCIe bus, PLL circuit 423, and SMBus. That is, the drive control unit 420 stops all operations of the PLL circuit 423, the first communication unit 421, and the second communication unit 424, and transitions to the L1.3 state.

[0070] Next, the notebook PC 1 sets the CLKREQ# signal lines of the main control unit 10, SSD 40, and embedded controller 31 (EC) to the release state (Release state, i.e., High state) (step S103).

[0071] Next, the drive control unit 420 determines whether the CLKREQ# signal line has gone low (step S104). The release processing unit 422 of the drive control unit 420 determines whether the CLKREQ# signal line has gone low. If the CLKREQ# signal line has gone low (step S104: YES), the release processing unit 422 proceeds to step S105. If the CLKREQ# signal line has not gone low (step S104: NO), the release processing unit 422 returns to step S104.

[0072] In step S105, the release processing unit 422 restarts the operation of the PCIe bus, PLL circuit 423, and SMBus. That is, the release processing unit 422 restarts the PLL circuit 423, the first communication unit 421, and the second communication unit 424, releasing the L1.3 state and transitioning to the L0 state. After the processing in step S105, the drive control unit 420 returns the process to step S101.

[0073] As described above, the notebook PC 1 (information processing device) according to this embodiment comprises an SSD 40 (memory drive device), a main control unit 10, and an embedded controller 31 (sub-control unit), and the SSD 40 stores data used for information processing. The main control unit 10 is a main control unit 10 that executes information processing and is connected to the SSD 40 by a PCI-Express bus interface (first interface) that sends and receives data used for information processing. The embedded controller 31 operates independently of the main control unit 10 and is connected to the SSD 40 by an SMBus interface (second interface) for managing the state of the SSD 40. The SSD 40 comprises a drive control unit 420 and a release processing unit 422. The drive control unit 420 can change the PCIe bus interface and the SMBus interface from an active state that allows communication to an inactive state that does not allow communication. The release processing unit 422, in response to a request (request to release the deactivated state) from the main control unit 10 or the embedded controller 31, releases the deactivated state of the PCIe bus interface and the SMBus interface and changes them to the activated state.

[0074] As a result, the notebook PC 1 (information processing device) according to this embodiment can reduce the power consumption of the SSD 40 to PW4 (approximately several mW) by setting the PCIe bus interface and SMBus interface of the SSD 40 to an inactive state (L1.3 state). Furthermore, the release processing unit 422 of the notebook PC 1 (information processing device) according to this embodiment can appropriately release the state in which the PCIe bus interface and SMBus interface of the SSD 40 are inactive (L1.3 state) from either the main control unit 10 or the embedded controller 31. Therefore, the notebook PC 1 (information processing device) according to this embodiment can reduce power consumption.

[0075] Furthermore, in this embodiment, the PCIe bus interface is a PCI-Express (PCIe) bus interface. The CLKREQ# signal line of the PCI-Express bus interface is connected between the main control unit 10, the embedded controller 31, and the SSD 40. The release processing unit 422 releases the inactive state of the PCIe bus interface and the inactive state of the SMBus interface and changes them to the active state in response to a change in the CLKREQ# signal line from the main control unit 10 or the embedded controller 31 to the active state.

[0076] As a result, the notebook PC 1 according to this embodiment can easily and simply release the deactivated state (L1.3 state) of the PCI-Express (PCIe) bus interface and SMBus interface of the SSD 40 by using the CLKREQ# signal line of the PCI-Express (PCIe) bus interface with a simple configuration.

[0077] Furthermore, in this embodiment, the SSD 40 includes a PLL circuit 423 that generates a multiplier synchronous clock signal used for sending and receiving data on the PCI-Express bus interface from a basic clock signal. The PLL circuit 423 is stopped when the PCIe bus interface is inactive. The release processing unit 422 starts the operation of the PLL circuit 423 in response to a change in the CLKREQ# signal line to an active state (asserted state, low state) and releases the inactive state of the PCIe bus interface.

[0078] As a result, the notebook PC 1 according to this embodiment can further reduce power consumption by stopping the operation of the PLL circuit 423. Furthermore, the notebook PC 1 according to this embodiment can appropriately release the L1.3 state (low power consumption state) described above by using the CLKREQ# signal line to release the PLL circuit 423 and restart it.

[0079] Furthermore, in this embodiment, the second interface described above is one of the SMBus interface, the I2C bus interface, or the I3C bus interface.

[0080] As a result, the notebook PC 1 according to this embodiment achieves the same effect with the I2C bus interface and the I3C bus interface in addition to the SMBus interface, thereby reducing the power consumption of the notebook PC 1.

[0081] Furthermore, the control method according to this embodiment is a control method for an information processing device (notebook PC 1) comprising an SSD 40 for storing data used for information processing, a main control unit 10 for executing information processing, the main control unit 10 being connected to the SSD 40 by a PCIe bus interface for sending and receiving data used for information processing, and an embedded controller 31 operating independently of the main control unit 10 and connected to the SSD 40 by an SMBus interface for managing the state of the SSD 40, and includes a first step and a second step. In the first step, the drive control unit 420 changes the PCIe bus interface and the SMBus interface on the SSD 40 from an active state where communication is possible to an inactive state where communication is impossible. In the second step, the release processing unit 422 releases the inactive state of the PCIe bus interface and the SMBus interface and changes them to an active state in response to a request from the main control unit 10 or the embedded controller 31.

[0082] As a result, the control method according to this embodiment has the same effect as the notebook PC 1 described above, and by putting it into the L1.3 state, the power consumption can be reduced to PW4 (approximately a few mW), and the L1.3 state can be appropriately released. Therefore, the control method according to this embodiment can reduce the power consumption of the notebook PC 1.

[0083] It should be noted that the present invention is not limited to the embodiments described above, and can be modified without departing from the spirit of the invention. For example, in the above embodiment, the information processing device was described as a notebook PC (notebook-type personal computer), but it is not limited to this, and may be other information processing devices such as a desktop personal computer or a tablet terminal device.

[0084] Furthermore, in the above embodiment, an example was described in which the release processing unit 422 releases the deactivated state of the PCIe bus interface and the deactivated state of the SMBus interface according to the asserted state (Low state) of the CLKREQ# signal line. However, the invention is not limited to this, and the deactivated state may be released by other methods.

[0085] Furthermore, although the above embodiment describes an example where the first interface is a PCIe bus interface and the second interface is an SMBus interface, the invention is not limited to this, and the first and second interfaces may be other interfaces.

[0086] Furthermore, in the above embodiment, the SSD 40 may be an information communication device that combines a first communication unit and a second communication unit, such as a PCIe bus interface and an SMBus interface, like a WAN (Wide Area Network Device) or a LAN device (Local Area Network Device). In other words, the present invention may be applied to an information communication device for communicating data used for information processing, instead of a memory drive device (SSD 40).

[0087] Furthermore, each component of the aforementioned Notebook PC 1 and SSD 40 has a computer system inside. The processing in each component of Notebook PC 1 and SSD 40 may be performed by recording a program for realizing the functions of each component on a computer-readable storage medium, loading this program onto the computer system, and executing it. Here, "loading and executing a program recorded on a storage medium onto the computer system" includes installing the program on the computer system. Here, "computer system" includes hardware such as the operating system and peripheral devices.

[0088] Furthermore, "computer system" may include multiple computer devices connected via a network, including communication lines such as the Internet, WAN, LAN, and dedicated lines. "Computer-readable recording medium" refers to portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. Thus, the recording medium storing the program may be a non-transient recording medium such as a CD-ROM.

[0089] Furthermore, the recording medium includes internal or external recording media accessible from the distribution server for distributing the program. The program may be divided into multiple parts, downloaded at different times, and then combined in the respective configurations of Notebook PC1 and SSD40. The distribution servers for each of the divided programs may also be different. Additionally, "computer-readable recording media" includes volatile memory (RAM) within computer systems that act as servers or clients when a program is transmitted over a network, which retains the program for a certain period. Moreover, the program may be intended to implement only a portion of the functions described above. Furthermore, the program may be a so-called differential file (differential program) that can implement the functions described above in combination with programs already recorded in the computer system.

[0090] Furthermore, some or all of the above-mentioned functions may be implemented as integrated circuits such as LSIs (Large Scale Integrations). Each of the above-mentioned functions may be implemented as an individual processor, or some or all of them may be integrated into a single processor. In addition, the method of implementing integrated circuits is not limited to LSIs; they may also be implemented using dedicated circuits or general-purpose processors. Furthermore, if advances in semiconductor technology lead to the emergence of integrated circuit technologies that can replace LSIs, integrated circuits using such technologies may be used. [Explanation of symbols]

[0091] 1. Laptop 10 Main Control Unit 11 CPU 12 Main Memory 13 Video Subsystems 14 Display section 21 Chipset 22 BIOS memory 31. Embedded Controller (EC) 32 Input section 33 Power supply circuit 40 SSD 41 Flash memory 42 Memory Controllers 101, 421 First Communications Department 102, 422 Release Processing Unit 103, 423 PLL circuit 104 Third Communications Department 424 Second Communications Department

Claims

1. A memory drive device for storing data used in information processing, A main control unit that performs the aforementioned information processing, the main control unit being connected to the memory drive device by a first interface for sending and receiving the data used in the information processing, A sub-control unit that operates independently of the main control unit and is connected to the memory drive device via a second interface for managing the state of the memory drive device. Equipped with, The memory drive device, A drive control unit capable of changing the first interface and the second interface from a communication-enabled active state to a communication-disabled inactive state, A release processing unit that, in response to a request from the main control unit or the sub-control unit, releases the deactivated state of the first interface and the deactivated state of the second interface and changes them to the activated state. An information processing device equipped with the following features.

2. The first interface is a PCI-Express bus interface, The CLKREQ# signal line of the PCI-Express bus interface is connected between the main control unit, the sub-control unit, and the memory drive device. The release processing unit, in response to the change from the main control unit or the sub-control unit to the enabled state of the CLKREQ# signal line, releases the inactive state of the first interface and the inactive state of the second interface and changes them to the enabled state. The information processing apparatus according to claim 1.

3. The memory drive device, It includes a PLL (Phase Locked Loop) circuit that generates a multiplier synchronous clock signal used for transmitting and receiving data in the PCI-Express bus interface from a basic clock signal. When the first interface is inactive, the PLL circuit is stopped. The release processing unit initiates the operation of the PLL circuit in response to the change in the CLKREQ# signal line to an active state, thereby releasing the deactivated state of the first interface. The information processing apparatus according to claim 2.

4. The second interface is one of the following: an SMBus (System Management Bus) interface, an I2C bus interface, or an I3C bus interface. The information processing apparatus according to any one of claims 1 to 3.

5. A control method for an information processing apparatus comprising: a memory drive device for storing data used for information processing; a main control unit for executing the information processing, the main control unit being connected to the memory drive device by a first interface for sending and receiving the data used for the information processing; and a sub-control unit operating independently of the main control unit and connected to the memory drive device by a second interface for managing the state of the memory drive device, The drive control unit performs the steps of changing the first interface and the second interface in the memory drive device from a communication-enabled active state to a communication-disabled inactive state, The release processing unit, in response to a request from the main control unit or the sub-control unit, releases the deactivated state of the first interface and the deactivated state of the second interface and changes them to the activated state. A control method including

6. An information communication device for communicating data used in information processing, A main control unit that performs the aforementioned information processing, the main control unit being connected to the information communication device by a first interface for sending and receiving the data used in the aforementioned information processing, A sub-control unit that operates independently of the main control unit and is connected to the information communication device via a second interface for managing the status of the information communication device. Equipped with, The aforementioned information and communication device is A control unit capable of changing the first interface and the second interface from a communication-enabled active state to a communication-disabled inactive state, A release processing unit that, in response to a request from the main control unit or the sub-control unit, releases the deactivated state of the first interface and the deactivated state of the second interface and changes them to the activated state. An information processing device equipped with the following features.

7. A control method for an information processing apparatus comprising: an information communication device for communicating data used for information processing; a main control unit for executing the information processing, the main control unit being connected to the information communication device by a first interface for sending and receiving the data used for the information processing; and a sub-control unit operating independently of the main control unit and connected to the information communication device by a second interface for managing the state of the information communication device, The control unit performs the steps of changing the first interface and the second interface in the information communication device from a communication-enabled active state to a communication-disabled inactive state, The release processing unit, in response to a request from the main control unit or the sub-control unit, releases the deactivated state of the first interface and the deactivated state of the second interface and changes them to the activated state. A control method including

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