Pixel driving circuit and its driving method, and display panel

Abstract

The present invention provides a pixel driving circuit and a method for driving the same, as well as a display panel. [Solution] The pixel driving circuit includes a driving transistor T3, a data writing circuit 7, a threshold compensation circuit 8, a first capacitor C1, and a second capacitor C2. The gate of the driving transistor T3 is connected to the first node N1, the first pole is connected to the second node N2, and the second pole is connected to the third node N3. The data writing circuit 7 transmits the signal from the data signal terminal Da to the second node N2 in response to the signal from the first gate driving signal terminal G1. The threshold compensation circuit 8 connects the first node N1 and the third node N3 in response to the signal from the second gate driving signal terminal G2. The first capacitor C1 is connected between the first node N1 and the first gate driving signal terminal G1, and the second capacitor C2 is connected between the first node N1 and the second gate driving signal terminal G2. The conduction level of the data writing circuit 7 is low, and the conduction level of the threshold compensation circuit 8 is high.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to pixel driving circuits, driving methods thereof, and display panels.

Background Art

[0002] In related technologies, in order to reduce the leakage current of a driving transistor in a light-emitting stage, a pixel driving circuit can be formed using low temperature polycrystalline oxide (LTPO) technology.

[0003] A display panel formed by LTPO technology includes N-type oxide transistors and P-type low-temperature polysilicon transistors. Another gate line for supplying a gate driving signal is required for the oxide transistors, and voltage changes in the gate line may adversely affect the normal driving of the display panel.

[0004] It should be noted that the information disclosed in the above background art is only intended to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those skilled in the art.

Summary of the Invention

[0005] According to one aspect of the present disclosure, a pixel driving circuit is provided. The pixel driving circuit includes a driving transistor, a data writing circuit, a threshold compensation circuit, a first capacitor, and a second capacitor. The driving transistor has its gate connected to a first node, its first pole connected to a second node, and its second pole connected to a third node. The data writing circuit is connected to the second node and the data signal terminal and transmits the signal at the data signal terminal to the second node in response to the signal at the first gate driving signal terminal. The threshold compensation circuit is connected to the first node, the third node, and the second gate driving signal terminal and communicates the first node and the third node in response to the signal at the second gate driving signal terminal. The first capacitor is connected between the first node and the first gate driving signal terminal. The second capacitor is connected between the first node and the second gate driving signal terminal. The conduction level of the data writing circuit is low, the conduction level of the threshold compensation circuit is high, and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0006] In exemplary embodiments of this disclosure, the capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, and C1 / C2 is between 1.5 and 4.

[0007] In exemplary embodiments of the present disclosure, the data writing circuit includes a fourth P-type transistor, the gate of which is connected to the first gate drive signal terminal, the first pole of which is connected to the second node, and the second pole of which is connected to the data signal terminal; and the threshold compensation circuit includes a second N-type transistor, the gate of which is connected to the second gate drive signal terminal, the first pole of which is connected to the first node, and the second pole of which is connected to the third node.

[0008] In exemplary embodiments of the present disclosure, the drive transistor is a P-type transistor, and the pixel drive circuit further includes a control circuit and a coupling circuit. The control circuit is connected to a second power terminal, a second node, a third node, a fourth node, and an enable signal terminal, and in response to a signal at the enable signal terminal, transmits a signal at the second power terminal to the second node, and in response to a signal at the enable signal terminal, connects the third node and the fourth node. The coupling circuit is connected between the first node and the second power terminal.

[0009] In exemplary embodiments of the present disclosure, the pixel driving circuit further includes a first reset circuit connected to the first node, a first initial signal terminal, and a first reset signal terminal, which transmits a signal from the first initial signal terminal to the first node in response to a signal from the first reset signal terminal.

[0010] In exemplary embodiments of the present disclosure, the fourth node is connected to a light-emitting unit, and the pixel driving circuit further includes a third reset circuit connected to the fourth node, a second initial signal terminal, and a third reset signal terminal, which transmits a signal from the second initial signal terminal to the fourth node in response to a signal from the third reset signal terminal.

[0011] In exemplary embodiments of the present disclosure, the pixel driving circuit further includes a second reset circuit connected to the second node and the first power terminal, which transmits a signal from the first power terminal to the second node in response to a control signal.

[0012] In exemplary embodiments of the present disclosure, the drive transistor is a P-type transistor, and the pixel drive circuit further includes a control circuit and a third reset circuit. The control circuit is connected to a second power terminal, a second node, a third node, a fourth node, and an enable signal terminal, and in response to a signal at the enable signal terminal, transmits the signal at the second power terminal to the second node, and in response to a signal at the enable signal terminal, connects the third node and the fourth node. The third reset circuit is connected to the fourth node, a second initial signal terminal, and a third reset signal terminal, and in response to a signal at the third reset signal terminal, transmits the signal at the second initial signal terminal to the fourth node. The conduction signal of the first reset circuit has the opposite polarity to the conduction signal of the third reset circuit, the signal at the first reset signal terminal has the opposite polarity to the signal at the third reset signal terminal, the conduction level of the second reset circuit has the opposite polarity to the conduction level of the first reset circuit, the second reset circuit is also connected to the third reset signal terminal and transmits the signal at the first power supply terminal to the second node in response to the signal at the third reset signal terminal.

[0013] In exemplary embodiments of this disclosure, the first power supply terminal is shared with the second power supply terminal.

[0014] In exemplary embodiments of the present disclosure, the coupling circuit includes a third capacitor connected between the first node and the second power supply terminal, wherein the capacitance value of the third capacitor is greater than that of the first capacitor, and the capacitance value of the third capacitor is greater than that of the second capacitor.

[0015] In exemplary embodiments of the present disclosure, the control circuit includes a fifth transistor whose gate is connected to the enable signal terminal, whose first pole is connected to the second power terminal, and whose second pole is connected to the second node, and a sixth transistor whose gate is connected to the enable signal terminal, whose first pole is connected to the third node, and whose second pole is connected to the fourth node.

[0016] In exemplary embodiments of the present disclosure, the first reset circuit includes a first transistor, the gate of which is connected to the first reset signal terminal, the first pole of which is connected to the first initial signal terminal, and the second pole of which is connected to the first node; the third reset circuit includes a seventh transistor, the gate of which is connected to the third reset signal terminal, the first pole of which is connected to the second initial signal terminal, and the second pole of which is connected to the fourth node; and the second reset circuit includes an eighth transistor, the gate of which is connected to the third reset signal terminal, the first pole of which is connected to the first power terminal, and the second pole of which is connected to the second node, wherein the first transistor is an N-type transistor, and the seventh and eighth transistors are P-type transistors.

[0017] In exemplary embodiments of the present disclosure, the data writing circuit includes a fourth transistor, the gate of which is connected to the first gate drive signal terminal, the first pole of which is connected to the second node, and the second pole of which is connected to the data signal terminal; the threshold compensation circuit includes a second transistor, the gate of which is connected to the second gate drive signal terminal, the first pole of which is connected to the first node, and the second pole of which is connected to the third node; the pixel driving circuit further includes a control circuit, a coupling circuit, a first reset circuit, a third reset circuit, and a second reset circuit, the control circuit including a fifth transistor, the gate of which is connected to the enable signal terminal, the first pole of which is connected to the second power terminal, and the second pole of which is connected to the second node; and a sixth transistor, the gate of which is connected to the enable signal terminal, the first pole of which is connected to the third node, and the second pole of which is connected to the fourth node. The coupling circuit includes a third capacitor connected between the first node and the second power supply terminal; the first reset circuit includes a first transistor whose gate is connected to a first reset signal terminal, whose first pole is connected to a first initial signal terminal, and whose second pole is connected to the first node; the third reset circuit includes a seventh transistor whose gate is connected to a third reset signal terminal, whose first pole is connected to a second initial signal terminal, and whose second pole is connected to the fourth node; and the second reset circuit includes an eighth transistor whose gate is connected to the third reset signal terminal, whose first pole is connected to a first power supply terminal, and whose second pole is connected to the second node, wherein the first and second transistors are oxide transistors, and the drive transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor and eighth transistor are low-temperature polysilicon transistors.

[0018] According to one aspect of this disclosure, a method for driving a pixel driving circuit is provided, which drives the above-mentioned pixel driving circuit. During the reset phase, a high-level signal is input to the enable signal terminal, the first reset signal terminal, and the first gate drive signal terminal, and a low-level signal is input to the second gate drive signal terminal and the third reset signal terminal. In the threshold compensation stage, a high-level signal is input to the enable signal terminal, the second gate drive signal terminal, and the third reset signal terminal, and a low-level signal is input to the first reset signal terminal and the first gate drive signal terminal. The process includes, during the light emission stage, inputting a high-level signal to the third reset signal terminal and the first gate drive signal terminal, and inputting a low-level signal to the enable signal terminal, the second gate drive signal terminal, and the first reset signal terminal.

[0019] According to one aspect of this disclosure, a display panel comprising the above-described pixel driving circuit is provided.

[0020] According to one aspect of the present disclosure, a display panel is provided that includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a second N-type transistor whose gate is connected to a second gate line and a third gate line, whose first pole is connected to the gate of the driving transistor, and whose second pole is connected to the second pole of the driving transistor, a fourth P-type transistor whose gate is connected to a first gate line, whose first pole is connected to a data line, and whose second pole is connected to the first pole of the driving transistor, a first capacitor whose first electrode is connected to the first gate line, and whose second electrode is connected to the gate of the driving transistor, and a second capacitor whose first electrode is connected to the second gate line and the third gate line, and whose second electrode is connected to the gate of the driving transistor, wherein the polarity of the signal on the first gate line is opposite to the polarity of the signal on the second gate line, and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor. The display panel further includes a base substrate, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer, wherein the first conductive layer is located on one side of the base substrate and includes a first conductive portion and the first gate line, the first conductive portion being used to form the gate of the drive transistor, and the orthographic projection of the first gate line on the base substrate extends along a first direction. The second conductive layer is located on the side of the first conductive layer away from the base substrate and includes the second gate line, the orthographic projection of the second gate line on the base substrate extends along the first direction. The second active layer is located on the side of the second conductive layer away from the base substrate and includes a first active portion, a second active portion, and a third active portion, the second active portion being connected between the first active portion and the third active portion, the first active portion being used to form the channel region of the second transistor, and the orthographic projection of the second gate line on the base substrate covers the orthographic projection of the first active portion on the base substrate. The third conductive layer is located on the side of the second active layer away from the base substrate, includes the third gate line, the orthographic projection of the third gate line on the base substrate extends along the first direction, and the orthographic projection of the third gate line on the base substrate covers the orthographic projection of the first active portion on the base substrate.The fourth conductive layer is located on the side of the third conductive layer away from the base substrate and includes a connection portion, which is connected to the first conductive portion and the third active portion, respectively, via via holes. The first gate line has a first extension portion, the orthographic projection of the first extension portion on the base substrate overlaps with the orthographic projection of the third active portion on the base substrate, the first extension portion is used to form the first electrode of the first capacitor, and the third active portion is used to form the second electrode of the first capacitor. The second gate line has a second extension portion, the orthographic projection of the second extension portion on the base substrate overlaps with the orthographic projection of the second active portion on the base substrate, the orthographic projection of the third gate line on the base substrate is located on one side of the orthographic projection of the second active portion on the base substrate, the second extension portion is used to form part of the first electrode of the second capacitor, and the second active portion is used to form part of the second electrode of the second capacitor. The third gate line has a third extension, the connection portion has a fourth extension, the orthographic projection of the third extension on the base substrate overlaps with the orthographic projection of the fourth extension on the base substrate, the third extension is used to form a part of the first electrode of the second capacitor, and the fourth extension is used to form a part of the second electrode of the second capacitor.

[0021] In exemplary embodiments of the present disclosure, the size of the orthographic projection of the third active portion on the base substrate in the first direction is greater than the size of the orthographic projection of the second active portion on the base substrate in the first direction.

[0022] Please understand that the general descriptions above and the detailed descriptions below are illustrative and explanatory only, and do not limit this disclosure. The drawings herein are incorporated into the specification, constitute part of the specification, illustrate embodiments consistent with the disclosure, and are provided together with the specification to illustrate the principles of the disclosure. The drawings in the following description are merely illustrative embodiments, and those skilled in the art can obtain other drawings by following these without creative effort. [Brief explanation of the drawing]

[0023] [Figure 1] It is a schematic diagram showing the circuit configuration of a pixel driving circuit in the prior art. [Figure 2] It is a timing diagram of each node in the driving method of the pixel driving circuit of FIG. 1. [Figure 3] It is a simulation timing diagram of the first node, the second node, and the third node in the driving method shown in FIG. 2 of the pixel driving circuit of FIG. 1. [Figure 4] It is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 5] It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 6] It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 7] It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 8] It is a timing diagram of each node in the driving method of the pixel driving circuit of FIG. 7. [Figure 9] It is a simulation timing diagram of the first node, the second node, and the third node in the driving method shown in FIG. 8 of the pixel driving circuit of FIG. 7. [Figure 10] It is a structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 11] It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 12] It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 13] It is a timing diagram of each node in the driving method of the pixel driving circuit of FIG. 12. [Figure 14] It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. [Figure 15] It is a distribution diagram of the pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure. [Figure 16]This is a distribution diagram of a pixel driving circuit in another exemplary embodiment of the display panel of the present disclosure. [Figure 17] This is a distribution diagram of a pixel driving circuit in another exemplary embodiment of the display panel of the present disclosure. [Figure 18] This is a partial structural layout of an exemplary embodiment of a display panel of the present disclosure. [Figure 19] This figure shows the structural layout of the first conductive layer in Figure 18. [Figure 20] This figure shows the structural layout of the second conductive layer, as shown in Figure 18. [Figure 21] This figure shows the structural layout of the second active layer, as shown in Figure 18. [Figure 22] This figure shows the structural layout of the third conductive layer in Figure 18. [Figure 23] This figure shows the structural layout of the fourth conductive layer in Figure 18. [Figure 24] This figure shows the structural layout of the first conductive layer, the second conductive layer, and the second active layer as shown in Figure 18. [Figure 25] This figure shows the structural layout of the first conductive layer, second conductive layer, second active layer, and third conductive layer in Figure 18. [Figure 26] This is a partial cross-sectional view along the dotted line A in Figure 18. [Figure 27] This is a first schematic diagram of a pixel circuit provided by one embodiment of the present disclosure. [Figure 28] This is a second schematic diagram of a pixel circuit provided by one embodiment of the present disclosure. [Figure 29] This is a schematic diagram of a first reset subcircuit provided by one embodiment of the present disclosure. [Figure 30] This is a schematic diagram of the compensation subcircuit provided by one embodiment of the present disclosure. [Figure 31] This is a schematic diagram of the drive subcircuit provided by one embodiment of the present disclosure. [Figure 32] This is a schematic diagram of the writing subcircuit provided by one embodiment of the present disclosure. [Figure 33]This is a schematic diagram of a first light emission control subcircuit provided by one embodiment of the present disclosure. [Figure 34] This is a schematic diagram of a second light emission control subcircuit provided by one embodiment of the present disclosure. [Figure 35] This is a first schematic diagram of a second reset subcircuit provided by one embodiment of the present disclosure. [Figure 36] This is a second schematic diagram of a second reset subcircuit provided by one embodiment of the present disclosure. [Figure 37a] This is a first equivalent circuit diagram of a pixel circuit provided by one embodiment of the present disclosure. [Figure 37b] This is a second equivalent circuit diagram of a pixel circuit provided by one embodiment of the present disclosure. [Figure 38a] This is a third equivalent circuit diagram of a pixel circuit provided by one embodiment of the present disclosure. [Figure 38b] This is a third equivalent circuit diagram of a pixel circuit provided by one embodiment of the present disclosure. [Figure 39] This is a timing diagram of the operation of the pixel circuit shown in Figure 37a or Figure 37b during one scan cycle. [Figure 40] This is a timing diagram of the operation of the pixel circuit shown in Figure 38a or Figure 38b during one scan cycle. [Figure 41] Figure 37a is a schematic diagram showing the operating state of the transistor during the reset phase of the pixel circuit. [Figure 42] Figure 37a is a schematic diagram showing the operating state of the transistors during the resetting stage of the pixel circuit. [Figure 43] Figure 37a is a schematic diagram showing the operation state of the transistors during the data writing stage of the pixel circuit. [Figure 44] Figure 37a is a schematic diagram showing the operating state of the transistor during the light emission stage of the pixel circuit. [Figure 45] This is a schematic flowchart of a method for driving a pixel circuit provided by one embodiment of the present disclosure. [Figure 46]This is a structural diagram of a pixel circuit according to at least one embodiment of the present invention. [Figure 47] This is a structural diagram of a pixel circuit according to at least one embodiment of the present invention. [Figure 48] This is a structural diagram of a pixel circuit according to at least one embodiment of the present invention. [Figure 49] This is a structural diagram of a pixel circuit according to at least one embodiment of the present invention. [Figure 50] This is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 51] Figure 50 of this disclosure is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 52] This is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 53] This is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 54] This is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 55] This is a schematic diagram of the electrical connections between two adjacent rows of the pixel circuit and the same row of the reset voltage line. [Figure 56] This is a schematic diagram of the electrical connections between two adjacent rows of pixel circuits and the same row of reset voltage lines. [Figure 57] This is a schematic diagram of the reset voltage lines shared by the pixel circuits of adjacent rows and columns. [Figure 58] This is a schematic diagram showing the connection and positional relationships between reset voltage lines arranged in a grid and multiple pixel circuits. [Figure 59] This is a structural diagram of a display device according to at least one embodiment of the present disclosure. [Figure 60] This is a structural diagram of a display device according to at least one embodiment of the present disclosure. [Figure 61] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 62]This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 63] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 64] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 65] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 66] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 67] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 68] This is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 69] Figure 68 is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 70] Figure 68 is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 71] Figure 68 is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 72] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 73] Figure 72 is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 74] Figure 72 is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 75] This is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 76] Figure 75 is a timing diagram of the operation of at least one embodiment of the pixel circuit shown. [Figure 77] This is a structural diagram of a display device according to at least one embodiment of the present disclosure. [Figure 78] This is a structural diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0024] Next, exemplary embodiments will be described in more detail with reference to the accompanying drawings. However, exemplary embodiments can be embodied in many forms and should not be construed as being limited to the examples described herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the concepts of the exemplary embodiments to those skilled in the art. Note that the same reference numerals in each figure indicate the same or similar components, and their detailed descriptions are omitted.

[0025] The terms “one,” “one,” and “the aforementioned” are constructed to indicate that there is one or more elements / components, etc., while the terms “including” and “equipped with” are used in a broad, comprehensive sense, meaning that there may be additional elements / components, etc., in addition to those listed.

[0026] Figure 1 is a schematic diagram showing the circuit configuration of a pixel driving circuit in the prior art. This pixel driving circuit may include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The gate of the driving transistor T3 is connected to the first node N1, the first pole is connected to the second node N2, and the second pole is connected to the third node N3. The fourth transistor T4 has its first pole connected to the data signal terminal Da, its second pole connected to the second node N2, and its gate connected to the gate driving signal terminal G2. The fifth transistor T5 has its first pole connected to the first power supply terminal VDD, its second pole connected to the second node N2, and its gate connected to the enable signal terminal EM. The second transistor T2 has its first pole connected to the first node N1, its second pole connected to the third node N3, and its gate connected to the gate driving signal terminal G1. The sixth transistor T6 has its first pole connected to the third node N3, its second pole connected to the first pole of the seventh transistor T7, and its gate connected to the enable signal terminal EM. The seventh transistor T7 has its second pole connected to the second initial signal terminal Vinit2, and its gate connected to the second reset signal terminal Re2. The first transistor T1 has its first pole connected to the first node N1, its second pole connected to the first initial signal terminal Vinit1, and its gate connected to the first reset signal terminal Re1. Capacitor C is connected between the first power supply terminal VDD and the first node N1. This pixel driving circuit can be connected to the light-emitting OLED to drive the light-emitting OLED to emit light. The light-emitting OLED is connected between the second pole of the sixth transistor T6 and the power supply terminal VSS. The first transistor T1 and the second transistor T2 may be N-type transistors. For example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors. Because N-type metal oxide transistors have low leakage current, it is possible to avoid leakage of node N through the first transistor T1 and the second transistor T2 during the light emission stage.On the other hand, the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. For example, the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon transistors. Low-temperature polysilicon transistors have high carrier mobility, which helps in realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals depending on the actual situation.

[0027] Figure 2 is a timing diagram of each node in the driving method of the pixel driving circuit shown in Figure 1. G1 indicates the timing of the gate drive signal terminal G1, G2 indicates the timing of the gate drive signal terminal G2, Re1 indicates the timing of the first reset signal terminal Re1, Re2 indicates the timing of the second reset signal terminal Re2, EM indicates the timing of the enable signal terminal EM, Da indicates the timing of the data signal terminal Da, and N1 indicates the timing of the first node N1. This driving method of the pixel driving circuit may include a first reset stage t1, a threshold compensation stage t2, a second reset stage t3, and an emission stage t4. In the first reset stage t1, the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 turns on, and the first initial signal terminal Vinit1 inputs an initial signal to the first node N1. In threshold compensation stage t2, the gate drive signal terminal G1 outputs a high-level signal, the gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 turn on, and simultaneously, the data signal terminal Da outputs a drive signal to write the voltage Vdata + Vth to node N. Here, Vdata is the voltage of the drive signal, and Vth is the threshold voltage of the drive transistor T3. In second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 turns on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. In light emission stage t4, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 turn on, and the drive transistor T3 emits light due to the action of the voltage Vdata + Vth stored in capacitor C. The formula for the output current of the drive transistor is I = (μWCox / 2L)(Vgs-Vth). 2 According to the documentation, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the channel width of the drive transistor, L is the channel length of the drive transistor, Vgs is the gate-source voltage difference of the drive transistor, and Vth is the threshold voltage of the drive transistor. In the pixel drive circuit of this disclosure, the output current of the drive transistor is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2This pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.

[0028] In related technologies, parasitic capacitance exists between the gate and source of the drive transistor in the pixel drive circuit. During the reset phase, the gate voltage of the drive transistor is initialized to the initialization voltage, and due to the coupling effect of the parasitic capacitance, the source voltage of the drive transistor also changes accordingly. When different grayscale levels are reset during the reset phase, the gate voltage of the drive transistor changes by different amounts, and therefore the source voltage of the drive transistor also changes by different amounts. As a result, after the reset phase is completed, the Vgs (gate-source voltage difference) of the drive transistor is different. Figure 3 shows the simulation timing diagrams of the first, second, and third nodes in the driving method shown in Figure 2 for the pixel drive circuit of Figure 1, where N1 is the timing diagram for the first node N1, N2 is the timing diagram for the second node N2, and N3 is the timing diagram for the third node N3. Figure 3 specifically shows the timing diagrams for each node of the pixel driving circuit shown in Figure 1, based on four types of data signals. In the reset stage t1 of Figure 3, it is necessary to reset the first node N1 based on the four types of data signals. In the exemplary embodiments of this disclosure, the timing of each node based on two types of data signals will be described. As shown in Figure 3, the timing of each node based on the first data signal is shown by curve Vda1, and the timing of each node based on the second data signal is shown by curve Vda2. Because the voltages of the first and second data signals are different, before the reset stage t1, the voltage of the first node N1 is different, the voltage of the third node N3 is also different, and the voltage of the second node is all the voltage of the first power supply terminal VDD. In the reset stage t1, the voltages of the first node N1 based on the two types of data signals are all reduced to the initialization voltage. The pull-down change at the first node N1 due to the first data signal is smaller than the pull-down change at the first node N1 due to the second data signal. Therefore, the pull-down change at the second node due to the first data signal is smaller than the pull-down change at the second node N2 due to the second data signal. In other words, during the reset phase, the voltage at the second node N2 due to the first data signal is lower than the voltage at the second node N2 due to the second data signal. As a result, the drive transistor Vgs (gate-source voltage difference) is different under different data signals.Furthermore, because the Vgs of the drive transistors affects their threshold voltage, display panels can experience afterimages and flickering. For example, when a display panel converts from a grayscale image to an image of the same grayscale, the threshold voltages of the drive transistors in the pixels corresponding to the grayscale image are different. As a result, after conversion to an image of the same grayscale, the area where the previous frame's grayscale image was located will display a different grayscale, resulting in an afterimage problem.

[0029] Based on this, exemplary embodiments of the present disclosure provide a pixel driving circuit. Figure 4 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include a driving circuit 1, a first reset circuit 2, and a second reset circuit 3. The driving circuit 1 is connected to a first node N1 and a second node N2 and outputs a driving current in accordance with the voltage difference between the first node N1 and the second node N2. The first reset circuit 2 is connected to the first node N1, a first initial signal terminal Vinit1, and a first reset signal terminal Re1, and transmits the signal of the first initial signal terminal Vinit1 to the first node N1 in response to the signal of the first reset signal terminal Re1. The second reset circuit 3 is connected to the second node N2 and a first power terminal VGH, and transmits the signal of the first power terminal VGH to the second node N2 in response to a control signal. In exemplary embodiments of this disclosure, the pixel driving circuit, in the reset phase, performs a first reset

[0030] By using circuit 2 to transmit the signal from the first initial signal terminal Vinit1 to the first node N1, and simultaneously using the second reset circuit 3 to transmit the signal from the first power terminal VGH to the second node N2, the pixel driving circuit can reset the gate-source voltage difference of the driving transistors to the same value under different data signals, thereby improving the afterimage and flickering problems of the display panel.

[0031] In exemplary embodiments of the present disclosure, as shown in Figure 4, the drive circuit 1 may be further connected to a third node N3, and the drive circuit 1 may include a drive transistor T3. The drive transistor T3 has its gate connected to the first node N1, its first pole connected to the second node N2, and its second pole connected to the third node N3. The drive transistor T3 may be a P-type transistor, for example, a P-type low-temperature polysilicon transistor, and the drive transistor T3 can input a drive current to the third node in accordance with the voltage difference between the first node N1 and the second node N2. In other exemplary embodiments of the present disclosure, the drive transistor T3 may be an N-type transistor, and if the drive transistor T3 is an N-type transistor, it should be understood that the drive transistor may input a drive current to the second node in accordance with the voltage difference between the first node N1 and the second node N2. Furthermore, the drive circuit 1 may include a plurality of drive transistors, and the plurality of drive transistors may be connected in parallel between the second node and the third node.

[0032] In exemplary embodiments of the present disclosure, as shown in Figure 4, the first reset circuit 2 includes a first transistor T1, the gate of which is connected to a first reset signal terminal Re1, the first pole of which is connected to a first initial signal terminal Vinit1, and the second pole of which is connected to a first node N1. The conduction level of the second reset circuit 3 and the conduction level of the first reset circuit 2 may have the same polarity. The second reset circuit 3 may be further connected to the first reset signal terminal Re1 and configured to transmit a signal from the first power terminal VGH to the second node N2 in response to a signal from the first reset signal terminal Re1. As shown in Figure 4, the second reset circuit 3 includes an eighth transistor T8, the gate of which is connected to a first reset signal terminal Re1, the first pole of which is connected to the first power terminal VGH, and the second pole of which is connected to the second node N2.

[0033] It should be noted that, since this pixel driving circuit requires the driving transistor T3 to be turned on during the threshold compensation stage, the voltage difference Vinit1-Vgh between the first initial signal terminal Vinit1 and the first power supply terminal VGH must be smaller than the threshold voltage of the driving transistor T3. Here, Vinit1 is the voltage at the first initial signal terminal, and Vgh is the voltage at the first power supply terminal VGH. In another exemplary embodiment, the second reset circuit 3 may also reset the second node by transmitting signals from other signal terminals to the second node in response to a control signal.

[0034] In exemplary embodiments of this disclosure, both the first transistor T1 and the eighth transistor T8 may be oxide transistors. For example, the semiconductor material of the first transistor T1 and the eighth transistor T8 may be indium gallium zinc oxide (InGaZnO), and accordingly, the first transistor T1 and the eighth transistor T8 may be N-type transistors. Because oxide transistors have a low turn-off leakage current, the leakage current at the first node N1 via the first transistor T1 and the leakage current at the second node N2 via the eighth transistor T8 can be reduced.

[0035] It should be understood that in other exemplary embodiments of the present disclosure, the conduction levels of the second reset circuit 3 and the first reset circuit 2 may have opposite polarities. For example, Figure 5 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The second reset circuit 3 may also be connected to a second reset signal terminal Re2 and configured to transmit a signal from the first power terminal VGH to a second node N2 in response to a signal from the second reset signal terminal Re2. The polarity of the signal from the second reset signal terminal Re2 may be opposite to the polarity of the signal from the first reset signal terminal Re1. The first reset circuit 2 includes an N-type first transistor T1, the gate of which is connected to the first reset signal terminal Re1, the first pole of which is connected to the first initial signal terminal Vinit1, and the second pole of which is connected to the first node N1. The second reset circuit 3 includes a P-type eighth transistor T8, the eighth transistor T8 having its gate connected to the second reset signal terminal Re2, its first pole connected to the first power supply terminal VGH, and its second pole connected to the second node N2.

[0036] In an exemplary embodiment of the present disclosure, Figure 6 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may further include a control circuit 5 and a coupling circuit 6. The control circuit 5 is connected to a second power terminal VDD, a second node N2, a third node N3, a fourth node N4 and an enable signal terminal EM, and is configured to transmit a signal from the second power terminal VDD to the second node N2 in response to a signal from the enable signal terminal EM, and to connect the third node N3 and the fourth node N4 in response to a signal from the enable signal terminal EM. The coupling circuit 6 is connected between the second power terminal VDD and the first node N1.

[0037] In exemplary embodiments of the present disclosure, as shown in Figure 6, the pixel driving circuit may further include a data writing circuit 7 and a threshold compensation circuit 8. The data writing circuit 7 is connected to a second node N2, a data signal terminal Vdata, and a first gate drive signal terminal G1, and is configured to transmit the signal at the data signal terminal Vdata to the second node N2 in response to the signal at the first gate drive signal terminal G1. The threshold compensation circuit 8 is connected to a first node N1 and a third node N3, and is configured to communicate the first node N1 and the third node N3 in response to a control signal. The data writing circuit 7 and the threshold compensation circuit 8 are configured to turn on during the threshold compensation stage and write a compensation voltage Vdata + Vth to the first node N1, where Vdata is the voltage at the data signal terminal and Vth is the threshold voltage of the driving transistor. It should be understood that in other exemplary embodiments of the present disclosure, there are other ways of writing the compensation voltage to the first node N1. For example, the data writing circuit may be connected to the third node N3, the data signal terminal Vdata, and the first gate drive signal terminal G1, and transmit the signal from the data signal terminal Vdata to the third node N3 in response to the signal from the first gate drive signal terminal G1. The threshold compensation circuit 8 may be connected to the first node N1 and the second node N2, and configured to communicate the first node N1 and the second node N2 in response to a control signal. When the data writing circuit 7 and the threshold compensation circuit 8 are turned on, the pixel drive circuit can also write the compensation voltage Vdata + Vth to the first node N1.

[0038] In exemplary embodiments of the present disclosure, as shown in Figure 6, the fourth node N4 is connected to a light-emitting section OLED, which is a light-emitting diode, and the other electrode of the light-emitting section OLED is connected to a fourth power terminal VSS. The voltage at the fourth power terminal VSS is lower than the voltage at the second power terminal VDD. The pixel driving circuit may further include a third reset circuit 4 connected to the fourth node N4 and a second initial signal terminal Vinit2, which transmits a signal from the second initial signal terminal Vinit2 to the fourth node N4 in response to a control signal. By writing an initial signal to the fourth node N4, carriers that do not recombine at the light-emitting interface inside the light-emitting diode can be removed, thereby reducing the degradation of the light-emitting diode over time.

[0039] In exemplary embodiments of the present disclosure, the control circuit 5 may include a fifth transistor T5 and a sixth transistor T6, as shown in Figure 6. The gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first pole is connected to the second power supply terminal VDD, and the second pole is connected to the second node N2. The gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first pole is connected to the third node N3, and the second pole is connected to the fourth node N4. The coupling circuit 6 may include a third capacitor C3 connected between the second power supply terminal VDD and the first node N1.

[0040] In exemplary embodiments of the present disclosure, as shown in Figure 6, the polarity of the conduction levels of the threshold compensation circuit 8 and the data writing circuit 7 may be reversed. The threshold compensation circuit 8 is further connected to a second gate drive signal terminal G2 and configured to connect a first node N1 and a third node N3 in response to a signal at the second gate drive signal terminal G2. The polarity of the signal at the first gate drive signal terminal G1 and the signal at the second gate drive signal terminal G2 may be reversed. The data writing circuit 7 includes a fourth transistor T4, the gate of which is connected to the first gate drive signal terminal G1, the first pole of which is connected to the data signal terminal Vdata, and the second pole of which is connected to the second node N2. The threshold compensation circuit 8 includes a second transistor T2, the gate of which is connected to the second gate drive signal terminal G2, the first pole of which is connected to the first node N1, and the second pole of which is connected to the third node N3. The fourth transistor T4 may be a P-type transistor, for example, a P-type low-temperature polysilicon transistor. Low-temperature polysilicon transistors have high carrier mobility, which improves the response speed of the fourth transistor T4. The second transistor T2 may be an N-type transistor, for example, an oxide transistor, and the semiconductor material of the second transistor T2 may be indium gallium zinc oxide (InGaZnO). By making the second transistor T2 an oxide transistor, the leakage current of the pixel driving circuit passing through the second transistor at the first node N1 of the light-emitting node can be reduced.

[0041] In other exemplary embodiments, both the fourth transistor T4 and the second transistor T2 may be N-type or P-type transistors, and accordingly, the fourth transistor T4 and the second transistor T2 may share the same gate drive signal terminal.

[0042] In exemplary embodiments of the present disclosure, as shown in Figure 6, the third reset circuit 4 may be further connected to the third reset signal terminal Re3 and configured to transmit the signal from the second initial signal terminal Vinit2 to the fourth node N4 in response to the signal from the third reset signal terminal Re3. The third reset circuit 4 includes a seventh transistor T7, the seventh transistor T7 having its gate connected to the third reset signal terminal Re3, its first pole connected to the second initial signal terminal Vinit2, and its second pole connected to the fourth node N4. The seventh transistor T7 may be a P-type transistor, for example, the seventh transistor T7 may be a P-type low-temperature polysilicon transistor, which has high carrier mobility and therefore improves the response speed of the seventh transistor T7.

[0043] In an exemplary embodiment of the present disclosure, as shown in Figure 6, the first pole of the eighth transistor T8 and the first pole of the fifth transistor T5 are connected to different power supply terminals. Figure 7 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. In other exemplary embodiments of the present disclosure, the first pole of the eighth transistor T8 and the first pole of the fifth transistor T5 may be connected to the same power supply terminal, i.e., the second power supply terminal VDD may be shared with the first power supply terminal VGH.

[0044] Figure 8 is a timing diagram of each node in the pixel driving circuit driving method of Figure 7. G1 indicates the timing of the first gate driving signal terminal, G2 indicates the timing of the second gate driving signal terminal, Re1 indicates the timing of the first reset signal terminal, Re3 indicates the timing of the third reset signal terminal, and EM represents the timing of the enable signal terminal. The pixel driving circuit driving method may include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light emission stage t4. In reset stage t1, the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal output high-level signals, the second gate drive signal terminal G2, and the third reset signal terminal Re3 output low-level signals, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, the first power supply terminal VDD inputs the power supply signal to the second node N2, and the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node, and the voltages of the first and second initial signals may be the same or different. In threshold compensation stage t2, the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal output high-level signals, the first reset signal terminal Re1, and the first gate drive signal terminal G1 output low-level signals, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Vdata writes the compensation voltage Vdata+Vth to the first node N1. Here, Vdata is the voltage at the data signal terminal, and Vth is the threshold voltage of the drive transistor. In buffer stage t3, the enable signal terminal EM, the third reset signal terminal Re3, and the first gate drive signal terminal G1 output high-level signals, while the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals, and all transistors turn off. In light emission stage t4, the third reset signal terminal Re3 and the first gate drive signal terminal G1 output high-level signals, while the enable signal terminal EM, the second gate drive signal terminal G2, and the first reset signal terminal Re1 output low-level signals, turning on the fifth transistor T5 and the sixth transistor T6, and causing the drive transistor T3 to emit light due to the action of the voltage Vdata + Vth stored in the third capacitor C3.It should be understood that in other exemplary embodiments of this disclosure, the driving method does not have to include a buffering stage, and the first transistor T1 and the seventh transistor T7 may be turned on at different stages. In the threshold compensation stage t2, the duration of the active level (low level) of the first gate drive signal terminal G1 may be shorter than the duration of the active level (high level) of the second gate drive signal terminal G2. In the threshold compensation stage t2, the first gate drive signal terminal G1 can scan one row of pixel drive circuitry, and the second gate drive signal terminal G2 can scan multiple rows of pixel drive circuitry (e.g., two rows of pixel drive circuitry) one row at a time.

[0045] Figure 9 is a simulation timing diagram of the first, second, and third nodes in the pixel driving circuit of Figure 7 in the driving method shown in Figure 8. N1 shows the timing diagram of the first node N1, N2 shows the timing diagram of the second node N2, and N3 shows the timing diagram of the third node N3. Figure 9 specifically shows the timing diagrams of each node of the pixel driving circuit shown in Figure 7 with four types of data signals. In the reset stage t1 of Figure 9, it is necessary to reset the first node N1 with four types of data signals. In exemplary embodiments of this disclosure, the timing of each node with two types of data signals will be described. As shown in Figure 9, the timing of each node with the first data signal is shown by curve Vda1, and the timing of each node with the second data signal is shown by curve Vda2. As shown in Figure 9, since the voltages of the first data signal and the second data signal are different, before the reset stage t1, the voltage of the first node N1 is different, the voltage of the third node N3 is also different, and the voltage of the second node is all the voltage of the first power supply terminal VDD. In the reset phase t1, the voltages at the first node N1, based on the two data signals, are all reduced to the voltage of the first initial signal, and the voltage at the second node N2 is also initialized to the voltage of the first power supply terminal VDD. Therefore, at the end of the reset phase, the gate-source voltage difference of the drive transistor based on the first data signal becomes equal to the gate-source voltage difference of the drive transistor based on the second data signal, and this pixel drive circuit can improve the afterimage problem caused by the different gate-source voltage differences of drive transistors based on different data signals.

[0046] Exemplary embodiments of this disclosure further provide a method for driving a pixel driver circuit that drives the pixel driver circuit described above. This driving method includes the following steps:

[0047] During the reset phase, the signal from the first initial signal terminal Vinit1 is transmitted to the first node N1 by the first reset circuit 2, while the signal from the first power terminal VGH is transmitted to the second node N2 by the second reset circuit 3. The pixel driving method has been explained in detail above, so it will not be repeated here.

[0048] Exemplary embodiments of this disclosure further provide a display panel comprising the pixel driving circuit described above. The display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.

[0049] As shown in Figure 1, in the conventional technology, parasitic capacitance exists between the first node N1 and the gate drive signal terminal G1. As shown in Figure 2, at the end of the threshold compensation stage t2, the signal at the gate drive signal terminal G1 changes from a high level to a low level, and due to the coupling effect of the parasitic capacitance, the voltage at the first node N1 is pulled down by the gate drive signal terminal G1. As a result, it becomes impossible to display 0 grayscale (black image) at the maximum voltage of the data signal terminal. In other words, to display 0 grayscale normally, a larger voltage signal needs to be applied to the data signal terminal.

[0050] Based on this, exemplary embodiments of the present disclosure provide a pixel driving circuit. Figure 10 is a structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include a driving transistor T3, a data writing circuit 7, a threshold compensation circuit 8, a first capacitor C1, and a second capacitor C2. The driving transistor T3 has its gate connected to a first node N1, its first pole connected to a second node N2, and its second pole connected to a third node N3. The data writing circuit 7 is connected to the second node N2 and a data signal terminal Vdata and is configured to transmit the signal at the data signal terminal Vdata to the second node N2 in response to the signal at the first gate driving signal terminal G1. The threshold compensation circuit 8 is connected to the first node N1, the third node N3, and the second gate driving signal terminal G2 and is configured to communicate the first node N1 and the third node N3 in response to the signal at the second gate driving signal terminal G2. The first capacitor C1 is connected between the first node N1 and the first gate drive signal terminal G1. The second capacitor C2 is connected between the first node N1 and the second gate drive signal terminal G2. The conduction level of the data writing circuit 7 is low, the conduction level of the threshold compensation circuit 8 is high, and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2.

[0051] In exemplary embodiments of this disclosure, during the threshold compensation stage, the first gate drive signal terminal G1 outputs a low-level signal and the second gate drive signal terminal G2 outputs a high-level signal, allowing the compensation voltage Vdata + Vth to be written to the first node N1, where Vdata is the voltage at the data signal terminal and Vth is the threshold voltage of the drive transistor T3. After the threshold compensation stage is completed, the signal at the first gate drive signal terminal G1 changes from low to high, and due to the coupling effect of the first capacitor C1, the first node N1 is pulled up by the first gate drive signal terminal G1, and the signal at the second gate drive signal terminal G2 changes from high to low, and due to the coupling effect of the second capacitor C2, the first node N1 is pulled down by the second gate drive signal terminal G2. Since the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2, the first node N1 as a whole is pulled up. Therefore, the source drive circuit, which is provided in conjunction with the pixel drive circuit, can achieve the display of the pixel drive circuit's limit gradation (minimum or maximum gradation) simply by supplying a small voltage signal to the data signal terminal, meaning that the power consumption of the display panel to which this pixel drive circuit is applied is relatively low.

[0052] In exemplary embodiments of this disclosure, the drive transistor T3 may be a P-type transistor, for example, a P-type low-temperature polysilicon transistor. When the drive transistor T3 is a P-type transistor, the higher the voltage at the first node N1, the smaller the output current of the drive transistor T3, i.e., the pixel drive circuit can lower the voltage of the data signal output by the source drive circuit at 0 grayscale. It should be understood that in other exemplary embodiments of this disclosure, the drive transistor T3 may be an N-type transistor. When the drive transistor T3 is an N-type transistor, the higher the voltage at the first node N1, the larger the output current of the drive transistor T3, i.e., the pixel drive circuit can lower the voltage of the data signal output by the source drive circuit at maximum grayscale.

[0053] In exemplary embodiments of this disclosure, when the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C1 / C2 may be between 1.5 and 4. For example, C1 / C2 may be 1.5, 2, 2.3, 2.5, 3, 3.5, or 4. The larger the value of C1 / C2, the more pronounced the effect of pulling up the first node N1 becomes. [Table 1]

[0054] As shown in the table above, Vdata-L0 represents the voltage of the data signal required by each sub-pixel of each color at level 0, ΔV represents the difference between the maximum output voltage of the source drive circuit and the maximum voltage of the data signal required at level 0, with the maximum output voltage of the source drive circuit being 6.89V. The multiple data points corresponding to C1 / C2 values ​​of 1.35, 1.73, 2.05, and 2.3 are multiple data points based on the same design structure (same structure except for differences in C1 / C2), while the data point corresponding to C1 / C2 value 2.2 is data from a different design structure. As can be seen from this table, under the same design structure, the larger the C1 / C2, the more pronounced the effect of pulling up the first node N1 becomes, and therefore the lower the voltage of the data signal required at level 0.

[0055] In exemplary embodiments of the present disclosure, as shown in Figure 10, the data writing circuit 7 may include a P-type fourth transistor T4, which may be, for example, a P-type low-temperature polysilicon transistor. The gate of the fourth transistor T4 is connected to a first gate drive signal terminal G1, a first pole is connected to a second node N2, and a second pole is connected to a data signal terminal Vdata. The threshold compensation circuit 8 may include an N-type second transistor T2, which may be, for example, an N-type oxide transistor, and the semiconductor material of the oxide transistor may be indium gallium zinc oxide (InGaZnO). The gate of the second transistor T2 is connected to a second gate drive signal terminal G2, a first pole is connected to a first node N1, and a second pole is connected to a third node N3.

[0056] In an exemplary embodiment of the present disclosure, Figure 11 is a schematic diagram of another exemplary embodiment of the pixel driver circuit of the present disclosure. The pixel driver circuit may further include a control circuit 5 and a coupling circuit 6. The control circuit 5 is connected to a second power terminal VDD, a second node N2, a third node N3, a fourth node N4, and an enable signal terminal EM, and is configured to transmit a signal from the second power terminal VDD to the second node N2 in response to a signal from the enable signal terminal EM, and to connect the third node N3 and the fourth node N4 in response to a signal from the enable signal terminal EM. The coupling circuit 6 is connected between the first node N1 and the second power terminal VDD. In another exemplary embodiment of the present disclosure, it should be understood that the control circuit 5 may be configured to transmit a signal from the second power terminal VDD to the third node N3 in response to a signal from the enable signal terminal EM, and to connect the second node N2 and the fourth node N4 in response to a signal from the enable signal terminal EM.

[0057] In exemplary embodiments of the present disclosure, as shown in Figure 11, the pixel driving circuit may further include a first reset circuit 2. The first reset circuit 2 may be connected to a first node N1, a first initial signal terminal Vinit1, and a first reset signal terminal Re1, and may be configured to transmit the signal from the first initial signal terminal Vinit1 to the first node N1 in response to the signal from the first reset signal terminal Re1.

[0058] In exemplary embodiments of the present disclosure, as shown in Figure 11, the fourth node N4 is configured to be connected to the light-emitting OLED, and the pixel driving circuit may further include a third reset circuit 4, which is connected to the fourth node N4, a second initial signal terminal Vinit2, and a third reset signal terminal Re3, and is configured to transmit the signal from the second initial signal terminal Vinit2 to the fourth node N4 in response to the signal from the third reset signal terminal Re3. The other end of the light-emitting OLED is connected to a third power terminal VSS, and the light-emitting OLED may be a light-emitting diode. By writing an initial signal to the fourth node N4, carriers that do not recombine at the light-emitting interface inside the light-emitting diode can be removed, thereby reducing the degradation of the light-emitting diode over time.

[0059] In exemplary embodiments of the present disclosure, as shown in Figure 11, the coupling circuit 6 may include a third capacitor C3 connected between a first node N1 and a second power supply terminal VDD, wherein the capacitance value of the third capacitor C3 is greater than that of the first capacitor C1 and greater than that of the second capacitor C2. By setting the capacitance value of the third capacitor C3 to a larger value, the charge storage capacitance of the third capacitor C3 can be increased, thereby extending the maximum duration of the light-emitting phase. The control circuit 5 may include a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first pole is connected to the second power supply terminal VDD, and the second pole is connected to the second node N2. The gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first pole is connected to the third node N3, and the second pole is connected to the fourth node N4. The first reset circuit 2 includes a first transistor T1, the gate of which is connected to the first reset signal terminal Re1, the first pole connected to the first initial signal terminal Vinit1, and the second pole connected to the first node N1. The third reset circuit 4 includes a seventh transistor T7, the gate of which is connected to the third reset signal terminal Re3, the first pole connected to the second initial signal terminal Vinit2, and the second pole connected to the fourth node N4. The first transistor T1 and the second transistor T2 may be N-type transistors, and the semiconductor material of the N-type transistors may be indium gallium zinc oxide (InGaZnO). Oxide transistors have a small turn-off leakage current, which can reduce the leakage current at the first node N1 via the first transistor T1 and the second transistor T2 during the light emission stage. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. For example, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon transistors. Low-temperature polysilicon transistors have high carrier mobility, which helps in realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio.

[0060] Figure 12 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may further include a second reset circuit 3, which is connected to a second node N2 and a first power terminal VGH, and transmits a signal from the first power terminal VGH to the second node N2 in response to a control signal. In the exemplary embodiment of the present disclosure, the conduction level of the first reset circuit may be opposite in polarity to the conduction level of the third reset circuit, the signal from the first reset signal terminal Re1 may be opposite in polarity to the signal from the third reset signal terminal Re3, and the conduction level of the second reset circuit 3 may be opposite in polarity to the conduction level of the first reset circuit 2. The second reset circuit 3 may also be connected to a third reset signal terminal Re3 and configured to transmit a signal from the first power terminal VGH to the second node N2 in response to a signal from the third reset signal terminal Re3.

[0061] In exemplary embodiments of this disclosure, parasitic capacitance exists between the gate and source of a drive transistor in a pixel drive circuit. In the pixel drive circuit, during the reset phase, the gate voltage of the drive transistor is initialized to the initialization voltage, and due to the coupling effect of the parasitic capacitance, the source voltage of the drive transistor also changes accordingly. When different grayscale levels are reset during the reset phase, the gate voltage of the drive transistor changes by different amounts, and therefore the source voltage of the drive transistor also changes by different amounts. As a result, after the reset phase is completed, the Vgs (gate-source voltage difference) of the drive transistor is different. Furthermore, because the Vgs of the drive transistor affects its threshold voltage, afterimage problems occur in the display panel. For example, when a display panel converts from a grayscale image to an image of the same grayscale level, the threshold voltage of the drive transistor in the pixel corresponding to the grayscale image is different. Therefore, after conversion to an image of the same grayscale level, the area where the grayscale image of the previous frame was located displays a different grayscale, i.e., afterimage problems occur. In exemplary embodiments of this disclosure, the pixel driving circuit uses a first reset circuit 2 to transmit a signal from the first initial signal terminal Vinit1 to the first node N1 during the reset phase, and simultaneously uses a second reset circuit 3 to transmit a signal from the first power terminal VGH to the first node N1. This allows the pixel driving circuit to reset the gate-source voltage difference of the driving transistors to the same value under different data signals, thereby improving the afterimage problem of the display panel.

[0062] In exemplary embodiments of this disclosure, the second reset circuit 3 may include an eighth transistor T8, the gate of which is connected to a third reset signal terminal Re3, the first pole connected to a first power terminal VGH, and the second pole connected to a second node N2, and the eighth transistor T8 may be a P-type transistor. In other exemplary embodiments of this disclosure, the conduction levels of the second reset circuit and the first reset circuit may have the same polarity, and the second reset circuit may be connected to the first reset signal terminal and transmit the signal at the first power terminal VGH to the second node in response to the signal at the first reset signal terminal. Correspondingly, the eighth transistor may be an N-type transistor, and the semiconductor material of the N-type transistor may be indium gallium zinc oxide (InGaZnO). The first power terminal VGH may be shared with the second power terminal VDD, for example, the second reset circuit may be connected to the second power terminal VDD.

[0063] Figure 13 is a timing diagram of each node in the pixel driving circuit driving method of Figure 12. G1 indicates the timing of the first gate drive signal terminal, G2 indicates the timing of the second gate drive signal terminal, Re1 indicates the timing of the first reset signal terminal, Re3 indicates the timing of the third reset signal terminal, and EM represents the timing of the enable signal terminal. The pixel driving circuit driving method can include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light emission stage t4. In reset stage t1, the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal output high-level signals, the second gate drive signal terminal G2, and the third reset signal terminal Re3 output low-level signals, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, the first power supply terminal VDD inputs the power supply signal to the second node N2, and the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node. The voltages of the first and second initial signals may be the same or different. In threshold compensation stage t2, the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal output high-level signals, while the first reset signal terminal Re1 outputs a low-level signal. For at least a portion of the threshold compensation stage t2, the first gate drive signal terminal G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Vdata writes the compensation voltage Vdata + Vth to the first node N1. Here, Vdata is the voltage at the data signal terminal, and Vth is the threshold voltage of the drive transistor. In buffer stage t3, the enable signal terminal EM, the third reset signal terminal Re3, and the first gate drive signal terminal G1 output high-level signals, while the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals, and all transistors are turned off.In the light emission stage t4, the third reset signal terminal Re3 and the first gate drive signal terminal G1 output high-level signals, the enable signal terminal EM, the second gate drive signal terminal G2, and the first reset signal terminal Re1 output low-level signals, the fifth transistor T5 and the sixth transistor T6 turn on, and the drive transistor T3 emits light due to the action of the voltage Vdata + Vth stored in the capacitor C. In exemplary embodiments of this disclosure, in the threshold compensation stage t2, the duration of the active level (low level) of the first gate drive signal terminal G1 may be shorter than the duration of the active level (high level) of the second gate drive signal terminal G2. In the threshold compensation stage t2, the first gate drive signal terminal G1 can scan one row of pixel drive circuitry, and the second gate drive signal terminal G2 can scan multiple rows of pixel drive circuitry one row at a time. For example, the gate drive signal terminal G2 can scan two rows of pixel drive circuitry one row at a time. In other exemplary embodiments of this disclosure, the drive method does not have to include a buffering stage, and the first transistor T1 and the seventh transistor T7 may be turned on at different stages. The duration of the active level (low level) of the first gate drive signal terminal G1 may be equal to the duration of the active level (high level) of the second gate drive signal terminal G2.

[0064] Figure 14 is a schematic diagram of another exemplary embodiment of the pixel driver circuit of the present disclosure. The pixel driver circuit may further include a fourth capacitor C4 whose first electrode is connected to a second node N2. The pixel driver circuit is configured such that, in the light emission phase, the second power terminal VDD can charge the fourth capacitor C4, and the fourth capacitor C4 can maintain a high level at the start of the reset phase, thereby speeding up the rate at which the first power terminal VGH writes a high-level signal to the second node N2 in the reset phase. The second electrode of the fourth capacitor C4 is connected to a fifth node N5, and if the equipotential conduction portion of the fifth node N5 has a pull-down operation before or at the start of the threshold compensation phase, the fifth node N5 has a pull-down effect on the second node N2, resulting in a voltage difference at the second node N2 at different locations on the display panel. For example, the equipotential conduction portion of the fifth node N5 may be a first gate line providing the first gate drive signal terminal G1, and the first gate line may partially overlap with the equipotential conduction portion of the second node N2, and a portion of the structure of the first gate line may be used to form the second electrode of the fourth capacitor C4. The first gate line changes from a high level to a low level at the start of the threshold compensation stage, and as a result, the first gate line pulls down the voltage of the second node N2. Exemplary embodiments of this disclosure can reduce the pull-down effect of the first gate line on the second node N2 by reducing the overlap area between the equipotential conduction portion of the second node N2 and the first gate line as much as possible. The capacitance value C4 of the fourth capacitor C4 may be smaller than the capacitance value of the second capacitor C2, and the fourth capacitor C4 may be 0.5fF to 4fF, for example, 0.5fF, 2fF, or 4fF. The capacitance value C4 of the fourth capacitor C4 may be less than half the capacitance value of the first capacitor C1. For example, the capacitance value C4 of the fourth capacitor C4 may be 1 / 3, 1 / 4, or 1 / 5 of the capacitance value of the first capacitor C1.

[0065] In exemplary embodiments of this disclosure, as shown in Figures 12 and 14, the pixel driving circuit needs to turn on the driving transistor T3 in the threshold compensation stage, so the voltage difference Vinit1-Vgh between the first initial signal terminal Vinit1 and the first power supply terminal VGH must be lower than the threshold voltage Vth of the driving transistor T3. Here, Vinit1 is the voltage at the first initial signal terminal and Vgh is the voltage at the first power supply terminal VGH. Here, Vinit1 may be -2 to -6V, for example -2V, -3V, -4V, -5V, -6V, etc. Vinit1-Vgh may be less than a*Vth, and a may be 2 to 7, for example a may be 2, 4, 6, 7. Vth may be -2 to -5V, for example -2V, -3V, -5V, etc. Vgh may be greater than 1.5 times Vth, for example Vgh may be 1.6 times, 1.8 times, 2 times Vth, etc.

[0066] Figure 15 is a distribution diagram of pixel driver circuits in an exemplary embodiment of a display panel of the present disclosure. Two adjacent rows of pixel circuits can be connected to a first power line VGH extending in the same column direction, the first power line VGH providing a first power terminal to the pixel driver circuit, and the first power line VGH can be located between the aforementioned two adjacent rows of pixel driver circuits. As shown in Figure 15, two pixel circuits located in adjacent columns within the same pixel row can be arranged mirror-image to facilitate wiring.

[0067] Figure 16 is a distribution diagram of pixel driver circuits in another exemplary embodiment of a display panel of the present disclosure. Two adjacent rows of pixel circuits can be connected to a first power line VGH extending in the same row direction, the first power line VGH providing a first power terminal to the pixel driver circuit, and the first power line VGH can be located between the aforementioned two adjacent rows of pixel driver circuits. As shown in Figure 16, two pixel circuits located in adjacent columns within the same pixel row can be arranged mirror-image to facilitate wiring.

[0068] Figure 17 is a distribution diagram of pixel driving circuits in another exemplary embodiment of a display panel of the present disclosure. The display panel includes a plurality of pixel driving circuits P distributed in an array and a plurality of first power lines VGH11, VGH12, VGH21, VGH22 providing first power terminals. As shown in Figure 17, the first power lines VGH11, VGH12 extend in the column direction, and the first power lines VGH21, VGH22 extend in the row direction. Pixel circuits in two adjacent rows are connected to the same first power line extending in the row direction, and the first power line VGH is located between the above-mentioned two adjacent rows of pixel driving circuits. The first power line extending in the column direction is connected to a plurality of first power lines extending in the row direction that intersect it, and the plurality of power lines can form a grid structure. The first power line extending in the column direction may be located in the region where the red pixel driving circuit is located. Furthermore, in the same pixel row, two pixel circuits located in adjacent columns can be placed mirror-image to facilitate wiring.

[0069] Exemplary embodiments of this disclosure further provide a method for driving a pixel driver circuit that drives the pixel driver circuit described above. This driving method includes the following steps:

[0070] During the reset phase, high-level signals are input to the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal G1, while low-level signals are input to the second gate drive signal terminal G2 and the third reset signal terminal Re3.

[0071] During the threshold compensation phase, high-level signals are input to the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal Re3, while low-level signals are input to the first reset signal terminal Re1 and the first gate drive signal terminal G1.

[0072] During the light emission phase, high-level signals are input to the third reset signal terminal Re3 and the first gate drive signal terminal G1, while low-level signals are input to the enable signal terminal EM, the second gate drive signal terminal G2, and the first reset signal terminal Re1.

[0073] This drive method has been explained in detail above, so it will not be repeated here.

[0074] Exemplary embodiments of the present disclosure further provide a display panel comprising the pixel driving circuit described above. The display panel can be applied to display devices such as mobile phones, tablet computers, and televisions. The pixel driving circuit of the display panel may be configured as shown in Figure 10. The display panel includes, in order, a base substrate, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer, with insulating layers interposed between each of the above-mentioned hierarchical structures. As shown in Figures 18 to 25, Figure 18 is a partial structural layout of an exemplary embodiment of a display panel of the present disclosure; Figure 19 is a diagram showing the structural layout of the first conductive layer in Figure 18; Figure 20 is a diagram showing the structural layout of the second conductive layer in Figure 18; Figure 21 is a diagram showing the structural layout of the second active layer in Figure 18; Figure 22 is a diagram showing the structural layout of the third conductive layer in Figure 18; Figure 23 is a diagram showing the structural layout of the fourth conductive layer in Figure 18; Figure 24 is a diagram showing the structural layout of the first conductive layer, the second conductive layer and the second active layer in Figure 18; and Figure 25 is a diagram showing the structural layout of the first conductive layer, the second conductive layer, the second active layer and the third conductive layer in Figure 18.

[0075] As shown in Figures 18, 19, and 24, the first conductive layer may include a first conductive portion 11 and a first gate line G1, the first conductive portion 11 being used to form the gate of the drive transistor T3, the orthographic projection of the first gate line G1 on the base substrate may extend along a first direction X, and the first gate line G1 may be connected to the gate of a fourth transistor T4, for example, a portion of the structure of the first gate line G1 can be used to form the gate of the fourth transistor.

[0076] As shown in Figures 18, 20, and 24, the second conductive layer may include a second gate line 2G2, the orthographic projection of the second gate line 2G2 on the base substrate may extend along a first direction X, and the second gate line 2G2 may be connected to the gate of the second transistor, for example, a portion of the structure of the second gate line 2G2 can be used to form the bottom gate of the second transistor.

[0077] As shown in Figures 18, 21, and 24, the second active layer may include a first active portion 71, a second active portion 72, and a third active portion 73, the second active portion 72 being connected between the first active portion 71 and the third active portion 73, the first active portion 71 being used to form the channel region of the second transistor T2, and the orthogonal projection of the second gate line 2G2 on the base substrate may cover the orthogonal projection of the first active portion 71 on the base substrate. The material of the second active layer may be indium gallium zinc oxide (InGaZnO).

[0078] As shown in Figures 18, 22, and 25, the third conductive layer may include a third gate line 3G2, the orthographic projection of the third gate line 3G2 on the base substrate extends along the first direction X, the orthographic projection of the third gate line 3G2 on the base substrate can cover the orthographic projection of the first active portion 71 on the base substrate, and a part of the structure of the third gate line 3G2 can be used to form the top gate of the second transistor. The display panel can use the third conductive portion as a mask to perform a conductive treatment on the second active layer. That is, the region of the second active layer covered by the third conductive layer forms the channel region of the transistor, and the region of the second active layer not covered by the third conductive layer forms the conductor structure.

[0079] As shown in Figures 18 and 23, the fourth conductive layer includes a connection portion 41, which may be connected to the first conductive portion 11 through a via hole H1 and to the third active portion 73 through a via hole H2.

[0080] Figure 26 is a partial cross-sectional view along the dotted line A in Figure 18. This display panel may further include a first insulating layer 92, a second insulating layer 93, a third insulating layer 94, and a dielectric layer 95, and the base substrate 91, first conductive layer, first insulating layer 92, second conductive layer, second insulating layer 93, second active layer, third insulating layer 94, third conductive layer, dielectric layer 95, and fourth conductive layer are laminated in order. The first insulating layer 92, second insulating layer 93, and third insulating layer 94 may include silicon oxide layers, and the dielectric layer 95 may include silicon nitride layers. The material of the fourth conductive layer may include a metallic material, which may be, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate.

[0081] As shown in Figures 18 to 26, the first gate line G1 may include a first extension G11, and the orthographic projection of the first extension G11 on the base substrate may overlap with the orthographic projection of the third active portion 73 on the base substrate. The extension G11 is used to form the first electrode of the first capacitor C1, and the third active portion 73 is used to form the second electrode of the first capacitor C1. The second gate line 2G2 may include a second extension 2G22, and the orthographic projection of the second extension 2G22 on the base substrate overlaps with the orthographic projection of the second active portion 72 on the base substrate, while the orthographic projection of the third gate line 3G2 on the base substrate is located on one side of the orthographic projection of the second active portion 72 on the base substrate, that is, the orthographic projection of the third gate line 3G2 on the base substrate does not overlap with the orthographic projection of the second active portion 72 on the base substrate. For example, as shown in Figure 18, the orthographic projection of the third gate line 3G2 on the base substrate is located on the second direction Y side of the orthographic projection of the second active portion 72 on the base substrate, and the second direction Y may intersect with the first direction X, for example, the second direction Y may be perpendicular to the first direction X. The second extension portion 2G22 may be used to form a part of the first electrode of the second capacitor C2, and the second active portion 72 may be used to form a part of the second electrode of the second capacitor C2. The third gate line 3G2 may include a third extension portion 3G23, and the connection portion 41 may include a fourth extension portion 414, and the orthographic projection of the third extension portion 3G23 on the base substrate may overlap with the orthographic projection of the fourth extension portion 414 on the base substrate, and the third extension portion 3G23 may be used to form a part of the first electrode of the second capacitor C2, and the fourth extension portion 414 may be used to form a part of the second electrode of the second capacitor C2. The size of the third active portion 73 on the base substrate in the first direction X of the orthographic projection may be larger than the size of the second active portion 72 on the base substrate in the first direction X of the orthographic projection. This setting allows for a larger capacitance value of the first capacitor C1, and in exemplary embodiments of this disclosure, the capacitance value of the first capacitor can be adjusted by adjusting the size of the third active portion 73 on the base substrate in the first direction X of the orthographic projection. The size of the third active portion 73 on the base substrate in the first direction X of the orthographic projection may be 5 μm to 20 μm, for example, 5 μm, 9.7 μm, 12 μm, 15.55 μm, 50 μm, etc.Furthermore, in exemplary embodiments of this disclosure, the capacitance value of the first capacitor C1 can also be adjusted by adjusting the thickness of the first insulating layer 92 and the second insulating layer 93 in the third active portion 73. For example, in exemplary embodiments of this disclosure, the capacitance value of the first capacitor C1 can be increased by reducing the thickness of the first insulating layer 92 and / or the second insulating layer 93 in the third active portion 73. In exemplary embodiments of this disclosure, the capacitance value of the second capacitor can also be adjusted by adjusting the size of the fourth extension portion 414 on the base substrate in the first direction X of the orthographic projection. The smaller the size of the fourth extension portion 414 on the base substrate in the first direction X of the orthographic projection, the smaller the capacitance value of the second capacitor. The size of the fourth extension portion 414 on the base substrate in the first direction X of the orthographic projection may be 2 μm to 4 μm, for example, 4 μm, 3.7 μm, 3.5 μm, 2.95 μm, 2.2 μm, 2 μm, etc. Furthermore, in exemplary embodiments of this disclosure, the capacitance value of the second capacitor can also be adjusted by adjusting the size of the second extension portion 2G22 on the base substrate in the second direction Y of the orthographic projection, and the smaller the size of the second extension portion 2G22 on the base substrate in the second direction Y of the orthographic projection, the smaller the capacitance value of the second capacitor.

[0082] As shown in Figures 18 and 26, in the region where the fourth extension 414 is located, the orthographic projection of the third gate wiring 3G2 on the base substrate covers the orthographic projection of the second gate wiring 2G2 on the base substrate. In this region, the orthographic projection of the second gate line 2G2 on the base substrate overlaps with the orthographic projection of the fourth extension 414 on the base substrate. However, due to the shielding effect of the third gate line 3G2, in this region, the change in the area of ​​the orthographic projection of the second gate line 2G2 on the base substrate does not affect the capacitance value of the second capacitor. Similarly, in the region where the first extension G11 is located, the orthographic projection of the third active portion 73 on the base substrate covers the orthographic projection of the connection portion 41 on the base substrate. In this region, the orthographic projection of the connection portion 41 on the base substrate overlaps with the orthographic projection of the first extension portion G11 on the base substrate. However, due to the shielding effect of the third active portion 73, in this region, the change in the area of ​​the orthographic projection of the connection portion 41 on the base substrate does not affect the capacitance value of the first capacitor.

[0083] Figures 27-45 are drawings of another exemplary embodiment of the pixel driving circuit of the present disclosure.

[0084] In exemplary embodiments of this disclosure, a transistor means an element having at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain pole) and the source (source terminal, source region, or source pole), and current can flow through the drain, the channel region, and the source. In this specification, the channel region means the region through which current primarily flows.

[0085] Those skilled in the art will understand that the transistors used in all embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other devices having the same characteristics. In this specification, the first pole may be the drain and the second pole the source, or the first pole may be the source and the second pole the drain. The functions of “source” and “drain” may also be reversed, for example, when transistors with reversed polarity are used, or when the direction of current changes during circuit operation. Therefore, in this specification, “source” and “drain” can be interpreted interchangeably.

[0086] In this specification, “connection” includes cases where components are connected via an element having some electrical function. “Element having some electrical function” is not particularly limited as long as it can send and receive electrical signals between connected components. “Element having some electrical function” includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements having different functions.

[0087] Figures 27 and 28 are schematic diagrams of two pixel circuits according to exemplary embodiments of the present disclosure. As shown in Figures 27 and 28, the pixel circuits provided in the exemplary embodiments of the present disclosure include a drive subcircuit, a first reset subcircuit, a second reset subcircuit, and a light-emitting element.

[0088] The drive subcircuit is connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to generate a drive current between the second node N2 and the third node N3 in response to the control signal from the first node N1.

[0089] The first reset subcircuit is connected to the first reset signal line INIT1 and the anode terminal of the light-emitting element, respectively, and further connected to the first light emission control line EM1 or the second reset control line Reset2. The first reset subcircuit is configured to write the first reset signal provided by the first reset signal line INIT1 to the anode terminal of the light-emitting element in response to the signal from the first light emission control line EM1 or the second reset control line Reset2.

[0090] The second reset subcircuit is connected to the first reset control signal line Reset1 and the second reset signal line INIT2, respectively, and further connected to either the second node N2 or the third node N3. The second reset subcircuit is configured to write the second reset signal provided by the second reset signal line INIT2 to the first or second pole of the drive subcircuit in response to the signal on the first reset control signal line Reset1, wherein the second reset signal is greater than the first reset signal.

[0091] In some exemplary embodiments, the absolute value of the second reset signal is greater than 1.5 times the threshold voltage of the drive subcircuit.

[0092] In some exemplary embodiments, the magnitude of the second reset signal is greater than zero.

[0093] For example, the second reset signal is generally a reset voltage of 4 to 10V, the first reset signal is generally a reset voltage of -2V to -6V, and the threshold voltage of the drive subcircuit is generally -5V to -2V. Selectively, the threshold voltage of the drive subcircuit may be -3V.

[0094] In some exemplary embodiments, as shown in Figures 27 and 28, the pixel circuit further includes a write subcircuit, a compensation subcircuit, a first light emission control subcircuit, and a second light emission control subcircuit.

[0095] The writing subcircuit is connected to the second scan signal line G2, the data signal line Data, and the second node N2, respectively, and is configured to write the data signal from the data signal line Data to the second node N2 in response to the signal from the second scan signal line G2.

[0096] The compensation subcircuit is connected to the first power line VDD, the first scan signal line G1, the first node N1, and the third node N3, respectively, and is configured to write the first reset signal or the second reset signal from the third node N3 to the first node N1 in response to the signal on the first scan signal line G1, and to compensate the first node N1 in response to the signal on the first scan signal line G1.

[0097] The first light emission control subcircuit is coupled to the first light emission control line EM1, the first power supply line VDD, and the second node N2, respectively, and is configured to supply the signal from the first power supply line VDD to the second node N2 in response to the signal from the first light emission control line EM1.

[0098] The second light emission control subcircuit is connected to the second light emission control line EM2, the third node N3, and the fourth node N4, respectively. It is configured to write the first reset signal from the fourth node N4 to the third node N3 in response to the signal from the second light emission control line EM2, and to flow a drive current between the third node N3 and the fourth node N4 in response to the signal from the second light emission control line EM2.

[0099] In some exemplary embodiments, when the second reset subcircuit writes the second reset signal to the second node N2, the drive subcircuit is further configured to write the second reset signal from the second node N2 to the third node N3 in response to a control signal from the first node N1. In some exemplary embodiments, as shown in Figures 27 and 28, one end of the light-emitting element is connected to the fourth node N4, and the other end of the light-emitting element is connected to the second power line VSS.

[0100] In some exemplary embodiments, as shown in Figure 29, the first reset subcircuit includes a first transistor T1.

[0101] The control pole of the first transistor T1 is connected to the first light emission control line EM1 or the second reset control line Reset2 (not shown), the first pole of the first transistor T1 is connected to the first reset signal line INIT1, and the second pole of the first transistor T1 is connected to the fourth node N4.

[0102] Figure 29 is an exemplary schematic diagram of the first reset subcircuit. Those skilled in the art will readily understand that the implementation of the first reset subcircuit is not limited to this, as long as its function can be realized.

[0103] In some exemplary embodiments, as shown in Figure 30, the compensation subcircuit includes a second transistor T2 and a first capacitor C1.

[0104] The control pole of the second transistor T2 is connected to the first scan signal line G1, the first pole of the second transistor T2 is connected to the third node N3, and the second pole of the second transistor T2 is connected to the first node N1.

[0105] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first power line VDD.

[0106] Figure 30 is an exemplary schematic diagram of a compensation subcircuit. Those skilled in the art will readily understand that the implementation of the compensation subcircuit is not limited to this, as long as its function can be realized.

[0107] In some exemplary embodiments, the drive subcircuit includes a third transistor T3, as shown in Figure 31.

[0108] The control pole of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3.

[0109] Figure 31 is an exemplary schematic diagram of a drive subcircuit. Those skilled in the art will readily understand that the implementation of the drive subcircuit is not limited to this, as long as its function can be achieved.

[0110] In some exemplary embodiments, the writing subcircuit includes a fourth transistor T4, as shown in Figure 32.

[0111] The control pole of the fourth transistor T4 is connected to the second scan signal line G2, the first pole of the fourth transistor T4 is connected to the data signal line Data, and the second pole of the fourth transistor T4 is connected to the second node N2.

[0112] Figure 32 is an exemplary schematic diagram of a writing subcircuit. Those skilled in the art will readily understand that the implementation of the writing subcircuit is not limited to this, as long as its function can be achieved.

[0113] In some exemplary embodiments, as shown in Figure 33, the first light emission control subcircuit includes a fifth transistor T5.

[0114] The control pole of the fifth transistor T5 is connected to the first light emission control line EM1, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2.

[0115] Figure 33 is an exemplary schematic configuration diagram of the first light emission control subcircuit. Those skilled in the art will readily understand that the implementation of the first light emission control subcircuit is not limited to this, as long as it can realize its function.

[0116] In some exemplary embodiments, as shown in Figure 34, the second light emission control subcircuit includes a sixth transistor T6.

[0117] The control pole of the sixth transistor T6 is connected to the second light emission control line EM2, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4.

[0118] Figure 34 is an exemplary schematic diagram of the second light emission control subcircuit. Those skilled in the art will readily understand that the implementation of the second light emission control subcircuit is not limited to this, as long as it can realize its function.

[0119] In some exemplary embodiments, as shown in Figure 35, the second reset subcircuit includes a seventh transistor T7.

[0120] The control pole of the seventh transistor T7 is connected to the reset control signal line Reset, the first pole of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second pole of the seventh transistor T7 is connected to the second node N2.

[0121] In some exemplary embodiments, as shown in Figure 36, the second reset subcircuit includes a seventh transistor T7.

[0122] The control pole of the seventh transistor T7 is connected to the reset control signal line Reset, the first pole of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second pole of the seventh transistor T7 is connected to the third node N3.

[0123] Figures 35 and 36 are two exemplary schematic diagrams of the second reset subcircuit. Those skilled in the art will readily understand that the implementation of the second reset subcircuit is not limited to these, as long as its function can be realized.

[0124] In some exemplary embodiments, as shown in Figure 37a or Figure 37b, the first reset subcircuit includes a first transistor T1, the compensation subcircuit includes a second transistor T2 and a first capacitor C1, the drive subcircuit includes a third transistor T3, the write subcircuit includes a fourth transistor T4, the first light emission control subcircuit includes a fifth transistor T5, the second light emission control subcircuit includes a sixth transistor T6, and the second reset subcircuit includes a seventh transistor T7.

[0125] The control pole of the first transistor T1 is connected to the first light emission control line EM1, the first pole of the first transistor T1 is connected to the first reset signal line INIT1, and the second pole of the first transistor T1 is connected to the fourth node N4.

[0126] The control pole of the second transistor T2 is connected to the first scan signal line G1, the first pole of the second transistor T2 is connected to the third node N3, and the second pole of the second transistor T2 is connected to the first node N1.

[0127] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first power line VDD.

[0128] The control pole of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3.

[0129] The control pole of the fourth transistor T4 is connected to the second scan signal line G2, the first pole of the fourth transistor T4 is connected to the data signal line Data, and the second pole of the fourth transistor T4 is connected to the second node N2.

[0130] The control pole of the fifth transistor T5 is connected to the first light emission control line EM1, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2.

[0131] The control pole of the sixth transistor T6 is connected to the second light emission control line EM2, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4.

[0132] The control pole of the seventh transistor T7 is connected to the first reset control signal line Reset1, the first pole of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second pole of the seventh transistor T7 is connected to the second node N2 or the third node N3.

[0133] Figures 37a and 37b show two exemplary configurations of a first reset subcircuit, a compensation subcircuit, a drive subcircuit, a write subcircuit, a first light emission control subcircuit, a second light emission control subcircuit, and a second reset subcircuit. Those skilled in the art will readily understand that the implementation of each of the above subcircuits is not limited to those described above, as long as their respective functions can be realized. The small number of transistors in the pixel circuits of this disclosure reduces the space occupied by the pixel circuits, thereby improving the pixel resolution of the display device.

[0134] In some exemplary embodiments, the second reset signal line INIT2 may be the same power line as at least one of the first power line VDD, the first light emission control line EM1, the second light emission control line EM2, and the third power line. The third power line supplies a third power supply voltage, which is greater than the first reset voltage supplied by the first reset signal line INIT1. In some exemplary embodiments, the pulse width of the signal on the reset control signal line Reset is approximately the same as the pulse width of the signal on the second scan signal line G2.

[0135] In some exemplary embodiments, the difference between the signal pulse of the first light emission control line EM1 and the signal pulse of the second light emission control line EM2 is 1 or 2 hours h, where 1 hour h is the scan time for one row of subpixels.

[0136] In some exemplary embodiments, as shown in Figure 38a or Figure 38b, the first reset subcircuit includes a first transistor T1, the compensation subcircuit includes a second transistor T2 and a first capacitor C1, the drive subcircuit includes a third transistor T3, the write subcircuit includes a fourth transistor T4, the first light emission control subcircuit includes a fifth transistor T5, the second light emission control subcircuit includes a sixth transistor T6, and the second reset subcircuit includes a seventh transistor T7.

[0137] The control pole of the first transistor T1 is connected to the second reset control signal line Reset2, the first pole of the first transistor T1 is connected to the first reset signal line INIT1, and the second pole of the first transistor T1 is connected to the fourth node N4.

[0138] The control pole of the second transistor T2 is connected to the first scan signal line G1, the first pole of the second transistor T2 is connected to the third node N3, and the second pole of the second transistor T2 is connected to the first node N1.

[0139] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first power line VDD.

[0140] The control pole of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3.

[0141] The control pole of the fourth transistor T4 is connected to the second scan signal line G2, the first pole of the fourth transistor T4 is connected to the data signal line Data, and the second pole of the fourth transistor T4 is connected to the second node N2.

[0142] The control pole of the fifth transistor T5 is connected to the first light emission control line EM1, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2.

[0143] The control pole of the sixth transistor T6 is connected to the second light emission control line EM2, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4.

[0144] The control pole of the seventh transistor T7 is connected to the first reset control signal line Reset1, the first pole of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second pole of the seventh transistor T7 is connected to the second node N2 or the third node N3.

[0145] Figures 38a and 38b show two other exemplary configurations of the first reset subcircuit, compensation subcircuit, drive subcircuit, write subcircuit, first light emission control subcircuit, second light emission control subcircuit, and second reset subcircuit. Those skilled in the art will readily understand that the implementation of each of the above subcircuits is not limited to those described above, as long as their respective functions can be realized.

[0146] In some exemplary embodiments, the light-emitting element (EL) may be an organic light-emitting diode (OLED), or another type of light-emitting diode such as mini light-emitting diodes (Mini Light-Emitting Diodes), micro light-emitting diodes (Micro Light-Emitting Diodes), and quantum-dot light-emitting diodes (QLEDs). In actual applications, the structure of the light-emitting element (EL) needs to be designed and determined according to the actual usage environment, but is not limited here. The following description will use the case where the light-emitting element (EL) is an organic light-emitting diode as an example.

[0147] In some exemplary embodiments, at least one of the first transistor T1, the second transistor T2, and the seventh transistor T7 is a type 1 transistor, and the type 1 transistors include either an N-type or P-type transistor; the third transistor T3 to the sixth transistor T6 are all type 2 transistors, and the type 2 transistors include either a P-type or N-type transistor, with the type 2 transistors being of a different type from the type 1 transistors. That is, if the type 1 transistor is an N-type transistor, then the type 2 transistor is a P-type transistor, and if the type 1 transistor is a P-type transistor, then the type 2 transistor is an N-type transistor.

[0148] In some exemplary embodiments, as shown in Figures 37a and 37b, the first transistor T1 and the second transistor T2 are both N-type thin-film transistors, and the third transistor T3 to the seventh transistor T7 are all P-type thin-film transistors.

[0149] In some exemplary embodiments, the first transistor T1, the second transistor T2, and the seventh transistor T7 are all N-type thin-film transistors, while the third transistor T3 to the sixth transistor T6 are all P-type thin-film transistors.

[0150] In some exemplary embodiments, as shown in Figures 38a and 38b, the second transistor T2 is an N-type thin-film transistor, and the first transistor T1 and the third to seventh transistors T3 to T7 are all P-type thin-film transistors.

[0151] In some exemplary embodiments, the N-type thin-film transistor may be a low-temperature polysilicon (LTPS) thin-film transistor (TFT), and the P-type thin-film transistor may be an indium gallium zinc oxide (IGZO) thin-film transistor. Alternatively, the N-type thin-film transistor may be an IGZO thin-film transistor, and the P-type thin-film transistor may be an LTPS thin-film transistor.

[0152] In some exemplary embodiments, the first transistor T1 and the second transistor T2 are both IGZO thin-film transistors, and the third transistor T3 to the seventh transistor T7 are all LTPS thin-film transistors.

[0153] In the embodiments of this disclosure, since indium gallium zinc oxide thin-film transistors have lower leakage current compared to low-temperature polysilicon thin-film transistors, by using indium gallium zinc oxide thin-film transistors for the first transistor T1 and the second transistor T2, leakage of the control pole of the driving transistor during the light emission stage can be significantly reduced, thereby improving the problem of low-frequency, low-brightness flicker in the display panel.

[0154] In some exemplary embodiments, the first transistor T1, the second transistor T2, and the seventh transistor T7 are all IGZO thin-film transistors, while the third transistor T3 to the sixth transistor T6 are all LTPS thin-film transistors.

[0155] In some exemplary embodiments, the second transistor T2 is an IGZO thin-film transistor, and the first transistor T1 and the third to seventh transistors T3 to T7 are all LTPS thin-film transistors. In some exemplary embodiments, the first capacitor C1 may be a liquid crystal capacitor composed of a pixel electrode and a common electrode, or it may be an equivalent capacitor composed of a liquid crystal capacitor composed of a pixel electrode and a common electrode and a storage capacitor, but the disclosure is not limited thereto.

[0156] Figure 39 is a timing diagram of the operation of the pixel circuit shown in Figure 37a or Figure 37b during one scan cycle. In the following, using as an example the pixel circuit provided in the embodiments of this disclosure, where the first transistor T1 and the second transistor T2 are N-type transistors, and the third transistor T3 to the seventh transistor T7 are all P-type transistors, the operation process of one pixel circuit during one frame cycle will be described in combination with the pixel circuit shown in Figure 11a and the operation timing diagram shown in Figure 39. As shown in Figure 37a, the pixel circuit provided by the embodiment of the present disclosure includes seven transistor units (T1 to T7), one capacitor unit (C1), and three power lines (VDD, VSS, and INIT1. The second reset signal line INIT2 is not included in the above three power lines because it is the same power line as the first power line VDD, the first light emission control line EM1, or the second light emission control line EM2). The first power line VDD provides a continuously high-level signal, the second power line VSS provides a continuously low-level signal, and the first reset signal line INIT1 provides a first reset voltage (initialization voltage signal). As shown in Figure 39, its operation process includes the following t1 to t4.

[0157] In the first stage t1, i.e., the reset stage, the first scan signal line G1, the second scan signal line G2, the first reset control signal line Reset1, and the first light emission control signal line EM1 are at a high level, and the second light emission control signal line EM2 is at a low level. Because the first light emission control signal line EM1 is at a high level, the first transistor T1 is turned on, and the fourth node N4 (i.e., the anode terminal of the light-emitting element EL) is reset to the first reset voltage of the first reset signal line INIT1. Because the second light emission control signal line EM2 is at a low level, the sixth transistor T6 is turned on, and because the first scan signal line G1 is at a high level, the second transistor T2 is turned on, and the first node N1 (i.e., the gate of the third transistor T3 and one end of the first capacitor C1) and the third node N3 are reset to the first reset voltage of the first reset signal line INIT1. In this stage, as shown in Figure 41, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are kept in the off state.

[0158] In the second stage t2, i.e., the reset stage, the first scan signal line G1, the second scan signal line G2, the first light emission control line EM1, and the second light emission control line EM2 are at a high level, and the first reset control line Reset is at a low level. Because the second light emission control line EM2 is at a high level, the sixth transistor T6 is turned off. Because the first reset control line Reset1 is at a low level, the seventh transistor T7 is turned on (in this timing diagram, the case where the seventh transistor T7 is a P-type thin-film transistor is used as an example, but if the seventh transistor T7 is an N-type thin-film transistor, the first reset control line Reset1 provides a high-level signal in the second stage t2 and a low-level signal in other stages), and the second node N2 is reset to the second reset voltage. The second reset voltage is a voltage signal provided by the first power line VDD, the first light emission control line EM1, the second light emission control line EM2, or the third power line, and the second reset voltage is greater than the first reset voltage. Since the first node N1 is the first reset voltage of the first reset signal line INIT1, the third transistor T3 is turned on, and since the first scan signal line G1 is high level, the second transistor T2 is turned on, and the voltage of the second node N2 is transmitted to the first node N1 via the third transistor T3 and the second transistor T2. At this stage, as shown in Figure 42, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are kept in the off state.

[0159] In the third stage t3, i.e., the data writing stage, the first scan signal line G1, the first reset control signal line Reset1, the first light emission control line EM1, and the second light emission control line EM2 are at a high level, while the second scan signal line G2 is at a low level. In this case, because the second scan signal line G2 is at a low level, the fourth transistor T4 is turned on, and the data voltage signal Vdata output from the data signal line Data is provided to the first node N1 via the turned-on fourth transistor T4, third transistor T3, and second transistor T2. The sum of the data voltage signal Vdata output from the data signal line Data and the threshold voltage Vth of the third transistor T3 is stored in the first capacitor C1. In this stage, as shown in Figure 43, the fifth transistor T5, sixth transistor T6, and seventh transistor T7 are kept in the off state.

[0160] In the fourth stage t4, i.e., the light emission stage, the second scan signal line G2 and the first reset control signal line Reset1 are at a high level, while the first scan signal line G1, the first light emission control signal line EM1, and the second light emission control signal line EM2 are at a low level. Because the first light emission control signal line EM1 is at a low level, the fifth transistor T5 is turned on and the first transistor T1 is turned off. Because the second light emission control signal line EM2 is at a low level, the sixth transistor T6 is turned on, and the power supply voltage output from the first power supply line VDD provides a drive voltage to the fourth node N4 (i.e., the anode terminal of the light-emitting element EL) via the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6. In this stage, as shown in Figure 44, the first transistor T1, second transistor T2, fourth transistor T4, and seventh transistor T7 remain in the off state.

[0161] Figure 40 is a timing diagram of the operation of the pixel circuit shown in Figure 38a or Figure 38b during one scan cycle. In the following, using as an example the pixel circuit provided in the embodiments of this disclosure, where the second transistor T2 is an N-type transistor and the first transistor T1, third transistors T3 to seventh transistors T7 are all P-type transistors, the operation process of one pixel circuit during one frame cycle will be described in combination with the pixel circuit shown in Figure 38a and the operation timing diagram shown in Figure 40. As shown in Figure 38a, the pixel circuit provided by the embodiment of the present disclosure includes seven transistor units (T1 to T7), one capacitor unit (C1), and three power lines (VDD, VSS, and INIT1. The second reset signal line INIT2 is not included in the three power lines if it is the same power line as the first power line VDD, the first light emission control line EM1, or the second light emission control line EM2). The first power line VDD continuously provides a high-level signal, the second power line VSS continuously provides a low-level signal, and the first reset signal line INIT1 provides a first reset voltage (initialization voltage signal). As shown in Figure 40, its operation process includes the following A1 to A4.

[0162] In the first stage A1, i.e., the reset stage, the first scan signal line G1, the second scan signal line G2, the first reset control signal line Reset1, and the first light emission control signal line EM1 are at a high level, while the second reset control signal line Reset2 and the second light emission control signal line EM2 are at a low level. The first transistor T1, the sixth transistor T6, and the second transistor T2 are turned on, and the fourth node N4 (the anode terminal of the light-emitting element EL), the third node N3, and the first node N1 (i.e., the gate of the third transistor T3 and one end of the first capacitor C1) are reset to the first reset voltage of the first reset signal line INIT1. In this stage, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain in the off state.

[0163] In the second stage A2, i.e., the reset stage, the first scan signal line G1, the second scan signal line G2, the second reset control signal line Reset2, the first light emission control signal line EM1, and the second light emission control signal line EM2 are at a high level, while the first reset control signal line Reset1 is at a low level. Because the second light emission control signal line EM2 is at a high level, the sixth transistor T6 is turned off. Because the first reset control signal line Reset1 is at a low level, the seventh transistor T7 is turned on (in this timing diagram, the case where the seventh transistor T7 is a P-type thin-film transistor is used as an example, but if the seventh transistor T7 is an N-type thin-film transistor, the first reset control signal line Reset1 provides a high-level signal in the second stage A2 and a low-level signal in other stages), resetting the second node N2 to the second reset voltage. The second reset voltage is a voltage signal provided by the first power line VDD, the first light emission control signal line EM1, the second light emission control signal line EM2, or the third power line, and the second reset voltage is greater than the first reset voltage. Since the first node N1 is the first reset voltage of the first reset signal line INIT1, the third transistor T3 is turned on, and since the first scan signal line G1 is high level, the second transistor T2 is turned on, and the voltage of the second node N2 is transmitted to the first node N1 via the third transistor T3 and the second transistor T2. At this stage, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 remain in the off state.

[0164] In the third stage A3, i.e., the data writing stage, the first scan signal line G1, the second reset control signal line Reset2, the first reset control signal line Reset1, the first light emission control signal line EM1, and the second light emission control signal line EM2 are at a high level, and the second scan signal line G2 is at a low level. In this case, because the second scan signal line G2 is at a low level, the fourth transistor T4 is turned on, and the data voltage signal Vdata output from the data signal line Data is provided to the first node N1 via the turned-on fourth transistor T4, third transistor T3, and second transistor T2, and the sum of the data voltage signal Vdata output from the data signal line Data and the threshold voltage Vth of the third transistor T3 is stored in the first capacitor C1. In this stage, the fifth transistor T5, sixth transistor T6, and seventh transistor T7 are kept in the off state.

[0165] In the fourth stage A4, i.e., the light emission stage, the second scan signal line G2, the second reset control signal line Reset2, and the first reset control signal line Reset1 are at a high level, while the first scan signal line G1, the first light emission control signal line EM1, and the second light emission control signal line EM2 are at a low level. Because the first light emission control signal line EM1 is at a low level, the fifth transistor T5 is turned on; because the second reset control signal line Reset2 is at a high level, the first transistor T1 is turned off; and because the second light emission control signal line EM2 is at a low level, the sixth transistor T6 is turned on. The power supply voltage output from the first power supply line VDD provides a drive voltage to the fourth node N4 (i.e., the anode terminal of the light-emitting element EL) via the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light. In this stage, the first transistor T1, second transistor T2, fourth transistor T4, and seventh transistor T7 remain in the off state.

[0166] In the pixel circuit driving process, the drive current flowing through the third transistor T3 (i.e., the driving transistor) is determined by the voltage difference between its gate and the first pole. Since the voltage at the first node N1 is Vdata + Vth, the drive current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdata-Vdd)] 2 That is the case.

[0167] Here, I is the drive current flowing through the third transistor T3, i.e., the drive current driving the light-emitting element EL; K is a constant; Vgs is the voltage difference between the gate of the third transistor and the first pole; Vth is the threshold voltage of transistor T3; Vdata is the data voltage output by the data signal line Data; and Vdd is the power supply voltage output by the first power supply line VDD.

[0168] From the above equation, it can be seen that the current I flowing through the light-emitting element EL is independent of the threshold voltage Vth of the third transistor T3. This eliminates the influence of the threshold voltage Vth of the third transistor T3 on the current I, ensuring uniformity of brightness.

[0169] Due to the long response time of the LTPO (LTPS low-temperature polysilicon transistor + oxide transistor) pixel circuit, brightness flicker occurs in the image when switching to a low frequency. The pixel circuit of the embodiment of this disclosure improves hysteresis by applying a large bias voltage to the third transistor T3 (driving transistor) during the resetting stage of the driving transistor, thereby maintaining screen brightness when switching between high and low frequencies and reducing the risk of flicker.

[0170] In a column of subpixels, for at least two adjacent subpixels, the second light emission control line EM2 of the subpixel in the previous row is electrically connected to the first light emission control line EM1 of the subpixel in the next row, and the second scan signal line G2 of the subpixel in the previous row is electrically connected to the first reset control line Reset1 of the subpixel in the next row.

[0171] Embodiments of the present disclosure further provide a method for driving a pixel circuit that drives the aforementioned pixel circuit, wherein the pixel circuit has a plurality of scan cycles, and as shown in Figure 45, the driving method includes steps 100 to 300 within one scan cycle.

[0172] Step 100 includes, in the reset phase, the first reset subcircuit writing a first reset signal to the anode terminal (i.e., the fourth node) of the light-emitting element in response to a signal on the first light-emitting control line or the second reset control line.

[0173] In some exemplary embodiments, step 100 further includes the second light emission control subcircuit writing a first reset signal from the fourth node to the third node in response to a signal on the second light emission control line, and the compensation subcircuit writing a first reset signal from the third node to the first node in response to a signal on the first scan signal line.

[0174] Step 200, in the setting stage, includes the second reset subcircuit writing a second reset signal to the first pole (i.e., the second node) or the second pole (i.e., the third node) of the drive subcircuit in response to a signal on the first reset control signal line, wherein the second reset signal is greater than the first reset signal.

[0175] In some exemplary embodiments, step 100 further includes the compensation subcircuit writing a second reset signal from the third node to the first node in response to a signal on the first scan signal line.

[0176] In some exemplary embodiments, the second reset signal may be a signal from at least one voltage line among the first power line, the first light emission control line, the second light emission control line, and the third power line.

[0177] Step 300 includes, during the light emission stage, the drive subcircuit generating a drive current between the second and third nodes in response to a control signal from the first node.

[0178] In some exemplary embodiments, prior to step 300, the method further includes, in the data writing stage, a writing subcircuit writing a data signal to a second node in response to a signal on a second scan signal line, and a compensation subcircuit compensating a first node in response to a signal on a first scan signal line.

[0179] In some exemplary embodiments, step 300 further includes, during the light emission stage, a first light emission control subcircuit providing a signal from a first power line to a second node in response to a signal from a first light emission control line, and a second light emission control subcircuit supplying a drive current between a third node and a fourth node in response to a signal from a second light emission control line.

[0180] In the pixel circuit and its driving method, as well as the display device according to the embodiments of this disclosure, the second reset subcircuit writes the second reset signal to the first or second pole of the driving subcircuit in response to the signal of the first reset control signal line, and applies a large bias voltage to the driving subcircuit to improve hysteresis. This allows the brightness of the screen to be maintained when switching between high and low frequencies, reduces the risk of flicker, and improves the display effect of the display device under high and low gradation. Furthermore, because the number of transistors in the pixel circuit of this disclosure is small, the space occupied by the pixel circuit is reduced, thereby improving the pixel resolution of the display device. The following points need to be explained.

[0181] The drawings of embodiments of this disclosure relate only to structures relevant to embodiments of this disclosure; other structures may refer to general designs.

[0182] Where there are no inconsistencies, new embodiments can be obtained by combining the embodiments and features of the embodiments of this disclosure with each other.

[0183] Figures 46 to 60 illustrate illustrative drawings of a series of other embodiments of the pixel driving circuit of the present disclosure.

[0184] The transistors used in all embodiments of this disclosure may be triodes, thin-film transistors, field-effect transistors, or other devices having the same characteristics. In embodiments of this disclosure, in order to distinguish between the two electrodes of the transistor excluding the control electrode, one electrode is referred to as the first electrode and the other electrode as the second electrode.

[0185] In actual operation, if the transistor is a thin-film transistor or a field-effect transistor, the first pole may be the drain and the second pole may be the source. Alternatively, the first pole may be the source and the second pole may be the drain.

[0186] As shown in Figure 46, the pixel circuit described in the embodiments of this disclosure includes a drive circuit 11, a first control circuit 12, a compensation control circuit 13, and a first initialization circuit 14.

[0187] The first control circuit 12 is electrically connected to the first scan line S1, the control terminal of the drive circuit 11, and the connection node N0, respectively, and controls communication between the control terminal of the drive circuit 11 and the connection node N0 based on the control of the first scan signal supplied by the first scan line S1.

[0188] The compensation control circuit 13 is electrically connected to the second scan line S2, the connection node N0, and the first end of the drive circuit 11, respectively, and controls communication between the connection node N0 and the first end of the drive circuit 11 based on the control of the second scan signal supplied by the second scan line S2.

[0189] The first initialization circuit 14 is electrically connected to the initialization control line R1, the first initialization voltage line, and the connection node N0, respectively, and writes the first initialization voltage Vi1 provided by the first initialization voltage line to the connection node N0 based on the control of the initialization control signal provided by the initialization control line R1.

[0190] The drive circuit 11 is configured to control communication between the first end of the drive circuit 11 and the second end of the drive circuit 11 based on the control of the potential of its control terminal.

[0191] In at least one embodiment shown in Figure 46, the first node N1 is a node connected to the control terminal of the drive circuit 11.

[0192] In the pixel circuit described in the embodiments of this disclosure, the first control circuit 12 is directly electrically connected to the first node N1, and neither the first initialization circuit 14 nor the compensation control circuit 13 are directly electrically connected to the first node N1. This reduces the leakage path of the first node N1 and ensures the voltage stability of the first node during low-frequency operation, which is advantageous for improving display quality, improving display uniformity, and reducing flicker.

[0193] The embodiment of the pixel circuit shown in Figure 46 of this disclosure, during operation, has a display cycle that includes an initialization phase and a data writing phase. The driving method includes the following:

[0194] During the initialization phase, the first control circuit 12 controls communication between the control terminal of the drive circuit 11 and the connection node N0 based on the control of the first scan signal, and the first initialization circuit 14 writes the first initialization voltage Vi1 to the control terminal of the drive circuit 11 by writing it to the connection node N0 based on the control of the initialization control signal. This allows the drive circuit 11 to control communication between its first terminal and its second terminal at the start of the data writing phase.

[0195] During the data writing phase, the first control circuit 12 controls communication between the control end of the drive circuit 11 and the connection node N0 based on the control of the first scan signal, and the compensation control circuit 13 controls communication between the connection node N0 and the first end of the drive circuit 11 based on the control of the second scan signal, thereby connecting the control end of the drive circuit 11 and the first end of the drive circuit 11. Selectively, the first control circuit includes a first transistor.

[0196] The control pole of the first transistor is electrically connected to the first scan line, the first pole of the first transistor is electrically connected to the control terminal of the drive circuit, and the second pole of the first transistor is electrically connected to the connection node.

[0197] The first control transistor is an oxide thin-film transistor.

[0198] In at least one embodiment of the present disclosure, the first transistor included in the control circuit is an oxide thin-film transistor.

[0199] Oxide transistors possess excellent hysteresis characteristics, low leakage current, and low mobility. Therefore, in at least one embodiment of this disclosure, the first transistor is made an oxide thin-film transistor to achieve low leakage and ensure the stability of the potential at the control terminal of the drive circuit.

[0200] Selectively, the compensation control circuit includes a second transistor.

[0201] The control pole of the second transistor is electrically connected to the second scan line, the first pole of the second transistor is electrically connected to the connection node, and the second pole of the second transistor is electrically connected to the first end of the drive circuit.

[0202] In at least one embodiment of this disclosure, the second transistor may be, but is not limited to, a low-temperature polysilicon thin-film transistor. In specific embodiments, the second transistor may be of a different type.

[0203] Selectively, the first initialization circuit includes a third transistor.

[0204] The control pole of the third transistor is electrically connected to the initialization control line, the first pole of the third transistor is electrically connected to the first initialization voltage line, and the second pole of the third transistor is electrically connected to the connection node.

[0205] In at least one embodiment of this disclosure, the third transistor is a low-temperature polysilicon thin-film transistor. In a specific embodiment, the third transistor may be of a different type.

[0206] As shown in Figure 47, based on the pixel circuit shown in Figure 46, the pixel circuit described in at least one embodiment of the present disclosure may further include a reset circuit 20.

[0207] The reset circuit 20 is electrically connected to the third scan line S3, the reset voltage line DR, and the second terminal of the drive circuit 11, respectively, and writes the reset voltage supplied by the reset voltage line DR to the second terminal of the drive circuit 11 based on the control of the third scan signal supplied by the third scan line S3.

[0208] In at least one embodiment of the pixel circuit shown in Figure 47 of the present disclosure, a reset circuit 20 is added, which, based on the control of the third scan signal, supplies a bias voltage to the drive transistor in the drive circuit 11 by writing a reset voltage to the second terminal of the drive circuit 11 during the non-emitting period before the data voltage is written to the second terminal of the drive circuit 11 (in this case, the gate potential of the drive transistor is also initialized to Vi1), thereby maintaining the drive transistor in a reset state, improving the hysteresis of the drive transistor and shortening the response time (FFR) of the first frame of the display screen.

[0209] In specific embodiments, hysteresis in the drive transistor may slow down the characteristic response of the drive transistor. However, in at least one embodiment of the present disclosure, the gate-source voltage of the drive transistor is rapidly reset before the data voltage is written, which is advantageous for accelerating the recovery speed of the drive transistor, thereby improving the hysteresis phenomenon of the drive transistor and improving the hysteresis recovery speed.

[0210] At least one embodiment of the pixel circuit shown in Figure 47 of this disclosure can extend the reset time of the second end of the drive circuit 11 so as to enhance the effect of resetting the potential of the second end of the drive circuit 11 by increasing the duty cycle of the third scan signal before the data voltage is written to the second end of the drive circuit 11 during operation, in a non-emitting period (the non-emitting period may refer to a period other than the emitting period included in the display cycle).

[0211] In at least one embodiment of the pixel circuit shown in Figure 47 of this disclosure, during operation, in the initialization phase, the reset circuit writes a reset voltage to the second terminal of the drive circuit based on the control of the third scan signal.

[0212] In at least one embodiment of the present disclosure, the reset voltage is a DC voltage signal that provides a fixed bias voltage to the drive transistor to improve hysteresis.

[0213] Selectively, the reset voltage may be a high voltage, but is not limited to this.

[0214] In at least one embodiment of the present disclosure, a separate third scan signal generation module can be used to supply a third scan signal to the third scan line, which is advantageous for resetting the potential of the second end of the drive circuit.

[0215] In at least one embodiment of this disclosure, the reset voltage line and the first voltage line can be the same voltage line, thereby reducing the number of signal lines used. The voltage value of the reset voltage is greater than the voltage value of the first initialization voltage, and the first voltage line is configured to supply the first voltage signal (the first voltage line may be a high-voltage line). The voltage value of the first voltage signal is greater than 0V and less than or equal to 5V, for example, the voltage value of the first voltage signal is 4.6V, but is not limited thereto. The first initialization voltage may be a DC voltage. The voltage value of the first initialization voltage can be greater than or equal to -7V and less than or equal to 0V, for example, the voltage value of the first initialization voltage may be -6V, -5V, -4V, -3V, or -2V, but is not limited thereto.

[0216] In at least one embodiment of the present disclosure, the threshold voltage Vth of the drive transistor in the drive circuit can be -5V or more and -2V or less, preferably Vth is -4V or more and -2.5V or less, for example, Vth may be -4V, -3.5V, -3V, or -2.5V.

[0217] To ensure that the bias effect is achieved relatively quickly, the absolute value of the reset voltage may be greater than 1.5 times the absolute value of the threshold voltage. For example, the absolute value of the reset voltage may be greater than 2, 2.5, or 3 times the absolute value of the threshold voltage, but is not limited to these.

[0218] Selectively, the reset circuit includes a fourth transistor.

[0219] The control pole of the fourth transistor is electrically connected to the third scan line, the first pole of the fourth transistor is electrically connected to the reset voltage line, and the second pole of the fourth transistor is electrically connected to the second terminal of the drive circuit.

[0220] In at least one embodiment of the present disclosure, the fourth transistor may be, but is not limited to, a low-temperature polysilicon thin-film transistor.

[0221] As shown in Figure 48, a pixel circuit according to at least one embodiment of the present disclosure may further include a light-emitting element 30, a light-emitting control circuit 31, and a second initialization circuit 32.

[0222] The light emission control circuit 31 is electrically connected to the light emission control line E1, the first voltage line V1, the second end of the drive circuit 11, the first end of the drive circuit 11, and the first pole of the light-emitting element 30, respectively. Based on the control of the light emission control signal supplied from the light emission control line E1, it controls the communication between the first voltage line V1 and the second end of the drive circuit 11, and controls the communication between the first end of the drive circuit 11 and the first pole of the light-emitting element 30.

[0223] The second initialization circuit 32 is electrically connected to the fourth scan line S4, the second initialization voltage line, and the first pole of the light-emitting element 30, respectively, and writes the second initialization voltage Vi2 supplied from the second initialization voltage line to the first pole of the light-emitting element 30 based on the control of the fourth scan signal supplied from the fourth scan line S4.

[0224] The second pole of the light-emitting element 30 is electrically connected to the second voltage line V2.

[0225] In at least one embodiment of the present disclosure, the first voltage line V1 may be a high-voltage line and the second voltage line V2 may be a low-voltage line, but is not limited thereto.

[0226] The light-emitting element 30 may be an OLED (organic light-emitting diode), the first electrode of the light-emitting element 30 may be the anode of the OLED, and the second electrode of the light-emitting element 30 may be the cathode of the OLED, but is not limited to these.

[0227] In at least one embodiment of the pixel circuit shown in Figure 48 of this disclosure, a separate fourth scan signal generation module can be used to provide the fourth scan signal to the fourth scan line, which is advantageous for the degree of freedom in switching the switching frequency under low-frequency flicker (the switching frequency being the switching frequency of the transistors provided in the second initialization circuit 32). When the display panel to which the pixel circuit is applied operates at a low frequency, if the light emission control circuit 31 controls the off-circuiting between the first voltage line V1 and the second terminal of the drive circuit 11, and controls the off-circuiting between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 30, flicker can be reduced by increasing the frequency of the fourth scan signal.

[0228] In at least one embodiment of the present disclosure, the third scan signal and the fourth scan signal may be the same scan signal, and the third scan signal generation module and the fourth scan signal generation module may be the same module, but are not limited thereto.

[0229] In at least one embodiment of the pixel circuit shown in Figure 48 of this disclosure, the first scan signal and the light emission control signal may be the same signal during operation, but considering that when PWM (pulse width modulation) controls the light emission function, the EM may supply a high voltage signal during light emission, the first scan signal is supplied to the first scan line through a separate first scan signal generation module and the light emission control signal is supplied to the light emission control line through a light emission control signal generation module.

[0230] In at least one embodiment of the present disclosure, if the reset voltage line is the first voltage line, the voltage value of the reset voltage may be greater than the voltage value of the second initialization voltage.

[0231] The voltage value of the second initialization voltage may be between -7V and 0V. For example, the voltage value of the second initialization voltage may be -6V, -5V, -4V, -3V, or -2V.

[0232] Selectively, the light-emitting control circuit includes a fifth transistor and a sixth transistor.

[0233] The control pole of the fifth transistor is electrically connected to the light emission control line, the first pole of the fifth transistor is electrically connected to the first voltage line, and the second pole of the fifth transistor is electrically connected to the second terminal of the drive circuit.

[0234] The control pole of the sixth transistor is electrically connected to the light emission control line, the first pole of the sixth transistor is electrically connected to the first end of the drive circuit, and the second pole of the sixth transistor is electrically connected to the first pole of the light-emitting element.

[0235] The second initialization circuit includes a seventh transistor.

[0236] The control electrode of the seventh transistor is electrically connected to the fourth scanning line, the first electrode of the seventh transistor is electrically connected to the second initialization voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element.

[0237] Optionally, the seventh transistor may be an oxide thin-film transistor.

[0238] In at least one embodiment of the present disclosure, by using an oxide thin-film transistor as the seventh transistor, leakage can be reduced and the stability of the potential of the first electrode of the light-emitting element can be ensured.

[0239] As shown in FIG. 49, in addition to at least one embodiment of the pixel circuit shown in FIG. 48, the pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit 41 and an energy storage circuit 42.

[0240] The data writing circuit 41 is electrically connected to the second scanning line S2, the data line D1, and the second end of the driving circuit 11 respectively, and writes the data voltage on the data line D1 to the second end of the driving circuit 11 based on the control of the second scanning signal supplied from the second scanning line S2.

[0241] The energy storage circuit 42 is electrically connected to the control end of the driving circuit 11 and stores electrical energy.

[0242] In at least one embodiment of the pixel circuit shown in FIG. 49 of the present disclosure, during operation, the display cycle further includes a light-emitting stage provided after the data writing stage.

[0243] In the initialization stage, the second initialization circuit 32 writes the second initialization voltage Vi2 supplied from the second initialization voltage line to the first electrode of the light-emitting element 30 based on the control of the fourth scanning signal supplied from the fourth scanning line S4.

[0244] During the data writing phase, the data writing circuit 41 writes the data voltage Vdata on the data line D1 to the second terminal of the drive circuit 11 based on the control of the second scan signal.

[0245] At the start of the data writing phase, the drive circuit 11 controls the communication between its first terminal and its second terminal so that the energy storage circuit 42 is charged via the data voltage Vdata, and changes the potential of the control terminal of the drive circuit 11 until the potential of the control terminal of the drive circuit 11 changes to Vdata + Vth, where Vth is the threshold voltage of the drive transistor of the drive circuit 11.

[0246] During the light emission phase, the light emission control circuit 31 controls the communication between the first voltage line V1 and the second end of the drive circuit 11, and controls the communication between the first end of the drive circuit 11 and the first pole of the light-emitting element 30, based on the control of the light emission control signal, and the drive circuit 11 drives the light-emitting element 30 to emit light.

[0247] Selectively, the data writing circuit includes an eighth transistor, and the energy storage circuit includes a storage capacitor.

[0248] The control pole of the eighth transistor is electrically connected to the second scan line, the first pole of the eighth transistor is electrically connected to the data line, and the second pole of the eighth transistor is electrically connected to the second terminal of the drive circuit.

[0249] The first terminal of the storage capacitor is electrically connected to the control terminal of the drive circuit, and the second terminal of the storage capacitor is electrically connected to the first voltage line.

[0250] In at least one embodiment of the present disclosure, the drive circuit may include a drive transistor.

[0251] The drive transistor is a single-gate transistor, the gate of the drive transistor is electrically connected to the control terminal of the drive circuit, the first pole of the drive transistor is electrically connected to the first terminal of the drive circuit, the second pole of the drive transistor is electrically connected to the second terminal of the drive circuit, or, The drive transistor is a double-gate transistor, the first gate of the drive transistor is electrically connected to the control terminal of the drive circuit, the second gate of the drive transistor is electrically connected to the first voltage line, the first pole of the drive transistor is electrically connected to the first terminal of the drive circuit, the second pole of the drive transistor is electrically connected to the second terminal of the drive circuit, the first gate is a top gate, and the second gate is a bottom gate.

[0252] Selectively, the drive transistor may be a single-gate transistor or a double-gate transistor. When the drive transistor is a double-gate transistor, the first gate of the drive transistor is electrically connected to the control terminal of the drive circuit, and the second gate of the drive transistor is electrically connected to the first voltage line, the first gate is the top gate and the second gate is the bottom gate, and a bias voltage is applied to the substrate of the drive transistor to improve the hysteresis phenomenon of the drive transistor.

[0253] As shown in Figure 50, in addition to at least one embodiment of the pixel circuit shown in Figure 49, the first control circuit 12 includes a first transistor T1, the drive circuit 11 includes a drive transistor T0, and the light-emitting element is an organic light-emitting diode O1.

[0254] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0. The compensation control circuit 13 includes a second transistor T2.

[0255] The gate of the second transistor T2 is electrically connected to the second scanning line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0. The first initialization circuit 14 includes a third transistor T3.

[0256] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, the source of the third transistor T3 is electrically connected to the connection node N0, and the first initialization voltage line is used to supply the first initialization voltage Vi1.

[0257] The reset circuit 20 includes a fourth transistor T4.

[0258] The gate of the fourth transistor T4 is electrically connected to the third scanning line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0.

[0259] The light emission control circuit includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0, and the high voltage line is used to supply the high voltage signal VDD.

[0260] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1.

[0261] The second initialization circuit 32 includes a seventh transistor T7. The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage line is used to supply the second initialization voltage Vi2.

[0262] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C.

[0263] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the drive transistor T0.

[0264] The first terminal of the storage capacitor C is electrically connected to the gate of the drive transistor T0, and the second terminal of the storage capacitor C is electrically connected to the high-voltage line.

[0265] The cathode of O1 is electrically connected to a low-voltage line that supplies the low-voltage VSS.

[0266] In Figure 50, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0.

[0267] The node labeled N2 is the second node, and the node labeled N3 is the third node. N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0268] In at least one embodiment shown in Figure 50, the first voltage line is a high-voltage line and the second voltage line is a low-voltage line.

[0269] In at least one embodiment of the pixel circuit shown in Figure 50, T1 may be an oxide thin-film transistor, and T0, T2, T3, T4, T5, T6, T7, and T8 may all be low-temperature polysilicon thin-film transistors, T1 is an N-type transistor, T0, T2, T3, T4, T5, T6, T7, and T8 are P-type transistors, and T0 is a single-gate transistor, but is not limited to this.

[0270] In at least one embodiment of the pixel circuit shown in Figure 50, N1 is directly electrically connected only to T1, and not directly electrically connected to T2 and T3, in order to reduce leakage of N1 and stabilize the gate potential of T0.

[0271] In at least one embodiment of the pixel circuit shown in Figure 50, T1 is an oxide thin-film transistor to reduce leakage and ensure the stability of the potential of N1.

[0272] Selectively, T2 and T3 are single-gate transistors, which can save space.

[0273] In at least one embodiment of the pixel circuit shown in Figure 50, the initialization control signal supplied by the initialization control line R1 and the second scan signal supplied by the second scan line may both be supplied by a second scan signal generation module.

[0274] Selectively, in at least one embodiment of the pixel circuit, each transistor included in the pixel circuit may be placed on a substrate, and in order to reduce parasitic capacitance, the overlapping area between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the fourth scan line S4 on the substrate is kept to a minimum, and the overlapping area between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the initialization control line R1 on the substrate is kept to a minimum. Preferably, the capacitance between the conductive pattern and the fourth scan line S4 is less than 0.3 Cz, and the capacitance between the conductive pattern for electrically connecting the source of T0 and the source of T5 and the initialization control line R1 is less than 0.3 Cz, where Cz is the capacitance value of the storage capacitor C.

[0275] The conductive pattern includes a source T0, a source T5, and a connecting conductive pattern for electrically connecting the source T0 and the source T5.

[0276] As shown in Figure 51, in at least one embodiment of the pixel circuit shown in Figure 50 of this disclosure, during operation, the display cycle includes an initialization stage t1, a data writing stage t2, and a light emission stage t3, which are set sequentially.

[0277] In initialization phase t1, E1 provides a high voltage signal, S1 provides a high voltage signal, T1 is turned on, R1 provides a low voltage signal, S2 provides a high voltage signal, T2 is turned on, T3 is turned off, Vi1 writes to N1, and T0 is turned on at the start of data writing phase t2. S3 and S4 provide low voltage signals, T7 is turned on, T4 is turned on, the reset voltage supplied from DR is written to N2, Vi2 is written to the anode of O1, O1 is not emitted, and any remaining charge on the anode of O1 is removed.

[0278] During the data writing phase t2, E1 provides a high voltage signal, S1 provides a high voltage signal, T1 is turned on, R1 provides a high voltage signal, S2 provides a high voltage signal, T2 is turned on, T3 is turned off, T8 is turned on, S3 and S4 provide high voltage signals, T7 and T4 are turned off, and the data voltage Vdata on data line D1 is written to N2.

[0279] At the start of data writing phase t2, T0 is turned on, and C is charged through Vdata via the turned-on T8, T0, T2, and T1, causing the potential of N1 to rise until T0 is turned off. When T0 is turned off, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0280] In the light emission stage t3, E1 provides a low voltage signal, R1 provides a high voltage signal, S1 provides a low voltage signal, S2, S3, and S4 provide high voltage signals, T1, T2, T3, T4, T7, and T8 are turned off, T5 and T6 are turned on, T0 is turned on, and O1 is driven to emit light.

[0281] In at least one embodiment of the pixel circuit shown in Figure 50, T4 is added to supply a high voltage to N2, initializing the potential of N2 during non-emitting periods, which is advantageous for improving T0 stability. Then, T7 is provided to initialize the potential of the anode O1, which is advantageous for freely switching the switching frequency under low-frequency flicker.

[0282] As shown in Figure 52, in addition to at least one embodiment of the pixel circuit shown in Figure 49, the first control circuit 12 includes a first transistor T1, the drive circuit 11 includes a drive transistor T0, and the light-emitting element is an organic light-emitting diode O1.

[0283] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0.

[0284] The compensation control circuit 13 includes a second transistor T2.

[0285] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the drive transistor T0.

[0286] The first initialization circuit 14 includes a third transistor T3.

[0287] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, the source of the third transistor T3 is electrically connected to the connection node N0, and the first initialization voltage line is used to supply the first initialization voltage Vi1.

[0288] The reset circuit 20 includes a fourth transistor T4.

[0289] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the source of the drive transistor T0.

[0290] The light emission control circuit includes a fifth transistor T5 and a sixth transistor T6.

[0291] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to a high-voltage line, the source of the fifth transistor T5 is electrically connected to the source of the drive transistor T0, and the high-voltage line is used to supply a high-voltage signal VDD.

[0292] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the drive transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1.

[0293] The second initialization circuit 32 includes a seventh transistor T7.

[0294] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage line is used to supply the second initialization voltage Vi2.

[0295] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C.

[0296] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the drive transistor T0.

[0297] The first terminal of the storage capacitor C is electrically connected to the gate of the drive transistor T0, and the second terminal of the storage capacitor C is electrically connected to the high-voltage line.

[0298] The cathode of O1 is electrically connected to a low-voltage line that supplies the low-voltage VSS.

[0299] In Figure 52, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0.

[0300] The node labeled N2 is the second node, and the node labeled N3 is the third node. N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0301] In at least one embodiment shown in Figure 52, the first voltage line is a high-voltage line and the second voltage line is a low-voltage line.

[0302] In at least one embodiment of the pixel circuit shown in Figure 52, T1 and T7 may be oxide thin-film transistors, and T0, T2, T3, T4, T5, T6, and T8 may all be low-temperature polysilicon thin-film transistors, T1 and T7 are N-type transistors, and T0, T2, T3, T4, T5, T6, and T8 are P-type transistors, and T0 is a single-gate transistor, but is not limited to this.

[0303] At least one embodiment of the pixel circuit shown in Figure 52 of this disclosure differs from at least one embodiment of the pixel circuit shown in Figure 50 of this disclosure in that T7 is an oxide thin-film transistor.

[0304] In at least one embodiment of the pixel circuit shown in Figure 52, N1 is directly electrically connected only to T1, and not directly electrically connected to T2 and T3, in order to reduce leakage of N1 and stabilize the gate potential of T0.

[0305] In at least one embodiment of the pixel circuit shown in Figure 52, T1 and T7 are oxide thin-film transistors to reduce leakage and ensure the stability of the potential of N1 and the anode potential of O1.

[0306] In at least one embodiment of the pixel circuit shown in Figure 52, a separate fourth scan signal generation module can be used to provide the fourth scan signal to the fourth scan line, which is advantageous for the degree of freedom in switching the switching frequency under low-frequency flicker (the switching frequency being the switching frequency of the transistors provided in the second initialization circuit 32). When the display panel to which the pixel circuit is applied operates at a low frequency, if the light emission control circuit 31 controls the off-circuiting between the first voltage line V1 and the second terminal of the drive circuit 11, and controls the off-circuiting between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 30, flicker can be reduced by increasing the frequency of the fourth scan signal, or The fourth scanning line may be the light emission control line, such that, in the low-frequency refresh stage, the light emission control signal supplied from the light emission control line is periodically controlled to periodically reset / adjust the brightness of the light-emitting element and achieve brightness balance.

[0307] As shown in Figure 53, in addition to at least one embodiment of the pixel circuit shown in Figure 49, the first control circuit 12 includes a first transistor T1, the drive circuit 11 includes a drive transistor T0, and the light-emitting element is an organic light-emitting diode O1.

[0308] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0.

[0309] The compensation control circuit 13 includes a second transistor T2.

[0310] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the drive transistor T0.

[0311] The first initialization circuit 14 includes a third transistor T3.

[0312] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, the source of the third transistor T3 is electrically connected to the connection node N0, and the first initialization voltage line is used to supply the first initialization voltage Vi1.

[0313] The reset circuit 20 includes a fourth transistor T4.

[0314] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to a high-voltage line, the source of the fourth transistor T4 is electrically connected to the source of the drive transistor T0, and the high-voltage line is used to supply a high-voltage signal VDD.

[0315] The light emission control circuit includes a fifth transistor T5 and a sixth transistor T6.

[0316] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the source of the drive transistor T0.

[0317] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the drive transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1.

[0318] The second initialization circuit 32 includes a seventh transistor T7.

[0319] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage line is used to supply the second initialization voltage Vi2.

[0320] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C.

[0321] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the drive transistor T0.

[0322] The first terminal of the storage capacitor C is electrically connected to the gate of the drive transistor T0, and the second terminal of the storage capacitor C is electrically connected to the high-voltage line.

[0323] The cathode of O1 is electrically connected to a low-voltage line that supplies the low-voltage VSS.

[0324] In Figure 53, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0.

[0325] The node labeled N2 is the second node, and the node labeled N3 is the third node. N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0326] In at least one embodiment shown in Figure 53, the first voltage line is a high-voltage line and the second voltage line is a low-voltage line.

[0327] In at least one embodiment of the pixel circuit shown in Figure 53, T1 may be an oxide thin-film transistor, and T0, T2, T3, T4, T5, T6, T7, and T8 may all be low-temperature polysilicon thin-film transistors, T1 is an N-type transistor, T0, T2, T3, T4, T5, T6, T7, and T8 are P-type transistors, and T0 is a single-gate transistor, but is not limited to this.

[0328] In at least one embodiment of the pixel circuit shown in Figure 53, N1 is directly electrically connected only to T1, and not directly electrically connected to T2 and T3, in order to reduce leakage of N1 and stabilize the gate potential of T0.

[0329] T1 is an oxide thin-film transistor to reduce leakage in N1 and stabilize the gate potential of T0.

[0330] The difference between at least one embodiment of the pixel circuit shown in Figure 53 of this disclosure and at least one embodiment of the pixel circuit shown in Figure 50 of this disclosure is that the reset voltage line DR is the high voltage line, which reduces the number of signal lines used.

[0331] In at least one embodiment of the pixel circuit shown in Figure 53 of this disclosure, the voltage value of VDD may be 4.6V, the voltage value of VDD is greater than the voltage value of Vi1, and the voltage value of VDD is greater than the voltage value of Vi2.

[0332] In at least one embodiment of the pixel circuit shown in Figure 53 of this disclosure, T7 may be replaced with an oxide thin-film transistor and T0 may be replaced with a double-gate transistor, but is not limited thereto.

[0333] As shown in Figure 54, in addition to at least one embodiment of the pixel circuit shown in Figure 49, the first control circuit 12 includes a first transistor T1, the drive circuit 11 includes a drive transistor T0, and the light-emitting element is an organic light-emitting diode O1.

[0334] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the first gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0.

[0335] The compensation control circuit 13 includes a second transistor T2.

[0336] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the drive transistor T0.

[0337] The first initialization circuit 14 includes a third transistor T3.

[0338] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, the source of the third transistor T3 is electrically connected to the connection node N0, and the first initialization voltage line is used to supply the first initialization voltage Vi1.

[0339] The reset circuit 20 includes a fourth transistor T4.

[0340] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the source of the drive transistor T0.

[0341] The light emission control circuit includes a fifth transistor T5 and a sixth transistor T6.

[0342] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to a high-voltage line, the source of the fifth transistor T5 is electrically connected to the source of the drive transistor T0, and the high-voltage line is used to supply a high-voltage signal VDD.

[0343] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the drive transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1.

[0344] The second initialization circuit 32 includes a seventh transistor T7.

[0345] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage line is used to supply the second initialization voltage Vi2.

[0346] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C.

[0347] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the drive transistor T0.

[0348] The first terminal of the storage capacitor C is electrically connected to the first gate of the drive transistor T0, and the second terminal of the storage capacitor C is electrically connected to the high-voltage line.

[0349] The second gate of the drive transistor T0 is electrically connected to the high-voltage line.

[0350] The cathode of O1 is electrically connected to a low-voltage line that supplies the low-voltage VSS.

[0351] In Figure 54, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0.

[0352] The node labeled N2 is the second node, and the node labeled N3 is the third node. N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0353] In at least one embodiment shown in Figure 54, the first voltage line is a high-voltage line and the second voltage line is a low-voltage line.

[0354] In at least one embodiment of the pixel circuit shown in Figure 54, T1 may be an oxide thin-film transistor, and T0, T2, T3, T4, T5, T6, T7, and T8 may all be low-temperature polysilicon thin-film transistors, T1 is an N-type transistor, T0, T2, T3, T4, T5, T6, T7, and T8 are P-type transistors, and T0 is a double-gate transistor, but is not limited to this.

[0355] In at least one embodiment of the pixel circuit shown in Figure 54, N1 is directly electrically connected only to T1, and not directly electrically connected to T2 and T3, in order to reduce leakage of N1 and stabilize the gate potential of T0.

[0356] In at least one embodiment of the pixel circuit shown in Figure 54, T1 is an oxide thin-film transistor to reduce leakage and ensure the stability of the potential of N1.

[0357] In at least one embodiment of the pixel circuit shown in Figure 54, T0 is a double-gate transistor, the first gate of T0 is the top gate, and the second gate of T0 is the bottom gate. The second gate of T0 is electrically connected to the high-voltage line to apply a bias voltage to the substrate of T0, which is advantageous in improving the hysteresis phenomenon of T0.

[0358] At least one embodiment of the pixel circuit shown in Figure 54 of this disclosure differs from at least one embodiment of the pixel circuit shown in Figure 50 of this disclosure in that T0 is a double-gate transistor.

[0359] In at least one embodiment of the pixel circuit shown in Figure 54 of this disclosure, T7 may be replaced with an oxide thin-film transistor, and DR may be a first voltage line, but is not limited thereto.

[0360] In at least one embodiment of the pixel circuit shown in Figures 50, 52, 53, and 54 of this disclosure, the on-time of T4 can be increased to improve the reset effect of the potential of N2 by increasing the duty cycle of the third scan signal before the data voltage Vdata is written to N2 during the non-emitting period (the non-emitting period may refer to the period excluding the light-emitting stage included in the display cycle).

[0361] As shown in Figure 55, two adjacent rows of pixel circuits can be electrically connected to the reset voltage line of the same row. In Figure 55, the nth row reset voltage line (where n is a positive integer) is labeled DRn, and two pixel circuits located in adjacent columns can be placed mirror images of each other to facilitate wiring.

[0362] As shown in Figure 56, two adjacent rows of pixel circuits can be electrically connected to the reset voltage line of the same row. In Figure 56, the reset voltage line of the mth row (where m is a positive integer) is labeled DRm, and two pixel circuits located in adjacent rows are positioned mirror-image to facilitate wiring.

[0363] As shown in Figure 57, two adjacent rows of pixel circuits can be electrically connected to the reset voltage line of the same row, two adjacent columns of pixel circuits can be electrically connected to the reset voltage line of the same column, two pixel circuits located in adjacent columns are arranged mirror-image, and multiple reset voltage lines are arranged in a grid pattern to facilitate wiring.

[0364] In Figure 57, the line labeled DR11 is the reset voltage line in the first row, the line labeled DR12 is the reset voltage line in the second row, the line labeled DR21 is the reset voltage line in the first column, the line labeled DR22 is the reset voltage line in the second column, and the line labeled DR23 is the reset voltage line in the third column.

[0365] In Figure 58, the line labeled DR11 is the first row reset voltage line, the line labeled DR12 is the second row reset voltage line, the line labeled DR13 is the third row reset voltage line, the line labeled DR14 is the fourth row reset voltage line, the line labeled DR21 is the first column reset voltage line, and the line labeled DR22 is the second column reset voltage line.

[0366] As shown in Figure 58, all pixel circuits in the first row are electrically connected to the first row reset voltage line DR11, all pixel circuits in the second row are electrically connected to the second row reset voltage line DR12, all pixel circuits in the third row are electrically connected to the third row reset voltage line DR13, and all pixel circuits in the fourth row are electrically connected to the fourth row reset voltage line DR14.

[0367] Vertically extending reset voltage lines are provided so that multiple reset voltage lines are arranged in a grid pattern, and to save wiring space, rows of reset voltage lines can be provided for every few rows of pixel circuits.

[0368] Specifically, a reset voltage line extending vertically can be provided on one side of the red pixel circuit array.

[0369] The driving method described in the embodiments of this disclosure is applied to the above-described pixel circuit, and the display cycle includes an initialization stage and a data writing stage. The driving method includes the following:

[0370] During the initialization phase, the first control circuit controls communication between the control terminal of the drive circuit and the connection node based on the control of the first scan signal, and the first initialization circuit writes the first initialization voltage to the control terminal of the drive circuit by writing the first initialization voltage to the connection node based on the control of the initialization control signal. This allows the drive circuit to control communication between its first terminal and its second terminal at the start of the data writing phase.

[0371] During the data writing phase, the first control circuit controls communication between the control terminal of the drive circuit and the connection node based on the control of the first scan signal, and the compensation control circuit controls communication between the connection node and the first terminal of the drive circuit based on the control of the second scan signal, thereby creating communication between the control terminal of the drive circuit and the first terminal of the drive circuit.

[0372] In the driving method according to the embodiment of this disclosure, the first control circuit controls communication between the control terminal of the driving circuit and the connection node, the first initialization circuit writes a first initialization voltage to the connection node based on the control of the initialization control signal, and the compensation control circuit controls communication between the connection node and the first terminal of the driving circuit based on the control of the second scan signal. The first control circuit is directly electrically connected to the control terminal of the driving circuit, while the first initialization circuit and the compensation control circuit are not directly electrically connected to the control terminal of the driving circuit. This reduces the leakage path of the first node (the node electrically connected to the control terminal of the driving circuit), thereby ensuring voltage stability at the first node during low-frequency operation, which is advantageous for improving display quality, display uniformity, and reducing flicker.

[0373] In specific embodiments, the pixel circuit may further include a reset circuit, and the driving method further includes the following:

[0374] In the initialization stage, the reset circuit writes a reset voltage to the second terminal of the drive circuit based on the control of the third scan signal.

[0375] Selectively, the pixel circuit may further include a light-emitting element and a second initialization circuit, and the driving method further includes the following:

[0376] The second initialization circuit writes the second initialization voltage to the first pole of the light-emitting element based on the control of the fourth scanning signal, thereby controlling the light-emitting element to a non-emitting state.

[0377] In a specific embodiment, the pixel circuit further includes a light emission control circuit, a data writing circuit, and an energy storage circuit, the display cycle includes a light emission stage provided after the data writing stage, and the driving method further includes the following:

[0378] During the data writing phase, the data writing circuit writes the data voltage Vdata on the data line to the second terminal of the drive circuit based on the control of the second scan signal.

[0379] At the start of the data writing phase, the drive circuit controls the communication between its first end and its second end so as to charge the energy storage circuit via the data voltage Vdata, and changes the potential of the control end of the drive circuit until the potential of the control end of the drive circuit becomes Vdata + Vth, where Vth is the threshold voltage of the drive transistor included in the drive circuit.

[0380] During the light emission phase, the light emission control circuit controls the communication between the first voltage line and the second end of the drive circuit, and controls the communication between the first end of the drive circuit and the first pole of the light-emitting element, based on the control of the light emission control signal, so that the drive circuit drives the light-emitting element to emit light.

[0381] The display device according to the embodiment of this disclosure includes the pixel circuit described above.

[0382] Selectively, the pixel circuit includes a reset circuit electrically connected to the third scan line and a second initialization circuit electrically connected to the fourth scan line, and the display device receives the third scan signal

[0383] It further includes a generation module and a fourth scanning signal generation module.

[0384] The third scanning signal generation module is electrically connected to the third scanning line in order to supply the third scanning signal to the third scanning line.

[0385] The fourth scanning signal generation module is electrically connected to the fourth scanning line in order to supply the fourth scanning signal to the fourth scanning line.

[0386] In at least one embodiment of the present disclosure, the third scan signal and the fourth scan signal may be the same scan signal, and the third scan signal generation module and the fourth scan signal generation module may be the same module.

[0387] As shown in Figure 59, a display device according to at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, the pixel module P0 includes multiple rows and multiple columns of the above-described pixel circuits, and the pixel module P0 is provided within the effective display area of ​​the display panel.

[0388] The display panel further includes a light emission control signal generation module 70, a first scanning signal generation module 71, a second-first scanning signal generation module 721, a second-second scanning signal generation module 722, a third scanning signal generation module 73, and a fourth scanning signal generation module 74.

[0389] The light emission control signal generation module 70 is used to supply the light emission control signal, the first scan signal generation module 71 is used to supply the first scan signal, the second-first scan signal generation module 721 and the second-second scan signal generation module 722 are used to supply the second scan signal, the third scan signal generation module 73 is used to supply the third scan signal, and the fourth scan signal generation module 74 is used to supply the fourth scan signal.

[0390] The light emission control signal generation module 70, the first scanning signal generation module 71, and the second-first scanning signal generation module 721 are located on the left side of the display panel.

[0391] The second-second scanning signal generation module 722, the third scanning signal generation module 73, and the fourth scanning signal generation module 74 are located to the right of the display panel.

[0392] As shown in Figure 60, a display device according to at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, the pixel module P0 includes multiple rows and multiple columns of the above-described pixel circuit, and the pixel module P0 is provided within the effective display area of ​​the display panel.

[0393] The display panel further includes a light emission control signal generation module 70, a first-first scan signal generation module 711, a first-second scan signal generation module 712, a second-first scan signal generation module 721, a second-second scan signal generation module 722, and a fourth scan signal generation module 74.

[0394] The light emission control signal generation module 70 is used to supply the light emission control signal, the 1-1 scan signal generation module 711 and the 1-2 scan signal generation module 712 are used to supply the first scan signal, and the 2-1 scan signal generation module 721 and the 2-2 scan signal generation module 722 are used to supply the second scan signal. The third scan signal and the fourth scan signal are the same scan signal.

[0395] The fourth scanning signal generation module 74 is used to supply the third scanning signal and the fourth scanning signal.

[0396] The light emission control signal generation module 70, the first-first scanning signal generation module 711, and the second-first scanning signal generation module 721 are located on the left side of the display panel.

[0397] The first-to-second scanning signal generation module 712, the second-to-second scanning signal generation module 722, and the fourth scanning signal generation module 74 are located to the right of the display panel.

[0398] In Figures 55 and 56, the line labeled Vi1 is the first initialization voltage, the line labeled Vi2 is the second initialization voltage, the line labeled VDD is the high-voltage signal, the line labeled D1 is the data line, and the line labeled DR is the reset voltage line.

[0399] The display devices provided by embodiments of this disclosure may be any product or component having a display function, such as a mobile phone, tablet, television, display, laptop computer, digital photo frame, or navigator.

[0400] Figures 61–78 illustrate a series of exemplary embodiments of the pixel driving circuit of the present disclosure.

[0401] The transistors used in all embodiments of this disclosure may be triodes, thin-film transistors, field-effect transistors, or other devices having the same characteristics. In embodiments of this disclosure, in order to distinguish between the two electrodes of the transistor excluding the control electrode, one electrode is referred to as the first electrode and the other electrode as the second electrode.

[0402] In actual operation, if the transistor is a thin-film transistor or a field-effect transistor, the first pole may be the drain and the second pole may be the source. Alternatively, the first pole may be the source and the second pole may be the drain.

[0403] The pixel circuit according to the embodiment of this disclosure includes a drive circuit, a first initialization circuit, and a reset circuit.

[0404] The first initialization circuit is electrically connected to the initialization control line, the first end of the drive circuit, and the first initialization voltage end, respectively, and writes the first initialization voltage supplied from the first initialization voltage end to the first end of the drive circuit based on the control of the initialization control signal supplied from the initialization control line.

[0405] The reset circuit is electrically connected to the second scan line and the reset voltage terminal, respectively, and is also electrically connected to the second terminal or the first terminal of the drive circuit, and controls the writing of the reset voltage supplied from the reset voltage terminal to the second terminal or the first terminal of the drive circuit based on the control of the second scan signal supplied from the second scan line.

[0406] The drive circuit is used to control communication between the first end of the drive circuit and the second end of the drive circuit based on the control of the potential of its control terminal.

[0407] At least one embodiment of the pixel circuit of the present disclosure includes a first initialization circuit and a reset circuit, the first initialization circuit writing a first initialization voltage to the first end of the drive circuit in order to write the first initialization voltage to the control end of the drive circuit in accordance with a compensation control circuit of the pixel circuit before the data voltage is written to the second end of the drive circuit. The reset circuit, based on control of a second scan signal, writes a reset voltage to the second end or the first end of the drive circuit during a non-emitting period before the data voltage is written to the second end of the drive circuit, thereby supplying a bias voltage to the drive transistor in the drive circuit (at which time the gate potential of the drive transistor is also initialized to Vi1), so that the drive transistor maintains a reset state, thereby improving the hysteresis of the drive transistor and shortening the response time (FFR) of the first frame of the display screen.

[0408] In specific embodiments, hysteresis in the drive transistor may slow down the characteristic response of the drive transistor. However, in at least one embodiment of the present disclosure, the gate-source voltage of the drive transistor is rapidly reset before the data voltage is written, which is advantageous for accelerating the recovery speed of the drive transistor, thereby improving the hysteresis phenomenon of the drive transistor and improving the hysteresis recovery speed.

[0409] In at least one embodiment of the present disclosure, a separate second scan signal generation module can be used to supply a second scan signal to the second scan line, which is advantageous for resetting the potential of the second end of the drive circuit.

[0410] In at least one embodiment of the present disclosure, the reset voltage is a constant voltage, supplying a fixed bias voltage to the drive transistor and improving hysteresis.

[0411] Selectively, the first initialization voltage is a low-potential constant voltage, and the voltage value of the first initialization voltage is between -6V and -2V. For example, the voltage value of the first initialization voltage may be -6V, -5V, -4V, -3V, or -2V, but is not limited to these.

[0412] In a specific embodiment, the reset voltage may be a high-potential constant voltage to ensure that the drive transistor in the drive circuit conducts quickly at the start of the data writing phase, and the voltage value of the reset voltage is 4V or more and 10V or less. Alternatively, The reset voltage may be a low-potential constant voltage, and the voltage value of the reset voltage is between -6V and -2V.

[0413] Selectively, when the reset voltage is a high-potential constant voltage, the voltage value of the reset voltage may be, for example, 4V, 5V, 6V, 7V, 8V, 9V, or 10V, but is not limited thereto.

[0414] When the reset voltage is a low-potential constant voltage, the voltage value of the reset voltage may be, for example, -6V, -5V, -4V, -3V, or -2V, but is not limited to these.

[0415] In at least one embodiment of the present disclosure, when the reset voltage is a low-potential constant voltage, the voltage value of the reset voltage is approximately the same as the voltage value of the first initialization voltage so as not to cause failure of the drive transistor in the drive circuit when the reset voltage is written to the second terminal of the drive circuit via the reset circuit and the first initialization voltage is written to the first terminal of the drive circuit via the first initialization circuit.

[0416] The statement that the reset voltage is approximately the same as the first initialization voltage means that the absolute difference between the reset voltage and the first initialization voltage is smaller than a predetermined voltage difference. For example, the predetermined voltage difference may be 0.1V or 0.05V, but is not limited to these.

[0417] In at least one embodiment of the present disclosure, the threshold voltage Vth of the drive transistor in the drive circuit may be -5V or more and -2V or less, preferably Vth may be -4V or more and -2.5V or less, for example, Vth may be -4V, -3.5V, -3V, or -2.5V, but is not limited thereto.

[0418] Selectively, the drive circuit includes a drive transistor, and the absolute value of the reset voltage is greater than 1.5 times the absolute value of the threshold voltage, to ensure that the bias effect can be achieved quickly in a short time. The threshold voltage is the threshold voltage of the drive transistor. For example, the absolute value of the reset voltage may be greater than 2, 2.5, or 3 times the absolute value of the threshold voltage, but is not limited to these.

[0419] As shown in Figure 61, the pixel circuit according to the embodiment of this disclosure includes a drive circuit 11, a first initialization circuit 13, and a reset circuit 20.

[0420] The first initialization circuit 13 is electrically connected to the initialization control line R1, the first terminal of the drive circuit 11, and the first initial voltage terminal, respectively, and writes the first initialization voltage Vi1 supplied from the first initial voltage terminal to the first terminal of the drive circuit 11 based on the control of the initialization control signal supplied from the initialization control line R1.

[0421] The reset circuit 20 is electrically connected to the second scan line S2 and the reset voltage terminal DR, respectively, and is also electrically connected to the second terminal of the drive circuit 11. Based on the control of the second scan signal supplied from the second scan line S2, the reset circuit 20 controls the reset voltage supplied from the reset voltage terminal DR to be written to the second terminal of the drive circuit 11.

[0422] The drive circuit 11 is used to control communication between the first end of the drive circuit 11 and the second end of the drive circuit 12 based on the control of the potential of its control terminal. In Figure 61, the node labeled N1 is the first node, and the first node N

[0423] 1 is electrically connected to the control terminal of the drive circuit 11.

[0424] In at least one embodiment of the pixel circuit shown in Figure 61 of this disclosure, the display cycle may include an initialization step and a reset step during operation.

[0425] In the initialization stage, the first initialization circuit 13 writes the first initialization voltage Vi1 to the first terminal of the drive circuit 11 based on the control of the initialization control signal.

[0426] During the reset phase, the reset circuit 20 writes a reset voltage to the second terminal of the drive circuit 11 based on the control of the second scan signal.

[0427] As shown in Figure 62, a pixel circuit according to at least one embodiment of the present disclosure includes a drive circuit 11, a first initialization circuit 13, and a reset circuit 20.

[0428] The first initialization circuit 13 is electrically connected to the initialization control line R1, the first terminal of the drive circuit 11, and the first initial voltage terminal, respectively, and writes the first initialization voltage Vi1 supplied from the first initial voltage terminal to the first terminal of the drive circuit 11 based on the control of the initialization control signal supplied from the initialization control line R1.

[0429] The reset circuit 20 is electrically connected to the second scan line S2 and the reset voltage terminal DR, respectively, and is also electrically connected to the first terminal of the drive circuit 11. Based on the control of the second scan signal supplied from the second scan line S2, the reset circuit 20 controls the reset voltage supplied from the reset voltage terminal DR to be written to the first terminal of the drive circuit 11.

[0430] In at least one embodiment of the pixel circuit shown in Figure 62 of this disclosure, the display cycle may include an initialization step and a reset step during operation.

[0431] In the initialization stage, the first initialization circuit 13 writes the first initialization voltage Vi1 to the first terminal of the drive circuit 11 based on the control of the initialization control signal.

[0432] During the reset phase, the reset circuit 20 writes a reset voltage to the first terminal of the drive circuit 11 based on the control of the second scan signal.

[0433] Selectively, the first initialization circuit includes a second transistor.

[0434] The control pole of the second transistor is electrically connected to the initialization control line, the first pole of the second transistor is electrically connected to the first initialization voltage terminal, and the second pole of the second transistor is electrically connected to the first terminal of the drive circuit.

[0435] In at least one embodiment of the present disclosure, the second transistor may be, but is not limited to, a low-temperature polysilicon thin-film transistor.

[0436] Selectively, the reset circuit includes a third transistor.

[0437] The control pole of the third transistor is electrically connected to the second scan line, the first pole of the third transistor is electrically connected to the reset voltage terminal, and the second pole of the third transistor is electrically connected to the second terminal or the first terminal of the drive circuit.

[0438] In at least one embodiment of the present disclosure, the pixel circuit may include a compensation control circuit.

[0439] The compensation control circuit is electrically connected to the first scan line, the control terminal of the drive circuit, and the first terminal of the drive circuit, respectively, and controls communication between the control terminal of the drive circuit and the first terminal of the drive circuit based on the control of the first scan signal supplied from the first scan line.

[0440] In at least one embodiment of the present disclosure, the pixel circuit may, during operation, have a display cycle that includes an initialization phase, in which a first initialization circuit writes a first initialization voltage to the first end of a drive circuit based on the control of an initialization control signal, and a compensation control circuit writes the first initialization voltage to the control end of the drive circuit by controlling the communication between the control end of the drive circuit and the first end of the drive circuit based on the control of a first scan signal. Therefore, at the start of the data writing phase, the drive circuit can control the communication between the first end of the drive circuit and the second end of the drive transistor based on the control of the potential of its control end.

[0441] In the pixel circuit described in at least one embodiment of the present disclosure, the control terminal of the drive circuit is directly electrically connected only to the compensation control circuit, and the first initialization circuit is directly electrically connected to the first terminal of the drive circuit. This initializes the potential of the control terminal of the drive circuit via the compensation control circuit and the first initialization circuit, reducing leakage paths to the control terminal of the drive circuit and ensuring voltage stability at the first node without significantly increasing the design complexity of the pixel circuit, which is advantageous for improving display quality, display uniformity, and reducing flicker.

[0442] Selectively, the compensation control circuit includes a first transistor.

[0443] The control pole of the first transistor is electrically connected to the first scan line, the first pole of the first transistor is electrically connected to the control terminal of the drive circuit, and the second pole of the first transistor is electrically connected to the first terminal of the drive circuit.

[0444] The first transistor is an oxide thin-film transistor.

[0445] In embodiments of this disclosure, the compensation control circuit may include a first transistor which is an oxide thin-film transistor. Oxide transistors have good hysteresis characteristics and low leakage current, but low mobility. Therefore, in at least one embodiment of this disclosure, the first transistor is provided as an oxide thin-film transistor to achieve low leakage and ensure the stability of the potential at the control terminal of the drive circuit.

[0446] As shown in Figure 63, in addition to the at least one embodiment of the pixel circuit shown in Figure 61, the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit 12.

[0447] The compensation control circuit 12 is electrically connected to the first scan line S1, the control terminal of the drive circuit 11, and the first terminal of the drive circuit 11, respectively, and controls communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal supplied from the first scan line S1.

[0448] In at least one embodiment of the pixel circuit shown in Figure 63 of this disclosure, during operation, the display cycle may include an initialization phase, in which the compensation control circuit 12 controls communication between the control end of the drive circuit 11 and the first end of the drive circuit 11 based on the control of the first scan signal.

[0449] As shown in Figure 64, in addition to the at least one embodiment of the pixel circuit shown in Figure 62, the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit 12.

[0450] The compensation control circuit 12 is electrically connected to the first scan line S1, the control terminal of the drive circuit 11, and the first terminal of the drive circuit 11, respectively, and controls communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal supplied from the first scan line S1.

[0451] In at least one embodiment of the pixel circuit shown in Figure 64 of this disclosure, during operation, the display cycle may include an initialization phase, in which the compensation control circuit 12 controls communication between the control end of the drive circuit 11 and the first end of the drive circuit 11 based on the control of the first scan signal.

[0452] In at least one embodiment of the present disclosure, the pixel circuit may further include a light-emitting element, an energy storage circuit, a second initialization circuit, a data writing circuit, and a light-emitting control circuit.

[0453] The energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy. The second initialization circuit is electrically connected to the third scan line, the second initialization voltage terminal, and the first pole of the light-emitting element, respectively, and writes the second initialization voltage supplied from the second initialization voltage terminal to the first pole of the light-emitting element based on the control of the third scan signal supplied from the third scan line.

[0454] The data writing circuit is electrically connected to the fourth scan line, the data line, and the second terminal of the drive circuit, respectively, and writes the data voltage supplied from the data line to the second terminal of the drive circuit based on the control of the fourth scan signal supplied from the fourth scan line.

[0455] The light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, the second terminal of the drive circuit, the first terminal of the drive circuit, and the first pole of the light-emitting element, respectively. Based on the control of the light-emitting control signal supplied from the light-emitting control line, it controls the communication between the first voltage terminal and the second terminal of the drive circuit, and controls the communication between the first terminal of the drive circuit and the first pole of the light-emitting element.

[0456] The second pole of the light-emitting element is electrically connected to the second voltage terminal.

[0457] In at least one embodiment of the present disclosure, the pixel circuit further includes a light-emitting element, an energy storage circuit, a second initialization circuit, a data writing circuit, and a light-emitting control circuit. The second initialization circuit initializes a first pole of the light-emitting element; the data writing circuit writes a data voltage to a second terminal of a drive circuit; and the light-emitting control circuit controls communication between the first voltage terminal and the second terminal of the drive circuit, and communication between the first terminal of the drive circuit and the first pole of the light-emitting element, based on control of a light-emitting control signal.

[0458] Selectively, the light-emitting element may be an organic light-emitting diode, the first electrode of the light-emitting element may be the anode of the organic light-emitting diode, and the second electrode of the light-emitting element may be the cathode of the organic light-emitting diode.

[0459] The first voltage terminal may be a high-voltage terminal, and the second voltage terminal may be a low-voltage terminal.

[0460] However, this is not the only option.

[0461] As shown in Figure 65, in addition to the at least one embodiment of the pixel circuit shown in Figure 63, the pixel circuit according to at least one embodiment of the present disclosure may further include a light-emitting element 40, an energy storage circuit 41, a second initialization circuit 42, a data writing circuit 43, and a light-emitting control circuit 44.

[0462] The energy storage circuit 41 is electrically connected to the control terminal of the drive circuit 11 and is used to store electrical energy.

[0463] The second initialization circuit 42 is electrically connected to the third scan line S3, the second initialization voltage terminal, and the first pole of the light-emitting element 40, respectively, and writes the second initialization voltage Vi2 supplied from the second initialization voltage terminal to the first pole of the light-emitting element 40 based on the control of the third scan signal supplied from the third scan line S3.

[0464] The data writing circuit 43 is electrically connected to the fourth scan line S4, the data line D1, and the second terminal of the drive circuit 11, respectively, and writes the data voltage supplied from the data line D1 to the second terminal of the drive circuit 11 based on the control of the fourth scan signal supplied from the fourth scan line S4.

[0465] The light emission control circuit 44 is electrically connected to the light emission control line E1, the first voltage terminal V1, the second terminal of the drive circuit 11, the first terminal of the drive circuit 11, and the first pole of the light-emitting element 40, respectively. Based on the control of the light emission control signal supplied from the light emission control line E1, it controls the communication between the first voltage terminal V1 and the second terminal of the drive circuit 11, and controls the communication between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40.

[0466] The second pole of the light-emitting element 40 is electrically connected to the second voltage terminal V2.

[0467] In at least one embodiment of the pixel circuit shown in Figure 65 of this disclosure, during operation, the display cycle further includes a data writing step and an illumination step, which are provided after the initialization step.

[0468] During the data writing stage, the data writing circuit 43 writes the data voltage Vdata supplied from the data line D1 to the second terminal of the drive circuit 11 based on the control of the fourth scan signal, and the compensation control circuit 12 controls the communication between the control terminal of the control drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal.

[0469] At the start of the data writing stage, the drive circuit 11 changes the potential of the control terminal of the drive circuit 11 until the potential of the control terminal of the drive circuit 11 becomes Vdata + Vth, by conducting the connection between the first terminal and the second terminal of the drive circuit 11, based on the control of its control terminal, so as to charge the energy storage circuit 41 via the data voltage Vdata, where Vth is the threshold voltage of the drive transistor provided in the drive circuit 11.

[0470] During the light emission phase, the light emission control circuit 44 controls the communication between the first voltage terminal V1 and the second terminal of the drive circuit 11 based on the control of the light emission control signal, and controls the communication between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40, so that the drive circuit 11 drives the light-emitting element 40 to emit light.

[0471] In a specific embodiment, the reset step may be set between the initialization step and the data writing step, but is not limited thereto.

[0472] As shown in Figure 66, in addition to the at least one embodiment of the pixel circuit shown in Figure 64, the pixel circuit described in at least one embodiment of the present disclosure may further include a light-emitting element 40, an energy storage circuit 41, a second initialization circuit 42, a data writing circuit 43, and a light-emitting control circuit 44.

[0473] The energy storage circuit 41 is electrically connected to the control terminal of the drive circuit 11 and is used to store electrical energy.

[0474] The second initialization circuit 42 is electrically connected to the third scan line S3, the second initialization voltage terminal, and the first pole of the light-emitting element 40, respectively, and writes the second initialization voltage Vi2 supplied from the second initialization voltage terminal to the first pole of the light-emitting element 40 based on the control of the third scan signal supplied from the third scan line S3.

[0475] The data writing circuit 43 is electrically connected to the fourth scan line S4, the data line D1, and the second terminal of the drive circuit 11, respectively, and writes the data voltage supplied from the data line D1 to the second terminal of the drive circuit 11 based on the control of the fourth scan signal supplied from the fourth scan line S4.

[0476] The light emission control circuit 44 is electrically connected to the light emission control line E1, the first voltage terminal V1, the second terminal of the drive circuit 11, the first terminal of the drive circuit 11, and the first pole of the light-emitting element 40, respectively. Based on the control of the light emission control signal supplied from the light emission control line E1, it controls the communication between the first voltage terminal V1 and the second terminal of the drive circuit 11, and controls the communication between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40.

[0477] The second pole of the light-emitting element 40 is electrically connected to the second voltage terminal V2.

[0478] In at least one embodiment of the pixel circuit shown in Figure 66 of this disclosure, during operation, the display cycle further includes a data writing step and an illumination step, which are provided after the initialization step.

[0479] During the data writing stage, the data writing circuit 43 writes the data voltage Vdata supplied from the data line D1 to the second terminal of the drive circuit 11 based on the control of the fourth scan signal, and the compensation control circuit 12 controls the communication between the control terminal of the control drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal.

[0480] At the start of the data writing stage, the drive circuit 11 changes the potential of the control terminal of the drive circuit 11 until the potential of the control terminal of the drive circuit 11 becomes Vdata + Vth, by conducting the connection between the first terminal and the second terminal of the drive circuit 11, based on the control of its control terminal, so as to charge the energy storage circuit 41 via the data voltage Vdata, where Vth is the threshold voltage of the drive transistor provided in the drive circuit 11.

[0481] During the light emission phase, the light emission control circuit 44 controls the communication between the first voltage terminal V1 and the second terminal of the drive circuit 11 based on the control of the light emission control signal, and controls the communication between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40, so that the drive circuit 11 drives the light-emitting element 40 to emit light.

[0482] As shown in Figure 67, a pixel circuit according to at least one embodiment of the present disclosure may further include a drive circuit 11, a compensation control circuit 12, a first initialization circuit 13, a light-emitting element 40, an energy storage circuit 41, a second initialization circuit 42, a data writing circuit 43, and a light-emitting control circuit 44.

[0483] The compensation control circuit 12 is electrically connected to the first scan line S1, the control terminal of the drive circuit 11, and the first terminal of the drive circuit 11, respectively, and controls communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal supplied from the first scan line S1.

[0484] The first initialization circuit 13 is electrically connected to the initialization control line R1, the first end of the drive circuit 11, and the first initialization voltage terminal, respectively, and writes the first initialization voltage Vi1 supplied from the first initialization voltage terminal to the first end of the drive circuit 11 based on the control of the initialization control signal supplied from the initialization control line R1.

[0485] The drive circuit 11 controls communication between the first end of the drive circuit 11 and the second end of the drive circuit 12 based on the control of the potential of its control terminal.

[0486] The energy storage circuit 41 is electrically connected to the control terminal of the drive circuit 11 and is used to store electrical energy.

[0487] The second initialization circuit 42 is electrically connected to the third scan line S3, the second initialization voltage terminal, and the first pole of the light-emitting element 40, respectively, and writes the second initialization voltage Vi2 supplied from the second initialization voltage terminal to the first pole of the light-emitting element 40 based on the control of the third scan signal supplied from the third scan line S3.

[0488] The data writing circuit 43 is electrically connected to the fourth scan line S4, the data line D1, and the second terminal of the drive circuit 11, respectively, and writes the data voltage supplied from the data line D1 to the second terminal of the drive circuit 11 based on the control of the fourth scan signal supplied from the fourth scan line S4.

[0489] The light emission control circuit 44 is electrically connected to the light emission control line E1, the first voltage terminal V1, the second terminal of the drive circuit 11, the first terminal of the drive circuit 11, and the first pole of the light-emitting element 40, respectively. Based on the control of the light emission control signal supplied from the light emission control line E1, it controls the communication between the first voltage terminal V1 and the second terminal of the drive circuit 11, and controls the communication between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40.

[0490] The second pole of the light-emitting element 40 is electrically connected to the second voltage terminal V2.

[0491] In at least one embodiment of the pixel circuit shown in Figure 67 of this disclosure, during operation, the display cycle includes sequentially set initialization steps, data writing steps, and light emission steps.

[0492] During the initialization phase, the first initialization circuit 13 writes a first initialization voltage Vi1 to the first terminal of the drive circuit 11 based on the control of the initialization control signal, and the compensation control circuit 12 writes the first initialization voltage Vi1 to the control terminal of the drive circuit 11 by controlling the communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal. Therefore, at the start of the data writing phase, the drive circuit 11 can control the communication between the first terminal of the drive circuit 11 and the second terminal of the drive transistor 11 based on the control of the potential of its control terminal.

[0493] During the data writing stage, the data writing circuit 43 writes the data voltage Vdata supplied from the data line D1 to the second terminal of the drive circuit 11 based on the control of the fourth scan signal, and the compensation control circuit 12 can control the communication between the control terminal of the drive circuit 11 and the first terminal of the drive circuit 11 based on the control of the first scan signal.

[0494] At the start of the data writing stage, the drive circuit 11 changes the potential of the control terminal of the drive circuit 11 until the potential of the control terminal of the drive circuit 11 becomes Vdata + Vth, by conducting the connection between the first terminal and the second terminal of the drive circuit 11, based on the control of its control terminal, so as to charge the energy storage circuit 41 via the data voltage Vdata, where Vth is the threshold voltage of the drive transistor provided in the drive circuit 11.

[0495] During the light emission phase, the light emission control circuit 44 controls the communication between the first voltage terminal V1 and the second terminal of the drive circuit 11 based on the control of the light emission control signal, and controls the communication between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40, so that the drive circuit 11 drives the light-emitting element 40 to emit light.

[0496] In at least one embodiment of the pixel circuit shown in Figures 65, 66, and 67, a separate third scan signal generation module can be used to provide a third scan signal to the third scan line, which is advantageous, but not limited to, the degree of freedom in switching the switching frequency under low-frequency flicker (the switching frequency being the switching frequency of the transistors in the second initialization circuit). In a specific embodiment, the third scan signal may be the same scan signal as the fourth scan signal.

[0497] When the display panel to which the pixel circuit is applied operates at a low frequency, if the light emission control circuit 44 controls the off-circuit between the first voltage line V1 and the second terminal of the drive circuit 11, and controls the off-circuit between the first terminal of the drive circuit 11 and the first pole of the light-emitting element 40, flicker can be reduced by increasing the frequency of the third scanning signal.

[0498] In at least one embodiment of this disclosure, the second scan signal and the third scan signal may be the same scan signal, and the second scan signal generation module and the third scan signal generation module may be the same module, but are not limited thereto. In specific implementations, the second scan signal may be a different scan signal from the third scan signal.

[0499] In at least one embodiment of the pixel circuit shown in Figures 65, 66, and 67 of the present disclosure, during operation, in a non-emitting period, before the data voltage is written to the second terminal of the drive circuit 11, the second initialization circuit 42 controls the light-emitting element 40 to not emit light by writing a second initialization voltage Vi2 supplied from the second initialization voltage terminal to the first pole of the light-emitting element 40 based on the control of the third scan signal supplied from the third scan line S3, thereby removing any residual charge on the first pole of the light-emitting element 40.

[0500] In at least one embodiment of the present disclosure, the time interval between the initialization step and the data writing step is made larger than a predetermined time interval in order to improve the hysteresis phenomenon of the drive transistor and reduce high and low frequency flicker of the pixel circuit by pre-initializing the gate potential of the drive transistor.

[0501] In specific embodiments, the predetermined time interval can be selected according to the actual circumstances.

[0502] In at least one embodiment of the pixel circuit shown in Figures 65, 66, and 67 of this disclosure, the initialization control signal and the fourth scan signal supplied from the initialization control line R1 may be generated by the same fourth scan signal generation module, the fourth scan signal may be the Nth stage fourth scan signal generated by the fourth scan signal generation module, and the initialization control signal may be the NMth stage fourth scan signal generated by the fourth scan signal generation module, thereby pre-initializing the gate potential of the drive transistor. N is a positive integer and M is a positive integer greater than 6, for example, M may be 14, but is not limited thereto.

[0503] Selectively, the data writing circuit includes a fourth transistor.

[0504] The control pole of the fourth transistor is electrically connected to the fourth scan line, the first pole of the fourth transistor is electrically connected to the data line, and the second pole of the fourth transistor is electrically connected to the second terminal of the drive circuit.

[0505] The light-emitting control circuit includes a fifth transistor and a sixth transistor.

[0506] The control pole of the fifth transistor is electrically connected to the light emission control line, the first pole of the fifth transistor is electrically connected to the first voltage terminal, and the second pole of the fifth transistor is electrically connected to the second terminal of the drive circuit.

[0507] The control pole of the sixth transistor is electrically connected to the light emission control line, the first pole of the sixth transistor is electrically connected to the first end of the drive circuit, and the second pole of the sixth transistor is electrically connected to the first pole of the light-emitting element.

[0508] The second initialization circuit includes a seventh transistor.

[0509] The control pole of the seventh transistor is electrically connected to the third scanning line, the first pole of the seventh transistor is electrically connected to the second initialization voltage terminal, and the second pole of the seventh transistor is electrically connected to the first pole of the light-emitting element.

[0510] The drive circuit includes a drive transistor, the control pole of the drive transistor is electrically connected to the control terminal of the drive circuit, the first pole of the drive transistor is electrically connected to the first terminal of the drive circuit, and the second pole of the drive circuit is electrically connected to the second terminal of the drive circuit.

[0511] The energy storage circuit includes a storage capacitor, the first terminal of which is electrically connected to the control terminal of the drive circuit, and the second terminal of which is connected to the first voltage terminal.

[0512] As shown in Figure 68, in addition to at least one embodiment of the pixel circuit shown in Figure 65, the light-emitting element is an organic light-emitting diode O1, the compensation control circuit 12 includes a first transistor T1, and the drive circuit 11 includes a drive transistor T0.

[0513] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the drive transistor T1.

[0514] The first initialization circuit 13 includes a second transistor T2.

[0515] The gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initialization voltage terminal, the source of the second transistor T2 is electrically connected to the drain of the drive transistor T0, and the first initialization voltage terminal is for supplying the first initialization voltage Vi1.

[0516] The reset circuit 20 includes a third transistor T3.

[0517] The gate of the third transistor T3 is electrically connected to the second scan line S2, the drain of the third transistor T3 is electrically connected to the reset voltage terminal DR, and the source of the third transistor T3 is electrically connected to the source of the drive transistor T0.

[0518] The data writing circuit 43 includes a fourth transistor T4.

[0519] The gate of the fourth transistor T4 is electrically connected to the fourth scan line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the source of the drive transistor T0.

[0520] The light emission control circuit includes a fifth transistor T5 and a sixth transistor T6.

[0521] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high-voltage terminal, the source of the fifth transistor T5 is electrically connected to the source of the drive transistor T0, and the high-voltage terminal is for supplying the high-voltage signal VDD.

[0522] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the drive transistor T0, the source of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low-voltage terminal for supplying the low-voltage signal VSS.

[0523] The second initialization circuit 42 includes a seventh transistor T7.

[0524] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage terminal, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage terminal is for supplying the second initialization voltage Vi2.

[0525] The energy storage circuit 41 includes a storage capacitor C, the first terminal of which is electrically connected to the gate of the drive transistor T0, and the second terminal of which is connected to the high-voltage terminal.

[0526] In at least one embodiment of the pixel circuit shown in Figure 68, T1 is an oxide thin-film transistor, T2, T3, T4, T5, T6, and T7 are low-temperature polysilicon thin-film transistors, T1 is an N-type transistor, and T2, T3, T4, T5, T6, and T7 are P-type transistors.

[0527] In at least one embodiment of the pixel circuit shown in Figure 68, N1 is a first node electrically connected to the gate of T0, N2 is a second node electrically connected to the source of T0, and N3 is a third node electrically connected to the drain of T0.

[0528] In at least one embodiment of the pixel circuit shown in Figure 68, the initialization control signal and the fourth scan signal may be provided by the same fourth scan signal generation module.

[0529] In a specific embodiment, if the reset voltage supplied from DR is high, the reset stage and the initialization stage may be different to avoid a gate-source short circuit at T0, while if the reset voltage supplied from DR is low, the reset stage and the initialization stage may be the same.

[0530] As shown in Figure 69, in at least one embodiment of the pixel circuit shown in Figure 68 of this disclosure, when operating, if the reset voltage supplied from the DR is high voltage, the display cycle may include, in order, an initialization stage t1, a reset stage t2, a data writing stage t3, and an illumination stage t4.

[0531] In initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, S4 provides a high voltage signal, S1 provides a high voltage signal, S2 and S3 both provide high voltage signals, T1 and T2 are turned on, and Vi1 is written to N1 to initialize the gate potential of T0 so that T0 is turned on at the start of data writing phase t3.

[0532] In reset phase t2, E1 provides a high voltage signal, R1 provides a high voltage signal, S4 provides a high voltage signal, S1 provides a low voltage signal, S2 and S3 both provide low voltage signals, T3 and T7 are turned on, and the potential of N2 is initialized by the high voltage supplied from DR, resetting the gate-source voltage of T0, thereby increasing the recovery speed of T0, improving the hysteresis phenomenon of T0, and improving the hysteresis recovery speed. In addition, Vi2 is written to the anode of O1 to prevent O1 from emitting light, and any remaining charge on the anode of O1 is removed.

[0533] During the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S4 provides a low voltage signal, S1 provides a high voltage signal, S2 and S3 both provide high voltage signals, T1 is turned on, and T4 is turned on.

[0534] At the start of the data writing phase t3, T0 turns on, and the data voltage Vdata supplied from D1 charges C, raising the potential of N1 until T0 turns off. When T0 turns off, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0535] During the light emission phase, E1 provides a low voltage signal, R1 provides a high voltage signal, S4 provides a high voltage signal, S1 provides a low voltage signal, S2 and S3 both provide high voltage signals, T5, T0 and T6 are turned on, and T0 drives O1 to emit light.

[0536] As shown in Figure 70, in at least one embodiment of the pixel circuit shown in Figure 68 of this disclosure, when the reset voltage supplied from the DR is low during operation, the display cycle may include, in order, an initialization stage t1, a data writing stage t3, and an illumination stage t4.

[0537] In initialization phase t1, E1 provides a high-voltage signal, R1 provides a low-voltage signal, S4 provides a high-voltage signal, S1 provides a high-voltage signal, S2 and S3 both provide low-voltage signals, T1 and T2 are turned on, and Vi1 is written to N1 so that T0 is turned on at the start of data writing phase t3. T3 and T7 are turned on, the reset voltage supplied from DR is written to N2, and Vi2 is written to the anode of O1, resetting the gate-source voltage of T0, thereby increasing the recovery speed of T0, improving the hysteresis phenomenon of T0, and improving the hysteresis recovery speed. In addition, Vi2 is written to the anode of O1 so that O1 does not emit light, and any remaining charge on the anode of O1 is removed.

[0538] During the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S4 provides a low voltage signal, S1 provides a high voltage signal, S2 and S3 provide high voltage signals, T1 is turned on, and T4 is turned on.

[0539] At the start of the data writing phase t3, T0 turns on, and the data voltage Vdata supplied from D1 charges C, raising the potential of N1 until T0 turns off. When T0 turns off, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0540] During the light emission phase, E1 provides a low voltage signal, R1 provides a high voltage signal, S4 provides a high voltage signal, S1 provides a low voltage signal, S2 and S3 provide high voltage signals, T5, T0 and T6 are turned on, and T0 drives O1 to emit light.

[0541] As shown in Figure 71, in at least one embodiment of the pixel circuit shown in Figure 68 of this disclosure, when operating, the initialization control signal supplied from R1 is the N-14th stage fourth scan signal, and the fourth scan signal supplied from S4 is the Nth stage fourth scan signal, the display cycle may include, in order, an initialization stage t1, a reset stage t2, a data writing stage t3, and an illumination stage t4. In the initialization stage t1, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a low voltage signal, S2 and S3 both provide high voltage signals, S4 provides a high voltage signal, T1 and T2 are turned on, and Vi1 is written to N1 such that T0 is turned on at the start of the data writing stage t3.

[0542] In reset phase t2, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 provide low voltage signals, S4 provides a high voltage signal, T3 and T7 are turned on to initialize the potential of N2 with the high voltage supplied from DR and reset the gate-source voltage of T0, thereby increasing the recovery speed of T0, improving the hysteresis phenomenon of T0, and improving the hysteresis recovery speed. In addition, Vi2 is written to the anode of O1 to prevent O1 from emitting light and remove any remaining charge on the anode of O1. Also, T1 is turned on, T2 is turned off, and T5 and T6 are turned off.

[0543] During the data writing phase t3, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 both provide high voltage signals, S4 provides a low voltage signal, T1 and T4 are turned on, Vdata is written to N2, N1 and N3 are connected, C is charged through the data voltage Vdata on D1, the potential of N1 is raised until T0 is turned off, and when T0 is turned off, the gate potential of T0 is Vdata + Vth.

[0544] In the light emission stage t4, E1 provides a low voltage signal, S1 provides a low voltage signal, R1 provides a high voltage signal, S2 and S3 provide high voltage signals, S4 provides a high voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0545] In at least one embodiment of the pixel circuit shown in Figure 68, the reset voltage supplied from DR may be VDD, or DR may be the same signal terminal as E1, or the reset voltage supplied from D4 may be a third initialization voltage, but is not limited to these.

[0546] As shown in Figure 72, in addition to at least one embodiment of the pixel circuit shown in Figure 67, the light-emitting element is an organic light-emitting diode O1, the compensation control circuit 12 includes a first transistor T1, and the drive circuit 11 includes a drive transistor T0.

[0547] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the drive transistor T1.

[0548] The first initialization circuit 13 includes a second transistor T2.

[0549] The gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initialization voltage terminal, the source of the second transistor T2 is electrically connected to the drain of the drive transistor T0, and the first initialization voltage terminal is for supplying the first initialization voltage Vi1.

[0550] The data writing circuit 43 includes a fourth transistor T4.

[0551] The gate of the fourth transistor T4 is electrically connected to the fourth scan line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the source of the drive transistor T0.

[0552] The light emission control circuit includes a fifth transistor T5 and a sixth transistor T6.

[0553] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high-voltage terminal, the source of the fifth transistor T5 is electrically connected to the source of the drive transistor T0, and the high-voltage terminal is for supplying the high-voltage signal VDD.

[0554] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the drive transistor T0, the source of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low-voltage terminal for supplying the low-voltage signal VSS.

[0555] The second initialization circuit 42 includes a seventh transistor T7.

[0556] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage terminal, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage terminal is for supplying the second initialization voltage Vi2.

[0557] The energy storage circuit 41 includes a storage capacitor C, the first terminal of which is electrically connected to the gate of the drive transistor T0, and the second terminal of which is connected to the high-voltage terminal.

[0558] In at least one embodiment of the pixel circuit shown in Figure 72, T1 is an oxide thin-film transistor, T2, T4, T5, T6, and T7 are low-temperature polysilicon thin-film transistors, T1 is an N-type transistor, and T2, T4, T5, T6, and T7 are P-type transistors.

[0559] In at least one embodiment of the pixel circuit shown in Figure 72, N1 is a first node electrically connected to the gate of T0, N2 is a second node electrically connected to the source of T0, and N3 is a third node electrically connected to the drain of T0.

[0560] In at least one embodiment of the pixel circuit shown in Figure 72, the third scan signal and the fourth scan signal are the same scan signal, but are not limited to this.

[0561] As shown in Figure 73, in at least one embodiment of the pixel circuit shown in Figure 72 of this disclosure, during operation, the display cycle may include, in order, an initialization stage t1, a data writing stage t3, and a light emission stage t4.

[0562] In initialization phase t1, E1 provides a high-voltage signal, R1 provides a low-voltage signal, S3 and S4 both provide high-voltage signals, S1 provides a high-voltage signal, T1 and T2 are turned on, and Vi1 is written to N1 so that T0 turns on at the start of data writing phase t3.

[0563] During the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S3 and S4 both provide low voltage signals, S1 provides a high voltage signal, T7 is turned on and Vi2 is written to the anode of O1, T1 and T4 are turned on and the data voltage Vdata of D1 is written to N2, and communication is established between N1 and N3.

[0564] At the start of data writing phase t3, T0 turns on, charges C through Vdata, and raises the gate potential of T0 until the gate potential of T0 becomes Vdata + Vth, and T0 turns off, where Vth is the threshold voltage of T0.

[0565] In the light emission stage t4, E1 provides a low voltage signal, R1 provides a high voltage signal, S3 and S4 provide high voltage signals, S1 provides a low voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0566] As shown in Figure 74, in at least one embodiment of the pixel circuit shown in Figure 72 of this disclosure, when operating, if the initialization control signal supplied from R1 is the N-14th stage fourth scan signal and the fourth scan signal supplied from S4 is the Nth stage fourth scan signal, the display cycle may include, in order, an initialization stage t1, a data writing stage t3, and an illumination stage t4.

[0567] In initialization phase t1, E1 provides a high-voltage signal, R1 provides a low-voltage signal, S3 and S4 both provide high-voltage signals, S1 provides a high-voltage signal, T1 and T2 are turned on, and Vi1 is written to N1 so that T0 turns on at the start of data writing phase t3.

[0568] During the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S3 and S4 both provide low voltage signals, S1 provides a high voltage signal, T7 is turned on and Vi2 is written to the anode of O1, T1 and T4 are turned on and the data voltage Vdata of D1 is written to N2, and communication is established between N1 and N3.

[0569] At the start of data writing phase t3, T0 turns on, charges C through Vdata, and raises the gate potential of T0 until the gate potential of T0 becomes Vdata + Vth, and T0 turns off, where Vth is the threshold voltage of T0.

[0570] In the light emission stage t4, E1 provides a low voltage signal, R1 provides a high voltage signal, S3 and S4 provide high voltage signals, S1 provides a low voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0571] As shown in Figure 74, the time interval between the initialization stage t1 and the data writing stage t3 is relatively long, which allows the potential of N1 to be reset in advance, and is advantageous for improving the hysteresis phenomenon of T0.

[0572] As shown in Figure 75, in addition to at least one embodiment of the pixel circuit shown in Figure 66, the light-emitting element is an organic light-emitting diode O1, the compensation control circuit 12 includes a first transistor T1, and the drive circuit 11 includes a drive transistor T0.

[0573] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the drive transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the drive transistor T1.

[0574] The first initialization circuit 13 includes a second transistor T2.

[0575] The gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initialization voltage terminal, the source of the second transistor T2 is electrically connected to the first pole of the drive transistor T0, and the first initialization voltage terminal is for supplying the first initialization voltage Vi1.

[0576] The reset circuit 20 includes a third transistor T3.

[0577] The gate of the third transistor T3 is electrically connected to the second scan line S2, the drain of the third transistor T3 is electrically connected to the reset voltage terminal DR, and the source of the third transistor T3 is electrically connected to the second pole of the drive transistor T0.

[0578] The data writing circuit 43 includes a fourth transistor T4.

[0579] The gate of the fourth transistor T4 is electrically connected to the fourth scan line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the second pole of the drive transistor T0.

[0580] The light emission control circuit 44 includes a fifth transistor T5 and a sixth transistor T6.

[0581] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high-voltage terminal, the source of the fifth transistor T5 is electrically connected to the second pole of the drive transistor T0, and the high-voltage terminal is for supplying the high-voltage signal VDD.

[0582] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the first pole of the drive transistor T0, the source of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low-voltage terminal for supplying the low-voltage signal VSS.

[0583] The second initialization circuit 42 includes a seventh transistor T7.

[0584] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage terminal, the source of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode O1, and the second initialization voltage terminal is for supplying the second initialization voltage Vi2.

[0585] The energy storage circuit 41 includes a storage capacitor C, the first terminal of which is electrically connected to the gate of the drive transistor T0, and the second terminal of which is connected to the high-voltage terminal.

[0586] In at least one embodiment of the pixel circuit shown in Figure 75, T1 is an oxide thin-film transistor, T2, T3, T4, T5, T6, and T7 are low-temperature polysilicon thin-film transistors, T1 is an N-type transistor, and T2, T3, T4, T5, T6, and T7 are P-type transistors.

[0587] In at least one embodiment of the pixel circuit shown in Figure 75, N1 is a first node electrically connected to the gate of T0, N2 is a second node electrically connected to the second pole of T0, and N3 is a third node electrically connected to the first pole of T0.

[0588] In at least one embodiment of the pixel circuit shown in Figure 75, the first pole of T0 may be a drain and the first pole of T0 may be a source, or the first pole of T0 may be a source and the second pole of T0 may be a drain.

[0589] In at least one embodiment of the pixel circuit shown in Figure 75 of this disclosure, the initialization control signal supplied from R1 may be the N-14th stage fourth scan signal, and the fourth scan signal supplied from S4 may be the Nth stage fourth scan signal, but is not limited thereto.

[0590] As shown in Figure 76, in at least one embodiment of the pixel circuit shown in Figure 75 of this disclosure, during operation, the display cycle may include, in order, an initialization stage t1, a reset stage t2, a data writing stage t3, and an illumination stage t4.

[0591] In initialization phase t1, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a low voltage signal, S2 and S3 both provide high voltage signals, S4 provides a high voltage signal, T1 and T2 are turned on, and Vi1 is written to N1 so that T0 turns on at the start of data writing phase t3.

[0592] In reset phase t2, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 provide low voltage signals, S4 provides a high voltage signal, T3 and T7 are turned on to initialize the potential of N2 with the high voltage supplied from DR and reset the gate-source voltage of T0, thereby increasing the recovery speed of T0, improving the hysteresis phenomenon of T0, and improving the hysteresis recovery speed. In addition, Vi2 is written to the anode of O1 to prevent O1 from emitting light and remove any remaining charge on the anode of O1. Also, T1 is turned on, T2 is turned off, and T5 and T6 are turned off.

[0593] During the data writing phase t3, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 both provide high voltage signals, S4 provides a low voltage signal, T1 and T4 are turned on, Vdata is written to N2, N1 and N3 are connected, C is charged through the data voltage Vdata on D1, the potential of N1 is raised until T0 is turned off, at which point the gate potential of T0 becomes Vdata + Vth.

[0594] In the light emission stage t4, E1 provides a low voltage signal, S1 provides a low voltage signal, R1 provides a high voltage signal, S2 and S3 provide high voltage signals, S4 provides a high voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0595] A driving method according to at least one embodiment of the present disclosure is applied to the above-described pixel circuit, and the display cycle includes an initialization step and a reset step. The driving method includes the following:

[0596] In the initialization stage, the first initialization circuit writes a first initialization voltage to the first terminal of the drive circuit based on the control of the initialization control signal.

[0597] During the reset phase, the reset circuit writes a reset voltage to the second terminal or the first terminal of the drive circuit based on the control of the second scan signal.

[0598] In at least one embodiment of the driving method of the present disclosure, the reset circuit, based on control of the second scan signal, supplies a bias voltage to the drive transistor in the drive circuit (at which time the gate potential of the drive transistor is also initialized to Vi1) by writing a reset voltage to the second or first end of the drive circuit during the non-emitting period before the data voltage is written to the second end of the drive circuit, thereby maintaining the drive transistor in a reset state, improving the hysteresis of the drive transistor and shortening the response time (FFR) of the first frame of the display screen.

[0599] In at least one embodiment of the present disclosure, during the reset phase, when the reset circuit writes a reset voltage to the second terminal of the drive circuit based on the control of the second scan signal, The reset voltage is a high-potential constant voltage, the first initialization voltage is a low-potential constant voltage, the initialization stage and the reset stage are in different time periods, or The reset voltage and the first initialization voltage are low-potential constant voltages, and the initialization stage and the reset stage occur during the same time period or different time periods.

[0600] If, selectively, during the reset phase, the reset circuit writes a reset voltage to the first terminal of the drive circuit based on the control of the second scan signal, then the reset phase and the initialization phase are in different time zones, thereby writing a first initialization voltage to the first terminal of the drive circuit during the initialization phase and writing a reset voltage to the first terminal of the drive circuit during the reset phase.

[0601] In specific embodiments, the pixel circuit may further include a compensation control circuit, and the driving method may also include the following:

[0602] In the initialization stage, the compensation control circuit controls the connection between the control terminal of the drive circuit and the first terminal of the drive circuit based on the control of the first scan signal, and writes the first initialization voltage to the control terminal of the drive circuit.

[0603] In the driving method described in the embodiments of this disclosure, the compensation control circuit controls communication between the control terminal of a control drive circuit and the first terminal of the drive circuit based on the control of a first scan signal, the control terminal of the drive circuit is directly electrically connected only to the compensation control circuit, and the first initialization circuit writes a first initialization voltage to the first terminal of the drive circuit based on the control of an initialization control signal, and the first initialization circuit is directly electrically connected to the first terminal of the drive circuit, thereby initializing the potential of the control terminal of the drive circuit via the compensation control circuit and the first initialization circuit, reducing leakage paths to the control terminal of the drive circuit and ensuring voltage stability at the first node under conditions where the design complexity of the pixel circuit does not significantly increase, which is advantageous for improving display quality, improving display uniformity, and reducing flicker.

[0604] In a specific embodiment, the pixel circuit further includes a data writing circuit and an energy storage circuit, the display cycle further includes a data writing step set after the initialization step, and the driving method further includes the following:

[0605] In the data writing stage, the data writing circuit writes the data voltage Vdata supplied from the data line to the second terminal of the drive circuit based on the control of the fourth scan signal, and the compensation control circuit controls the communication between the control terminal of the control drive circuit and the first terminal of the drive circuit based on the control of the first scan signal.

[0606] At the start of the data writing stage, the drive circuit, based on the control of its control terminal, turns on the connection between the first terminal and the second terminal of the drive circuit and charges the energy storage circuit via the data voltage Vdata, thereby changing the potential of the control terminal of the drive circuit until the potential of the control terminal of the drive circuit becomes Vdata + Vth, where Vth is the threshold voltage of the drive transistor provided in the drive circuit.

[0607] In a specific embodiment, the data writing step may be set after the reset step.

[0608] To selectively pre-initialize the gate potential of the drive transistor, thereby improving the hysteresis phenomenon of the drive transistor and reducing high and low frequency flicker of the pixel circuit, the time interval between the initialization step and the data writing step is made larger than a predetermined time interval.

[0609] In at least one embodiment of the present disclosure, the pixel circuit further includes a light emission control circuit, the display cycle further includes a light emission step set after the data writing step, and the driving method further includes:

[0610] During the light emission phase, the light emission control circuit controls the communication between the first voltage terminal and the second terminal of the drive circuit, and controls the communication between the first terminal of the drive circuit and the first pole of the light-emitting element, based on the control of the light emission control signal, and the drive circuit drives the light emission of the light-emitting element.

[0611] A display device described in at least one embodiment of the present disclosure includes the pixel circuit described above.

[0612] Selectively, the pixel circuit includes a reset circuit and a second initialization circuit, and the display device further includes a second scanning signal generation module and a third scanning signal generation module.

[0613] The reset circuit is electrically connected to the second scan line, and the second initialization circuit is electrically connected to the third scan line.

[0614] The second scanning signal generation module is electrically connected to the second scanning line in order to supply the second scanning signal to the second scanning line.

[0615] The third scanning signal generation module is electrically connected to the third scanning line in order to supply the third scanning signal to the third scanning line.

[0616] Selectively, the second scan signal is the same control signal as the third scan signal.

[0617] The second scanning signal generation module is the same module as the third scanning signal generation module.

[0618] As shown in Figure 77, a display device according to at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, the pixel module P0 includes multiple rows and multiple columns of the above-described pixel circuits, and the pixel module P0 is provided within the effective display area of ​​the display panel.

[0619] The display panel further includes a light emission control signal generation module 70, a first scanning signal generation module 71, a 4-1 scanning signal generation module 721, a 4-2 scanning signal generation module 722, a second scanning signal generation module 73, and a third scanning signal generation module 74.

[0620] The light emission control signal generation module 70 is used to supply the light emission control signal, the first scan signal generation module 71 is used to supply the first scan signal, the 4-1 scan signal generation module 721 and the 4-2 scan signal generation module 722 are used to supply the fourth scan signal, the second scan signal generation module 73 is used to supply the second scan signal, and the third scan signal generation module 74 is used to supply the third scan signal.

[0621] The light emission control signal generation module 70, the first scanning signal generation module 71, and the 4-1 scanning signal generation module 721 are located on the left side of the display panel.

[0622] The 4-2 scanning signal generation module 722, the 2nd scanning signal generation module 73, and the 3rd scanning signal generation module 74 are located to the right of the display panel.

[0623] As shown in Figure 78, a display device according to at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, the pixel module P0 includes multiple rows and multiple columns of the above-described pixel circuits, and the pixel module P0 is provided within the effective display area of ​​the display panel.

[0624] The display panel further includes a light emission control signal generation module 70, a first-first scan signal generation module 711, a first-second scan signal generation module 712, a fourth-first scan signal generation module 721, a fourth-second scan signal generation module 722, and a third scan signal generation module 74.

[0625] The light emission control signal generation module 70 is used to supply the light emission control signal, the first scan signal generation module 71 is used to supply the first scan signal, the 4-1 scan signal generation module 721 and the 4-2 scan signal generation module 722 are used to supply the fourth scan signal, and the third scan signal generation module 74 is used to supply the second scan signal and the third scan signal.

[0626] The light emission control signal generation module 70, the 1-1 scanning signal generation module 711, and the 4-1 scanning signal generation module 721 are located on the left side of the display panel.

[0627] The 4-2 scanning signal generation module 722, the 1-2 scanning signal generation module 712, and the 3rd scanning signal generation module 74 are located to the right of the display panel.

[0628] In Figures 77 and 78, Vi1 is the first initialization voltage, Vi2 is the second initialization voltage, VDD is the high-voltage signal, D1 is the data line, and DR is the reset voltage terminal.

[0629] In embodiments of this disclosure, referring to Figures 6, 7, 12, 14, etc., the width-to-length ratio W / L of the eighth transistor T8 may be approximately equal to the width-to-length ratio W / L of the seventh transistor T7, or, for example, the width-to-length ratio W / L of the eighth transistor T8 may be greater than the width-to-length ratio W / L of the seventh transistor T7, that is, the width-to-length ratio W / L of T8 may be slightly larger, thereby enabling a rapid reset of the N2 node.

[0630] In embodiments of this disclosure, referring to Figures 6, 7, 12, 14, etc., the channel width W of the eighth transistor T8 is 1.5 to 3.5, and may be, for example, 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc., and the channel length L is 2.0 to 4.5, and may be, for example, 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc. The channel width W of the seventh transistor T7 is 1.5 to 3.5, and may be, for example, 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc., and the channel length L is 2.0 to 4.5, and may be, for example, 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0631] Furthermore, referring to Figures 38a and 50, the above-described transistor design can also be applied to the seventh transistor T7 and the first transistor T1 in embodiments such as Figure 38a, and to the fourth transistor T4 and the seventh transistor T7 in embodiments such as Figure 50.

[0632] In embodiments of this disclosure, referring to Figures 6, 7, 12, 14, etc., the width-to-length ratio W / L of the eighth transistor T8 may be approximately equal to the width-to-length ratio W / L of the first transistor T1, or, for example, the width-to-length ratio W / L of the eighth transistor T8 may be smaller than the width-to-length ratio W / L of the first transistor T1, thereby balancing the reset capabilities of the N1 node and the N2 node.

[0633] In embodiments of this disclosure, referring to Figures 6, 7, 12, 14, etc., the width-to-length ratio W / L of the eighth transistor T8 may be greater than the width-to-length ratio W / L of the first transistor T1, thereby improving the reset capability of the N2 node.

[0634] In embodiments of this disclosure, referring to Figures 6, 7, 12, 14, etc., the channel width W of the eighth transistor T8 is 1.5 to 3.5, and may be, for example, 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc., and the channel length L is 2.0 to 4.5, and may be, for example, 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc. The channel width W of the first transistor T1 is 1.5 to 3.5, and may be, for example, 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc., and the channel length L is 2.0 to 4.5, and may be, for example, 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0635] Furthermore, referring to Figure 50, etc., the above transistor design is also applied to the fourth transistor T4 and the third transistor T3 in the embodiment shown in Figure 50, etc.

[0636] The display devices provided by embodiments of this disclosure may be any product or component having a display function, such as a mobile phone, tablet, television, display, laptop computer, digital photo frame, or navigator.

[0637] In all embodiments shown in Figures 1 to 78, the names and reference numerals of functional modules / electrical devices do not limit the specific functions of those functional modules / electrical devices. For example, the drive circuit 1 in Figure 3-26, the drive sub-circuit in Figure 27-45, the drive circuit 11 in Figure 46-60, and the drive circuit 11 in Figure 61-48 all have the same function. Also, for example, the second reset circuit 3 in Figure 3-26, the second complex sub-circuit in Figure 27-45, the reset circuit 20 in Figure 46-60, and the reset circuit 20 in Figure 61-48 all have the same function. Furthermore, for example, the third reset circuit 4 in Figure 3-26, the first reset sub-circuit in Figure 27-45, the second initialization circuit 32 in Figure 46-60, and the second initialization circuit 42 in Figure 60-78 all have the same function. Furthermore, for example, the threshold compensation circuit 8 in Figure 3-26, the second transistor T2 in Figure 27-45, and the compensation control circuits 13 and 12 in Figure 46-60 all have the same function. Also, for example, the data writing circuit 7 in Figure 3-26, the writing sub-circuit in Figure 27-45, the data writing circuit 41 in Figure 46-60, and the data writing circuit 43 in Figure 60-78 all have the same function. Also, for example, the control circuit 5 in Figure 3-26, the first and second light emission control sub-circuits in Figure 27-45, the light emission control circuit 31 in Figure 46-60, and the light emission control circuit 44 in Figure 61-78 all have the same function. For example, the coupling circuit 6 in Figure 3-26, the first capacitor C1 in Figure 27-45, the energy storage circuit 42 in Figure 46-60, and the energy storage circuit 41 in Figure 61-78 all have the same function. Furthermore, for example, the drive transistor T3 in Figure 3-26, the drive transistor T3 in Figure 27-45, the drive transistor T0 in Figure 46-60, and the drive transistor T0 in Figure 61-78 all have the same function. The functional modules / electrical devices having the same function as described above can be substituted for each other to form new embodiments, where the substitution of a functional module / electrical device may include substitution of the structure of the functional module / electrical device itself, or substitution of the voltage state of the signal terminal to which the functional module / electrical device is connected.

[0638] Other embodiments of the Disclosure will be readily apparent to those skilled in the art from the considerations herein and the practice of the Disclosure. This application is intended to cover any variations, uses, or adaptability changes of the Disclosure, which, in accordance with the general principles of the Disclosure, include common or conventional means of the art not disclosed herein. The specification and embodiments are illustrative only, and the true scope and spirit of the Disclosure are shown by the appended claims.

[0639] This disclosure is not limited to the exact configuration described above and shown in the accompanying drawings, and it should be understood that various modifications and changes can be made without departing from the scope of the invention. The scope of this disclosure is limited only by the appended claims.

Claims

1. A pixel driving circuit, A drive transistor in which the gate is connected to the first node, the first pole is connected to the second node, and the second pole is connected to the third node, A data writing circuit connected to the second node and the data signal terminal, which transmits the signal from the data signal terminal to the second node in response to the signal from the first gate drive signal terminal, A threshold compensation circuit connected to the first node, the third node, and the second gate drive signal terminal, which communicates the first node and the third node in response to the signal at the second gate drive signal terminal, A first capacitor connected between the first node and the first gate drive signal terminal, A first control circuit connected to a second power supply terminal and the second node, which transmits the signal from the second power supply terminal to the second node in response to the signal from the enable signal terminal, A third capacitor connected between the first node and the second power supply terminal, A first reset circuit connected to the first node, the first initial signal terminal, and the first reset signal terminal, which transmits the signal from the first initial signal terminal to the first node in response to the signal from the first reset signal terminal, The system includes a second reset circuit connected to the second node and the first power supply terminal, which transmits a signal from the first power supply terminal to the second node in response to a control signal, The first reset circuit includes a first transistor, The first transistor has its gate connected to the first reset signal terminal, its first pole connected to the first initial signal terminal, and its second pole connected to the first node. The second reset circuit includes an eighth transistor, The eighth transistor has a gate that receives the control signal, a first pole connected to the first power supply terminal, and a second pole connected to the second node. The channel width-to-length ratio of the eighth transistor is smaller than the channel width-to-length ratio of the first transistor. A pixel driving circuit characterized by the following features.

2. The channel width of the eighth transistor is 1.5 to 3.5, and the channel length is 2.0 to 4.

5. The channel width of the first transistor is 1.5 to 3.5, and the channel length is 2.0 to 4.

5. The pixel driving circuit according to feature 1.

3. The aforementioned pixel driving circuit further, The system includes a third reset circuit connected to a fourth node, a second initial signal terminal, and a third reset signal terminal, which transmits the signal from the second initial signal terminal to the fourth node in response to the signal from the third reset signal terminal. The fourth node is connected to the light-emitting section. The pixel driving circuit according to feature 1.

4. The third reset circuit includes a seventh transistor, The seventh transistor has its gate connected to the third reset signal terminal, its first pole connected to the second initial signal terminal, and its second pole connected to the fourth node. The channel width-to-length ratio of the eighth transistor is approximately equal to the channel width-to-length ratio of the seventh transistor. The pixel driving circuit according to feature 3.

5. The channel width of the eighth transistor is 1.5 to 3.5, and the channel length is 2.0 to 4.

5. The channel width of the seventh transistor is 1.5 to 3.5, and the channel length is 2.0 to 4.

5. The pixel driving circuit according to feature 4.

6. The aforementioned pixel driving circuit further, A second capacitor is connected between the first node and the second gate drive signal terminal, The conduction level of the data writing circuit is low, the conduction level of the threshold compensation circuit is high, and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor. The pixel driving circuit according to feature 1.

7. The absolute value of the voltage at the first power supply terminal is greater than 1.5 times the absolute value of the threshold voltage of the drive transistor. The pixel driving circuit according to feature 1.

8. The data writing circuit includes a fourth P-type transistor, The P-type fourth transistor has its gate connected to the first gate drive signal terminal, its first pole connected to the second node, and its second pole connected to the data signal terminal. The threshold compensation circuit includes a second N-type transistor, The N-type second transistor has its gate connected to the second gate drive signal terminal, its first pole connected to the first node, and its second pole connected to the third node. The pixel driving circuit according to feature 1.

9. The aforementioned drive transistor is a P-type transistor, The first control circuit is further connected to the third node, the fourth node, and the enable signal terminal, and in response to the signal at the enable signal terminal, it connects the third node and the fourth node. The aforementioned pixel driving circuit further, Includes a coupling circuit connected between the first node and the second power supply terminal. The pixel driving circuit according to feature 1.

10. The voltage at the second initial signal terminal is between -7V and 0V. The pixel driving circuit according to feature 3.

11. The coupling circuit is The third capacitor is connected between the first node and the second power supply terminal, The capacitance value of the third capacitor is greater than the capacitance value of the first capacitor, and the capacitance value of the third capacitor is greater than the capacitance value of the second capacitor. The pixel driving circuit according to feature 9.

12. The third reset circuit includes a seventh transistor, The seventh transistor has its gate connected to the third reset signal terminal, its first pole connected to the second initial signal terminal, and its second pole connected to the fourth node. Here, the first transistor is an N-type transistor, and the seventh and eighth transistors are P-type transistors. The pixel driving circuit according to feature 3.

13. The pixel driving circuit further includes a coupling circuit and a third reset circuit, The first control circuit is, A fifth transistor having its gate connected to the enable signal terminal, its first pole connected to the second power supply terminal, and its second pole connected to the second node, The system includes a sixth transistor whose gate is connected to the enable signal terminal, whose first pole is connected to the third node, and whose second pole is connected to the fourth node, The coupling circuit is The third capacitor is connected between the first node and the second power supply terminal, The third reset circuit is, The system includes a seventh transistor whose gate is connected to the third reset signal terminal, whose first pole is connected to the second initial signal terminal, and whose second pole is connected to the fourth node. Here, the first and second transistors are oxide transistors, and the drive transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, and eighth transistor are low-temperature polysilicon transistors. The pixel driving circuit according to feature 8.

14. The aforementioned pixel driving circuit further, It includes a seventh transistor whose gate is connected to the third reset signal terminal, whose first pole is connected to the second initial signal terminal, and whose second pole is connected to the fourth node, The channel width-to-length ratio of the eighth transistor is greater than the channel width-to-length ratio of the seventh transistor. The pixel driving circuit according to feature 1.

15. The aforementioned pixel driving circuit further, It includes a fourth capacitor connected to the second node and the fifth node, The fifth node receives a pull-down signal before the threshold compensation stage or the initialization stage. The pixel driving circuit according to feature 1.

16. The fifth node receives the pull-down signal before the initialization stage, and the equipotential portion of the fifth node is the third reset signal terminal. The pixel driving circuit according to feature 15.

17. A pixel driving circuit, A drive transistor in which the gate is connected to the first node, the first pole is connected to the second node, and the second pole is connected to the third node, A data writing circuit connected to the second node and the data signal terminal, which transmits the signal from the data signal terminal to the second node in response to the signal from the first gate drive signal terminal, A threshold compensation circuit connected to the first node, the third node, and the second gate drive signal terminal, which communicates the first node and the third node in response to the signal at the second gate drive signal terminal, A first capacitor connected between the first node and the first gate drive signal terminal, A first control circuit connected to a second power supply terminal and the second node, which transmits the signal from the second power supply terminal to the second node in response to the signal from the enable signal terminal, A third capacitor connected between the first node and the second power supply terminal, A first reset circuit connected to the first node, the first initial signal terminal, and the first reset signal terminal, which transmits the signal from the first initial signal terminal to the first node in response to the signal from the first reset signal terminal, The system includes a second reset circuit connected to the second node and the first power supply terminal, which transmits a signal from the first power supply terminal to the second node in response to a control signal, The first reset circuit includes a first transistor, The first transistor has its gate connected to the first reset signal terminal, its first pole connected to the first initial signal terminal, and its second pole connected to the first node. The second reset circuit includes an eighth transistor, The eighth transistor has a gate that receives the control signal, a first pole connected to the first power supply terminal, and a second pole connected to the second node. The channel width-to-length ratio of the eighth transistor is greater than the channel width-to-length ratio of the first transistor. A pixel driving circuit characterized by the following features.

18. The channel width of the eighth transistor is 1.5 to 3.5, and the channel length is 2.0 to 4.

5. The channel width of the first transistor is 1.5 to 3.5, and the channel length is 2.0 to 4.

5. The pixel driving circuit according to feature 17.

19. The aforementioned pixel driving circuit further, The system includes a third reset circuit connected to a fourth node, a second initial signal terminal, and a third reset signal terminal, which transmits the signal from the second initial signal terminal to the fourth node in response to the signal from the third reset signal terminal. The fourth node is connected to the light-emitting section. The pixel driving circuit according to feature 17.

20. The third reset circuit includes a seventh transistor, The seventh transistor has its gate connected to the third reset signal terminal, its first pole connected to the second initial signal terminal, and its second pole connected to the fourth node. The channel width-to-length ratio of the eighth transistor is approximately equal to the channel width-to-length ratio of the seventh transistor. The pixel driving circuit according to feature 19.

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