On-SSD copy techniques using copy-on-write

Abstract

It improves copy performance, saves media durability and logical / physical capacity, reduces power consumption, and improves internal read / write bandwidth. [Solution] The on-SSD copy-on-write operation receives a copy command from the source LBA to copy data to the destination LBA, updates the entry in the logical / physical (L2P) table corresponding to the destination LBA to refer to the same physical address as the entry for the source LBA in the L2P table, updates a flag in the L2P table to indicate that more than one LBA refers to the same physical address, stores a token in the storage device after updating the L2P table but before copying the data, sends an acknowledgment to the host indicating that the copy command is complete after storing the token but before copying the data, and triggers the copy of the data with a subsequent write to either the source or destination LBA.

Description

Technical Field

[0001] This specification generally relates to non-volatile storage media such as NAND flash memory, and specifically relates to on-SSD copy techniques.

Background Art

[0002] Data copy operations on storage devices such as solid state drives, hard disk drives, and memory devices are common operations in computer systems. The data copy operation can be user or system initiated and is used to copy data from a source location to a destination location. Excessive use of the data copy operation can affect the performance in a computer system because the host waits for the data copy operation to complete before executing subsequent tasks.

Brief Description of the Drawings

[0003] The following description includes a discussion of figures having illustrations provided as examples of implementations of embodiments of the present invention. The drawings should be understood as examples and not as limitations. As used herein, reference to one or more “embodiments” or “examples” is understood to describe specific features, structures, and / or characteristics included in at least one implementation of the present invention. Therefore, phrases such as “in one embodiment” or “in one example” that appear herein describe various embodiments and implementations of the present invention and do not necessarily all refer to the same embodiment. On the other hand, they are also not necessarily mutually exclusive.

[0004] [Figure 1] It is a block diagram of an exemplary system including a non-volatile memory (NVM) device.

[0005] [Figure 2] It is a block diagram of an example of an NVM device.

[0006] [Figure 3A] This figure shows an example of a logical-to-physical (L2P) table for an NVM device capable of performing on-SSD copy-on-write operations.

[0007] [Figure 3B] This figure shows an example of a subset physical-to-logical (P2L) table for NVM devices capable of performing on-SSD copy-on-write operations.

[0008] [Figure 3C] This is a block diagram of an example in which at least a portion of the P2L table is stored on a NAND medium and at least a portion of the P2L table is stored in DRAM.

[0009] [Figure 4] This is a flowchart illustrating how to perform on-SSD copy-on-write operation.

[0010] [Figure 5] This is an example of pseudocode that performs the functionality for on-SSD copy commands. [Figure 6] This is an example of pseudocode that performs the functionality for on-SSD copy commands. [Figure 7] This is an example of pseudocode that performs the functionality for on-SSD copy commands. [Figure 8] This is an example of pseudocode that performs the functionality for on-SSD copy commands.

[0011] [Figure 9] This is a flowchart illustrating one example of a defragmentation method.

[0012] [Figure 10] This is an example of pseudocode for defragmentation.

[0013] [Figure 11] A diagram providing an exemplary illustration of a computing system capable of implementing data copy techniques.

[0014] Following is an explanation of the drawings that may show some or all of the embodiments described below, and a discussion of other potential embodiments or implementations of the concepts of the present invention presented herein. Specific details and implementations are described below.

Embodiments for Implementing the Invention

[0015] The on-SSD copy technique using copy-on-write can enable improved copy performance, media durability, logical / physical capacity, power consumption, and internal read / write bandwidth.

[0016] Data copy operations are common in real-world applications. “On-SSD copy” is a technique for copying data inside a solid-state drive (SSD) without transferring the data to host memory. On-SSD copy can significantly improve host performance for copy commands with large data payloads.

[0017] However, on-SSD copy operations can significantly consume media durability, power, and internal read / write bandwidth. In addition, conventional on-SSD copy operations do not conserve the physical and logical capacity of the SSD.

[0018] In contrast, the on-SSD copy technique using copy-on-write (COW) tracks indirect updates to copied data without replicating the data. Therefore, on-SSD copy using copy-on-write significantly enhances copy performance, conserves media durability and logical / physical capacity, reduces power consumption, and improves internal read / write bandwidth.

[0019] In one example, the method of performing an on-SSD copy involves receiving, from a host, a copy command to copy data from a source logical block address (LBA) to a destination logical block address (LBA) in a non-volatile storage device. An entry in a logical / physical (L2P) table corresponding to the destination LBA is updated to reference the same physical address as the entry for the source LBA in the L2P table. A flag in the L2P table is updated to indicate that more than one LBA references the same physical address. After updating the L2P table and before copying the data, a token indicating that the copy command has completed is stored in the non-volatile storage device. After storing the token but before copying the data, an acknowledgement response indicating that the copy command has completed can be sent to the host. A subsequent write to either the source or destination LBA triggers the copy of the data.

[0020] FIG. 1 is a block diagram of an exemplary system that includes a non-volatile memory (NVM) or storage device. System 100 is an example of a system that may implement the on-SSD copy techniques described herein.

[0021] System 100 includes a host 150 and a non-volatile storage or non-volatile memory (NVM) device 120. The NVM device 120 may be a solid-state drive (SSD) or other non-volatile memory device or drive. The host 150 and NVM device 120 can be an example of a system residing within the confines of a computer package (e.g., a laptop / notebook, server, or other computer). In other examples, the NVM 120 may be accessed over a larger network such as a local area network (e.g., an Ethernet® network) or a wide area network (e.g., a wireless cellular network, the Internet, etc.). Such examples may conform to standards such as NVMe-oF (non-volatile memory express over fabrics). The host 150 includes one or more processors 152, memory 154, a storage controller 114, and other components omitted from the drawings for clarity.

[0022] The NVM device 120 includes one or more memory arrays 132 for storing data. Arrays 132 can be memory or storage media capable of storing one or more bits in memory cells. In one example, the array includes a string of memory cells, such as a NAND string, as shown in Figure 2, which is discussed below. In one example, the NVM device 120 includes one or more non-volatile memory dies, each divided into multiple planes or groups. NAND flash memory is typically block-addressable. A typical NAND die has multiple planes per die. One plane contains multiple memory cells, which can be grouped into multiple blocks. A block is typically the smallest erasable entity in a NAND flash die. In one example, one block contains multiple cells coupled to the same bit line. One block contains one or more pages of cells. The size of a page can vary depending on the implementation. In one example, a page has a size of 16kB. Page sizes smaller or larger than 16kB are also possible (e.g., 512B, 2kB, 4kB, etc.). In one example, the NVM device 120 may include a memory device using multi-threshold level NAND flash memory. The array 132 may include single-level cell (SLC) NAND storage devices, multi-level cell (MLC) NAND storage devices, triple-level cell (TLC) NAND storage devices, quad-level cell (QLC) storage devices, penta-level cell (PLC), and / or any other NAND.

[0023] The NVM device 120 communicates with the host system 150 using interfaces 121 and 156, respectively. In one example, interface 156 is part of a peripheral control hub (PCH). In the example shown in Figure 1, the host includes a controller 114 coupled to the NVM device 120 via interface 156 to communicate with and control the NVM device 120. In the example shown, the NVM device 120 includes a controller 104 coupled to a computing platform such as the host 150 via interface 121. In one example, the controller 104 is an ASIC (Application-Specific Integrated Circuit). In one example, the interfaces conform to standards such as PCI Express (PCIe), Serial Advanced Technology Attachment (ATA), Parallel ATA, Universal Serial Bus (USB), and / or other interface protocols. The controller 104 can communicate with elements of the computing platform to read data from or write data to the NAND die 130. In this disclosure, the term “host” refers to a system having an interface for communicating with a processor (or other device that sends requests to access data stored in non-volatile memory) and NAND (e.g., host 150), however, some implementations may refer to the controller 104 as the “host” to the NAND die 130.

[0024] The controller 104 can be configured to receive requests from the host 150 and generate and execute commands related to accessing the array 132 (e.g., reading data, writing data, or erasing data). Other commands may include, for example, commands to read status, commands to change configuration settings, and reset commands. The controller includes control logic that can be implemented using hardware (e.g., circuitry), software, firmware, or a combination of hardware, software, and firmware. Examples of logic circuits include dedicated wiring logic circuits (e.g., one or more state-machine logic circuits) and programmable logic circuits (e.g., field-programmable gate arrays (FPGAs) and programmable logic arrays (PLAs)). In one example, the logic circuit is designed to execute some form of program code, such as SSD firmware (e.g., an embedded processor, an embedded controller, etc.).

[0025] The NVM device 120 may include a memory 117 coupled to a controller 104, which can cache data from a non-volatile medium and store firmware 115 executed by the controller 104. In one example, the memory 117 is volatile memory. Volatile memory is memory whose state (and therefore the data stored in it) is uncertain when power is cut off to the device. Dynamic volatile memory requires refreshing the data stored in the device to maintain its state. One example of dynamic volatile memory is DRAM (Dynamic Random Access Memory), or some variation of synchronous DRAM (SDRAM). Memory subsystems described herein include DDR3 (Double Data Rate version 3, originally released by JEDEC (Japan Electronics Technology Council) on June 27, 2007), DDR4 (DDR version 4, initially published by JEDEC in September 2012), DDR5 (DDR version 5, initially published in July 2020), LPDDR3 (Low Power DDR version 3, JESD209-3B, initially published by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, initially published by JEDEC in August 2014), LPDDR5 (LPDDR version 5, JESD209-5A, initially published by JEDEC in January 2020), WIO2 (Wide Input / Output version 2, JESD229-2, initially published by JEDEC in August 2014), and HBM (High Bandwidth). Multiple memory technologies or combinations of memory technologies, such as Memory (JESD235, originally published by JEDEC in October 2013), HBM2 (HBM version 2, JESD235C, originally published by JEDEC in January 2020), or HBM3 (HBM version 3, currently under consideration by JEDEC), or others, and technologies based on derivatives or extensions of such specifications may be compatible. JEDEC standards are available at www.jedec.org.

[0026] Controller 104 is coupled to the NAND die 130 to control or command the circuitry on the die to trigger the operations to be performed (e.g., read, program, erase, hold, resume, and other operations). Communication between the NAND die 130 and Controller 104 may include writing to and / or reading from specific registers. Such registers may reside within Controller 104, on the NAND die 130, or outside Controller 104 and the NAND die 130. Registers or memory within the die 130 may be reachable by Controller 104, for example, by an internal interface between Controller 104 and the NAND die 130 (e.g., an Open NAND Flash Interface (ONFI) interface, a proprietary interface, or other interface) to enable communication coupling between Controller 104 and the array 132. Input / output (I / O) pins and signal lines enable Controller 104 to communicate with the NAND die 130 to allow the transmission of read and write data between Controller 104 and the NAND die 130. I / O pins may be used to transmit other data, such as die or plane status information of the NAND die 130. The NAND die may also include other pins, such as command pins (e.g., command latch enable (CLE), address latch enable (ALE), chip enable (CE#), read enable (RE#), and write enable (WE#)), and power and ground pins (e.g., Vcc, Vss, etc.). The voltage regulator 140 represents a circuit that provides one or more voltages to the access circuit 135, the sensing circuit 134, and / or the array 132.

[0027] The NAND die 130 includes an access circuit 135 that controls access to the array 132. For example, the access circuit 135 generates a voltage or applies such voltage to the array 132 in order to perform access operations (e.g., read operations, program operations, etc.) based on a command received from the controller 104. The access circuit on the NAND die 130 is coupled to the word lines of the array 132 to select one of the word lines, apply a read voltage, apply a program voltage combined with a bit line potential level, apply a verification voltage, or apply an erase voltage. The sensing circuit 134 and the access circuit 135 are coupled to the bit lines of the array 132 to read data stored in the memory cells, determine the state of the memory cells during a program operation, and control the bit line potential level to facilitate or prevent programming and erasing.

[0028] The example in Figure 1 refers to a NAND device, but other non-volatile memory devices may implement the on-SSD copy technique described herein. Furthermore, although this technique is referred to as "on-SSD" copy for ease of reference, the technique described herein may be implemented on NVM devices other than SSDs (e.g., memory modules such as dual inline DIMMs with non-volatile memory, or other NVM devices).

[0029] Figure 2 is a block diagram of the NVM device 120 in Figure 1. As mentioned above with respect to Figure 1, the NAND controller 104 runs firmware 115 stored in memory 117 to communicate with and control the NAND die 130. In one example, the on-SSD copy-on-write technique 160 is implemented in firmware 115. In the example shown in Figure 2, the firmware that performs on-SSD copy-on-write includes on-SSD copy function 161, trim function 163, write function 165, and defragmentation function 167. The firmware that implements on-SSD copy-on-write refers to modifying the logical / physical (L2P) table 151 and the physical / logical (P2L) table 153, which are also stored in memory 117. Although tables 151 and 153 are shown as being stored in the same memory as firmware 115, the NVM device 120 may include more than one memory or storage device to store the firmware and mapping tables. The NAND medium (e.g., array 132) stores data 169. The NAND medium may also store backups 155 and 157 of the L2P and P2L tables stored in memory. When performing an on-SSD copy-on-write operation, the firmware 115 stores a token 159 in the NAND medium indicating that the on-SSD copy command is complete.

[0030] Figure 3A shows an example of a logical / physical (L2P) table for an NVM device capable of performing on-SSD copy-on-write operation. The L2P table 151 is a mapping table that maps logical block addresses (LBAs) to physical block addresses (PBAs, physical addresses, or NAND addresses). Unlike conventional L2P tables, the L2P table 151 includes an additional reference flag corresponding to each entry or LBA. The reference flag contains one or more bits indicating whether the physical address pointed to by the LBA is referenced by more than one LBA. In the example shown, the reference flag contains one bit per entry indicating whether the NAND address is referenced by multiple L2P entries. In the example shown in Figure 3A, LBAs A and B point to the same NAND address X. Therefore, the reference flag set for the L2P entries corresponding to both LBAs A and B is set to a value indicating that more than one LBA references that physical address.

[0031] In the example shown in Figure 3A, the reference flag is set to "1" to indicate that more than one LBA points to the same physical address, and to "0" to indicate that more than one LBA does not point to the same physical address (for example, only one LBA points to that physical address). However, different conventions may be used for the reference flag. For example, another convention is to set the flag to "0" to indicate that more than one LBA points to the same physical address. In another example, more than one bit is used to indicate that more than one LBA points to the same physical address. For example, the reference flag may include a count of the number of LBAs pointing to the same physical address.

[0032] Figure 3B shows an example of a subset physical / logical (P2L) table for an NVM device capable of performing on-SSD copy-on-write operation. The subset P2L table 153 maps a given physical NAND address to all L2P entries that reference that physical address. Instead of mapping all NAND addresses, it maps only NAND addresses referenced by more than one L2P entry (e.g., more than one LBA). In one example, the subset P2L table is implemented using a hash table employing a chaining method. Any set of standard insert, lookup, and / or delete algorithms may be used to update the P2L table 153. In one example, the subset P2L table 153 is stored in DRAM as an extension of the L2P table 151 and can be periodically dropped to the NAND medium for backup or retrieval purposes.

[0033] Therefore, in the example shown, the P2L table 153 stores only physical addresses pointed to by more than one logical address, and thus typically stores a subset of all physical addresses. In the example shown in Figure 3B, physical address X has two entries in the P2L table 153 because two logical addresses (A and B) refer to physical address X. Physical address Y is not in the subset P2L table 153 because only one logical address (C) refers to physical address Y.

[0034] As previously shown, the subset P2L table is stored in DRAM and backed up on the NAND medium (see, for example, Figure 2). However, in another example, at least a portion of the subset P2L table is stored on the NAND medium, and at least a portion of the P2L table is stored in DRAM. For example, consider a case where the host issues many copy commands. If the number of copy commands received is sufficiently large, the subset P2L table size can expand to be the same size as, or even larger than, the L2P table size. In one example, the subset P2L table size may be limited by write-back, which caches it in the SSD's internal DRAM using the NAND medium as the backing medium and PLI energy to store dirty entries in the event of a power failure. Figure 3C is a block diagram of an example where at least a portion of the P2L table is stored on the NAND medium and at least a portion of the P2L table is stored in DRAM. As can be seen in Figure 3C, a portion of the subset P2L table 153A is stored in the NAND array 132, and a portion of the subset P2L table is stored in memory 117. In one example, the entire subset P2L table 153A is stored on the NAND medium and cached on DRAM. In one such example, the portion of the subset P2L table 153B stored in memory 117 stores the most recently and / or frequently accessed entries on the subset P2L table 153A. In another example, a hierarchical approach to the subset P2L table is implemented in which a portion of the subset P2L table 153B is stored in memory 117 and the rest of the subset P2L table 153A is stored on the NAND medium.

[0035] Therefore, the subset P2L table may be stored only on DRAM (as shown in Figure 2) and backed up on the NAND medium, or it may be stored on both DRAM and the NAND medium (as shown in Figure 3C). In one example where the subset P2L table is stored across both DRAM and the NAND medium, a hierarchical method is used in which the entries of the subset P2L table are divided between the DRAM and the NAND medium. In another example where the subset P2L table is stored across both DRAM and the NAND medium, a caching method is used in which the entire subset P2L table is stored on the NAND medium and a subset of its entries are stored (or cached) on the DRAM.

[0036] Figure 4 is a flowchart of a method for performing on-SSD copy-on-write operation. Method 400 may be performed by hardware (e.g., circuitry), firmware, or a combination of hardware and firmware, such as a controller in the NVM device. In one example, Method 400 is performed by an ASIC controller on the NVM device that executes firmware stored in memory on the NVM device. For example, referring to Figure 2, the NAND controller 104 can execute an instruction in firmware 115 that performs Method 400.

[0037] Method 400 in Figure 4 begins in 402 with the non-volatile storage device receiving a copy command from the host. For example, referring to Figure 1, the NVM device 120 receives a copy command from the host 150 to copy data from a source logical block address (LBA) to a destination logical block address (LBA). The command is transmitted via an interface (for example, via interfaces 156 and 121). Therefore, the host includes an input / output (I / O) circuit that sends the copy command to the NVM device, and the NVM device 120 includes an input / output (I / O) circuit that receives the command from the host according to one or more protocols. In addition to the source and destination addresses, the command may include or specify the number of blocks (or other granularity in memory units) to be copied.

[0038] After receiving a copy command, the controller on the NVM device modifies the logical / physical (L2P) table in 404 to map the destination LBA to the same physical address as the source LBA. For example, referring to Figure 3A, consider a scenario where the copy command indicates that data in LBA A should be copied to LBA C, and the physical address pointed to by LBA C will be updated to point to the same physical address (X) as LBA A. In one such example, before modifying the L2P table to point the destination LBA to the same physical address as the source LBA, any P2L table entries (if any) that associate a different physical address with the destination LBA may be removed. Similarly, before modifying the L2P table to map the destination address to the same physical address as the source address, entries for the destination address in the L2P table may be "zeroed out" or deleted. For example, referring to Figure 3A, consider a scenario where data in LBA A should be copied to LBA C, and the physical address and reference flag corresponding to LBA C will first be deleted (e.g., set to zero).

[0039] Referring again to method 400 in Figure 4, in 406, the flags in the L2P tables corresponding to the source LBA and destination LBA are updated to indicate that more than one LBA refers to the same physical address. For example, referring to Figure 3A, consider a scenario where data stored in LBA A should be copied to LBA C, and the reference flags corresponding to both LBA A and LBA C are set to "1" to indicate that more than one LBA points to physical address X. In this example, the flag for LBA A is already set to "1", so there is no actual change to the flag associated with LBA A. On the other hand, the flag for LBA C was previously set to "0" to indicate that more than one LBA does not refer to physical address Y, and therefore the flag associated with LBA C is changed from "0" to "1".

[0040] Referring again to Figure 4, at 407, the physical / logical (P2L) table is also updated to associate the physical address with both the destination and source LBAs. In one example, the P2L table is a subset P2L table that maps a subset of physical addresses referenced by more than one LBA. For example, referring to Figure 3B, consider a scenario where data in LBA A is copied to LBA C, and an entry associating physical address X with LBA C would be added to subset P2L table 153.

[0041] After the L2P table has been modified and before the data has been copied, in 408, a token indicating that the copy command has been completed is stored in a non-volatile storage device. The token may be a data structure containing information about the on-SSD copy command. In one example, the token may include a unique signature, such as a unique number, indicating that the token is a copy command token. In addition to the signature, the token may include the source LBA for the copy operation, the destination LBA for the copy operation, and the number of blocks to be copied. The token may also include a checksum indicating whether the token is corrupted or valid. In one example, the token is stored in a non-volatile medium and consumes an entire page or block. For example, referring to Figure 2, the on-SSD copy command token 159 is stored in array 132. The token may contain data that is smaller in size than the data granularity (e.g., block or page) within the NVM device, but the token may consume an entire block or page of data. For example, consider an NVM device where the data granularity is 4kB NAND pages. In one such example, a token might use up or consume an entire 4kB NAND page, but only a small portion of the NAND page (e.g., a few bytes or tens of bytes) would store the token.

[0042] Tokens may be used to enable the NVM device to rebuild or regenerate the L2P table and a subset of the P2L table in the event of an unexpected power loss. In one example, during regeneration, the controller scans all NAND pages, starting from the first page, to determine what data is in each page. Each NAND page may contain header information about what is stored within the NAND page. For example, the NAND page header may indicate the LBA that the controller reads and uses to rebuild the L2P table. During regeneration, if the controller encounters an on-SSD copy token, it indicates to the controller that the host sent a copy command and details of that copy command (e.g., the source and destination LBAs and the number of blocks to copy).

[0043] Therefore, tokens can enable the controller to reconstruct the L2P or P2L table. Since L2P and subset P2L table checkpoints can be periodically dropped (e.g., stored) on the NAND medium, in the event of an unexpected power loss, the most recent checkpoint of the L2P and subset P2L tables will be loaded upon subsequent power restoration. The controller can then reconstruct the L2P and subset P2L table using the most recent L2P and subset P2L table backups and tokens by replaying all NAND pages since the checkpoint. Tokens may be stored at the time the copy operation is performed (but before the actual data copy) or at a later time. For example, storing tokens may be delayed until the number of tokens to be stored exceeds a predetermined number. For example, tokens to be written to the NAND medium may be accumulated so as not to incur a NAND write penalty for each copy operation. Accumulating tokens before writing them can be beneficial for small copies (e.g., single indirect unit granularity length copies) because if the token for each small copy is stored at the time of the copy operation, the number of writes to the medium may not be reduced, and may even increase slightly due to writing a token for each copy and continuously updating the subset P2L.

[0044] Referring again to Figure 4, method 400 also includes sending an acknowledgment to the host in 410 that the copy command has been completed. The acknowledgment is sent after the L2P table has been updated, but before the actual data copy is performed. Alternatively, in 412, the data is copied in response to the receipt of a write command to write to the source LBA or destination LBA. In one example, copying the data involves allocating a new page, copying the data to the new page, and updating a flag in the L2P table to indicate that only one LBA refers to the same physical address.

[0045] Figures 5-8 are examples of pseudocode that executes functions for on-SSD copy commands on a NAND SSD. The examples in Figures 5-8 show functions with specific parameters, while fewer, additional, or different parameters are possible. Figure 5 is an example of pseudocode 500 for an L2P table entry. Lines 502-510 define the data structure for an entry (L2P_Entry) in the L2P table. An L2P entry includes a NAND_Address and a 1-bit Reference_Flag. Referring to Figure 3A, NAND_Address is an example of a physical block address PBA, and Reference_Flag is an example of a reference flag for L2P151. Referring again to Figure 5, at line 512, the table (L2P) is instantiated with a NUM_OF_ENTRIES entry. In an example where LBAs A and B point to the same NAND address X, in that case:

[0046] L2P[A].NAND_Address=x;

[0047] L2P[A].Reference_Flag=1;

[0048] L2P[B].NAND_Address=x;

[0049] L2P[B].Reference_Flag=1;

[0050] Therefore, the L2P table maps LBAs to NAND addresses. In addition to the NAND address, there is a 1-bit Reference_Flag for each entry, which indicates whether the NAND address is referenced by multiple L2P entries.

[0051] Figure 6 shows an example of pseudocode 600 for an on-SSD copy command. In the example shown in Figure 6, on line 602, the copy command has three parameters: the source LBA (src), the destination LBA (dest), and the number of LBAs (num). On line 606, the copy command executes a trim command on the destination LBA. In one example, the trim command is similar to a delete command but does not involve removing data from the physical medium. Instead, mapping information is removed (for example, by zeroing out or erasing the mapping information in the L2P table). An example of pseudocode for a trim command is described in more detail below with reference to Figure 7.

[0052] Referring again to Figure 6, in lines 608-618, the mapping information is updated for the destination LBA, and the reference flags for both the source and destination LBAs are updated in the L2P table. In line 612, the NAND_Address for the destination LBA is set to the NAND_Address for the source LBA. In line 614, the Reference_Flag for the entry in the L2P table associated with the destination LBA is set to 1. In line 616, the Reference_Flag for the entry in the L2P table associated with the source LBA is set to 1. The reference flag indicates that the NAND_Address pointed to by the source and destination LBAs is referenced by more than one LBA.

[0053] In lines 620 and 622, the subset P2L table is updated. For example, an entry is added (inserted) into the subset P2L table to map the physical address to both the source and destination LBAs. In line 624, the token is dropped (for example, stored on the NAND media) to indicate that the copy operation is complete. In one example, the token is dropped on the NAND media to support PLI (Power Loss Protection) / regeneration. In line 624, ackHostCompletion is a callback function to acknowledge command completion to the host.

[0054] Therefore, when the SSD receives a copy command, the controller updates the L2P table without copying the data. The controller also updates the P2L table to track the latest P2L mapping information. Next, the controller drops a token onto the NAND medium so that the SSD can rebuild the latest L2P and P2L tables in the event of a power failure. Once the token is dropped, the SSD acknowledges command completion to the host.

[0055] Figure 7 shows an example of pseudocode for an on-SSD copy-on-write command, but in one example, whether to perform a normal copy or an on-SSD copy-on-write command depends on the size of the copy. For example, a small data copy request (a single IU (indirect unit), or sub-IU) may be performed as a read + write operation, while a larger data copy (e.g., a data copy using more than one or more than a predetermined number of IUs) may be performed as an on-SSD copy-on-write operation. In one such example, referring to pseudocode 600 in Figure 6, the number of LBAs to be copied (num) is checked, and if the number of LBAs is greater than the predetermined number, an on-SSD copy-on-write operation is performed (e.g., lines 606-624). If the number of LBAs to be copied is less than or equal to the predetermined number, a read and write operation is performed instead of an on-SSD copy-on-write operation.

[0056] Figure 7 shows an example of pseudocode 700 for a trim command. In the example shown in Figure 7, the trim command has two parameters: the starting source LBA (src) and the number of LBAs to trim (num), as shown on line 702.

[0057] In one example, if an L2P entry was part of a previous on-SSD copy command that could be identified by a reference flag (for example, if the reference flag indicates that more than one LBA points to the physical address), the subset P2L table removes the L2P entry for the corresponding physical address. For example, referring to lines 706-716 in Figure 7, if the reference flag entry is equal to 1, the entry is removed from the P2L table. In one such example, with each subset P2L removal operation, if the physical address has only one or zero L2P entries that reference it, the physical address will be removed from the subset P2L table. In addition to the subset P2L update (if necessary), the L2P entries will be emptied, and the reference flags of the affected L2P entries (if any) will be cleared. For example, in lines 718 and 720, the physical address is cleared from the L2P entries, and the reference flags are cleared. In the example in Figure 7, after updating the P2L and L2P tables, a token is dropped onto the NAND medium at line 724 before command completion is sent to the host. The trim command token may be a data structure containing information about the on-SSD copy command. In one example, the token includes a unique signature, such as a unique number, indicating that the token is a trim command token. The trim command token can support PLI and regeneration. For example, an acknowledgment may be sent to the host while the controller is updating the L2P table. If power is lost before the L2P table update is complete, the L2P table can be correctly reconstructed using the trim token.

[0058] Figure 8 shows an example of pseudocode 800 for a write command. In the example shown in Figure 8, the write command has two parameters: the starting source LBA (src) and the number of LBAs to trim (num), as shown on line 802. Similar to the trim command, the P2L table is updated if the L2P entry was part of a previous on-SSD copy command (for example, if the reference flag indicates that more than one LBA points to the same physical address). For example, an entry associating an LBA with a physical address can be removed because more than one LBA no longer references the physical address (for example, only one LBA references the physical address). Referring to Figure 8, lines 806-814 show that, for each LBA, the reference flag of the entry in the L2P table for the source LBA is cleared to indicate that more than one LBA does not reference the physical address. On line 816, the entry associating the source LBA with a physical address is removed from the subset P2L. Lines 820-824 of the pseudocode handle NAND page allocation and DMA (Direct Memory Access) transfers so that host data can be written to the NAND medium. For example, in line 820, a new page is allocated for the source LBA. In line 824, a DMA transfer is set up to write data to the newly allocated page.

[0059] Figure 9 is a flowchart of an example of a defragmentation (defrag) method 900. During defragmentation, active pages from a selected band (e.g., a source band) are rearranged into a new band (e.g., a destination band). In one example, NAND pages are organized into bands, each containing multiple blocks, and each block containing multiple pages. In one such example, each band contains a band journal containing information about the physical pages to LBA mapping information for the pages within that band. Thus, the band journal is or may contain a local P2L table, which is independent of the subset P2L described herein. In one example, the band journal is a NAND SSD data structure that logs L2P entries as each NAND page is written. The band journal may be used to rebuild the L2P table in the event of power loss. The band journal may be used when performing a defragmentation operation. For example, to perform a defragmentation operation, the source band journal is loaded into memory.

[0060] Referring to Figure 9, after loading the band journal, at 902, for each page in the source band, the controller checks a subset P2L to determine whether the page's current physical address is referenced by more than one LBA. At 904, L2P entries referencing the current physical address are updated to reference the new physical address. If more than one LBA references the same physical address, multiple entries in the L2P table are updated to point to the new physical address. At 906, the data is then relocated from the current physical address to the new physical address.

[0061] Therefore, performing a defragmentation operation to move valid pages from the source band to the destination band involves updating all entries in the L2P table corresponding to each physical address in the source band that has an entry in the P2L table, with the new physical address in the destination band. In one example, each NAND page address in the source band is looked up in a subset P2L table. If the NAND page address is found, the page is valid and referenced by more than one L2P entry. Thus, the page will be relocated, and the corresponding L2P and P2L entries will be updated. If the NAND page address is not found in the subset P2L table, the SSD checks the L2P entry stored in the band journal. If the L2P entry stored in the band journal still points to this NAND address, the page is valid and will be relocated.

[0062] Figure 10 shows an example of pseudocode 1000 for a defragmentation operation. In the example shown in Figure 10, the defragmentation command has two parameters: source band index (source) and destination band index (dest), as shown on line 1002. On line 1006, the band journal for the source band is loaded. For each page in the band (line 1008), the current NAND address (currNandAddress) is set to be the current address of the source band (line 1012), and the new NAND page address (newNandAddress) is set to be an available page in the destination band (line 1014). On line 1016, the subset P2L table is checked for each current NAND address. If the current NAND address is in the subset P2L table, it indicates that the NAND page has more than one reference. On line 1020, all L2P entries pointing to the current NAND address are updated to point to the new NAND address. At line 1022, the data can then be relocated from the current NAND page to a new NAND page.

[0063] If the current NAND page is not in subset P2L (line 1026), it indicates that more than one LBA will not point to the current NAND page. If the entries in the L2P table are valid (lines 1030 and 1032), the L2P table entries are updated to point to the new NAND page address (line 1036), and the data can be relocated from the current NAND page to the new NAND page at line 1038.

[0064] Therefore, on-SSD copy-on-write operation can improve system performance. In one example, when the host issues a copy command, the SSD updates the L2P entries without migrating the data. Data migration is deferred until any of the copies are modified by the host. To support PLI and retrieval, tokens are dropped onto the NAND media for each copy command before the SSD sends command completion to the host. To support defragmentation, a subset of the P2L table is maintained in DRAM and periodically dropped onto the NAND media using the L2P table.

[0065] Figure 11 provides an illustrative diagram of a computing system 1100 (e.g., a smartphone, tablet computer, laptop computer, desktop computer, server computer, etc.). As observed in Figure 11, the system 1100 may include one or more processors or processing units 1101. The processor 1101 may include one or more central processing units (CPUs), each of which may include, for example, multiple general-purpose processing cores. The processor 1101 may similarly or alternatively include one or more graphics processing units (GPUs) or other processing units. The processor 1101 may include memory management logic (e.g., a memory controller) and I / O control logic. The processor 1101 may be similar to, or identical to, the processor 152 in Figure 1.

[0066] System 1100 also includes memory 1102 (e.g., system memory), non-volatile storage 1104, communication interface 1106, and other components 1108, which are similar to, or identical to, the components of host 150 in Figure 1. Other components may include, for example, a display (e.g., touchscreen, flat panel), power supply (e.g., battery and / or other power supply), sensors, power management logic, or other components. Communication interface 1106 may include logic and / or features that support the communication interface. For these examples, communication interface 1106 may include one or more communication interfaces that operate according to various communication protocols or standards for communicating directly or over a network communication link or channel. Direct communication may be performed via the use of communication protocols or standards described in one or more industry standards (including successors and variations), such as those associated with the PCIe specification. Network communication may be performed via the use of communication protocols or standards, such as those described in one or more standards published by the IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may be carried out in accordance with one or more OpenFlow specifications, such as the OpenFlow Switch specification. Other examples of communication interfaces include, for example, a locally wired point-to-point link (e.g., USB) interface, a wireless local area network (e.g., WiFi) interface, a wireless point-to-point link (e.g., Bluetooth®) interface, a global positioning system interface, and / or other interfaces.

[0067] The computing system also includes non-volatile storage 1104, which may be the system's mass storage component. The non-volatile storage 1104 may be similar to, or identical to, the NVM device 120 in Figure 1 described above. The non-volatile storage 1104 may include solid-state drives (SSDs), dual in-line memory modules (DIMMs), or other non-volatile storage. Non-volatile types of memory may include, but are not limited to, multi-threshold level NAND flash memory (e.g., 3D NAND flash memory). In one example, the non-volatile storage 1104 may include mass storage consisting of one or more SSDs. The SSDs may consist of flash memory chips capable of implementing the copy techniques described above.

[0068] An example of on-SSD copy-on-write is as follows:

[0069] Example 1: A method comprising the steps of: receiving a copy command from a host in a non-volatile storage device to copy data from a source logical block address (LBA) to a destination logical block address (LBA); modifying a logical / physical (L2P) table to map the destination LBA to the same physical address as the source LBA; updating flags in the L2P table corresponding to the source LBA and the destination LBA to indicate that more than one LBA refers to the same physical address; storing a token in the non-volatile storage device indicating that the copy command has been completed, after the L2P table has been modified and the flags have been set, but before the data has been copied; and sending an acknowledgment to the host indicating that the copy command has been completed.

[0070] Example 2: The method according to Example 1, wherein the token includes a signature, the signature includes a number indicating that the token is a copy command token.

[0071] Example 3: The token is: the method according to either one of Example 1 or 2, including the source LBA, the destination LBA, and the number of blocks to be copied.

[0072] Example 4: The token is: The method according to any one of Examples 1 to 3, wherein the token includes a checksum indicating whether the token is corrupted or not.

[0073] Example 5: The method according to any one of Examples 1 to 4, further comprising the step of updating the physical / logical (P2L) table to associate the physical address with both the destination LBA and the source LBA.

[0074] Example 6: The method described in any one of Examples 1-5, wherein the P2L table maps a subset of physical addresses referenced by more than one LBA.

[0075] Example 7: The method according to any one of Examples 1 to 6, further comprising the step of removing the entry in the P2L table that associates a second physical address with the destination LBA before modifying the L2P table to point the destination LBA to the same physical address as the source LBA.

[0076] Example 8: The method of any one of Examples 1 to 7, further comprising the steps of allocating a new page in response to receiving a write command to the source LBA or the destination LBA, copying the data to the new page, and updating the flag to indicate that only one LBA refers to the same physical address.

[0077] Example 9: The method according to any one of Examples 1 to 8, further comprising the step of performing a defragmentation (defrag) operation to move the active pages of the source band to the destination band, wherein the defragmentation operation includes the step of updating all entries in the L2P table corresponding to the physical address in the source band that has an entry in the P2L table with the new physical address in the destination band.

[0078] Example 10: The method according to any one of Examples 1 to 9, wherein the step of storing the tokens is delayed until the number of tokens to be stored exceeds a predetermined number.

[0079] Example 11: A manufactured product comprising a computer-readable storage medium that stores content which, when accessed, causes the execution of an action performed in any one of the methods described in Examples 1-10.

[0080] Example 12: A NAND controller running firmware that performs the method described in any one of Examples 1-10.

[0081] Example 13: A storage device comprising a NAND memory array and control logic coupled to the NAND memory array, wherein the control logic: receives a copy command from a host to copy data from a source logical block address (LBA) to a destination logical block address (LBA); updates an entry in the L2P table corresponding to the destination LBA to refer to the same physical address as a second entry in the logical / physical (L2P) table corresponding to the source LBA; updates flags in the entry corresponding to the destination LBA and the entry corresponding to the source LBA to indicate that more than one LBA refers to the same physical address; stores a token in the NAND memory array indicating that the copy command has been completed, after the updates in the L2P table and the second entry, but before the data is copied; and sends an acknowledgment to the host indicating that the copy command has been completed.

[0082] Example 14: The storage device described in Example 13, wherein the control logic performs the method described in any one of Examples 1 to 10.

[0083] Example 15: A system comprising a processor and a NAND storage device coupled to the processor, wherein the NAND storage device has: a NAND memory array and control logic coupled to the NAND memory array, the control logic: receives a copy command from a host to copy data from a source logical block address (LBA) to a destination logical block address (LBA); updates an entry in the L2P table corresponding to the destination LBA to refer to the same physical address as a second entry in the logical / physical (L2P) table corresponding to the source LBA; updates flags in the entry corresponding to the destination LBA and the entry corresponding to the source LBA to indicate that more than one LBA refers to the same physical address; stores a token in the NAND memory array indicating that the copy command has been completed after updating the entry in the L2P table and the second entry, and before the data is copied; and sends an acknowledgment to the host indicating that the copy command has been completed.

[0084] Example 16: The system according to Example 15, comprising one or more of the following: a display coupled with the processor, a network interface coupled with the processor, and a battery for powering the system.

[0085] Example 17: The control logic is the system described in Example 15 or 16, wherein the control logic performs the method described in any one of Examples 1 to 10.

[0086] Embodiments of the present invention may include various processes as described above. These processes may be embodied in machine-executable instructions. These instructions can be used to cause a general-purpose or dedicated processor to execute a particular process. Alternatively, these processes may be executed by special / custom hardware components, including wired logic circuits or programmable logic circuits (e.g., FPGAs, PLDs), or by any combination of programmed computer components and custom hardware components.

[0087] Elements of the present invention may be provided as a machine-readable medium for storing machine-executable instructions. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, flash memory, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, propagation media, or other types of media / machine-readable media suitable for storing electronic instructions. For example, the present invention may be downloaded as a computer program that can be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or network connection) by data signals embodied on a carrier or other propagation medium.

[0088] The flow diagrams shown herein provide examples of sequences of various process actions. Flow diagrams can illustrate operations performed by software or firmware routines, as well as physical operations. In one example, a flow diagram can illustrate the states of a finite state machine (FSM), which can be implemented in hardware, software, or a combination thereof. While shown in a specific sequence or order, the order of actions can be modified unless otherwise specified. Therefore, the exemplary embodiments should be understood as merely examples, processes can be executed in different orders, and some actions can be executed in parallel. In addition, one or more actions can be omitted in various examples, and therefore not all actions are required in all embodiments. Other process flows are possible.

[0089] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, data, or combinations. Content may be directly executable (in "object" or "executable" form), in source code, or in differential code ("delta" or "patch" code). Software content of embodiments described herein may be provided via a manufactured product storing the content, or via a method of operating a communication interface to transmit data via such communication interface. Machine-readable storage media include any mechanism that can cause a machine to perform the described functions or operations and stores information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such mechanism includes, for example, recordable / non-recordable media (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). Communication interfaces include any mechanism that interfaces to any medium such as wired, wireless, or optical to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, or a disk controller. A communication interface can be configured by providing configuration parameters, transmitting signals, or both, to prepare a communication interface that provides data signals describing software content. A communication interface can be accessed via one or more commands or signals transmitted to it.

[0090] The various components described herein can be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. Components can be implemented as software modules, hardware modules, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, wiring circuits, etc.

[0091] In addition to what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope. Therefore, the examples and illustrations herein should be interpreted as illustrative and not restrictive. The scope of the invention should be defined solely by reference to the claims that follow.

Claims

1. A manufactured product comprising a computer-readable storage medium that stores content that, when accessed, causes the execution of an action that performs a method, wherein the method is: In a non-volatile storage device, this is the stage where a copy command is received from the host to copy data from a source logical block address (LBA) to a destination logical block address (LBA); The step of modifying the logical / physical (L2P) table so that the destination LBA is mapped to the same physical address as the source LBA; A step of updating the flags in the L2P table corresponding to the source LBA and the destination LBA to indicate that more than one LBA refers to the same physical address; The steps include: modifying the L2P table, setting the flag, and storing a token in the non-volatile storage device indicating that the copy command has been completed, before copying the data; and Steps include sending an acknowledgment to the host indicating that the copy command has been completed. A manufactured product having the following characteristics.

2. The article according to claim 1, wherein the token includes a signature, the signature includes a number indicating that the token is a copy command token.

3. The product according to claim 2, wherein the token includes: the source LBA, the destination LBA, and the number of blocks to be copied.

4. The article according to claim 2, wherein the token includes a checksum indicating whether the token is damaged or not.

5. The article according to any one of claims 1 to 4, further comprising the step of updating a physical / logical (P2L) table to associate the physical address with both the destination LBA and the source LBA.

6. The article according to claim 5, wherein the P2L table maps a subset of physical addresses referenced by more than one LBA.

7. The article according to claim 5 or 6, further comprising the step of removing the entry in the P2L table that associates a second physical address with the destination LBA before modifying the L2P table to point the destination LBA to the same physical address as the source LBA.

8. In response to receiving a write command to the source LBA or destination LBA, the process involves allocating a new page. The step of copying the aforementioned data to the new page, and The step of updating the flag to indicate that only one LBA refers to the same physical address. A manufactured product according to any one of claims 1 to 7, further comprising the above.

9. The article according to any one of claims 1 to 8, further comprising a step of performing a defragmentation (defrag) operation to move the active pages of the source band to the destination band, wherein the defragmentation operation includes a step of updating all entries in the L2P table corresponding to the physical address in the source band that has an entry in the P2L table with a new physical address in the destination band.

10. The product according to any one of claims 1 to 9, wherein the step of storing the tokens is delayed until the number of tokens to be stored exceeds a predetermined number.

11. NAND memory array; and Control logic coupled with the aforementioned NAND memory array The control logic includes: Receiving a copy command from a host to copy data from a source logical block address (LBA) to a destination logical block address (LBA); Updating the entry in the L2P table corresponding to the destination LBA so that it refers to the same physical address as the second entry in the logical / physical (L2P) table corresponding to the source LBA; Updating the flags in the entry corresponding to the destination LBA and the entry corresponding to the source LBA to indicate that more than one LBA refers to the same physical address; After the updates of the entry and the second entry in the L2P table, and before the data is copied, a token indicating that the copy command has been completed is stored in the NAND memory array; and Send an acknowledgment to the host indicating that the copy command has been completed. A storage device that performs this task.

12. The storage device according to claim 11, wherein the token includes a signature, the signature includes a number indicating that the token is a copy command token.

13. The storage device according to claim 12, wherein the token includes: the source LBA, the destination LBA, and the number of blocks to be copied.

14. The storage device according to claim 12, wherein the token includes a checksum indicating whether the token is corrupted or not.

15. The storage device according to any one of claims 11 to 14, wherein the control logic updates the physical / logical (P2L) table to associate the physical address with both the destination LBA and the source LBA.

16. The storage device according to claim 15, wherein the P2L table maps a subset of physical addresses referenced by more than one LBA.

17. The storage device according to claim 15 or 16, wherein the control logic removes the entry in the P2L table that associates a second physical address with the destination LBA before modifying the L2P table to point the destination LBA to the same physical address as the source LBA.

18. The control logic responds to the receipt of a write command to the source LBA or destination LBA by: Assigning a new page, Copy the aforementioned data to the new page, and Updating the flag to indicate that only one LBA refers to the same physical address. A storage device according to any one of claims 11 to 17, which performs the following.

19. Processor; and The processor is coupled with a NAND storage device, the NAND storage device being: NAND memory array; and Control logic coupled with the aforementioned NAND memory array The control logic includes: Receiving a copy command from a host to copy data from a source logical block address (LBA) to a destination logical block address (LBA); Updating the entry in the L2P table corresponding to the destination LBA so that it refers to the same physical address as the second entry in the logical / physical (L2P) table corresponding to the source LBA; Updating the flags in the entry corresponding to the destination LBA and the entry corresponding to the source LBA to indicate that more than one LBA refers to the same physical address; After the updates of the entry and the second entry in the L2P table, and before the data is copied, a token indicating that the copy command has been completed is stored in the NAND memory array; and Send an acknowledgment to the host indicating that the copy command has been completed. A system that performs this task.

20. The system according to claim 19, comprising one or more of the following: a display coupled with the processor, a network interface coupled with the processor, and a battery for powering the system.

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