Image sensor, and method for manufacturing an image sensor

Abstract

The present invention provides an image sensor that can effectively prevent the deterioration of DCR caused by the multiplication of dark current generated between the insulating film and semiconductor used to isolate elements. [Solution] An image sensor having multiple SPAD elements, each SPAD element including a trench for separating one SPAD element from another, a charge discharge layer formed on the side wall of the trench and electrically connected to a charge discharge electrode, and an insulating film formed inside the trench and covering the charge discharge layer.

Description

Technical Field

[0001] The present invention relates to an image sensor and a method for manufacturing the image sensor.

Background Art

[0002] In recent years, a SPAD (Single Photon Avalanche Diode) that multiplies charges generated by photoelectric conversion of incident light by avalanche multiplication and outputs them as an electrical signal has attracted attention. The SPAD can detect light particles one by one and has extremely high time resolution.

[0003] Each SPAD element of an image sensor in which a plurality of SPAD elements are arranged is separated from each other by an element isolation layer. At this time, a defect level due to a defect in the crystal structure at the interface between the semiconductor in which the SPAD element is formed and the insulating film of the element isolation layer, or an energy band sinking at the interface of the semiconductor due to a work function difference between the semiconductor and the metal in the element isolation layer may cause a dark current. When the DCR (Dark Count Rate) increases due to the generation of the dark current, the detection accuracy of the image sensor decreases. For example, the ranging accuracy by the ToF (Time of Flight) method using a SPAD decreases.

[0004] The following Patent Document 1 discloses the following prior art. A hole accumulation region that is connected to an anode and accumulates holes to trap electrons is formed on the side wall of a separation region made of a silicon oxide film for separating elements including an avalanche photodiode from each other. Thereby, excitation of dark current between the element separation region and silicon is suppressed.

[0005] The following prior art is disclosed in Patent Document 2 below: A shallow trench isolation (STI) is used to isolate pixel transistors electrically connected to a photodiode within a pixel. Between this STI and the charge storage layer of the photodiode, a charge discharge layer with the same conductivity as the charge storage layer is formed. This prevents electrons generated at the bottom surface of the element isolation region from flowing into the charge storage layer of the photodiode by discharging them through the charge discharge layer to which a positive voltage is applied, thereby preventing an increase in dark current in the charge storage layer caused by electrons generated at the bottom surface of the element isolation region. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-201005 [Patent Document 2] Japanese Patent Publication No. 2019-4090 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, the prior art disclosed in Patent Document 1 does not always allow for sufficiently low dark current depending on the manufacturing process, in which case the DCR may become a significant value. Furthermore, the prior art disclosed in Patent Document 2 has the problem that the dark current generated between the pixel isolation wall and silicon flows into the charge storage layer of the photodiode and is amplified, potentially increasing the DCR.

[0008] This invention was made to solve the above problems. Specifically, the objective is to provide an image sensor and a method for manufacturing an image sensor that can effectively prevent deterioration of the DCR caused by the multiplication of the dark current generated between the insulating film and the semiconductor used to isolate the elements. [Means for solving the problem]

[0009] An image sensor having a plurality of SPAD elements, wherein each SPAD element includes a trench for separating the SPAD element from other SPAD elements, a charge discharge layer formed on the side wall of the trench and electrically connected to a charge discharge electrode, and an insulating film formed inside the trench and covering the charge discharge layer. [Effects of the Invention]

[0010] This effectively prevents the deterioration of the DCR caused by the multiplication of dark current generated between the insulating film used to isolate the elements and the semiconductor. [Brief explanation of the drawing]

[0011] [Figure 1] This block diagram shows the schematic configuration of an image sensor. [Figure 2] This is a circuit diagram showing a schematic example of a SPAD pixel configuration. [Figure 3] This diagram shows the stacked structure of a pixel array. [Figure 4A] This is a cross-sectional view of a SPAD pixel. [Figure 4B] This is a cross-sectional view of a SPAD pixel. [Figure 4C] This is a cross-sectional view of a SPAD pixel. [Figure 5] This figure shows the potentials corresponding to each position along the path indicated by the dashed line in Figure 4A. [Figure 6] This figure shows the potential at each position along the path indicated by the dashed line in Figure 4A. [Figure 7A] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 7B] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 8A] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 8B] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 9A]It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 9B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 10A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 10B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 11A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 11B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 12A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 12B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 13A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 13B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 14A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 14B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 15A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 15B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 16A] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 16B] It is an explanatory diagram with a cross-sectional view for explaining a method of manufacturing an image sensor. [Figure 17A] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 17B] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 18] These are flowcharts showing the main steps in the manufacturing method of an image sensor, corresponding to Figures 7A to 17B. [Figure 19A] This is a cross-sectional view of a SPAD element. [Figure 19B] This is a cross-sectional view of a SPAD element. [Figure 20A] This is a cross-sectional view of a SPAD element. [Figure 20B] This is a cross-sectional view of a SPAD element. [Figure 21A] This is a cross-sectional view of a SPAD element. [Figure 21B] This is a cross-sectional view of a SPAD element. [Figure 21C] This diagram shows the potential gradient in the vertical direction of the semiconductor substrate inside the charge discharge layer. [Figure 22A] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 22B] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 23A] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 23B] This is a cross-sectional diagram illustrating the manufacturing method of an image sensor. [Figure 24A] This is a cross-sectional view of a SPAD element. [Figure 24B] This is a cross-sectional view of a SPAD element. [Figure 24C] This figure shows the potentials corresponding to each position along the path indicated by the dashed line in Figure 24A. [Figure 25A] This is a cross-sectional view of a SPAD element. [Figure 25B] This is a cross-sectional view of a SPAD element. [Figure 26A] This is a cross-sectional view of a SPAD element. [Figure 26B] This is a cross-sectional view of a SPAD element. [Figure 26C] This diagram shows the potential gradient in the vertical direction of the semiconductor substrate inside the charge discharge layer. [Figure 27A] This is a cross-sectional view of a SPAD element. [Figure 27B] This is a cross-sectional view of a SPAD element. [Figure 28A] This is a cross-sectional view of a SPAD element. [Figure 28B] This is a cross-sectional view of a SPAD element. [Figure 28C] This diagram shows the potential gradient in the vertical direction of the semiconductor substrate inside the charge discharge layer. [Figure 29A] This is a cross-sectional view of a SPAD element. [Figure 29B] This is a cross-sectional view of a SPAD element. [Figure 30A] This is a cross-sectional view of a SPAD element. [Figure 30B] This is a cross-sectional view of a SPAD element. [Figure 30C] This diagram shows the potential gradient in the vertical direction of the semiconductor substrate inside the charge discharge layer. [Modes for carrying out the invention]

[0012] Hereinafter, an image sensor according to an embodiment and a method for manufacturing the image sensor will be described in detail based on the drawings. The embodiments described are merely illustrative, and various modifications are possible from such embodiments. Hereinafter, the same reference numerals in the drawings refer to the same components, and the size of each component in the drawings is represented in proportions different from those of the actual components for clarity and convenience of explanation.

[0013] In the following, expressions such as "top" or "upper" include not only those directly above / below / to the left / right upon contact, but also those above / below / to the left / right without direct contact.

[0014] Terms like the first and second are used to describe various components, but only for the purpose of distinguishing one component from others. Such terms do not limit the material or structure of the components to any particular degree.

[0015] A singular noun refers to a component that includes multiple components unless the context clearly indicates otherwise. Furthermore, when a part "includes" a component, this does not exclude other components, unless otherwise stated, but rather means that it may include other components.

[0016] Furthermore, terms such as "part" as used in the specification refer to a unit that processes one or more functions or operations, which may be embodied by hardware or software, or by a combination of hardware and software.

[0017] Furthermore, a cross-sectional view a (e.g., Figure 4C) of a cross-section parallel to the surface of the substrate and a cross-sectional view b (e.g., Figure 4A) of a cross-section perpendicular to the surface may be shown corresponding to each other by indicating the cutting line. In this case, one of the upper or lower cross-sectional views a of the cross-section corresponding to the cutting line shown in cross-sectional view b may be omitted, and the layer corresponding to the omitted cross-sectional view a may be shown in cross-sectional view b (e.g., wiring layer 520 in Figure 4A).

[0018] For the sake of simplicity, the following explanation will use the example where the first conductivity type is P-type and the second conductivity type is N-type. However, this is for the sake of simplicity, and the first conductivity type may also be N-type and the second conductivity type may be P-type. The first conductivity type semiconductor layer will be explained using the example where it is a P-type semiconductor layer. The second conductivity type semiconductor layer will be explained using the example where it is an N-type semiconductor layer. The first conductivity type semiconductor layer may also be an N-type semiconductor layer. The second conductivity type semiconductor layer may also be a P-type semiconductor layer.

[0019] (First Embodiment) <Image Sensor 1> Figure 1 is a block diagram showing the schematic configuration of the image sensor 1. The image sensor 1 is, for example, a back-illuminated image sensor 1. The image sensor 1 may also be a front-illuminated image sensor 1. In a back-illuminated image sensor 1, the side of the semiconductor substrate 510 (see Figure 4A, etc.) opposite to the element formation surface becomes the light incident surface. In a front-illuminated image sensor 1, the element formation surface becomes the light incident surface. To simplify the explanation, the following explanation will use the back-illuminated image sensor 1 as an example. The element formation surface of the semiconductor substrate 510 will also be referred to as the "front surface," and the side of the semiconductor substrate 510 opposite to the element formation surface will also be referred to as the "back surface."

[0020] The image sensor 1 includes a pixel array 10, a control circuit 20, a drive circuit 30, and an output circuit 40.

[0021] The pixel array 10 includes a plurality of SPAD pixels 11 arranged in a matrix. Each SPAD pixel 11 is connected to a pixel drive line 50 for each column and an output signal line 60 for each row. The pixel drive lines 50 are connected to the output terminals of the drive circuit 30 corresponding to each column. The output signal lines 60 are connected to the input terminals of the output circuit 40 corresponding to each row.

[0022] The drive circuit 30 includes a shift register, an address decoder, etc., and drives all SPAD pixels 11 of the pixel array 10 simultaneously or in column units. The drive circuit 30 includes a circuit that applies a quench voltage VQ, described later, to each SPAD pixel 11. When the drive circuit 30 drives each SPAD pixel 11 in column units, it may include a circuit that applies a selection signal voltage VSEL to each SPAD pixel 11 in the selected column. In this case, each SPAD pixel 11 is selected by the selection signal voltage VSEL, the power supply voltage is applied only to the selected SPAD pixel 11, and a detection signal VOUT is output from that SPAD pixel 11.

[0023] The detection signal VOUT output from each SPAD pixel 11 is input to the output circuit 40 through each output signal line 60. The output circuit 40 outputs the detection signal VOUT input from each SPAD pixel 11 as an image signal.

[0024] The control circuit 20 includes a timing generator that generates various timing signals, etc., and controls the drive circuit 30 and the output circuit 40 based on the various timing signals generated by the timing generator.

[0025] <SPAD pixel 11> FIG. 2 is a circuit diagram showing a schematic configuration example of the SPAD pixel 11.

[0026] The SPAD pixel 11 includes a SPAD element 100, a quench resistance transistor 200, and an inverter 300. As will be described later, the SPAD element 100 is formed on a pixel chip 500 (see FIG. 3), and the quench resistance transistor 200 and the inverter 300 can be formed on a logic chip 600. The pixel chip 500 and the logic chip 600 are aligned and joined for each SPAD pixel 11, thereby forming each SPAD pixel 11. In FIG. 2, the connection point where the SPAD element 100 and the quench resistance transistor 200 are connected by the joining of the pixel chip 500 and the logic chip 600 is shown as node N1. Also, the boundary between the pixel chip 500 and the logic chip 600 is shown by a dashed line.

[0027] The SPAD element 100 is a photodetector that generates an avalanche current when a photon is incident on it while a reverse bias of a voltage greater than the breakdown voltage is applied between the anode and cathode. The anode voltage VA is applied to the anode of the SPAD element 100, and the cathode voltage VC is applied to the cathode via a quench resistor transistor 200. The anode voltage VA is set to, for example, -15V to -30V. The cathode voltage VC is set to, for example, about 2 to 5V. The SPAD element 100 operates in Geiger mode when a reverse bias voltage VSPAD greater than the breakdown voltage is applied, and can detect a single photon. The reverse bias voltage VSPAD is the sum of the absolute values ​​of the anode voltage VA and the cathode voltage VC.

[0028] The quench resistor transistor 200 is composed of, for example, a PMOS (Metal Oxide Semiconductor) transistor. The quench resistor transistor 200 operates as a quench resistor when a quench voltage VQ supplied from the drive circuit 30 is applied to its gate. The quench resistor transistor 200 also has a recharge function, which returns the voltage supplied to the SPAD element 100 back to VC by allowing the current to flow that compensates for the voltage drop caused by the quench operation.

[0029] The current flowing through the SPAD element 100 is converted into a voltage by the quench resistor transistor 200 and output to the inverter 300.

[0030] The inverter 300 is composed of a PMOS transistor 300P and an NMOS transistor 300N connected in series. A power supply VHV for driving a digital circuit is connected to the source of the PMOS transistor 300P, and the drain of the NMOS transistor 300N is connected to the drain of the PMOS transistor 300P. The drain of the NMOS transistor 300N is connected to the drain of the PMOS transistor 300P, and the source of the NMOS transistor 300N is grounded. The gates of the PMOS transistor 300P and the NMOS transistor 300N are connected to each other, and the connection point serves as the input of the inverter 300. The connection point of the drains of the PMOS transistor 300P and the NMOS transistor 300N serves as the output of the inverter 300. The input of the inverter 300 is connected to node N1, which is the connection point of the SPAD element 100 and the quench resistance transistor 200.

[0031] The inverter 300 converts the input voltage into a digital signal and outputs it as a detection signal VOUT. Note that a buffer for impedance conversion may be provided at the output of the inverter 300, so that the impedance-converted detection signal VOUT may be output from each SPAD pixel 11.

[0032] The detection signal VOUT is input to the output circuit 40. The output circuit 40 outputs the detection signal VOUT to a processor (not shown) via, for example, a TDC (Time to Digital Converter) (not shown) in the case of a dToF (Direct Time of Flight) system or a counter (not shown) in the case of a photon counting system. The detection signal VOUT is subjected to various processes by the processor.

[0033] <Operation of the SPAD pixel 11> When a photon is incident on the SPAD element 100 while a reverse bias voltage VSPAD exceeding the breakdown voltage is applied to the SPAD element 100 via the quench resistor transistor 200, an avalanche current is generated in the SPAD element 100. As the avalanche current flows through the quench resistor transistor 200, the voltage at node N1 drops. When the voltage at node N1 falls below the threshold voltage of the PMOS transistor 300P of the inverter 300, the PMOS transistor 300P conducts, and the power supply VHV is output from the inverter 300 as a high-level detection signal.

[0034] Subsequently, as the voltage at node N1 continues to decrease, the voltage applied to the SPAD element 100 becomes lower than the breakdown voltage. This causes the avalanche current to stop flowing, and the voltage at node N1 rises. When the voltage at node N1 becomes higher than the threshold voltage of the NMOS transistor 300N of the inverter 300, the NMOS transistor 300N conducts, and the inverter 300 outputs a ground voltage as a low-level detection signal.

[0035] <Stacked structure of pixel array 10> Figure 3 shows the stacked structure of the pixel array 10.

[0036] The SPAD pixels 11 are arranged in an array to form a pixel array 10. The SPAD elements 100 are arranged in an array to form an element array 70. The pixel array 10 has a structure in which a pixel chip 500 and a logic chip 600 are stacked. The pixel chip 500 is a semiconductor chip in which SPAD elements 100 are formed in an array. The logic chip 600 is a semiconductor chip in which quench resistor transistors 200 and inverters 300 are formed at positions corresponding to each SPAD element 100. The logic chip 600 may further have a control circuit 20, a drive circuit 30, and an output circuit 40 formed thereon. The logic chip 600 may also have the above-described buffer for impedance conversion of the detection signal VOUT.

[0037] The pixel chip 500 and the logic chip 600 can be joined by an interelectronic force, for example, by flattening and contacting their respective joining surfaces. Specifically, the pixel chip 500 and the logic chip 600 can be joined by metal bonding of metal pads (not shown) formed on their respective surfaces (joining surfaces).

[0038] <Structure of the SPAD element 100> FIGS. 4A to 4C are cross-sectional views of the SPAD element 100. FIG. 4A corresponds to a cross-section taken along the A-A' plane in FIG. 4C. FIG. 4B corresponds to a cross-section taken along the B-B' plane in FIG. 4C. FIG. 4C is a plan view of the semiconductor substrate 510 corresponding to a cross-section taken along the C-C' plane in FIGS. 4A and 4B, viewed from above.

[0039] The surface where the light indicated by the straight arrow in FIG. 4A is incident is the light incident surface.

[0040] A plurality of SPAD elements 100 are formed in the semiconductor substrate 510 of the pixel chip 500. The semiconductor substrate 510 is, for example, a silicon substrate. Hereinafter, for simplicity of explanation, the case where the semiconductor substrate 510 is a silicon substrate will be described as an example.

[0041] Each of the SPAD elements 100 includes a trench 111 for separating it from other SPAD elements 100. The trenches 111 of the plurality of SPAD elements 100 formed in the semiconductor substrate 510 are connected to each other to form a lattice pattern when viewed in plan from the light incident surface.

[0042] The photoelectric conversion region 104 photoelectrically converts incident light to generate pairs of electrons and holes (hereinafter also referred to as "charges"). The photoelectric conversion region 104 is composed of a region doped with a relatively low concentration of impurities. Hereinafter, for simplicity of explanation, the case where the photoelectric conversion region 104 is a semiconductor layer doped with a relatively low concentration of acceptors will be described as an example. As the acceptor, for example, boron (B) is used. The photoelectric conversion region 104 may also have a configuration including an intrinsic semiconductor not doped with impurities.

[0043] The P-type semiconductor layer 105 is a layer containing an acceptor and is formed on the side wall of the trench 111 via the charge discharge layer 106. That is, the P-type semiconductor layer 105 is formed on the opposite side of the first insulating film 107 via the charge discharge layer 106. Boron (B), for example, is used as the acceptor. The P-type semiconductor layer 105 may be adjacent to the charge discharge layer 106. The P-type semiconductor layer 105 forms an electric field for guiding the charge generated in the photoelectric conversion region 104 to the avalanche multiplication region when a reverse bias voltage VSPAD is applied between the anode electrode 110 and the cathode electrode 101 of the SPAD element 100. The avalanche multiplication region is formed, for example, as a PN junction of an N+-type semiconductor region 102 and a P+-type semiconductor region 103. The P-type semiconductor layer 105 constitutes the first semiconductor layer.

[0044] The P+-type semiconductor region 103 is a region containing a relatively high concentration of acceptors. For example, boron (B) is used as the acceptor. The N+-type semiconductor region 102 is a region containing a relatively high concentration of donors. For example, phosphorus (P) or arsenic (As) is used as the donors. The P+-type semiconductor region 103 and the N+-type semiconductor region 102 are in contact with each other to form a PN junction and function as a multiplier region that accelerates the charge flowing into the P+-type semiconductor region 103 to generate an avalanche current.

[0045] The cathode electrode 101 is a region containing a higher concentration of donor than the N+-type semiconductor region 102 and is in contact with the N+-type semiconductor region 102. The cathode electrode 101 is ohmic-junctioned with the cathode wiring 541, which is a wiring pattern of the metal layer formed on the wiring layer 520.

[0046] The anode electrode 110 is a region containing a higher concentration of acceptors than the P-type semiconductor layer 105 and is in contact with the P-type semiconductor layer 105. The anode electrode 110 is ohmic-junctioned with the anode wiring 542, which is a wiring pattern of the metal layer formed on the wiring layer 520.

[0047] The charge emission layer 106 is an N-type semiconductor layer containing a relatively high concentration of donors and can be formed on the sidewall of the trench 111. The charge emission layer 106 formed on the sidewall of the trench 111 is adjacent to the first insulating film 107 formed inside the trench 111. The impurity concentration of the charge emission layer 106 can be lower than that of the P-type semiconductor layer 105. That is, the donor concentration of the charge emission layer 106 can be lower than the acceptor concentration of the P-type semiconductor layer 105.

[0048] The charge discharge layer 106 can be electrically connected to the charge discharge electrode 108 via the contact layer 109. A charge discharge voltage can be applied to the charge discharge layer 106 by the charge discharge electrode 108 via the contact layer 109. As a result, the potential of the charge discharge layer 106 is made higher than the potential of the P-type semiconductor layer 105 to which the anode voltage VA is applied. For example, the potential of the charge discharge layer 106 is made 1V higher than the potential of the P-type semiconductor layer 105 to which the anode voltage VA is applied. The charge discharge voltage is set so that the potential difference between the P-type semiconductor layer 105 to which the anode voltage VA is applied and the charge discharge layer 106 does not cause breakdown.

[0049] The separation metal layer 115 may be formed of a metal. For example, the separation metal layer 115 may be formed of tungsten (W) or polysilicon. The separation metal layer 115 is arranged around each SPAD pixel 11 and is configured in a grid pattern in the pixel array 10, and is formed of, for example, tungsten (W) or polysilicon.

[0050] A first insulating film 107 is formed inside the trench 111, covering the charge discharge layer 106. The formation of the separation metal layer 115 and the first insulating film 107 inside the trench 111 constitutes DTI (Deep Trench Isolation).

[0051] The contact layer 109 is formed on the surface of the semiconductor substrate 510 on the wiring layer 520 side and is connected to the charge discharge electrode 108. The contact layer 109 is formed of a conductor. For example, the contact layer 109 is formed of polysilicon (Poly-Si).

[0052] The contact layer 109 can be shared among multiple SPAD elements 100 by being formed in regions including the intersections of the grid-like trenches 111.

[0053] The charge emission layer 106 prevents the dark current generated at the interface between the silicon oxide film (SiO) and silicon (Si) from reaching the photoelectric conversion region 104 by emitting the dark current. Specifically, the charge emission layer 106 prevents electrons of the dark current generated at the interface between the first insulating film 107 and silicon (Si) from reaching the photoelectric conversion region 104.

[0054] Figure 5 shows the potentials corresponding to each position along the path indicated by the dashed line in Figure 4A. Figure 6 shows the potentials corresponding to each position along the path indicated by the dashed line in Figure 4A.

[0055] As shown in Figure 5, potential sinking occurs at the boundary between the silicon oxide (SiO) and silicon (Si) of the first insulating film 107, which forms a DTI together with the tungsten (W) of the separation metal layer 115. This is achieved by making the potential of the charge discharge layer 106 higher than the potential (anode potential) of the P-type semiconductor layer 105 to which the anode voltage VA is applied. Electrons can be generated as a dark current due to this potential sinking. Furthermore, electrons can also be generated as a dark current due to defect levels caused by defects in the crystal structure at the interface between the silicon oxide (SiO) and silicon (Si). Thus, electrons can be generated as a dark current at the boundary between the silicon (Si) charge discharge layer 106 and the first insulating film 107.

[0056] As shown in Figure 6, even if electrons are generated as a dark current at the boundary between the charge emission layer 106 and the first insulating film 107, the potential of the charge emission layer 106 can be made sufficiently higher than the anode potential by appropriately setting the charge emission voltage. Specifically, for example, by setting the anode potential 1V higher than the potential of the charge emission layer 106, a 1V potential barrier can be formed against the electrons as a dark current. This prevents the electrons as a dark current from exceeding the potential of the anode potential and reaching the multiplication region of the SPAD element 100, as shown by the curved arrows in Figure 6. The generated electrons as a dark current can then be discharged from the charge emission layer 106 to the outside of the SPAD element 100 via the charge emission electrode 108.

[0057] An anti-reflective coating (not shown) can be formed on the back surface (light incident surface) of the semiconductor substrate 510 (Figure 4A) to prevent reflection of incident light.

[0058] Color filters (not shown) and on-chip lenses (not shown) corresponding to each SPAD element 100 may be formed on the anti-reflective coating. Each color filter may be a color filter that selectively transmits light of the red (R) wavelength component, a color filter that selectively transmits light of the green (G) wavelength component, or a color filter that selectively transmits light of the blue (B) wavelength component, corresponding to each SPAD element 100. Each color filter may be formed in a Bayer array.

[0059] As shown in Figure 4A, a wiring layer 520 is formed on the surface of the semiconductor substrate 510. The wiring layer 520 is composed of a second insulating film 530 and individual wirings 540. Multiple layers of wiring 540 can be stacked via the second insulating film 530. In this case, adjacent wirings 540 of the same node are connected to each other via vias formed in the second insulating film 530. The wiring 540 may include an anode wiring 542 for supplying an anode voltage VA to the SPAD element 100 and a cathode wiring 541 for supplying a cathode voltage VC to the SPAD element 100. Furthermore, the wiring 540 may include a charge discharge electrode 108. The anode wiring 542 is connected to the anode electrode 110. The cathode wiring 541 is connected to the cathode electrode 101. The charge discharge electrode 108 is connected to the contact layer 109. The wiring 540 includes a first connection pad (not shown). The first connection pad may be exposed on the surface of the wiring layer 520 (the top surface in Figure 4A).

[0060] The first connection pad can be joined to a second connection pad (not shown) exposed on the surface of the logic chip 600 by metal bonding. This allows the pixel chip 500 and the logic chip 600 to be joined.

[0061] The logic chip 600 may consist of a substrate and a wiring layer. In this case, elements constituting a logic circuit, including a quench resistor transistor 200 and transistors constituting an inverter 300, are formed on the substrate. Wiring for constituting a logic circuit, including wiring connecting the quench resistor transistor 200 and the inverter 300, and wiring including a second connection pad are formed on the wiring layer.

[0062] <Manufacturing method for image sensor 1> A method for manufacturing the image sensor 1 will be described.

[0063] Figures 7A to 17B are explanatory cross-sectional views illustrating the manufacturing method of the image sensor 1. Figures 7A to 17B correspond to the manufacturing method of the image sensor 1 including the SPAD element 100 shown in Figures 4A to 4C. In Figures 7A to 17B, figures with the same figure number illustrate the same manufacturing step. Figures with a figure number including A correspond to the cross-section of the A-A' plane in figures with a figure number including B. Figures with a figure number including B are plan views of the semiconductor substrate 510 viewed from above, corresponding to the cross-section of the C-C' plane in figures with a figure number including A.

[0064] As shown in Figures 7A and 7B, a layer of hard mask material 900 is formed on the surface of the semiconductor substrate 510 opposite to the light incident surface, and the hard mask material 900 is etched using a mask in which openings corresponding to the positions of the trenches 111 are formed. Then, the trenches 111 are formed by etching the semiconductor substrate 510 using the hard mask material 900, which has openings corresponding to the positions of the trenches 111 formed by etching, as a mask. Specifically, the trenches 111 are formed by first forming a relatively wide and shallow second trench 111b, and then forming a relatively narrow and deep first trench 111a.

[0065] Next, as shown in Figures 8A and 8B, an acceptor, which is an impurity, is injected into the sidewall of the trench 111 and activated by heat treatment to form a P-type semiconductor layer 105 on the sidewall of the trench 111. For example, boron (B) is used as the acceptor.

[0066] Next, as shown in Figures 9A and 9B, a donor, which is an impurity, is further injected into the side wall of the trench 111 where the P-type semiconductor layer 105 is formed, and activated by heat treatment, thereby forming a charge discharge layer 106 adjacent to the P-type semiconductor layer 105 on the side wall of the trench 111.

[0067] Next, as shown in Figures 10A and 10B, the first insulating film 107 is formed inside the trench 111. This creates the first insulating film 107 covering the charge discharge layer 106 inside the trench 111.

[0068] Next, as shown in Figures 11A and 11B, a portion of the first insulating film 107 is removed to expose a portion of the charge discharge layer 106. Specifically, the portion of the first insulating film 107 formed inside the second trench 111b is removed to expose a portion of the charge discharge layer 106.

[0069] Next, as shown in Figures 12A and 12B, a contact layer 109 is formed by depositing, for example, polysilicon (Poly-Si) in the area where the first insulating film 107 has been removed.

[0070] Next, as shown in Figures 13A and 13B, each impurity is injected into the area surrounded by the trench 111 and activated by heat treatment to form a P+ type semiconductor region 103, an N+ type semiconductor region 102, and a cathode electrode 101.

[0071] Next, as shown in Figures 14A and 14B, a second insulating film 530 is formed, and via holes are formed in the portions of the second insulating film 530 corresponding to the cathode electrode 101, anode electrode 110, and charge discharge contact layer 109, respectively. By filling these via holes with metal, cathode wiring 541, anode wiring 542, and charge discharge electrode 108 are formed.

[0072] Next, as shown in Figures 15A and 15B, the semiconductor substrate 510 is inverted, and a layer of hard mask material 910 is formed on the back surface of the semiconductor substrate 510. The hard mask material 910 is then etched using a mask in which openings corresponding to some positions of the contact layer 109 are formed. Then, the first insulating film 107 is etched using the hard mask material 910, which has openings corresponding to some positions of the contact layer 109 formed by etching, as a mask, thereby removing a portion of the first insulating film 107 and exposing the contact layer 109 from the semiconductor substrate 510 side. Specifically, a portion of the first insulating film 107 is removed while leaving the portion covering the charge discharge layer 106 of the first insulating film 107 intact, thereby exposing the contact layer 109 from the semiconductor substrate 510 side.

[0073] Next, as shown in Figures 16A and 16B, a metal layer 115 is formed by depositing metal on the back surface of the semiconductor substrate 510 and filling the area where the first insulating film 107 has been removed with metal. For example, tungsten (W) is used as the metal.

[0074] Next, as shown in Figures 17A and 17B, the metal deposited in areas other than those from which the first insulating film 107 has been removed is removed.

[0075] Figure 18 is a flowchart showing the main steps in the manufacturing method of the image sensor 1, corresponding to Figures 7A to 17B.

[0076] Multiple SPAD elements 100 formed on a silicon substrate, which is a semiconductor substrate 510, are separated by creating a grid-like trench 111 to isolate them from one another (S101).

[0077] Next, a P-type semiconductor layer 105 is formed on the side wall of the trench 111 (S102).

[0078] Next, a charge discharge layer 106 is formed on the side wall of the trench 111, adjacent to the P-type semiconductor layer 105 (S103).

[0079] Next, a first insulating film 107 covering the charge discharge layer 106 is formed inside the trench 111 (S104).

[0080] Next, a portion of the first insulating film 107 is removed to expose a portion of the charge discharge layer 106 (S105).

[0081] Next, a contact layer 109 is formed on the portion removed in step S105 (S106).

[0082] Next, a P+-type semiconductor region 103, an N+-type semiconductor region 102, a cathode electrode 101, and an anode electrode 110 are formed in the area surrounded by the trench 111 (S107). The anode electrode 110 may be formed before or after step S107.

[0083] Next, cathode wiring 541 is formed to connect to the cathode electrode 101 (S108). In step S108, along with forming the cathode wiring 541, anode wiring 542 to connect to the anode electrode 110 and a charge discharge electrode 108 to connect to the charge discharge contact layer 109 may also be formed.

[0084] Next, the semiconductor substrate 510 is inverted, and a portion of the first insulating film 107 is removed to expose the contact layer 109 from the semiconductor substrate 510 side (S109).

[0085] Next, a separation metal layer 115 is formed in the portion where the first insulating film 107 was removed in step S109 (S110).

[0086] (Extreme Variation 1-1) A modified example 1-1 of the first embodiment will be described.

[0087] Figures 19A and 19B are a cross-sectional view and a plan view of the SPAD element 100. Figure 19A corresponds to the cross-section along the A-A' plane in Figure 19B. Figure 19B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 19A.

[0088] In the first embodiment described above, the charge discharge electrode 108 was provided on the surface side (upper side in the figure) of the substrate, and the contact layer 109 was configured separately. However, in Modification 1-1, as shown in Figures 19A and 19B, the function of the charge discharge electrode 108 is provided to the separation metal layer 115 of the first embodiment, and the charge discharge electrode 108 is formed from the same conductive material as the contact layer 109. For example, the charge discharge electrode 108 and the contact layer 109 are formed from polysilicon (Poly-Si). The charge discharge electrode 108 and the contact layer 109 may be formed integrally. Also, the shape of the contact layer 109 may be a cross shape when viewed from the light incident surface of the semiconductor substrate 510 in a plan view.

[0089] (Variations 1-2) Modification 1-2 of the first embodiment will be described below.

[0090] Figures 20A and 20B are a cross-sectional view and a plan view of the SPAD element 100. Figure 20A corresponds to the cross-section along the A-A' plane in Figure 20B. Figure 20B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 20A.

[0091] In Modification 1-1, the contact layer 109 was formed only at the intersections of the grid-like trenches 111. However, in Modification 1-2, as shown in Figures 20A and 20B, the contact layer 109 may be formed over the entire upper part of the grid-like trenches 111. This ensures that, when viewed from the surface of the semiconductor substrate 510, the contact layers 109 of each SPAD element 100 are interconnected and surround the charge discharge layer 106 of each SPAD element 100. Similar to Modification 1-1, the charge discharge electrode 108 may be formed from the same conductive material as the contact layer 109.

[0092] (Variations 1-3) Modifications 1-3 of the first embodiment will be described below.

[0093] Figures 21A and 21B are a cross-sectional view and a plan view of the SPAD element 100. Figure 21A corresponds to the cross-section along the A-A' plane in Figure 21B. Figure 21B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 21A. Figure 21C shows the vertical potential gradient of the semiconductor substrate 510 inside the charge discharge layer 106.

[0094] As shown in Figures 21A and 21B, the impurity concentration in the charge discharge layer 106 may be set so that it is higher in the area closer to the connection point with the charge discharge electrode 108 than in the area further away. Specifically, the impurity concentration in the charge discharge layer 106 is gradually changed so that it is higher in the area closer to the contact layer 109 than in the area further away. If the impurity concentration in the charge discharge layer 106 is uniform, it is difficult to create a potential gradient within the discharge layer 106, but by creating a concentration gradient, it is possible to generate a potential difference and form a potential gradient with enhanced charge discharge capability.

[0095] As shown in Figure 21C, by gradually changing the impurity concentration of the charge discharge layer 106 so that it is higher closer to the contact layer 109 than further away, the vertical potential gradient of the semiconductor substrate 510 can be made steeper. This improves the rate of electron discharge generated as dark current.

[0096] Figures 22A to 23B are cross-sectional diagrams illustrating the manufacturing method of the image sensor 1 according to modified examples 1-3. In Figures 22A to 23B, figures with the same figure number illustrate the same manufacturing step. Figures with a figure number including A correspond to the cross-section along the A-A' plane in figures with a figure number including B. Figures with a figure number including B are top views of the semiconductor substrate 510, corresponding to the cross-section along the C-C' plane in figures with a figure number including A.

[0097] As shown in Figures 22A and 22B, similar to the first embodiment, a donor, which is an impurity, is further injected into the side wall of the trench 111 in which the P-type semiconductor layer 105 is formed, and activated by heat treatment, thereby forming a charge discharge layer 106 adjacent to the P-type semiconductor layer 105 on the side wall of the trench 111.

[0098] As shown in Figures 23A and 23B, donors, which are impurities, are injected into the sidewall of the trench 111 on which the P-type semiconductor layer 105 is formed, by gradually changing the injection energy, and then activated by heat treatment. As a result, a charge discharge layer 106 is formed on the sidewall of the trench 111 adjacent to the P-type semiconductor layer 105, in which the impurity concentration of the charge discharge layer 106 is higher in positions closer to the contact layer 109 than in positions further away.

[0099] (Second Embodiment) A second embodiment will now be described. The differences between this embodiment and the first embodiment are as follows. In the first embodiment, the charge discharge layer 106 is composed of an N-type semiconductor layer. On the other hand, in this embodiment, by applying a voltage higher in the positive direction than the voltage of the P-type semiconductor layer 105 to the charge discharge electrode 108, a potential depression (channel) is formed at the interface between the P-type semiconductor layer 105 and the first insulating film 107, and the region where this potential depression occurs is defined as the charge discharge path 106A. That is, the charge discharge path 106A is composed of the potential depression (channel) generated at that interface. In other respects, this embodiment is the same as the first embodiment, so redundant explanations will be omitted or simplified.

[0100] Figures 24A and 24B are a cross-sectional view and a plan view of the SPAD element 100. Figure 24A corresponds to the cross-section along the A-A' plane in Figure 24B. Figure 24B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 24A.

[0101] The P-type semiconductor layer 105 is connected to the contact layer 109, and through the contact layer 109, is electrically connected to the charge discharge electrode 108. Furthermore, a voltage higher in the positive direction than the voltage across the P-type semiconductor layer 105 is applied to the charge discharge electrode 108. Through this configuration and voltage control, electrons from the dark current generated at the interface between the P-type semiconductor layer 105 and the first insulating film 107 are transferred to the charge discharge electrode 108 via the charge discharge path 106A and the contact layer 109. The charge discharge path 106A constitutes the charge discharge layer. An anode voltage VA is applied to the anode electrode 110 provided on the P-type semiconductor layer 105 from the anode wiring 542 (see Figure 4B).

[0102] Figure 24C shows the potentials corresponding to each position in the path indicated by the dashed line in Figure 24A. As shown in Figure 24C, when a predetermined charge discharge voltage is applied to the charge discharge electrode 108, a potential sink occurs at the boundary between the silicon oxide (SiO) and silicon (Si) of the first insulating film 107. Then, electrons as dark current generated at the boundary between the silicon oxide (SiO) and silicon (Si) of the first insulating film 107 are discharged through the charge discharge electrode 108. In this embodiment, for example, when the anode voltage VA is -20V, the charge discharge voltage is set to -18V, which is a predetermined potential higher than the anode voltage VA of -20V. By applying an appropriate charge discharge voltage, a charge transfer path 106A is formed at the boundary between the first insulating film 107 and the P-type semiconductor layer 105. The predetermined potential can be appropriately set experimentally from the viewpoint of reducing DCR.

[0103] (Third embodiment) A third embodiment will now be described. The differences between this embodiment and the first embodiment are as follows. In the first embodiment, a DTI is formed by forming a charge discharge electrode 108 and a first insulating film 107 inside the trench 111. On the other hand, in this embodiment, a DTI is formed by forming an in-trench anode electrode 112 and a first insulating film 107 inside the trench 111, and the in-trench anode electrode 112 and the P-type semiconductor layer 105 are connected by an anode contact 113 formed at a position relatively far from the cathode electrode 101. In other respects, this embodiment is the same as the first embodiment, so redundant explanations will be omitted or simplified.

[0104] Figures 25A and 25B are a cross-sectional view and a plan view of the SPAD element 100. Figure 25A corresponds to the cross-section along the A-A' plane in Figure 25B. Figure 25B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 25A.

[0105] As shown in Figures 25A and 25B, in this embodiment, a trench-internal anode electrode 112 and a first insulating film 107 are formed inside the trench 111. The trench-internal anode electrode 112 and the P-type semiconductor layer 105 are connected by an anode contact 113 formed at a position relatively far from the cathode electrode 101.

[0106] The trench anode electrode 112 can be made of a metal. For example, the trench anode electrode 112 can be made of tungsten (W).

[0107] The anode contact 113 is formed, for example, from P-type polysilicon (Poly-Si) with a doped acceptor.

[0108] The trench anode electrode 112 and anode contact 113 may be formed by the method described in Japanese Patent Application No. 2024-081552.

[0109] The N-type semiconductor layer forming the charge emission layer 106 can be formed such that the donor concentration is relatively low on the P-type semiconductor layer 105 side, and decreases as it approaches the first insulating film 107. By gradually changing the donor concentration of the charge emission layer 106 so that it is higher closer to the first insulating film 107 than further away, the potential gradient parallel to the semiconductor substrate 510 can be made steeper. Such a structure in which the donor concentration of the charge emission layer 106 is higher closer to the first insulating film 107 than further away can be realized, for example, by forming the charge emission layer 106 by plasma doping and heat treatment in the step of forming the charge emission layer 106 shown in Figures 9A and 9B.

[0110] The anode voltage VA can be applied to the trench anode electrode 112 and then applied to the P-type semiconductor layer 105 via the anode contact 113.

[0111] A charge discharge voltage is applied to the charge discharge layer 106 from the charge discharge electrode 108.

[0112] In this embodiment, the rate of electron emission as dark current can be improved by making the potential gradient parallel to the semiconductor substrate 510 of the charge emission layer 106 steeper. Furthermore, by supplying the anode voltage via the anode contact 113, which is relatively far from the cathode electrode 101, the electric field between the anode and cathode can be suppressed, thereby suppressing electrons generated as dark current due to the high electric field.

[0113] (Variation 3-1) A modified example 3-1 of the third embodiment will be described.

[0114] Figures 26A and 26B are a cross-sectional view and a plan view of the SPAD element 100. Figure 26A corresponds to the cross-section along the A-A' plane in Figure 26B. Figure 26B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 26A. Figure 26C is a diagram showing the potentials corresponding to each position along the path indicated by the dashed line in Figure 26A.

[0115] As shown in Figures 26A and 26B, the impurity concentration in the charge discharge layer 106 may be set so that it is higher closer to the connection point with the charge discharge electrode 108 than at the more distant point. Specifically, the impurity concentration in the charge discharge layer 106 is gradually changed so that it is higher closer to the connection point with the charge discharge electrode 108 than at the more distant point. If the impurity concentration in the charge discharge layer 106 is uniform, it is difficult to create a potential gradient, but by creating a concentration gradient, it is possible to generate a potential difference and form a potential gradient that enhances the charge discharge function.

[0116] As shown in Figure 26C, by gradually changing the impurity concentration of the charge emission layer 106 such that the potential gradient in the vertical direction of the semiconductor substrate 510 is made steeper at positions closer to the charge emission electrode 108 to which the charge emission voltage is applied to the charge emission layer 106 than at positions further away. This improves the emission rate of electrons generated as dark current.

[0117] (Fourth Embodiment) A fourth embodiment will now be described. The differences between this embodiment and the first embodiment are as follows. In the first embodiment, a contact layer 109 is formed on the surface side of the semiconductor substrate 510, and the contact layer 109 is connected to the charge discharge electrode 108. The charge discharge voltage is then applied to the charge discharge layer 106 via the contact layer 109. On the other hand, in this embodiment, a contact layer 114 is formed on the back side of the semiconductor substrate 510, and the contact layer 114 is connected to the charge discharge electrode 108. The charge discharge voltage applied to the charge discharge electrode 108 is then applied to the charge discharge layer 106 via the contact layer 114. In other respects, this embodiment is the same as the first embodiment, so redundant explanations will be omitted or simplified.

[0118] Figures 27A and 27B are a cross-sectional view and a plan view of the SPAD element 100. Figure 27A corresponds to the cross-section along the A-A' plane in Figure 27B. Figure 27B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 27A.

[0119] As shown in Figures 27A and 27B, in this embodiment, a contact layer 114 is formed on the back side of the semiconductor substrate 510 to connect the charge discharge electrode 108 and the charge discharge layer 106.

[0120] The contact layer 114 is connected to the charge discharge electrode 108. As a result, the charge discharge voltage applied to the charge discharge electrode 108 is applied to the charge discharge layer 106 via the contact layer 114.

[0121] The contact layer 114 is formed, for example, from donor-doped N-type polysilicon (Poly-Si).

[0122] Since the charge discharge electrodes 108 of each SPAD element 100 are formed in a grid-like trench 111, they can be interconnected in a grid-like manner. Therefore, for example, by applying a charge discharge electrode to at least one location on the grid-like charge discharge electrode 108 from the light incident surface side of the semiconductor substrate 510, the applied charge discharge voltage can be shared among each SPAD element 100.

[0123] (Variation 4-1) A modified example 4-1 of the fourth embodiment will be described.

[0124] Figures 28A and 28B are a cross-sectional view and a plan view of the SPAD element 100. Figure 28A corresponds to the cross-section along the A-A' plane in Figure 28B. Figure 28B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 28A. Figure 28C shows the vertical potential gradient of the semiconductor substrate 510 inside the charge discharge layer 106.

[0125] As shown in Figures 28A and 28B, the impurity concentration of the charge discharge layer 106 may be set so that it is higher in the area closer to the connection point with the charge discharge electrode 108 than in the area further away. Specifically, the impurity concentration of the charge discharge layer 106 is gradually changed so that it is higher in the area closer to the contact layer 114 than in the area further away.

[0126] The impurity concentration of the charge discharge layer 106 is gradually changed so that the charge discharge voltage is higher closer to the contact layer 114, which applies the charge discharge voltage to the charge discharge layer 106, than at positions further away. This makes the potential gradient of the charge discharge layer 106 in the vertical direction of the semiconductor substrate 510 steeper, thereby improving the discharge rate of electrons generated as dark current.

[0127] (Modification 4-2) A modified example 4-2 of the fourth embodiment will be described.

[0128] Figures 29A and 29B are a cross-sectional view and a plan view of the SPAD element 100. Figure 29A corresponds to the cross-section along the A-A' plane in Figure 29B. Figure 29B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 29A.

[0129] This modified example corresponds to an example in which the configuration of the second embodiment is applied to the configuration of the fourth embodiment. Specifically, the charge discharge layer 106 is composed of a charge discharge path 106A formed in a P-type semiconductor layer. As shown in Figures 29A and 29B, the charge discharge path 106A is formed in the P-type semiconductor layer 105.

[0130] The P-type semiconductor layer 105, on which the charge discharge path 106A is formed, is connected to the contact layer 114, and the charge discharge voltage applied to the charge discharge electrode 108 is applied to the P-type semiconductor layer 105 via the contact layer 114. In addition, the anode voltage VA is applied to the anode electrode 110 provided on the P-type semiconductor layer 105 from the anode wiring 542.

[0131] (Modification 4-3) A modified example 4-3 of the fourth embodiment will be described.

[0132] Figures 30A and 30B are a cross-sectional view and a plan view of the SPAD element 100. Figure 30A corresponds to the cross-section along the A-A' plane in Figure 30B. Figure 30B is a plan view of the semiconductor substrate 510 viewed from above, corresponding to the cross-section along the C-C' plane in Figure 30A. Figure 30C shows the vertical potential gradient of the semiconductor substrate 510 inside the charge discharge layer 106.

[0133] This modification corresponds to a further modification of the charge emission layer 106 in Modification 4-1. As shown in Figures 30A and 30B, the charge emission layer 106 is not exposed on the surface of the semiconductor substrate 510, and the length of the charge emission layer 106 in the depth direction of the semiconductor substrate 510 is made shorter than in Modification 4-1. This makes it possible to further increase the potential gradient of the charge emission layer 106 in the vertical direction of the semiconductor substrate 510, and to further improve the emission rate of electrons generated as dark current.

[0134] The embodiment provides the following effects:

[0135] Each SPAD element formed on the substrate includes a trench for isolation from other SPAD elements, a charge discharge layer formed on the side wall of the trench and electrically connected to the charge discharge electrode, and an insulating film formed inside the trench and covering the charge discharge layer. This effectively prevents deterioration of the DCR due to the multiplication of dark current generated between the insulating film and the semiconductor used to isolate the elements.

[0136] Furthermore, a first semiconductor layer of the first conductivity type is included on the opposite side of the insulating film via a charge discharge layer, and the potential of the charge discharge layer is made higher than the potential of the first semiconductor layer to which the anode voltage is applied. This makes it easy to prevent electrons of the dark current from reaching the multiplication region of the SPAD element.

[0137] Furthermore, the first semiconductor layer is positioned adjacent to the charge discharge layer. This makes it easy to prevent electrons from dark current from reaching the multiplication region of the SPAD element while suppressing an increase in the size of the SPAD element.

[0138] Furthermore, the charge emission layer is made of a second-conductivity semiconductor layer. This improves the trapping performance of dark current electrons in the charge emission layer.

[0139] Furthermore, the impurity concentration in the charge emission layer is made lower than that of the first semiconductor layer. This allows for a relatively high degree of carrier depletion within the charge emission layer, further improving the trapping performance of dark current electrons in the charge emission layer.

[0140] Furthermore, the impurity concentration in the charge evacuation layer is made higher closer to the connection point with the charge evacuation electrode than further away. This increases the potential gradient within the charge evacuation layer, thereby improving the rate of electron evacuation of the dark current.

[0141] Furthermore, the charge discharge layer is used as a charge discharge path in the first conductivity type semiconductor layer, and a potential predetermined to be higher than the potential applied to the anode electrode of the SPAD element is applied. This further suppresses the increase in the size of the SPAD element while making it easier to prevent electrons of dark current from reaching the multiplication region of the SPAD element.

[0142] Furthermore, the charge discharge electrodes are formed inside the trench. This suppresses crosstalk between SPAD elements, and by making the wiring for applying the charge discharge voltage to the charge discharge electrodes common to each SPAD element, the chip area of ​​the image sensor can be reduced.

[0143] Furthermore, a contact layer is formed on the front or back surface of the substrate. This facilitates the layout of wiring for applying the charge discharge voltage.

[0144] Furthermore, the structure includes an anode electrode formed inside the trench, and the anode electrode and the first semiconductor layer are in contact at the side wall of the trench. This allows for the formation of an anode contact at a position away from the cathode electrode, thereby suppressing the electric field between the anode and cathode and preventing the generation of electrons as dark current due to a high electric field.

[0145] The embodiments described above are illustrative only, and any person with ordinary skill in the art to which this invention pertains will understand that a variety of modifications and equivalent other embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered in an explanatory rather than restrictive manner. The scope of the rights is defined in the claims, and all configurations within an equivalent scope should be construed as being included within the scope of the rights. [Explanation of symbols]

[0146] 1 Image sensor, 10-pixel array, 11 SPAD pixels, 20 control circuits, 30 drive circuit, 40 output circuits, 50 pixel drive lines, 60 output signal lines, 70-element array, 100 SPAD elements, 101 Cathode electrode, 102 N+ type semiconductor layer, 103 P+ type semiconductor layer, 104 Photoelectric conversion region, 105 P-type semiconductor layer, 106 charge evacuation layer, 106A charge discharge path, 107 First insulating film, 108 charge discharge electrode, 109 Contact layer, 110 anode electrodes, 111 Trench, 112 Anode electrode inside the trench, 113 Anode contact, 114 Contact layer, 115 Separation metal layer, 200 Quench Resistor Transistors, 300 Inverter, 500-pixel chip, 510 silicon substrate, 511 Silicon, 520 wiring layer, 530 Second insulating film, 540 wiring, 541 Cathode wiring, 542 Anode wiring, 600 logic chips, 900 Hard mask material.

Claims

1. An image sensor having multiple SPAD elements, The aforementioned SPAD device is A trench for separating the SPAD element from other SPAD elements, A charge discharge layer is formed in the side wall of the trench and is electrically connected to the charge discharge electrode, An image sensor having an insulating film formed inside the trench and covering the charge discharge layer.

2. On the side opposite to the insulating film, via the charge discharge layer, there is a first semiconductor layer of a first conductivity type, The image sensor according to claim 1, wherein the potential of the charge discharge layer is higher than the potential of the first semiconductor layer to which the anode voltage is applied.

3. The image sensor according to claim 2, wherein the first semiconductor layer is adjacent to the charge discharge layer.

4. The image sensor according to claim 1, wherein the charge discharge layer is a second-conductivity semiconductor layer.

5. On the side opposite to the insulating film, via the charge discharge layer, there is a first semiconductor layer of a first conductivity type, The image sensor according to claim 4, wherein the impurity concentration of the charge discharge layer is lower than the impurity concentration of the first semiconductor layer.

6. The image sensor according to claim 4, wherein the impurity concentration in the charge discharge layer is higher at a position closer to the connection portion connected to the charge discharge electrode than at a position further away.

7. The image sensor according to claim 1, wherein the charge discharge layer is a semiconductor layer of a first conductivity type, and a potential predetermined to be higher than the potential applied to the anode electrode of the SPAD element is applied to it.

8. The image sensor according to claim 1, wherein the charge discharge electrode is formed inside the trench.

9. The charge discharge layer and the charge discharge electrode are further connected by a contact layer. The image sensor according to claim 8, wherein the contact layer is formed in a region including the intersection of the trench and is shared among the plurality of SPAD elements.

10. The SPAD element is formed on a substrate, The image sensor according to claim 9, wherein the contact layer is formed on the front or back surface of the substrate.

11. The system further comprises an anode electrode formed inside the trench, The image sensor according to claim 2, wherein the anode electrode and the first semiconductor layer are in contact at the side wall of the trench.

12. A method for manufacturing an image sensor having multiple SPAD elements, (a) A step of forming a trench to separate the SPAD element from other SPAD elements, Step (a) above is to form a charge discharge layer on the side wall of the trench formed in step (b), Step (c) is to form an insulating film covering the charge discharge layer formed in step (b) inside the trench, Step (d) involves removing a portion of the insulating film formed in step (c) to expose a portion of the charge discharge layer, Step (d) above is the step (e) of forming a contact layer in the portion where the insulating film was removed, (f) A step of forming a multiplication region of the SPAD element in the area surrounded by the trench, Step (g) involves removing a portion of the insulating film to expose the contact layer, Step (h) is to form a charge discharge electrode in the portion where the insulating film was removed in step (g), A method for manufacturing an image sensor having the following characteristics.

Images