Semiconductor equipment

Abstract

To provide a semiconductor device with reduced parasitic capacitance. [Solution] The transistor 10 comprises a first insulating layer 110, a first oxide layer thereon, a semiconductor layer 122 thereon, a source electrode layer 130 and a drain electrode layer 140 thereon, a second insulating layer 173 on the first insulating layer, a third insulating layer 175 on the second insulating layer, the source electrode layer and the drain electrode layer, a second oxide 123 on the semiconductor layer, a gate insulating layer 150 on the second oxide layer, a gate electrode layer 160 thereon, and a third The device has an insulating layer, a second oxide layer, and a fourth insulating layer 170 on the gate insulating layer and gate electrode layer, wherein the second insulating layer has a region on its side surface that is in contact with the first oxide layer, semiconductor layer, source electrode layer and drain electrode layer, and its upper surface is coplanar with the source electrode layer and drain electrode layer, and the second oxide layer has a region that is in contact with the side surfaces of the first oxide layer, source electrode layer, drain electrode layer, second insulating layer and third insulating layer.

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and their driving methods, or their manufacturing methods. In particular, one aspect of the present invention relates to a semiconductor device or a method for manufacturing the same.

[0002] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are an aspect of the semiconductor device. In addition, a storage device, a display device, and an electronic device may have a semiconductor device.

Background Art

Background Art

[0003] Techniques for constructing a transistor using a semiconductor film formed on a substrate having an insulating surface have attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor is attracting attention as another material. For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor.

[0004] For example, as an active layer of a transistor, a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0005] ​​​ [Patent Document 1] Special Publication No. 11-505377 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As semiconductor devices are miniaturized, parasitic capacitance near transistors becomes a major problem.

[0007] In transistor operation, near the channel (for example, between the source electrode and the drain electrode) If raw capacitance is present, time is required for the parasitic capacitance to charge, affecting the transistor's response. This can reduce performance and, consequently, the responsiveness of semiconductor devices.

[0008] Furthermore, the various processes involved in forming transistors (especially thin-film deposition and processing) are constantly evolving with increasing miniaturization. Controlling this is becoming increasingly difficult, as variations in the manufacturing process affect transistor characteristics, and furthermore... This can have a significant impact on reliability.

[0009] Furthermore, with miniaturization, the precision required for processing has become stricter, making processing more difficult. They're waiting.

[0010] Therefore, one aspect of the present invention aims to reduce parasitic capacitance near a transistor. One of the objectives is to provide a semiconductor device with good electrical characteristics. Alternatively, one of the objectives is to provide highly reliable semiconductor devices. One of the objectives is to reduce variations in the characteristics of devices or semiconductor equipment caused by the manufacturing process. Alternatively, one of the objectives is to stabilize the transistor manufacturing process. One of the objectives is to provide a semiconductor device having an oxide semiconductor layer with few oxygen vacancies. To do so. Or, to provide a semiconductor device that can be formed by a simple process. Alternatively, a semiconductor with a configuration that can reduce interface states near the oxide semiconductor layer. One of the objectives is to provide a device, or to provide a low-power semiconductor device. One of the objectives is to provide novel semiconductor devices, etc. Alternatively, one of the objectives is to provide a method for manufacturing the above-mentioned semiconductor device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first insulating layer, a first oxide layer on the first insulating layer, and a first oxide A semiconductor layer on a layer, a source electrode layer and a drain electrode layer on the semiconductor layer, and a first insulating layer on The second insulating layer, and the third insulating layer on the second insulating layer, the source electrode layer, and the drain electrode layer A layer, a second oxide layer on the semiconductor layer, a gate insulating layer on the second oxide layer, and gate insulating A gate electrode layer on top of the layers, a third insulating layer, a second oxide layer, a gate insulating layer, and a gate The electrode layer has a fourth insulating layer, and the second insulating layer has a first oxide layer, a semiconductor layer, and - It has an electrode layer and a region that is in contact with the side surface of the drain electrode layer. The upper surface of the second insulating layer is The second oxide layer is coplanar with the source electrode layer and the drain electrode layer, and the second oxide layer is the first The oxide layer, source electrode layer, drain electrode layer, second insulating layer, and side of the third insulating layer This semiconductor device is characterized by having a region that is in contact with a certain element.

[0013] Another aspect of the present invention involves forming a first insulating layer and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, and a first conductive film is formed on the semiconductor film, and the first A first mask is formed on the conductive film, and a portion of the first conductive film is etched using the first mask. Then, the first conductive layer is formed in an island shape, and the first mask and the first conductive layer are used as a mask. By using this method, the first oxide film and a portion of the semiconductor film are etched, thereby the first oxide A physical layer and a semiconductor layer are formed in an island-like manner, and a second insulating layer is formed on the first insulating layer and the first conductive layer. A film is formed, and the second insulating film is subjected to chemical mechanical polishing until the first conductive layer is exposed. This forms a second insulating layer, and a third insulating film is formed on the first conductive layer and the second insulating layer. Form a third insulating film, form a second mask on the third insulating film, and use the second mask to form the third insulating film By etching a portion of it, the source electrode layer, the drain electrode layer, and the third insulating layer An edge layer is formed, a third insulating layer, and a second oxide film is formed on the semiconductor layer, and the second oxide film A fourth insulating film is formed on top, a second conductive film is formed on the fourth insulating film, and the second conductive film, By performing chemical mechanical polishing on the insulating film 4 and the second oxide film, the second oxide layer A method for manufacturing a semiconductor device, characterized by forming a gate insulating layer and a gate electrode layer. .

[0014] Furthermore, after semiconductor film formation, a first heat treatment is performed to form a third insulating layer, a second oxide layer, and a gate. A fourth insulating layer containing oxygen is formed on the insulating layer and the gate electrode layer, and when the fourth insulating layer is formed, A mixed layer of the third insulating layer and the fourth insulating layer is formed, and at the same time, the mixed layer or the first insulating layer It is preferable to add oxygen and perform a second heat treatment to diffuse the oxygen into the semiconductor layer. stomach.

[0015] Furthermore, the third insulating film is an insulating film containing oxygen, and the fourth insulating layer uses oxygen gas. It is preferable to form it by sputtering.

[0016] Furthermore, the third insulating film is a silicon oxide film, and the fourth insulating layer is 50 volumes of oxygen gas. Formed by sputtering using % or more of and with an aluminum oxide target. It is preferable to do so.

[0017] Furthermore, it is preferable to perform the second heat treatment at a temperature of 300°C to 450°C.

[0018] Another aspect of the present invention involves forming a first insulating layer and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, and a first conductive film is formed on the semiconductor film, and the first A second insulating film is formed on the conductive film, a first mask is formed on the second insulating film, and the first mask Using a tool, the second insulating film and a portion of the first conductive film are etched, and the first conductive layer and a second insulating layer are formed, and a second mask is formed on the second insulating layer and the semiconductor film, Using mask 2, the second insulating layer, the first conductive layer, the first oxide film, and the semiconductor film By etching a portion of it, the first oxide layer, semiconductor layer, source electrode layer, and drain are separated. An electrode layer and a third insulating layer are formed on the first insulating layer, the third insulating layer, and the semiconductor layer. A second oxide film is formed on the second oxide film, and a third insulating film is formed on the second oxide film. A second conductive film is formed on top, a third mask is formed on the second conductive film, and the third mask is used Then, etching the second oxide film, the third insulating film, and a portion of the second conductive film. This process is characterized by forming a second oxide layer, a gate insulating layer, and a gate electrode layer. This is a method for manufacturing a body device.

[0019] Furthermore, after semiconductor film formation, a first heat treatment is performed, forming a first insulating layer, a third insulating layer, and a gate electrode. A fourth insulating layer containing oxygen is formed on the pole layer, and when the fourth insulating layer is formed, the first insulating layer and the It has a first mixed layer with four insulating layers, and a second mixed layer with the third insulating layer and the fourth insulating layer. And at the same time, acid is added to the first mixed layer, the second mixed layer, the first insulating layer, or the second insulating layer. It is preferable to add an element and perform a second heat treatment to diffuse oxygen into the semiconductor layer.

[0020] Furthermore, the first insulating film and the second insulating film are insulating films containing oxygen, and the fourth insulating layer It is preferable to form it by sputtering using oxygen gas.

[0021] Furthermore, the first insulating film and the second insulating film are silicon oxide films, and the fourth insulating layer is acid Using 50% or more of a primary gas and an aluminum oxide target, sputtering It is preferable to form it by the molding method.

[0022] Furthermore, it is preferable to perform the second heat treatment at a temperature of 300°C to 450°C.

[0023] Another aspect of the present invention involves forming a first insulating layer and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, and a first conductive film is formed on the semiconductor film, and the first A second insulating film is formed on the conductive film, a third insulating film is formed on the second insulating film, and the third insulating film A first mask is formed on the film, and a third insulating film and a second insulating film are formed using the first mask. Etching a portion of the first conductive film, the semiconductor film, and the first oxide film. This forms an island-like structure containing a first oxide layer, a semiconductor layer, a second insulating layer, and a third insulating layer. A fourth insulating film is formed on the first insulating layer and the third insulating layer until the third insulating layer is exposed. The fourth insulating film is subjected to chemical and mechanical polishing to form the fourth insulating layer, and the fourth insulating layer, A second mask is formed on the third insulating layer, and the source electrode layer is formed using the second mask. A rain electrode layer, a fifth insulating layer, and a sixth insulating layer are formed, and the fourth insulating layer and the sixth insulating layer A second oxide film is formed on the margin layer and on the semiconductor layer, and a fifth insulating film is formed on the second oxide film. A film is formed, and a second conductive film is formed on the fifth insulating film, and the second conductive film, the fifth insulating film, the By performing a chemical and mechanical polishing treatment on the oxide film 2, the second oxide layer and the gate insulating layer are formed. The present invention relates to a method for manufacturing a semiconductor device, characterized by forming a gate electrode layer.

[0024] Furthermore, after the semiconductor film is formed, a first heat treatment is performed, and when the third insulating film is formed, the second insulating film and A mixed layer is formed with a third insulating film, and at the same time, oxygen is added to the mixed layer or the second insulating film. The fourth insulating layer, the sixth insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer are then placed on top of each other. A seventh insulating layer is formed, and when the seventh insulating layer is formed, a mixed layer of the fourth insulating layer and the seventh insulating layer is formed. Form the mixture and simultaneously add oxygen to the mixed layer or the fourth insulating layer, then perform the second heat treatment. It is preferable to diffuse oxygen into the semiconductor layer.

[0025] Furthermore, the second insulating film and the fourth insulating film are insulating films containing oxygen, and the third insulating film and The seventh insulating layer is preferably formed by sputtering using oxygen gas.

[0026] Furthermore, the second insulating film and the fourth insulating film are silicon oxide films, and the third insulating film and the The insulating layer of 7 uses 50% or more by volume of oxygen gas and an aluminum oxide target. It is preferable to form it by sputtering.

[0027] Furthermore, it is preferable to perform the second heat treatment at a temperature of 300°C to 450°C.

[0028] Furthermore, the configuration can consist of a semiconductor device, a microphone, a speaker, and a housing. [Effects of the Invention]

[0029] By using one aspect of the present invention, it is possible to reduce parasitic capacitance near the transistor. Alternatively, it is possible to provide a semiconductor device with good electrical characteristics. Alternatively, high reliability We can provide semiconductor devices. Or, the manufacturing of transistors or semiconductor devices. This can reduce variations in characteristics caused by the manufacturing process. Alternatively, it can reduce variations in the transistor manufacturing process. The temperature can be stabilized. Alternatively, a semiconductor having an oxide semiconductor layer with few oxygen vacancies. A device can be provided, or a semiconductor device that can be formed by a simple process. This can provide the following: or it can reduce the interface states near the oxide semiconductor layer. A semiconductor device with the following configuration can be provided. Alternatively, a low-power semiconductor device can be provided. It is possible to provide a novel semiconductor device, etc. Or the above-mentioned semiconductor device. A method for manufacturing a conductive device can be provided.

[0030] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0031] [Figure 1] Top view and cross-sectional view illustrating a transistor. [Figure 2] A cross-sectional diagram illustrating a transistor. [Figure 3] Magnified cross-sectional view and band diagram of a transistor. [Figure 4] A schematic diagram illustrating the ALD film deposition principle. [Figure 5] ALD device overview diagram. [Figure 6] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 7] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 8] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 9] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 10] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 11] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 12] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 13] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 14] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 15]Top view and cross-sectional view illustrating a transistor. [Figure 16] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 17] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 18] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 19] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 20] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 21] A cross-sectional diagram illustrating the method of manufacturing a transistor. [Figure 22] A cross-sectional diagram illustrating the method of manufacturing a transistor. [Figure 23] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 24] Top view and cross-sectional view illustrating a transistor. [Figure 25] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 26] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 27] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 28] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 29] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 30] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 31] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 32] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 33] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 34]High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 35] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 36] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 37] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 38] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 39] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 40] A plan view showing the imaging device. [Figure 41] A plan view showing the pixels of an imaging device. [Figure 42] A cross-sectional view showing the imaging device. [Figure 43] A cross-sectional view showing the imaging device. [Figure 44] A diagram illustrating an example of RF tag configuration. [Figure 45] A diagram illustrating an example of a CPU configuration. [Figure 46] Circuit diagram of a memory element. [Figure 47] A diagram illustrating an example of a display device configuration and a circuit diagram of a pixel. [Figure 48] Top view and cross-sectional view illustrating the display device. [Figure 49] Top view and cross-sectional view illustrating the display device. [Figure 50] A diagram illustrating the display module. [Figure 51] A perspective view showing the cross-sectional structure of a package using a lead frame type interposer, and a diagram showing the configuration of the module. [Figure 52] A diagram illustrating electronic devices. [Figure 53] A diagram illustrating electronic devices. [Figure 54] A diagram illustrating electronic devices. [Figure 55] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0032] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0033] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0034] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0035] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0036] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0037] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0038] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., X and Y are connected) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0039] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0040] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0041] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is , it does not have a second connection path, and the second connection path is the source of the transistor (or The path between the first terminal (or the second terminal, etc.) and the drain of the transistor. The first connection path described above is a path via Z1, and the drain (or second) of the transistor The terminals (such as) are electrically connected to Y via at least a third connection path, and the third The connection path does not have the second connection path described above, and the third connection path goes through Z2. It can be expressed as "the path that was used." Or, "the source of the transistor (or the first) The terminals (such as those of the ) are electrically connected to X via Z1 by at least a first connection path. Furthermore, the first connection path does not have a second connection path, and the second connection path does not have a second connection path. It has a connection path via a transistor, and the drain (or second terminal, etc.) of the transistor It is electrically connected to Y via Z2 by at least a third connection path, and the above This can be expressed as, "Connection path 3 does not have the second connection path described above." The source (or first terminal, etc.) of the transistor is connected to at least the first electrical path. Therefore, it is electrically connected to X via Z1, and the first electrical path is connected to the second electrical path. It does not have a path, and the second electrical path is the source (or first terminal) of the transistor. This is an electrical path from (etc.) to the drain (or second terminal, etc.) of the transistor. The drain of the inverter (or the second terminal, etc.) is connected by at least a third electrical path. Z2 is electrically connected to Y, and the above third electrical path has a fourth electrical path. It is not done, and the fourth electrical path described above is the drain of the transistor (or the second terminal, etc.) This is the electrical path from the source (or first terminal, etc.) of the transistor. It is possible to express the connection paths in the circuit configuration using similar methods to these examples. By defining it this way, the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between (for example, a second terminal) and other components.

[0042] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0043] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0044] <Notes regarding descriptions of drawings> In this specification, terms indicating placement, such as "above" and "below," refer to the positional relationship between components. These are used for convenience in explaining with reference to the drawings. Also, the positional relationships between the components are as follows: It changes appropriately depending on the direction in which the configuration is described. Therefore, the words described in the specification It is not limited and can be appropriately rephrased depending on the situation.

[0045] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and are in direct contact. It does not limit the meaning to what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be in direct contact with insulating layer A, but rather between insulating layer A and electrode B. This does not exclude those that include other components.

[0046] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0047] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0048] Furthermore, in the drawings, the size, layer thickness, or area is shown at an arbitrary size for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are intended to be clear. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings.

[0049] Furthermore, in drawings, such as top views (also called plan views or layout drawings) and perspective views, To ensure clarity in the drawings, some components may be omitted from the description.

[0050] Furthermore, "identical" means that they may have the same area or the same shape. The same height is acceptable in the direction perpendicular to the board surface. The same height can be rephrased as being on the same plane. Yes, it is possible. However, due to the manufacturing process, they will not be perfectly identical in shape, plane, or height. Since this is also a possibility, even if they are nearly identical, it can be rephrased as being identical.

[0051] <Notes regarding paraphrasable descriptions> In this specification and other documents, when describing the connection relationships of transistors, one of the source and drain This is referred to as "either the source or the drain" (or the first electrode, or the first terminal), and the source and The other side of the drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). It is noted that the source and drain of a transistor are related to the structure or operation of the transistor. This is because it varies depending on the conditions, etc. Regarding the terminology for the source and drain of a transistor... This can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the situation. It is possible to obtain it.

[0052] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0053] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain A channel between the region (or drain electrode) and the source (source terminal, source region, or source electrode). It has a channel region, and current can be passed through the drain, channel region and source. It is something that can be worn.

[0054] Here, the source and drain vary depending on the transistor's structure or operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. Let's refer to one of the source and drain as the first electrode, and the other of the source and drain as the second electrode. It may be written as such.

[0055] The ordinal numbers "1st," "2nd," and "3rd" used in this specification are intended to avoid confusion of constituent elements. This is added to avoid any misunderstanding and does not mean that the number is limited.

[0056] Furthermore, in this specification, the substrate of the display panel may be, for example, FPC (Flexible Printed Circuit). (Tracked Circuits) or TCP (Tape Carrier Pack) Items with ge) etc. attached, or COG (Chip On Glass) on the substrate In some cases, devices in which ICs (integrated circuits) are directly mounted are called display devices.

[0057] Furthermore, the words "membrane" and "layer" can be used interchangeably depending on the context or situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0058] <Notes regarding the definition of terms> The following sections will explain the definitions of each term used in this specification.

[0059] In this specification, when the terms "trench" or "groove" are used, they refer to a narrow, band-shaped recess. To say.

[0060] Furthermore, in this specification, when silicon oxide nitride is shown as the film, for example, SiOxNy and It may be stated. In this case, x and y may be natural numbers or numbers with decimal points. That's good too.

[0061] <About the connection> In this specification, "A and B are connected" means that A and B are not directly connected. This also includes things that are electrically connected. Here, A and B are electrically connected "Continued" means that there is an object between A and B that has some kind of electrical effect. This refers to a device that enables the exchange of electrical signals between A and B.

[0062] Furthermore, the content described in one embodiment (even a part of it) may vary depending on the form of its implementation. Other content (even partial content) described in the voice, and / or one or more other facts The content described in the form of implementation (even if only a part of it) may be applied, combined, or replaced. It is possible to perform tasks such as drawing.

[0063] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content stated, or the content stated using the text described in the specification.

[0064] Furthermore, a diagram (even a partial one) described in one embodiment may refer to another part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more In the diagram (or even just a part of it) described in another embodiment of the number, by combining them... This allows for the creation of even more diagrams.

[0065] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the same are described using drawings. explain.

[0066] Figures 1(A), 1(B), and 1(C) are top views of a transistor 10 according to one embodiment of the present invention. These are cross-sectional views. Figure 1(A) is a top view, and Figure 1(B) is a cross-sectional view of the dashed line shown in Figure 1(A). Figure 1(C) is a cross-sectional view between A1 and A2, and Figure 1(A) is a cross-sectional view between A3 and A4. Note that in Figure 1(A), the diagram is For clarity, some elements have been enlarged, reduced, or omitted in the illustration. Also, dashed lines are used. The direction from A1 to A2 is referred to as the channel length direction, and the direction from the dashed line A3 to A4 is referred to as the channel width direction. There are cases where this is the case.

[0067] The transistor 10 consists of a substrate 100, an insulating layer 110, an insulator 121, and a semiconductor layer 122 The insulator 123, the source electrode layer 130, the drain electrode layer 140, and the gate insulating layer 1 It has 50, a gate electrode layer 160, an insulating layer 175, an insulating layer 173, and an insulating layer 170. Transistor 10 has an insulating layer 110 on the substrate 100. The transistor 10 has an insulator 121 on the insulating layer 110. It has a body layer 122. The transistor 10 has a source electrode layer 130 on the semiconductor layer 122, It has a drain electrode layer 140 and is electrically connected to the semiconductor layer 122. Transistor 1 0 has an insulating layer 173, and the insulating layer 173 consists of an insulator 121, a semiconductor layer 122, and an insulator 12 3. The source electrode layer 130 has a region that is in contact with the side surface of the drain electrode layer 140. STA 10 has an insulating layer 173, a source electrode layer 130, and a drain electrode layer 140, on top of which is an insulating layer 17 5 is present, and the insulating layer 175 has a region in contact with the side surface of the insulator 123. Transistor 10 The semiconductor layer 122 has an insulator 123, and the insulator 123 is as shown in Figure 1(C), insulator 1 21. It has regions that are in contact with the sides of the insulating layer 173 and the insulating layer 175. Also, the insulator 12 3, as shown in Figure 1(B), is the lower surface of the insulating layer 170, the insulating layer 175, the source electrode layer 130, and The transistor 10 has a region that is in contact with the side surface of the drain electrode layer 140. 3 has a gate insulating layer 150 on top. Transistor 10 has a gate insulating layer 150 on top It has an electrode layer 160.

[0068] <About insulators> Note that insulators (for example, insulator 121, insulator 123) basically have insulating properties and are used in games. When the drain electric field or the t-field becomes stronger, a current flows near the interface with the semiconductor layer. This refers to the layer that is capable of doing so.

[0069] Furthermore, in the structure described above, the semiconductor layer 122 is the source electrode layer 130 and the drain electrode The region in contact with layer 140, and the insulator 123 are in contact with the source electrode layer 130 and the drain. Because it has a region in contact with the electrode layer 140, the insulator 121, It has the characteristic of having a high heat dissipation effect against heat generated within the semiconductor layer 122 and the insulator 123. ru.

[0070] Furthermore, when the transistor 10 forms the insulating layer 170, an insulating layer is formed at the interface with the insulating layer 175. The material of layer 175 and the material of insulating layer 170, or the gas used when forming the insulating layer 170, etc. A mixed layer is formed, and oxygen (excess oxygen, exO) is added to the mixed layer or insulating layer 175. Further heating treatment causes the oxygen to diffuse to the semiconductor layer 122, providing insulation. It is possible to replenish the oxygen deficiencies present in the body 121 and the semiconductor layer 122. This allows for improvements in transistor characteristics (e.g., threshold, reliability, etc.). Cut.

[0071] Furthermore, the excess oxygen added during the formation of the insulating layer 170 is obtained, for example, by sputtering. During film deposition, the applied voltage, power, plasma, or substrate temperature can affect oxygen radiation. It exists in various states, such as calcium, oxygen ions, or oxygen atoms. At this time, the excess oxygen This is a state that has more energy than the stable state, and penetrates into the insulating layer 175. It is possible.

[0072] Furthermore, the method of adding oxygen is not limited to the method described above, and any excess oxygen during the formation of the insulating layer 110 is not limited to this method. It may contain oxygen, or after film formation, another method (e.g., ion implantation, ion plasma immersion) may be used. You may use laws, etc.

[0073] Transistor 10 is channeled as shown in the cross-sectional view between the dashed line A3-A4 in Figure 1(C). In the width direction, the gate electrode layer 160 is connected to the insulator 121 via the gate insulating layer 150, and semicircular The conductor layer 122 faces the side surface of the insulator 123. That is, a voltage is applied to the gate electrode layer 160. Then, the insulator 121, semiconductor layer 122, and insulator 123 are connected in the channel width direction. The electrode layer 160 is surrounded by an electric field. The semiconductor layer 122 is surrounded by an electric field of the gate electrode layer 160. The structure of a transistor is called a surrounded channel (s-channel) l) This is called the structure. Also, transistor 10 has a self-aligned gate electrode layer using grooves. Since a source electrode layer and a drain electrode layer can be formed, the alignment accuracy is relaxed. This makes it possible to easily fabricate miniature transistors. Such a structure is called a self-aligned s-channel FET. s-channel FET, SA s-channel FET) structure, or trace Trench gate s-channel FET FET) structure, or TGSA s-channel FET (Trench Gat Self-Aligned FET (EFET) structure, or GLSA s-channel FET This is called a T (Gate Last Self Align FET) structure.

[0074] Here, the insulator 121, the semiconductor layer 122, and the insulator 123 together form the semiconductor layer 120. In the case of a TGSA structured transistor, in the ON state, the entire semiconductor layer 120 ( Because a channel is formed in the bulk, the on-current increases. On the other hand, in the off state, half Since the entire channel region formed in the conductor layer 120 can be depleted, off-electric The flow can be made even smaller.

[0075] Furthermore, because transistor 10 has a TGSA structure, the gate electrode and source electrode are connected. Alternatively, it reduces the parasitic capacitance that occurs between the gate electrode and the drain electrode, and the cutoff frequency of transistor 10. This improves the wavenumber characteristics and makes it possible to enable a high-speed response for transistor 10.

[0076] Furthermore, in this embodiment, as will be described later, the second insulating film which becomes the insulating layer 175 is the source electrode layer 130, After performing a planarization process until the drain electrode layer 140 is exposed, the insulating layer 173 and When forming the third insulating film, the upper surface of the insulating layer 173 and the source electrode layer 130 and It is preferable that the upper surface of the rain electrode layer 140 is on the same plane as the substrate surface. The insulating layer 173 on the source electrode layer 130 and drain electrode layer 140 is made uniform within the substrate surface. It is possible to create a film and stabilize the groove formation process (e.g., etching time, etc.). This allows for stable fabrication of transistor 10. This stabilizes the shape of the transistor and reduces variations in transistor characteristics. It can be suppressed.

[0077] Note that the position of the upper surface of the source electrode layer 130 or the drain electrode layer 140 is the gate electrode layer It can be lower than the base of 160, the same as it, or higher.

[0078] Furthermore, the upper surface of the gate electrode layer 160 of transistor 10 is lower than the upper surface of the insulating layer 175. It is also acceptable. In addition, the transistor 10 has a source electrode layer 130 and a drain electrode layer 14 0 may have a shape that is shorter than the semiconductor layer 122 in the channel length direction, or a longer shape It may have.

[0079] <Regarding channel length> Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the gate electrode overlaps with the part of the semiconductor through which current flows when the zistor is ON. , or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the other element. In a zista, the channel length is not necessarily the same across all regions. That is, one channel The channel length of a transistor may not be fixed to a single value. Therefore, in this specification... The channel length is one of the following values ​​in the region where the channel is formed: maximum value, minimum value. Alternatively, use the average value.

[0080] <Regarding channel width> Channel width refers to, for example, the channel width of a semiconductor (or transistor) when it is in the ON state. This refers to the length of the region where the current-carrying part and the gate electrode overlap. In a channel, the channel width is not necessarily the same across all regions. That is, in a channel, The channel width of an inverter may not be fixed to a single value. Therefore, in this specification, The channel width is any one value, maximum value, or minimum value within the region where the channel is formed. The result will be the average value.

[0081] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. There are cases where this occurs. For example, in transistors containing fine and three-dimensional channels, the semiconductor side In some cases, the proportion of channel regions formed on the surface may be large. In such cases, in the top view... The effective channel formed is actually greater than the apparent channel width shown. The width will be larger.

[0082] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0083] <SCWについて> Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel width in a region is called the "enclosure channel width (SCW: Surround)". It is sometimes referred to as "ded Channel Width." Also, in this specification, simply When "channel width" is mentioned, it refers to the enclosed channel width or the apparent channel width. In some cases, the term "channel width" may refer to the effective channel width. It can refer to channel width. Other terms include channel length, channel width, effective channel width, and apparent width. The channel width and enclosure channel width are determined by acquiring cross-sectional TEM images and then viewing those images. The value can be determined by analysis, etc.

[0084] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0085] <Improved performance through miniaturization> Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, and the channel width shrinks. Reducing the ON current decreases the ON current.

[0086] However, in the transistor according to one embodiment of the present invention shown in Figure 1, as described above, the channel An insulator 123 is formed so as to cover the semiconductor layer 122 on which the channel is formed, The stratified layer and the gate insulating layer are not in contact. Therefore, the channel forming layer and the gate insulating layer are not in contact. This can suppress carrier scattering at the interface with the marginal layer, thereby increasing the transistor's on-current. It is possible to hear.

[0087] Furthermore, in a transistor according to one aspect of the present invention, the channel width of the semiconductor layer 122 which forms the channel Because the gate electrode layer 160 is formed so as to electrically surround the direction, the semiconductor layer 12 For 2, in addition to the gate electric field from the vertical direction, a gate electric field from the lateral direction is applied. In other words, the gate electric field is applied to the entire semiconductor layer 122, and the current is transmitted to the semiconductor Because the current flows throughout the entire body layer 122, the ON current can be further increased.

[0088] Furthermore, in one aspect of the present invention, the transistor has an insulator 123, an insulator 121, and a semiconductor layer 122 Forming it on top has the effect of making it difficult to form interface states, and also positions the semiconductor layer 122 in the middle. By creating a layer, it also has the effect of eliminating the influence of impurities from above and below. Therefore, in addition to improving the on-current of the transistor as described above, it also stabilizes the threshold voltage and S The value (subthreshold coefficient) can be reduced. Therefore, Icut(G This allows for a reduction in power consumption by lowering the current (when the voltage VG is 0V). Furthermore, stabilizing the transistor threshold voltage improves the long-term reliability of semiconductor devices. It can be raised.

[0089] In this embodiment, in the channel, the semiconductor layer 120 (semiconductor layer 122 Examples using the above have been shown, but one embodiment of the present invention is not limited thereto. For example, the channel and its vicinity, the source region, the drain region, etc., may be used in some cases. Alternatively, depending on the situation, it may be formed of a material having silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. ium, or the like. It may be formed of a material having silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like.

[0090] <Configuration of Transistor> The configuration of the transistor of the present embodiment is shown below.

[0091] <<Substrate 100>> For the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Also, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon n On Insulator) substrate, or the like can also be used, and a substrate having a semiconductor element provided thereon may be used. The substrate 100 is not limited to a mere support material, and may be a substrate on which other devices such as other transistors are formed. In this case, at least one of the gate electrode layer 160, the source electrode layer 130, and the drain electrode layer 140 of the transistor may be electrically connected to the above other devices. Further, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a woven sheet, a film, or a foil incorporating fibers may also be used. Further, the substrate 100 may have stretchability

[0092] Also, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a woven sheet, a film, or a foil incorporating fibers may also be used. Further, the substrate 100 may have stretchability substrate and the transistor. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a woven sheet, a film, or a foil incorporating fibers may also be used. Further, the substrate 100 may have stretchability It is also possible to return the substrate 100 to its original shape when bending or pulling is stopped. It may have a quality. Or it may have the property of not returning to its original shape. Thickness of substrate 100 For example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and further Preferably, the thickness is 15 μm or more and 300 μm or less. When the substrate 100 is thinned, the semiconductor device This makes it possible to reduce the weight. Also, by making the substrate 100 thinner, it becomes possible to use glass and other materials. In addition, it may also have elasticity, or it may have the property of returning to its original shape when bent or pulled. This may occur. Therefore, impacts applied to the semiconductor device on the substrate 100 due to dropping, etc. This can alleviate issues such as those mentioned above. In other words, it is possible to provide robust semiconductor devices.

[0093] The flexible substrate 100 can be, for example, a metal, an alloy, a resin, or a glass, These fibers can be used. The substrate 100, which is a flexible substrate, has a coefficient of linear expansion. A lower value is preferable as it suppresses deformation due to the environment. The flexible substrate 100 is: For example, the coefficient of thermal expansion is 1 × 10⁻⁶. -3 / K or less, 5×10 -5 / K or less, or 1 × 10 -5 Any material with a K value of 0.5 or less should be used. Examples of resins include polyester and polyolefin. Polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic Examples include polytetrafluoroethylene (PTFE). In particular, aramid has a high coefficient of thermal expansion. Because of its low coefficient of variation, it is suitable as a flexible substrate, substrate 100.

[0094] Insulating layer 110 The insulating layer 110 has the role of preventing the diffusion of impurities from the substrate 100, as well as the semiconductor layer It can play a role in supplying oxygen to layer 120 (semiconductor layer 122). Therefore, it provides insulation. Layer 110 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. It is more preferable that it be an insulating film. For example, oxygen emission in terms of oxygen atoms by the TDS method Discharge volume 1.0 × 10 19 The membrane should have a density of atoms / cm³ or higher. Note that the above TDS analysis... The surface temperature of the film at that time is between 100°C and 700°C, or between 100°C and 500°C. A range of °C or lower is preferred. Also, as described above, the substrate 100 is a base on which other devices are formed. If it is a plate, the insulating layer 110 also functions as an interlayer insulating film. In that case, the surface is To make it flat, CMP (Chemical Mechanical Polishing) It is preferable to perform a planarization treatment using method g) or the like.

[0095] 《Insulators 121, 123, Semiconductor layer 122》 The oxides that can be used as insulator 121, semiconductor layer 122, and insulator 123 are Preferably, it contains at least indium (In) or zinc (Zn). Or, It is preferable that the oxide contains both In and Zn. Furthermore, transients using the oxide as a semiconductor To reduce variations in the electrical characteristics of the stabilizers, it is preferable to include stabilizers along with them. Typical examples include In-Ga oxide, In-Zn oxide, In-Mg oxide, and Zn- Mg oxide, In-M-Zn oxide (where M is Al, Ti, Ga, Y, Zr, Sn, La, C) (e, Mg, or Nd) are present.

[0096] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Examples include aluminum (Al) or zirconium (Zr). Also, other stabilizers... include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium ( Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like. .

[0097] When the insulator 123 is an In-M-Zn oxide, the atomic ratio of In to M when the sum of In and M is 100 at omic% is preferably such that In is 25 atomic % or more and M is less than 75 atomic%, and more preferably, In is 34 atomic % or more and M is less than 66 atomic%.

[0098] The content of indium, gallium, etc. in the insulator 123 can be compared by time-of-flight secondary ion mass spectrometry (TOF-SIMS), X-ray photoelectron spectroscopy (XPS), or ICP mass spectrometry (ICP-MS ).

[0099] Since the semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, the off-current of the transistor 10 can be reduced. .

[0100] The thickness of the semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0101] The insulator 121 and the insulator 123 are oxide films composed of one or more of the elements constituting the semiconductor layer 122. Therefore, the semiconductor layer 122 and the insulator 121, and the insulator 12 3 are made of the same material, which can improve the interface characteristics between the semiconductor layer 122 and the insulator 121, and the insulator 12 At the interface with 3, interfacial scattering is unlikely to occur. Therefore, the movement of carriers at this interface Because the field effect is not inhibited, the field-effect mobility of transistor 10 increases.

[0102] Insulators 121 and 123 are typically In-Ga oxide, In-Zn oxide, and I n-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn oxide (where M is A) (I, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) and semiconductor The energy level at the lower end of the conduction band is closer to the vacuum level than that of layer 122, and typically, insulator 12 1. The energy level at the lower end of the conduction band of the insulator 123 and the energy at the lower end of the conduction band of the semiconductor layer 122 The difference from the energy level is 0.05 eV or greater, 0.07 eV or greater, 0.1 eV or greater, or 0. 0.2eV or higher, and 2eV or lower, 1eV or lower, 0.5eV or lower, or 0.4eV or lower Yes. That is, the electron affinity of insulators 121 and 123 and the electron affinity with semiconductor layer 122. The difference from the force is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV. The values ​​are above 2eV, below 1eV, below 0.5eV, or below 0.4eV. Oh, electron affinity indicates the difference between the vacuum level and the energy level at the bottom of the conduction band.

[0103] Insulators 121 and 123 are Al, Ti, Ga, Y, Zr, Sn, La, Ce, Having Mg or Nd in a higher atomic ratio than In may have the following effects: (1) The energy gap between the insulator 121, the semiconductor layer 122, and the insulator 123 (2) Make it larger. (3) Make the electron affinity of insulator 121 and insulator 123 smaller. (4) External (4) It shields against impurities from the semiconductor layer 122. (5) It has higher insulating properties compared to the semiconductor layer 122. Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd have a strong bond with oxygen. Because it is a strong metallic element, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Alternatively, having Nd in a higher atomic ratio than In makes oxygen deficiency less likely to occur.

[0104] Furthermore, since insulators 121 and 123 have higher insulating properties compared to semiconductor layer 122, It has the same function as an insulating layer.

[0105] When insulators 121 and 123 are In-M-Zn oxides, except for Zn and O The atomic ratio of In and M is preferably less than 50 atomic% for In and 50 atomic% for M. Atomic% or more, more preferably In is less than 25 atomic%, and M is 75 at The omic% must be greater than or equal to 0%.

[0106] Furthermore, insulators 121 and 123 are In-M-Zn oxide (where M is Al, Ti, Ga, Y). In the case of semiconductor layers 122 (Zr, Sn, La, Ce, Mg, or Nd), compared to semiconductor layer 122, The marginal material 121 and the insulator 123 contain M(Al, Ti, Ga, Y, Zr, Sn, La, C) The atomic ratio of e, Mg, or Nd is high, and typically the above is contained in semiconductor layer 122. Compared to an atom, the original material is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more high. This is the ratio of the number of atoms. The element represented by M above bonds more strongly with oxygen than indium, therefore oxygen It has the function of suppressing the occurrence of defects in the insulator 121 and insulator 123. That is, the insulator 121. The insulator 123 is an oxide film that is less prone to oxygen vacancies than the semiconductor layer 122.

[0107] Furthermore, the semiconductor layer 122 has a higher indium content than the insulators 121 and 123. It would be good to do so. In semiconductors, the s orbitals of heavy metals are the main contributors to carrier conduction. By increasing the In content, more s orbitals overlap, so In is more abundant than M. Oxides with a certain composition have higher mobility compared to oxides with a composition where In is equal to or less than M. The cost increases. Therefore, by using an oxide with a high indium content in the semiconductor layer 122, This makes it possible to realize transistors with high field-effect mobility.

[0108] Furthermore, the semiconductor layer 122 is made of In-M-Zn oxide (where M is Al, Ti, Ga, Y, Zr, S In the case of n, La, Ce, Mg, or Nd, the type used to form the semiconductor layer 122 is In a GET, if the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1, x1 / y1 is between 1 / 3 and 6, and moreover, between 1 and 6, and z1 / y1 is 1 / It is preferable that z1 / y1 be between 3 and 6, and more preferably between 1 and 6. By setting it to 6 or less, the semiconductor layer 122 is CAAC-OS (C Axis Align A film of ed Crystalline Oxide Semiconductor is formed. It becomes easier to remove. A typical example of the atomic ratio of the target metal elements is In:M:Zn=1 :1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2 Examples include 4:2:3 and 4:2:4.1.

[0109] Furthermore, insulators 121 and 123 are In-M-Zn oxide (where M is Al, Ti, Ga, For Y, Zr, Sn, La, Ce, Mg, or Nd, insulator 121, insulator 123 In a target used to deposit a thin film, the atomic ratio of metal elements is set to In:M:Zn=x Assuming 2:y2:z2, x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more 6 or less, more preferably 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less it becomes easier to form the CAAC-OS film as the insulator 121 and the insulator 123. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4:5, 1:4:6, 1:4: 7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1:5:8, 1:6:8, 1: 6:4, 1:9:6, etc. Note that the atomic ratio of the insulator 121 and the insulator 123 includes fluctuations of plus or minus 40% of the above atomic ratio as an error, respectively.

[0110] Note that the atomic ratio is not limited to these, and appropriate atomic ratios can be used according to the required semiconductor characteristics.

[0111] In addition, the insulator 123 can be replaced with a metal oxide, such as aluminum oxide (AlOx), gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), germanium oxide (GeOx), or zirconia (ZrOx), or the metal oxide can be provided on the insulator 123.

[0112] Note that the atomic ratio is not limited to these, and appropriate atomic ratios can be used according to the required semiconductor characteristics.

[0113] In addition, the insulator 121 and the insulator 123 may have the same composition. For example, as the insulator 121 and the insulator 123, an In-Ga-Zn oxide with an atomic ratio of the metal elements of the target used in the sputtering method of In:Ga :Zn = 1:3:2, 1:3:4, or 1:4:5 may be used.

[0114] Alternatively, insulators 121 and 123 may have different compositions. For example, insulator 121 and Therefore, the atomic ratio of the metal elements in the target used in the sputtering method is In:Ga:Zn= Using a 1:3:4 In-Ga-Zn oxide, the target metal element is used as insulator 123. In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2 may also be used.

[0115] The thickness of the insulator 121, semiconductor layer 122, and insulator 123 is 3 nm to 100 nm. It is preferable to have a wavelength of 3 nm or more and 50 nm or less.

[0116] Here, even if the thickness of the semiconductor layer 122 is formed to be thinner than that of the insulator 121 It is fine, it is fine to keep it the same, or it may be formed thicker. For example, the semiconductor layer 122 may be made thicker. In this case, the on-current of the transistor can be increased. Also, the insulator 121 is a semiconductor The thickness should be such that the effect of suppressing the formation of interface states in layer 122 is not lost. The thickness of the semiconductor layer 122 is greater than 1 times the thickness of the insulator 121, or 2 times. It can be more than double, or more than four times, or more than six times. Also, the transistor If it is not necessary to increase the current, the thickness of the insulator 121 shall be greater than or equal to the thickness of the semiconductor layer 122. This may also be the case. For example, insulating layer 110, insulating layer 170, insulating layer 173, or insulating layer 175 If the material contains an excess of oxygen, the heat treatment will cause the oxygen to diffuse and be incorporated into the semiconductor layer 122. This can reduce the amount of oxygen deficiency and stabilize the electrical characteristics of semiconductor devices.

[0117] Furthermore, the insulator 123, like the insulator 121, suppresses the generation of interface states in the semiconductor layer 122. The thickness should be such that the effect is not lost. For example, the thickness should be equivalent to or greater than that of insulator 121. The thickness shown below is appropriate. If the insulator 123 is thick, the electric field due to the gate electrode layer 160 will be a semiconductor. It is preferable to form the insulator 123 thinly, as this may make it difficult to reach layer 122. Furthermore, the oxygen contained in the insulator 123 spreads to the source electrode layer 130 and the drain electrode layer 140. To prevent oxidation of the source electrode layer 130 and the drain electrode layer 140, an insulator 12 A thinner film thickness is preferable for layer 3. For example, the insulator 123 should be thinner than the thickness of the semiconductor layer 122. This is sufficient. However, this is not limited to this, and the thickness of the insulator 123 should be such that the gate insulating layer 150 withstands pressure. Considering this, you should set it appropriately according to the voltage used to drive the transistor.

[0118] If the compositions of the insulator 121, semiconductor layer 122, and insulator 123 are different, The surface is a scanning transmission electron microscope (STEM). In some cases, observation can be performed using an electron microscope.

[0119] <Regarding hydrogen concentration> The hydrogen contained in the insulator 121, the semiconductor layer 122, and the insulator 123 is bonded with the metal atoms. It reacts with oxygen to form water, and at the same time, the lattice (or the part from which oxygen has been removed) from which oxygen has been removed An oxygen vacancy is formed. When hydrogen enters this oxygen vacancy, electrons, which are carriers, are generated. In some cases, this can occur. Also, when some of the hydrogen combines with oxygen that is bonded to a metal atom, carriers In some cases, electrons are generated. Therefore, oxides containing hydrogen can be used as semiconductors. The transistor used tends to exhibit normally-on characteristics.

[0120] Therefore, it is preferable that hydrogen is reduced as much as possible together with oxygen deficiency at the insulator 121, the semiconductor layer 122, the insulator 123, and each interface. For example, at the insulator 121, the semiconductor layer 122, the insulator 123, and each interface, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry ) is 1×10 atoms / cm 16 or more and 2×10 3 atoms / cm 20 or less, preferably 1×10 atoms / cm 3 or more and 5×10 16 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm or less, still more preferably 1×10 3 atoms / cm 16 or more and 1×10 3 atoms / cm 19 or less, even more preferably 1×10 atoms / cm 3 or more and 5×10 16 atoms / cm 3 or less, and most preferably 1×10 18 atoms / cm 3 or less. As a result, the transistor 10 can have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

[0121] <Regarding carbon and silicon concentrations> In addition, when silicon or carbon, which is one of the Group 14 elements, is contained at the insulator 121, the semiconductor layer 122, the insulator 123, and each interface, oxygen deficiency increases in the insulator 121, the semiconductor layer 122 and the insulator 123, and an n-type region is formed. Therefore, the silicon at the insulator 121, the semiconductor layer 122, the insulator 123, and each interface It is desirable to reduce the concentration of condensate and carbon. For example, insulator 121, semiconductor layer 1 22, insulator 123, and silicon obtained by SIMS at each interface The carbon concentration is 1 × 10⁻⁶ 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 Below Below, preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 Below Below, more preferably 1 × 10 16 atoms / cm 3 The above 2 x 10 18 ate / c m 3 The following is preferable. As a result, the threshold voltage of transistor 10 is positive. It has the following electrical characteristics (also called normally-off characteristics).

[0122] <Regarding the concentration of alkali metals or alkaline earth metals> Furthermore, alkali metals and alkaline earth metals generate carriers when they combine with oxides. In some cases, the transistor's off-current may increase. Therefore, insulator 1 21, semiconductor layer 122, insulator 123, and alkali metal at their respective interfaces It is preferable to reduce the concentration of alkaline earth metals. For example, insulator 121, semiconductor At layer 122, insulator 123, and their respective interfaces, aluminum obtained by SIMS The concentration of potassium metal or alkaline earth metal is 1 × 10⁻⁶ 18 atoms / cm 3 The following are preferred Or 2 x 10 16 atoms / cm 3 The following is preferable. As a result, STA10 has an electrical characteristic where the threshold voltage is positive (also called a normally-off characteristic). To possess.

[0123] <Regarding nitrogen concentration> Furthermore, nitrogen is contained in the insulator 121, the semiconductor layer 122, the insulator 123, and their respective interfaces. When this occurs, electrons, which act as carriers, are generated, increasing the carrier density and forming an n-type region. As a result, transistors using nitrogen-containing oxides are normally-on. This is likely to result in a characteristic. Therefore, the insulator 121, semiconductor layer 122, insulator 123 and each At this interface, it is preferable that nitrogen is reduced as much as possible, for example, insulator 1 21, semiconductor layer 122, insulator 123, and obtained by SIMS at their respective interfaces The nitrogen concentration that can be achieved is 1 × 10⁻⁶ 15 atoms / cm 3 The above 5 x 10 19 atoms / cm 3 The following is preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 More preferably 1 × 10 15 atoms / cm 3 The above 1 x 10 18 atom / cm 3 More preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 17 ato ms / cm 3 The following is preferable. As a result, transistor 10 has a threshold voltage It has an electrical characteristic where it is positive (also called a normally-off characteristic).

[0124] <About carrier density> By reducing impurities in the insulator 121, semiconductor layer 122, and insulator 123, the insulator The carrier density of 121, the semiconductor layer 122, and the insulator 123 can be reduced. Therefore, the insulator 121, the semiconductor layer 122, and the insulator 123 have a carrier density of 1 × 10 15 pieces / cm 3 The following is preferably 1 × 10 13 pieces / cm 3 More preferably, 8 ×10 11 pieces / cm 3 Less than 1 × 10 11 pieces / cm 3 Less than, most preferably is 1 x 10 10 pieces / cm 3 It is less than 1 × 10 -9 pieces / cm 3 That concludes this section.

[0125] The insulator 121, semiconductor layer 122, and insulator 123 have low impurity concentrations and defect levels. By using oxide films with low photon density, transistors with even better electrical properties can be created. It can be manufactured in a way that has a low impurity concentration and a low defect level density (low oxygen deficiency). The term "high-purity intrinsic" or "substantially high-purity intrinsic" refers to a substance that is (not) intrinsic or substantially high-purity intrinsic. Intrinsic purity oxides have few carrier sources, thus lowering the carrier density. In some cases, this is possible. Therefore, a transistor in which a channel region is formed on the oxide film is The electrical characteristics (also known as normally-off characteristics) tend to result in a positive threshold voltage. Furthermore, oxide films that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density. Furthermore, the trap level density may also be low. Transistors using oxide films have a remarkably low off-current, and the source electrode and drain When the voltage between the in-electrode (drain voltage) is in the range of 1V to 10V, the off-current is semiconductor Below the measurement limit of the body parameter analyzer, i.e., 1 × 10⁻⁶ -13 It acquires the characteristic of being A or less. Therefore, a transistor in which a channel region is formed in the oxide film can be electrically powered. This can result in transistors with small variations in atmospheric characteristics and thus high reliability.

[0126] Furthermore, as mentioned above, transistors using a highly purified oxide film in the channel formation region The off-current is extremely small. For example, if the voltage between the source and drain is 0.1V, 5V, Alternatively, if the voltage is around 10V, the off-current normalized by the transistor's channel width is several y It is possible to reduce the level to A / μm or even a few zA / μm.

[0127] The insulator 121, the semiconductor layer 122, and the insulator 123 may, for example, have a non-single crystal structure. Non-single-crystal structures include, for example, CAAC-OS, polycrystalline structures, microcrystalline structures, or non- It includes a crystalline structure. In non-single crystal structures, the amorphous structure has the highest defect level density, CAA C-OS has the lowest defect level density.

[0128] The insulator 121, the semiconductor layer 122, and the insulator 123 may, for example, have a microcrystalline structure. The crystalline insulator 121, semiconductor layer 122, and insulator 123 are, for example, 1 nm or larger. The film contains microcrystals smaller than 10 nm in size. Alternatively, an oxide film with a microcrystalline structure is, for example, It has a multiphase structure in which an amorphous phase has crystalline portions of 1 nm to less than 10 nm.

[0129] The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, an amorphous structure. The crystalline structure of the insulator 121, semiconductor layer 122, and insulator 123 is, for example, an atomic arrangement It is disordered and does not contain crystalline components. Or, an amorphous oxide film is, for example, perfectly It has an amorphous structure and does not contain crystalline parts.

[0130] Furthermore, the insulator 121, semiconductor layer 122, and insulator 123 are CAAC-OS, microcrystals. The mixed film may have regions of two or more structures, including a structure and an amorphous structure. For example, the amorphous region, the microcrystalline region, and the CAAC-OS region It has a monolayer structure. Alternatively, as a mixed film, for example, a region of amorphous structure and a microcrystalline structure There is a layered structure consisting of the fabrication region and the CAAC-OS region.

[0131] The insulator 121, semiconductor layer 122, and insulator 123 may, for example, have a single crystal structure. You may do so.

[0132] An oxide film, which is less prone to oxygen vacancies compared to the semiconductor layer 122, is placed in contact with the top and bottom of the semiconductor layer 122. By providing this, oxygen vacancies in the semiconductor layer 122 can be reduced. The body layer 122 is an insulator 121 having one or more metal elements that constitute the semiconductor layer 122, insulating Because it is in contact with body 123, the interface between the insulator 121 and the semiconductor layer 122, and the semiconductor layer 122 and the insulator The interface state density at the interface with body 123 is extremely low. For example, oxygen is added to the insulating layer 110. After adding the oxygen, a heat treatment is performed, which allows the oxygen to pass through the insulator 121 to the semiconductor layer 122. Although it moves, oxygen is less likely to be captured at the interface level at this time, and the insulator 12 It is possible to move the oxygen contained in 1 to the semiconductor layer 122. As a result, the semiconductor layer It is possible to reduce the oxygen deficiency contained in 122. Also, oxygen is present in the insulator 121. Because it is added, it is possible to reduce the oxygen deficiency of the insulator 121. That is, at least This also reduces the localized energy level density of the semiconductor layer 122.

[0133] Furthermore, the semiconductor layer 122 is an insulating film with different constituent elements (for example, a silicon oxide film). When in contact with an insulating layer, an interface state is formed, and this interface state forms a channel. Yes. In such cases, a second transistor with a different threshold voltage appears, and the transistor The apparent threshold voltage of the terminal may fluctuate. However, the semiconductor layer 122 is constructed Insulators 121 and 123, each containing one or more metallic elements, are in contact with the semiconductor layer 122. Therefore, the interface between the insulator 121 and the semiconductor layer 122, and the interface between the insulator 123 and the semiconductor layer 122 It becomes more difficult to form interface states at the interface.

[0134] Furthermore, the insulator 121 and the insulator 123 are composed of an insulating layer 110 and a gate insulating layer 150, respectively. To suppress the mixing of elemental compounds into the semiconductor layer 122 and the formation of energy levels due to impurities. It also functions as a barrier film.

[0135] For example, an insulating film containing silicon may be used as the insulating layer 110 or the gate insulating layer 150. In this case, the silicon in the gate insulating layer 150, or the insulating layer 110 and the gate insulating layer 150 The carbon that may be mixed in may enter the insulator 121 or insulator 123 from the interface to a distance of a few nanometers. This can occur when impurities such as silicon and carbon enter the semiconductor layer 122. It can become n-type by forming a position, and the impurity level acting as a donor to generate electrons.

[0136] However, if the film thickness of insulator 121 and insulator 123 is thicker than a few nanometers, the impurities will be present. Since impurities such as silicon and carbon do not reach semiconductor layer 122, the influence of impurity levels is It will be reduced.

[0137] Therefore, by providing insulators 121 and 123, the threshold voltage of the transistor is This can reduce variations in electrical characteristics such as those mentioned above.

[0138] Furthermore, the gate insulating layer 150 and the semiconductor layer 122 are in contact, and a channel is formed at their interface. In this case, interfacial scattering occurs at the interface, and the field-effect mobility of the transistor decreases. However, However, the insulators 121 and 123 that constitute the semiconductor layer 122 contain one or more metal elements. Since it is provided in contact with the semiconductor layer 122, the semiconductor layer 122 and the insulator 121 and insulator 123 Carrier scattering is less likely to occur at the interface, increasing the field-effect mobility of the transistor. It is possible.

[0139] In this embodiment, the amount of oxygen vacancies in the semiconductor layer 122, and furthermore, the amount of oxygen vacancies in contact with the semiconductor layer 122 It is possible to reduce the amount of oxygen deficiency in the insulators 121 and 123, and the semiconductor layer 12 The localized level density of 2 can be reduced. As a result, the transistor shown in this embodiment 10 can have characteristics that result in little fluctuation in the threshold voltage and high reliability. Also, The transistor 10 shown in this embodiment has excellent electrical characteristics.

[0140] Furthermore, silicon-containing insulating films are often used as the gate insulating layer of transistors. Therefore, for the reasons stated above, the region that becomes the channel of the oxide layer is the transistor of one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating layer is preferable. When a channel is formed at the interface between the oxide layer and the ion, carrier scattering occurs at the interface, The field-effect mobility of the transistor may decrease. From this perspective, the oxide layer It is preferable to keep the channel region separate from the gate insulating layer.

[0141] Therefore, the semiconductor layer 120 is a laminated structure of insulator 121, semiconductor layer 122, and insulator 123. By doing so, channels can be formed in the semiconductor layer 122, resulting in high field-effect mobility. This allows for the formation of transistors with stable electrical characteristics.

[0142] Furthermore, the semiconductor layer does not necessarily have to be three layers; it can be single-layer, double-layer, quadruple-layer, or even five or more layers. This configuration may also be used. When a single layer is used, it corresponds to the semiconductor layer 122 shown in this embodiment. You can use layers.

[0143] <Band Diagram> Now, let's explain the band diagram. For ease of understanding, the band diagram shows the insulating layer 110. Lower end of the conduction band of the insulator 121, semiconductor layer 122, insulator 123, and gate insulating layer 150 This shows the energy (Ec).

[0144] As shown in Figures 3(A) and 3(B), the insulator 121, semiconductor layer 122, and insulator 123 In this configuration, the energy at the lower end of the conduction band changes continuously. This is due to the insulator 121 and the semiconductor layer. Because the elements constituting 122 and the insulator 123 are common, oxygen can easily diffuse between them. This can also be understood from this point. Therefore, the composition of the insulator 121, semiconductor layer 122, and insulator 123 is Although it is a laminate of different films, it can be said to be physically continuous.

[0145] The oxide films, which are stacked with a common main component, are not simply stacked layers but are continuously bonded ( In particular, the energy at the lower end of the conduction band changes continuously between each layer in a U-shaped well (US Fabricate the layers so that a hape well structure is formed. That is, a trap is formed at the interface of each layer. The stacking process is designed to prevent the formation of defect levels such as hop centers and recombination centers by avoiding impurities. It forms a structure. If impurities are mixed between the layers of a stacked multilayer film, energy The continuity of the band is lost, and carriers disappear at the interface due to trapping or recombination. cormorant.

[0146] Note that Figure 3(B) shows the case where the Ec of insulator 121 and insulator 123 are the same. As shown, they may be different from each other.

[0147] From Figure 3(B), the semiconductor layer 122 becomes a well, and in transistor 10, It can be seen that a channel is formed in the semiconductor layer 122. Note that the semiconductor layer 122 is the bottom. A channel with a U-shaped well structure where the energy at the lower end of the conduction band changes continuously is embedded. You could also call it Nell.

[0148] Furthermore, near the interface between the insulator 121 and the insulator 123 and the insulating film such as the silicon oxide film Insulator 121, Insulator 123 This allows the semiconductor layer 122 to be kept away from the trap level. The energy difference between the Ec of insulator 121 or insulator 123 and the Ec of semiconductor layer 122. If the difference is small, electrons in semiconductor layer 122 will exceed the energy difference and reach the trap level. This can happen. Electrons that become negatively charged are trapped in trap levels at the insulating film interface. A negative fixed charge is generated, and the transistor's threshold voltage shifts in the positive direction. Furthermore, in long-term storage tests of transistors, the traps were not fixed, affecting the characteristics. There are concerns that this could cause fluctuations.

[0149] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, insulator 121, and It is necessary to create an energy difference between the Ec of the insulator 123 and the Ec of the semiconductor layer 122. The energy difference in each case is preferably 0.1 eV or more, and preferably 0.2 eV or more. More preferable.

[0150] Furthermore, it is preferable that the insulator 121, semiconductor layer 122, and insulator 123 include crystalline portions. In particular, using crystals oriented along the c-axis provides transistors with stable electrical characteristics. It is possible.

[0151] Furthermore, in the band diagram shown in Figure 3(B), if the insulator 123 is not provided, the semiconductor layer 12 Between 2 and the gate insulating layer 150 is an In-Ga oxide (for example, with an atomic ratio of In:Ga = 7 A 93 In-Ga oxide may be provided, or gallium oxide may be provided. Furthermore, with the insulator 123 present, an In-Ga layer is placed between the insulator 123 and the gate insulating layer 150. An oxide may be provided, or gallium oxide may be provided.

[0152] The semiconductor layer 122 is an oxide with a higher electron affinity than the insulators 121 and 123. For example, the semiconductor layer 122 is made of electrons that are more electron-rich than the insulators 121 and 123. The affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. More preferably, oxides with a higher emission factor of 0.2 eV or more and 0.4 eV or less can be used.

[0153] The transistor shown in this embodiment contains one or more metal elements that constitute the semiconductor layer 122. Because it has insulators 121 and 123, the insulator 121 and semiconductor layer 122 This makes it difficult to form interface states at the interface between the insulator 123 and the semiconductor layer 122. Therefore, by providing insulators 121 and 123, the threshold voltage of the transistor is This can reduce variations and fluctuations in any electrical characteristic.

[0154] Source electrode layer 130, drain electrode layer 140 The source electrode layer 130 and the drain electrode layer 140 contain copper (Cu), tungsten (W), and mo Ribdenum (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (T) i) Tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn) Iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (I r), elements or alloys made of materials such as strontium (Sr), or these A single or multilayer conductive layer containing compounds such as oxygen, nitrogen, fluorine, and silicon as its main components. It is preferable to form a layer. For example, when stacking, the lower guide that contacts the semiconductor layer 122 The electrical layer has a material that readily bonds with oxygen, and the upper conductive layer has a material that is highly resistant to oxidation. This is possible. In addition, high-melting-point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity. It is preferable to use materials. Alternatively, it may be formed from low-resistance conductive materials such as aluminum or copper. This is preferable. Furthermore, if a Cu-Mn alloy is used, oxidation occurs at the interface with the oxygen-containing insulator. It is preferable because it forms manganese, and manganese oxide has the function of suppressing the diffusion of Cu. When tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen (barrier properties), and Tantalum nitride itself is preferable because it has the effect of being resistant to oxidation.

[0155] Furthermore, when a conductive material that readily combines with oxygen is brought into contact with an oxide semiconductor layer, in the oxide semiconductor layer A phenomenon occurs where oxygen diffuses towards the conductive material side, which readily combines with oxygen. - Oxygen deficiency occurs in the region in contact with the electrode layer or drain electrode layer, resulting in a small amount of oxygen in the film. The hydrogen contained in the region enters the oxygen vacancy, causing that region to become significantly n-type. Therefore, the n-type region is made to act as the source or drain of the transistor. It is possible.

[0156] For example, a laminated structure using W as the lower conductive layer and Pt as the upper conductive layer This process converts the contacted oxide semiconductor to n-type while simultaneously providing conductivity through contact with the insulating layer 175. This can suppress oxidation of the electrolytic layer.

[0157] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), and aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) It may contain hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide. (SiOx), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy) Silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx) ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide ( An insulating film containing one or more types of TaOx can be used. Also, the gate insulating layer 150 is The materials may be laminated. In addition, the gate insulating layer 150 may contain lanthanum (La), nitrogen, It may contain impurities such as zirconium (Zr).

[0158] Furthermore, an example of the laminated structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide. , and preferably containing silicon oxide or silicon oxide nitride.

[0159] Hafnium oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Therefore Therefore, compared to the case where silicon oxide is used, the thickness of the gate insulating layer 150 can be increased. This reduces the leakage current due to tunnel current. In other words, a tunnel with a small off-current Rangista can be realized. Furthermore, hafnium oxide having a crystalline structure is amorphous. It has a higher dielectric constant compared to hafnium oxide, which has a crystalline structure. Therefore, the off-current To create small transistors, it is preferable to use hafnium oxide, which has a crystalline structure. It is so. Examples of crystal structures include monoclinic and cubic systems. However, this invention This is not limited to these aspects.

[0160] Incidentally, the surface of hafnium oxide having a crystalline structure has interface states due to defects. This may occur. The interface level may function as a trap center. Therefore, When hafnium oxide is placed in close proximity to the channel region of a transistor, the interface levels Therefore, the electrical characteristics of the transistor may deteriorate. To reduce the influence of the interface state, To achieve this, another film is placed between the transistor's channel region and the hafnium oxide. It is sometimes preferable to separate them from each other by doing so. This membrane has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or an oxide semiconductor. It may also be a film included in the conductive film. That is, the film having a buffering function may be silicon oxide. Silicon oxide nitride, oxide semiconductors, etc., can be used. The film contains, for example, a semiconductor with a larger energy gap than the semiconductor that forms the channel region. Alternatively, an insulator may be used. Or, a film having a buffering function may have, for example, a channel region. A semiconductor or insulator with lower electron affinity than the semiconductor is used. Alternatively, a semiconductor with a buffering function is used. For example, the film may have a semiconductor with a higher ionization energy than the semiconductor that forms the channel region. Use a conductor or an insulator.

[0161] On the other hand, the interface state (trap) on the surface of hafnium oxide having the above-described crystal structure By trapping charge at the center, the threshold voltage of the transistor can be controlled. There is a combination. In order to keep the charge stable, for example, the channel region and the hafny oxide If you place an insulator with a larger energy gap than hafnium oxide between the um and the other material... Alternatively, if a semiconductor or insulator with a lower electron affinity than hafnium oxide is placed in the environment, Good. Alternatively, for films with buffering properties, a higher ionization energy than hafnium oxide is used. A semiconductor or insulator can be placed. By using such an insulator, the interface state This makes it less likely for trapped charges to be released, and allows the charge to be retained for a long period of time. can.

[0162] Examples of such insulators include silicon oxide and silicon oxide-nitride. In order to trap charge in the interface state within the insulating layer 150, the gate charge must be removed from the oxide semiconductor film. The electrons should be moved toward the polar layer 160. A specific example would be at a high temperature (for example) Under temperatures between 125°C and 450°C (typically between 150°C and 300°C), the gate electric current is used. The potential of the polar layer 160 is higher than the potential of the source electrode layer 130 and the drain electrode layer 140. You just need to maintain it for more than one second, or more typically, more than one minute.

[0163] In this way, a desired amount of electrons is trapped in the interface state such as the gate insulating layer 150. The threshold voltage shifts to the positive side. The voltage of the gate electrode layer 160, or the applied voltage... By adjusting the timing, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. This is possible. Furthermore, if charge can be captured, within the gate insulating layer 150 It is not necessary. A laminated film with a similar structure may be used for other insulating layers.

[0164] 《Gate Entry Layer 160》 The gate electrode layer 160 may contain, for example, aluminum (Al), titanium (Ti), or chromium (C). r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium Nium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (T) a) and conductive films such as tungsten (W) can be used. The polar layer 160 can be laminated. In addition, nitrides of the above material, or other nitrogen-containing conductive materials, can be used. An electrolytic film may also be used. Furthermore, when tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen. It is preferable because it has barrier properties and tantalum nitride itself is resistant to oxidation.

[0165] Insulating layer 170 The insulating layer 170 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain elements such as nium (Hf), tantalum (Ta), and titanium (Ti). For example... Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Silicon oxide (Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaO) An insulating film containing one or more of x) can be used. Furthermore, the insulating layer 170 is a laminate of the above materials. That's fine.

[0166] Furthermore, the insulating layer 170 may also be made of an oxide containing In or Zn. Typically, In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (where M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ) exists.

[0167] The insulating layer 170 preferably contains an aluminum oxide film. The aluminum oxide film is It has a barrier effect that prevents both hydrogen, water and other impurities, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film is used during the transistor fabrication process and during production. After manufacturing, the insulation of impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of transistors. Body 121, prevention of contamination into semiconductor layer 122, oxygen insulator 121 which is the main component material, semiconductor This has the effect of preventing release from layer 122 and preventing unnecessary release of oxygen from the insulating layer 110. It is suitable for use as a protective film.

[0168] Furthermore, it is preferable that the insulating layer 170 be a film that has oxygen supply capacity. When forming the insulating film 170a, a mixed layer of insulating layer 170 and insulating layer 175 is formed. Then, oxygen is added to the mixed layer or insulating layer 175, and the oxygen is removed by subsequent heat treatment. It diffuses into oxide semiconductors and can replenish oxygen vacancies in the oxide semiconductors. This can improve transistor characteristics (e.g., threshold, reliability, etc.).

[0169] Furthermore, there may be other insulating layers above or below the insulating layer 170. For example, an oxidizing layer Magnesium, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, acid Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Using an insulating film containing one or more neodymium oxide, hafnium oxide, and tantalum oxide Yes, it's possible. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (H) f) It can contain tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide Aluminum (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), acid Silicon nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Um (YOx), Zirconium Oxide (ZrOx), Lanthanum Oxide (LaOx), Neo Oxide 1 type: dm (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) An insulating film containing the above materials can be used. Furthermore, the insulating layer may be a laminate of the above materials. The insulating layer preferably has more oxygen than the stoichiometric composition. The released oxygen spreads through the gate insulating layer 150 to the channel formation region of the semiconductor layer 120. Because it can be dispersed, it can replenish oxygen in the oxygen deficiency formed in the channel formation region. This allows for obtaining stable transistor electrical characteristics.

[0170] Insulating layer 173 and insulating layer 175 Insulating layers 173 and 175 contain oxygen (O), nitrogen (N), fluorine (F), and aluminum. Aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium Nium (Ge), Yttrium (Y), Zirconium (Zr), Lanthanum (La), Neo It contains elements such as gymnastics (Nd), hafnium (Hf), tantalum (Ta), and titanium (Ti). This can be done. For example, magnesium oxide (MgOx), silicon oxide (SiOx), oxide Silicon nitride (SiOxNx), silicon oxide nitride (SiNxOx), silicon nitride (S iNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Zirconium oxide (YOx), Zirconium oxide (ZrOx), Lanthanum oxide (LaOx), Neodymium oxide NdOx, hafnium oxide (HfOx), and tantalum oxide (TaOx), and ammonium oxide. An insulating film containing one or more types of luminium (AlOx) can be used. Also, insulating layer 17 3 and the insulating layer 175 may be laminates of the above materials. The insulating layer has a stoichiometric composition It is preferable to have more oxygen.

[0171] Alternatively, insulating layers 173 and 175 may be made of a low dielectric constant material (Low-k material). This may also be the case. For example, silicon oxide (SiOF) with a few percent of fluorine (F) introduced, a few percent Carbon (C)-introduced silicon oxide (SiOC), fluorinated silicate glass (FSG) Organic silicate glass (OSG), silsesquioxane hydrogenate (HSQ), methylsil Sesquioxane (MSQ), organic polymer, polyimide, fluororesin (polytetrafluoroethylene) It can be formed using materials such as polyethylene, fluorine-added amorphous carbon, etc. By using Low-k material for insulating layer 173 and insulating layer 175, the transient The capacity related to TA10 can be further reduced.

[0172] <Conductive layer 165> Furthermore, as shown in Figure 2, the transistor 10 has a conductive layer 165 beneath the insulating layer 110. The conductive layer 165 can function as a bottom gate. As shown in Figure 2(B), the same potential can be applied as the gate electrode layer 160, and Figure 2( As shown in D), different potentials can be applied. The conductive layer 165 can be made of, for example, copper (C u), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Nickel (Ni), Chromium (C) r), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), Platinum (Pt), iridium (Ir), strontium (Sr), and other elements are composed of these materials. Alternatively, alloys, or compounds mainly composed of oxygen, nitrogen, fluorine, silicon, etc. It is preferable to have a single or multilayer conductive layer containing a material. For example, the conductive layer 166 contains a resistant It can have materials with strong oxidizing properties. In addition, the conductive layer 167 can have both heat resistance and conductivity. It is preferable to use high melting point materials such as tungsten and molybdenum. Also, aluminum It is preferable to form it with a low-resistance conductive material such as nium or copper.

[0173] <Transistor manufacturing method> Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to Figures 6 to 14. Note that any parts that overlap with the parts described above in the transistor configuration will be omitted. Furthermore, the A1-A2 direction shown in Figures 6 to 14 is the channel shown in Figures 1(A) and 1(B). It is sometimes referred to as the longitudinal direction. Also, the A3-A4 direction shown in Figures 6 to 14 is the same as in Figure 1(A ) and the channel width direction shown in Figure 1(C) may also be referred to as the channel width direction.

[0174] In this embodiment, each layer constituting the transistor (insulating layer, oxide semiconductor layer, conductive layer These include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. It can be formed using the PLD (Plant Loading) method. Alternatively, it can be formed by coating or printing methods. This can be done. The film deposition methods include sputtering and plasma chemical vapor deposition (PECVD). ) The CVD method is representative, but the thermal CVD method may also be used. As an example of the thermal CVD method, MOCVD (metal-organic chemical vapor deposition) method or ALD (atomic layer deposition) method may be used.

[0175] <Thermal CVD method> Since the thermal CVD method is a film-forming method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0176] Also, in the thermal CVD method, the source gas and the oxidant are simultaneously fed into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to deposit on the substrate, thereby forming a film.

[0177] Also, thermal CVD methods such as MOCVD method and ALD method can form various films such as the metal films, semiconductor films, inorganic insulating films, etc. disclosed in the embodiments described so far. For example, when forming an In -Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In (CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3 . The chemical formula of dimethylzinc is Zn(CH3)2. Also, these combinations are not limited thereto, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc. )2) can also be used.

[0178] <ALD method> A film-forming apparatus using a conventional CVD method, during film formation, a source gas (precursor) for the reaction One or more types are supplied to the chamber simultaneously. The film deposition apparatus using the ALD method is The precursors for the reaction are sequentially introduced into the chamber, and the sequence of gas introduction is repeated. The film is formed by switching each switching valve (also called a high-speed valve) The system is then modified to supply two or more types of precursors to the chamber in sequence, and multiple types of precursors are mixed. To prevent this, an inert gas (such as argon or nitrogen) is applied after the first precursor. We will introduce a second precursor. Also, instead of introducing an inert gas, we will use vacuum evacuation. Therefore, after the first precursor is discharged, the second precursor can be introduced.

[0179] Figures 4(A), (B), (C), and (D) show the film deposition process of the ALD method. First precursor 6 01 is adsorbed onto the surface of the substrate (see Figure 4(A)), and a first single layer is formed (see Figure 4(B)). (See reference). In this case, metal atoms etc. contained in the precursor bond with hydroxyl groups present on the substrate surface. They can be combined. Alkyl groups such as methyl and ethyl groups are bonded to the metal atoms. This is also good. The second precursor 602 is introduced after the first precursor 601 has been exhausted and is in opposition to it. Accordingly (see Figure 4(C)), a second single layer is laminated on the first single layer to form a thin film. (See Figure 4(D)). For example, if an oxidizing agent is included as the second precursor A metal atom present in the first precursor or an alkyl group bonded to the metal atom, and an acid A chemical reaction occurs with the nitrifying agent, forming an oxide film. Also, the second precursor If a gas containing hydrogen is used, a metal film can be formed by a reduction reaction. ru.

[0180] The ALD method is a film deposition method based on surface chemical reactions, in which a precursor is adsorbed onto the surface to be deposited. Further formation occurs due to the action of a self-stopping mechanism. For example, trimethylaluminum The eel precursor reacts with the hydroxyl groups (OH groups) present on the surface of the film to be deposited. At this time, heat Because only surface reactions occur, the precursor comes into contact with the film surface and absorbs thermal energy. Metal atoms and the like in the precursor can be adsorbed onto the surface of the film to be deposited via this. Casa has a high vapor pressure, is thermally stable and does not self-decompose in the pre-deposition stage, and does not form on the substrate. It has characteristics such as rapid chemical adsorption. Also, since the precursor is introduced as a gas, If the precursors introduced to each other have enough time to diffuse, then high aspect Even in areas with uneven surface characteristics, a film can be formed with good coverage.

[0181] Furthermore, in the ALD method, the gas introduction sequence is controlled, and multiple passes are made until the desired thickness is achieved. By repeating the process, a thin film with excellent step coverage can be formed. The thickness of the thin film can be repeated. Because it can be adjusted by the number of times, precise film thickness adjustment is possible. Also, exhaust capacity By increasing the force, the film deposition rate can be increased, and furthermore, the impurity concentration in the film can be reduced. It is possible.

[0182] Furthermore, ALD methods include thermal ALD (thermal ALD) and plasma ALD ( There is the plasma ALD method. In the thermal ALD method, thermal energy is used to react the precursor. The plasma ALD method is a method that carries out the precursor reaction in a radical state. ru.

[0183] The ALD method allows for the precise deposition of extremely thin films. It can also be used for surface coating on surfaces with uneven surfaces. It has a high rate and a high film density.

[0184] <Plasma ALD> In addition, by forming a film by the plasma ALD method, compared with the ALD method using heat (thermal ALD method) it becomes possible to form a film at a lower temperature. The plasma ALD method can, for example, form a film without reducing the film formation rate even at 100°C or lower. Also, in the plasma ALD method, N2 can be radicalized by plasma, so not only oxides but also nitrides can be formed.

[0185] Also, in plasma ALD, the oxidizing power of the oxidizing agent can be enhanced. As a result, when forming a film by ALD, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and also carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained.

[0186] Also, when performing plasma ALD, radical species can be generated and plasma can be generated in a state separated from the substrate, such as Inductively Coupled Plasma (ICP), etc., and plasma damage to the substrate or the film on which the protective film is to be formed can be suppressed.

[0187] From the above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, and the surface coverage rate can be increased, and the film can be formed. As a result, intrusion of water and hydrogen from the outside can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

[0188] <Explanation of the ALD apparatus> Figure 5(A) shows an example of a film deposition apparatus that utilizes the ALD method. , film deposition chamber (chamber 1701), raw material supply unit 1711a, raw material supply unit 1711b, The high-speed valves 1712a and 1712b, which are flow controllers, and the raw material inlet 1713 a. It has a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b, installed inside the bar 1701, are connected via supply pipes and valves. The raw material supply sections 1711a and 1711b are connected to the raw material discharge port 1714. It is connected to the exhaust system 1715 via a discharge pipe, valves, and pressure regulators.

[0189] Inside the chamber is a substrate holder 1716 equipped with a heater, and a cover is placed on the substrate holder. Place the film substrate 1700.

[0190] In the raw material supply units 1711a and 1711b, solids are processed by vaporizers, heating means, etc. Raw material gas is formed from raw materials or liquid raw materials. Alternatively, raw material supply unit 1711a, raw material supply Section 1711b may also be configured to supply raw material gas.

[0191] Furthermore, an example is shown in which two raw material supply units 1711a and 1711b are provided. There are no particular limitations, and three or more may be provided. Also, high-speed valve 1712a, high-speed valve 17 12b can be precisely controlled by time, supplying either the source gas or the inert gas. The configuration is as follows. High-speed valves 1712a and 1712b are flow controllers for the raw material gas. Furthermore, it can also be described as a flow controller for inert gases.

[0192] In the film deposition apparatus shown in Figure 5(A), the substrate to be deposited 1700 is loaded onto the substrate holder 1716. After sealing the chamber 1701, the substrate holder 1716 is heated by a heater to deposit the film. The substrate 1700 is heated to a desired temperature (for example, 100°C or higher or 150°C or higher), and the source gas is added. The supply of, exhaust by exhaust device 1715, supply of inert gas, and exhaust by exhaust device 1715 A thin film is formed on the substrate surface by repeatedly exhaling air.

[0193] In the film deposition apparatus shown in Figure 5(A), raw material is prepared in raw material supply section 1711a and raw material supply section 1711b. By appropriately selecting raw materials (such as volatile organometallic compounds), hafnium (Hf), A type selected from aluminum (Al), tantalum (Ta), zirconium (Zr), etc. To form an insulating layer composed of oxides (including composite oxides) containing the above elements. This can be done. Specifically, an insulating layer composed of hafnium oxide and aluminum oxide An insulating layer comprising, an insulating layer comprising hafnium silicate, or aluminum Insulating layers and the like, composed of nium silicate, can be formed. The raw materials (volatile organometallic compounds, etc.) to be prepared in the feeding section 1711a and the raw material supply section 1711b By selecting appropriately, metal layers such as tungsten layers and titanium layers, and titanium nitride layers, etc. Thin films, such as nitride layers, can also be deposited.

[0194] For example, when forming a hafnium oxide layer using a film deposition apparatus that utilizes the ALD method, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl A raw material gas obtained by vaporizing hafnium amides (such as amide hafnium (TDMAH)) and an acid Two types of gases, ozone (O3), are used as nitrifying agents. In this case, the raw material supply unit 1711a or The first raw material gas supplied is TDMAH, and the second raw material supplied from the raw material supply unit 1711b is TDMAH. The raw material gas is ozone. The chemical formula for tetrakisdimethylamidehafnium is Hf It is [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Examples include hafnium. Furthermore, nitrogen has the function of eliminating charge trapping levels. Therefore, by using nitrogen as the raw material gas, a hafnium oxide film with a low charge trapping level density can be formed. It is possible.

[0195] For example, when forming an aluminum oxide layer using a film deposition apparatus that utilizes the ALD method, A raw material gas is obtained by vaporizing a liquid (such as TMA) containing a medium and an aluminum precursor compound, and oxidation Two types of gas, H2O, are used as the agent. In this case, they are supplied from the raw material supply unit 1711a. The first raw material gas is TMA, and the second raw material gas supplied from the raw material supply unit 1711b is H It becomes 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Also, Other material liquids include tris(dimethylamide)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include (T).

[0196] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, causing an oxidizing gas (O2) A radical (nitrous oxide) is supplied and reacted with the adsorbed material.

[0197] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 A tungsten film is formed by sequentially introducing gas and H2 gas. Note that B2H6 gas is also used. SiH4 gas may be used instead.

[0198] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. An O layer is formed, and then Ga(CH3)3 gas and O3 gas are repeatedly introduced in sequence to form GaO A layer is formed, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced sequentially to form ZnO Layers are formed. Note that the order of these layers is not limited to this example. Also, these gases are mixed. This forms mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. It is also acceptable to use H2O obtained by bubbling with an inert gas such as Ar instead of O3 gas. While gas can be used, it is preferable to use O3 gas that does not contain H. Also, In(CH) 3) In(C2H5)3 gas may be used instead of 3 gas. Also, Ga(CH3)3 Alternatively, Ga(C2H5)3 gas may be used instead of gas. Also, Zn(CH3)2 gas may be used. You may use it.

[0199] Multi-chamber film deposition system Furthermore, a multi-chamber manufacturing apparatus having at least one film deposition apparatus as shown in Figure 5(A) An example is shown in Figure 5(B).

[0200] The manufacturing apparatus shown in Figure 5(B) can continuously deposit laminated films without exposure to the atmosphere. This aims to prevent the inclusion of impurities and improve throughput.

[0201] The manufacturing apparatus shown in Figure 5(B) consists of a loading chamber 1702, a conveying chamber 1720, a pre-processing chamber 1703, It has at least a deposition chamber 1701 and an unloading chamber 1706. The chambers of the manufacturing equipment (including the loading chamber, processing chamber, transport chamber, film deposition chamber, unloading chamber, etc.) To prevent moisture from adhering, etc., an inert gas (such as nitrogen gas) with a controlled dew point is filled in. It is preferable to leave it as is, and preferably maintain reduced pressure.

[0202] Furthermore, chambers 1704 and 1705 utilize the same ALD method as chamber 1701. It may be a film deposition apparatus, or a film deposition apparatus that utilizes plasma CVD, or spa It may be a film deposition apparatus utilizing the taring method, or a metal-organic vapor deposition (MOCVD) apparatus. The tal Organic Chemical Vapor Deposition method It may also be used as a film deposition apparatus.

[0203] For example, Chamber 1704 is a film deposition apparatus that utilizes the plasma CVD method, The following is an example of a film deposition apparatus using the MOCVD method, designated as -1705, for the deposition of a multilayer film. show.

[0204] Figure 5(B) shows an example where the top view of the transport chamber 1720 is hexagonal, but depending on the number of layers of the laminated film... Furthermore, it may be used as a manufacturing apparatus with even more polygons, connected to a larger number of chambers. Furthermore, although the top surface shape of the substrate is shown as a rectangle in Figure 5(B), it is not particularly limited. Although Figure 5(B) shows an example of a single-wafer deposition process, there is also a batch deposition process where multiple substrates are deposited at once. It can also be used as a device.

[0205] <Formation of insulating layer 110> First, an insulating layer 110 is deposited on the substrate 100. The insulating layer 110 is deposited using plasma CVD, thermal By CVD (MOCVD, ALD) or sputtering, for example, aluminum oxide nium, magnesium oxide, silicon oxide, silicon nitride oxide, gallium oxide, gel oxide Manium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hazel oxide Oxide insulating films such as nitrium and tantalum oxide, silicon nitride, silicon oxide nitride, nitrogen Aluminum oxide, aluminum nitride, or other nitride insulating films, or mixtures thereof It can be formed using the above materials. Alternatively, it may be a laminate of the above materials, and later an insulator 121 The upper layer of the lamination in contact with the first insulating film can serve as a source of oxygen for the semiconductor layer 122. It is preferable to form it with a material containing excess oxygen.

[0206] For example, silicon oxide nitride with a thickness of 100 nm can be used as the insulating layer 110 by plasma CVD. A membrane can be used.

[0207] Next, a first heat treatment may be performed to remove water, hydrogen, etc., contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110. Heat treatment reduces the amount of water, hydrogen, etc., that diffuses into the first oxide semiconductor film that is formed later. It is possible.

[0208] <Formation of the first insulating film and semiconductor film> Next, a first insulating film, which will later become an insulator 121, is placed on the insulating layer 110, followed by a semiconductor layer 122. A semiconductor film is formed. The first insulating film and the semiconductor film are formed by sputtering, MOCVD, It can be formed by methods such as PLD, and it is more preferable to form it using the sputtering method. i. Sputtering methods include RF sputtering, DC sputtering, AC sputtering, etc. It is possible. Also, in the sputtering method, the opposing target method (opposing electrode method, gas phase sputtering) is possible. Patter method, VDSP (Vapor Deposition Spattering) method By forming it using the formula (also known as the formula), plasma damage during film deposition can be reduced. Cut.

[0209] For example, when forming the first insulating film by sputtering, each channel in the sputtering apparatus The number is used to remove as much water and other impurities as possible from oxide semiconductors, and is cryopreserved. Using an adsorption-type vacuum pump like a suction pump to create a high vacuum (5 × 10 -7 Pa~1×10 -4 The ability to process up to approximately Pa, and the substrate to which the film is to be deposited should be heated to 100°C or higher, preferably 40°C. It is preferable that the temperature can be heated to 0°C or higher. Alternatively, a turbomolecular pump and a cold trap can be used. Combined, this prevents gases containing carbon components and moisture from flowing back into the chamber from the exhaust system. It is preferable to do so. Also, exhaust gases using a combination of a turbomolecular pump and a cryopump are preferable. A system may also be used.

[0210] To obtain high-purity intrinsic oxide semiconductors, not only is the chamber evacuated to a high vacuum, but spa It is preferable to purify the sputtering gas as well. Oxygen gas and argon gas are used as sputtering gas. The gas has a dew point of -40°C or lower, preferably -80°C or lower, and more preferably -100°C or lower. By using gas purified to such a high degree, it becomes possible to incorporate moisture and other substances into the oxide semiconductor film. It can be prevented to the best of one's ability.

[0211] Sputtering gases include noble gases (typically argon), oxygen gas, and noble gas and oxygen gas. A mixed gas of a noble gas and oxygen gas is used as appropriate. In the case of a mixed gas of a noble gas and oxygen gas, the noble gas is used as It is preferable to increase the oxygen gas ratio.

[0212] Furthermore, when forming an oxide semiconductor film, for example, using the sputtering method, the substrate temperature The temperature is 150°C to 750°C, preferably 150°C to 450°C, and more preferably By depositing an oxide semiconductor film at a temperature between 200°C and 420°C, CAAC-OS is produced. It can form a film.

[0213] The first insulating film is made of a material selected to have a lower electron affinity than the semiconductor film. can.

[0214] Furthermore, the semiconductor film has a higher indium content than the first and second insulating films. This is also acceptable. In oxide semiconductors, the s orbitals of heavy metals primarily contribute to carrier conduction. By increasing the In content, more s orbitals overlap, so In is more effective than Ga. In oxides with a high concentration of In migrating compared to oxides with a concentration equal to or lower than Ga. The degree increases. Therefore, an oxide with a high indium content is used in the semiconductor layer 122. This makes it possible to realize transistors with high mobility.

[0215] Furthermore, in the case of the first insulating film and semiconductor film, for example, when the film is formed by sputtering, By using a Chi-chamber sputtering system, the first insulator film and the semiconductor film are exposed to the atmosphere. Continuous film deposition is possible without extrusion. In that case, the interface between the first insulating film and the semiconductor film This can prevent unwanted impurities from entering and reduce the number of interface states. This allows for stable performance in the electrical characteristics of transistors, particularly in reliability testing. It can be standardized.

[0216] Furthermore, if there is damage in the semiconductor film, the presence of the first insulating film makes it possible to This allows the semiconductor film, which forms the conductive path, to be moved away from the damaged area, and as a result, the transient The electrical characteristics of the device, particularly in reliability testing, can be stabilized.

[0217] For example, as the first insulating film, by sputtering, In:Ga:Zn=1:3: Using a target with an atomic ratio of 4, an oxide semiconductor film with a thickness of 20 nm is used. This can be done. Also, as a semiconductor film, In:Ga:Zn=1:1 can be produced by sputtering. Using an oxide semiconductor film with a thickness of 15 nm deposited with a target of :1 (atomic ratio) It is possible.

[0218] Furthermore, it is preferable to perform a second heat treatment after the formation of the first insulating film and the semiconductor film. Heat treatment can reduce the amount of oxygen vacancies in semiconductor films.

[0219] The temperature for the second heat treatment is 250°C or higher and below the substrate strain point, preferably 300°C or higher and 650°C. The temperature should be below ℃, and more preferably between 350℃ and 550℃.

[0220] The second heat treatment involves using noble gases such as helium, neon, argon, xenon, and krypton, Alternatively, the process may be carried out in an inert gas atmosphere containing nitrogen. Or, after heating in an inert gas atmosphere, oxygen Atmosphere or dry air (with a dew point of -80°C or lower, preferably -100°C or lower, preferably - Heating may be performed in an air atmosphere below 120°C, or under reduced pressure. In addition to the dry air mentioned above, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. In particular, the dew point is preferably -80°C or lower, and more preferably -100°C or lower. Processing time will range from 3 minutes to 24 hours.

[0221] Furthermore, in the second heat treatment, instead of an electric furnace, heat transfer from a heat source such as a resistance heating element is used. A device that heats the object to be processed by conduction or thermal radiation may be used. For example, GRTA( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) devices, etc. Anneal) equipment can be used. LRTA equipment uses halogen lamps and metal Halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The light (electromagnetic waves) emitted from lamps such as high-pressure mercury lamps heats the object being processed. The GRTA apparatus is a device that performs a second heat treatment using high-temperature gas. For high-temperature gases, noble gases such as argon, or inert gases such as nitrogen, are used. .

[0222] The second heat treatment involves etching to form the insulator 121 and semiconductor layer 122, which will be described later. You can go afterwards.

[0223] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, then in an oxygen atmosphere... It can then be subjected to a heat treatment at 450°C for 1 hour.

[0224] Through the above process, oxygen vacancies in the semiconductor film are reduced, and impurities such as hydrogen and water are also reduced. This allows for the formation of semiconductor films with reduced localized energy level density.

[0225] <Formation of the first conductive film> Next, a first conductive film is formed on the semiconductor film, which will be the source electrode layer 130 and the drain electrode layer 140. The first conductive film is produced by sputtering, chemical vapor deposition (CVD) (organometallic chemistry). Metal vapor deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD), or plasma deposition This includes chemical vapor deposition (PECVD), vapor deposition, and pulsed laser deposition (PLD). It can be formed using the following methods.

[0226] The material for the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), and gold (A). u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S) This includes elements or alloys made from materials such as r), or compounds that have these as their main components. It is preferable to have a single layer or a stack of conductive films. For example, when stacking, semiconductor layer 12 The lower conductive layer in contact with 2 has a material that readily bonds with oxygen, and the upper conductive layer has oxidation resistance. It can have a strong material. Also, tungsten (W) can achieve both heat resistance and conductivity. It is preferable to use high melting point materials such as molybdenum (Mo). Also, aluminum ( It is preferable to form it with a low-resistance conductive material such as Al or copper (Cu). Furthermore, Cu- When using a Mn alloy, a film containing manganese oxide is formed at the interface with an oxygen-containing insulator, and oxidation occurs. Manganese is preferable because it has the function of suppressing the diffusion of Cu.

[0227] For example, a tungsten film with a thickness of 20 to 100 nm is subjected to a first conductive process by sputtering. It can be formed as a membrane.

[0228] Furthermore, the conductive layer 130b, which is formed by processing the first conductive film in a later step, is in this subsequent step In this case, it has the function of a hard mask, as well as the functions of a source electrode layer and a drain electrode layer. This eliminates the need for additional film deposition steps, thus shortening the semiconductor manufacturing process. .

[0229] <Formation of insulator 121 and semiconductor layer 122> Next, a resist mask is formed by a lithography process, and using this resist mask, The first conductive film is selectively and partially etched to form a conductive layer 130b. Subsequently, the conductive After removing the resist on layer 130b, the conductive layer 130b is used as a hard mask to form a semiconductor film, The oxide semiconductor film 1 is selectively etched, and the semiconductor layer 122 and insulator 121 are obtained. It can be formed in an island-like shape (see Figure 6). Note that the etching method is dry etching. The ching method can be used. Furthermore, the conductive layer 130b can be used as a hard mask. By etching the body film and the first insulating film, compared to when only a resist mask is used... Compared to other methods, this method can reduce the edge roughness of the oxide semiconductor layer after etching.

[0230] For example, methane gas and argon gas are used as etching gases, and the resist mask and By using a hard mask, the first oxide semiconductor film and the semiconductor film are selectively etched. This allows for the formation of an insulator 121 and a semiconductor layer 122. 10 may be partially etched.

[0231] <Deposition of insulating films> Next, an insulating film 173a, which will become an insulating layer 173, is formed on the insulating layer 110 and the conductive layer 130b. (See Figure 7). Insulating film 173a is produced by plasma CVD, thermal CVD (MOCVD, AL) Method D), sputtering, or spin coating, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxide nitride Lycon (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) ), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (Ta Ox oxide dielectrics such as silicon nitride (SiNx), silicon nitride oxide (SiNxOx), silicon nitride (SiNxOx). y), aluminum nitride (AlNx), aluminum oxide nitride (AlNxOy), and other nitrogen compounds. It can be formed using a crystalline insulating film or a mixture thereof. Layering is also acceptable.

[0232] Alternatively, the insulating film 173a may be made of a low dielectric constant material (low-k material). For example, silicon oxide (SiOF) with a few percent of fluorine (F) introduced, and silicon oxide (SiOF) with a few percent of carbon (C) introduced. Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate Glass (OSG), silsesquioxane hydride (HSQ), methylsilsesquioxane ( MSQ), organic polymers, fluororesins (polytetrafluoroethylene), polyimide, f It can be formed using amorphous carbon with added ions, etc.

[0233] The second heat treatment may be performed after the deposition of the insulating film 173a.

[0234] <Planarization of the second insulating film> Next, the insulating film 173a is planarized until the conductive layer 130b is exposed, and the insulating layer 173 This forms (see Figure 8). The planarization process is performed using CMP (Chemical Mechanical Processing). This can be done using methods such as the polishing method described later. The thickness of the insulating film 175a on the conductive layer 130b within the plate surface can be made uniform.

[0235] The second heat treatment may be performed after the insulating film 173a has been planarized.

[0236] <Deposition of insulating films> Next, a third insulating film 175a, which will become an insulating layer 175, is formed on the insulating layer 173 and the conductive layer 130b. It forms a membrane (see Figure 9).

[0237] The insulating film 175a can be deposited using the same materials and methods as the insulating film 173a.

[0238] <Groove formation> Next, a resist mask 176 is formed on the insulating film 175a by a lithography process (Figure (See 10). Note that the organic film is coated onto the insulating film 175a, or onto the resist. The lithography process may be performed after coating with an organic film. The organic film may contain propylene glycol. It contains methyl monomethyl ether, ethyl lactate, etc., and has an anti-reflective coating (BA) during exposure. Function as RC (Bottom Anti-reflective Coating) In addition to having these properties, it can also improve the adhesion between the resist and the film, and improve resolution.

[0239] Furthermore, when forming transistors with extremely short channel lengths, at least the source electrode layer 130, in the region that divides the conductive layer 130b which becomes the drain electrode layer 140, electron beam exposure, immersion exposure, and EUV (Extreme Ultra-violet) exposure. A resist mask is processed using a method suitable for processing fine lines such as light, and then the etching process is performed. Then, the area in question should be etched. Furthermore, a resist mask is formed using electron beam lithography. In this case, if a positive-type resist is used as the resist mask, the exposure area can be minimized. This allows for improved throughput. Using this method, To form transistors with channel lengths of 100 nm or less, and even 30 nm or less. This can be done. Alternatively, fine processing may be performed using exposure techniques such as X-rays.

[0240] Using the resist mask, a portion of the insulating film 175a is etched by dry etching. Processing is performed from the ng. As a result, the insulating layer 175 is formed and at the same time the groove portion 174 It is formed.

[0241] Next, a portion of the exposed conductive layer 130b is etched in a way that divides it, and the source electrode layer 13 0. A drain electrode layer 140 can be formed (see Figure 11).

[0242] After forming the source electrode layer 130 and the drain electrode layer 140, the etching residue is removed. Therefore, a cleaning process may be performed. By performing this cleaning process, the source electrode layer 130, Short circuits in the drain electrode layer 140 can be suppressed. This cleaning process is performed using TMAH(Te Alkaline solutions such as tramethylammonium hydroxyl solution This can be done using a solution of acid, such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Furthermore, during the cleaning process, a portion of the semiconductor layer 122 is etched, and the semiconductor layer 122 A recess is formed.

[0243] For example, after planarizing the silicon oxidnitride film formed as insulating film 173a, the silicon oxidnitride film A resist mask is formed on the recon film by lithography, and the resist mask and carbon By dry etching using a gas containing fluorine, silicon oxidiznitride is produced. The conductive layer 130b is dry-etched using a chlorine- and fluorine-based gas after opening the holes. This allows the source electrode layer 130 and the drain electrode layer 140 to be formed.

[0244] <Formation of the second insulating film 123a> Next, a second insulating film used as an insulator 123 is placed on the semiconductor layer 122 and the insulating layer 175. The second insulating film 123a is deposited in the same manner as the first insulating film. This allows the second insulating film 123a to have a lower electron affinity than the semiconductor film. You can choose the materials.

[0245] For example, as the second insulating film 123a, by sputtering, In:Ga:Zn= Using a 1:3:2 (atomic ratio) target, an oxide semiconductor film with a thickness of 5 nm was deposited. It is possible.

[0246] <Formation of insulating film 150a> Next, an insulating film 150a, which will become the gate insulating layer 150, is formed on the second insulating film 123a. The insulating film 150a contains, for example, aluminum oxide (AlOx), magnesium oxide (M (gOx), silicon oxide (SiOx), silicon oxide nitride (SiOxNy), silicon nitride oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zircon oxide Using conium, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, etc. This is possible. Note that the insulating film 150a may be a laminate of the above materials. Insulating film 15 0a is the sputtering method, CVD method (plasma CVD, MOCVD, ALD, etc.), M It can be formed using the BE method, etc. Also, the insulating film 150a is the insulating layer 110 and An insulating film can be formed using a similar method as appropriate.

[0247] For example, silicon oxidiznitride is formed as insulating film 150a by plasma CVD to a thickness of 10 nm. It is possible.

[0248] <Formation of conductive film 160a> Next, a conductive film 160a, which will become the gate electrode layer 160, is formed on the insulating film 150a (Figure 1). (See 2). Examples of conductive films 160a include aluminum (Al), titanium (Ti), Chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y) ), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), or materials mainly composed of these. A suitable alloy material can be used. The conductive film 160a can be produced by sputtering or CVD (P (e.g., razma CVD, MOCVD, ALD), MBE, vapor deposition, plating, etc.) It can be formed in this way. Furthermore, as the conductive film 160a, a conductive film containing nitrogen can be used. Alternatively, a laminate of the above conductive film and a conductive film containing nitrogen may be used. Also, conductive film 160a It can be a single layer or a multi-layer structure.

[0249] For example, titanium nitride is formed to a thickness of 10 nm by the ALD method, and tungsten is treated with metal CVD. A laminated structure with a thickness of 150 nm can be used according to the method.

[0250] <Plating process> Next, a planarization process is performed. This planarization process is carried out using methods such as CMP or dry etching. This can be done. The planarization process may be terminated when the insulating film 150a is exposed, or The process may be terminated when the insulating film 123a of layer 2 is exposed, or when the insulating layer 175 is exposed. The process may end there. This results in gate electrode layer 160, gate insulating layer 150, insulator 12 3 can be formed (see Figure 13).

[0251] Furthermore, a second insulating film 123a or insulating film 150a is applied to the flattened insulating layer 175. If present, processing may be carried out using a new resist mask. Second insulating film 1 A resist mask is formed on 23a or the insulating film 150a by a lithography process. The mask has a larger area than the upper surface of the gate electrode layer 160, and the mask has The insulating film 150a and the second insulating film 123a are selectively etched, and the gate insulating layer is further etched. 150, an insulator 123 can be formed.

[0252] In transistor 10, an insulator 123 that is less prone to oxygen deficiency is provided, The desorption of oxygen from the side surface of the insulator 123 in the channel width direction is suppressed, and oxygen deficiency is prevented. This can suppress the formation of transistors. As a result, electrical characteristics are improved, and the transistors become more reliable. It can be achieved.

[0253] <Deposition of insulating layer 170> Next, on the insulating layer 173, the insulator 123, the gate insulating layer 150, and the gate electrode layer 160 An insulating layer 170 is then formed on top of it.

[0254] The insulating layer 170 is made by plasma CVD, thermal CVD (MOCVD, ALD), or For example, aluminum oxide (AlOx), magnesium oxide (MgO), etc., can be produced using methods such as the Patta process. x), silicon oxide (SiOx), silicon oxide nitride (SiOxNy), gallium oxide ( GaOx, germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide Nium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), halogen oxide Oxide insulating films such as nium (HfOx) and tantalum oxide (TaOx), silicon nitride (SiNx), silicon nitride (SiNxOy), aluminum nitride (AlNx), nitrile Nitride insulating films such as aluminum oxide (AlNxOy), or mixtures thereof, are used. It can be formed by laminating the above materials. Also, the insulating layer 170 In or Zn oxides may be used. Typical examples include In-Ga oxide. In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is These include Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd.

[0255] Furthermore, the insulating layer 170 is formed by depositing an aluminum oxide film using a sputtering method. This is desirable. Also, using aluminum oxide as a target for sputtering is preferable. This is desirable. Furthermore, it is desirable to have oxygen gas as the gas used during film formation.

[0256] When the aluminum oxide film is formed, a mixed layer 171 is formed at the interface with the insulating layer 173. ru.

[0257] For example, the oxygen gas used when forming the insulating layer 170 is applied during film formation by the sputtering method. Due to the influence of the applied voltage, power, plasma, substrate temperature, etc., oxygen radicals, oxygen ions, Oxygen atoms and other elements exist in various states, and some states have higher energy levels compared to their stable states. At this time, oxygen (excess oxygen, called exO) 172 is mixed with the insulating layer 173. It is added to layer 171.

[0258] <Oxygen addition> Furthermore, in fabricating transistor 10, the above method is not the only option, and the addition of oxygen may also be used. This may be done separately. The oxygen addition process may be performed on the insulating layer 110, or the first This may also be performed on an oxide semiconductor film or the second insulating film 123a mentioned above. The oxygen to be added... For example, one or more of the following: oxygen radical, oxygen atom, oxygen atom ion, oxygen molecular ion, etc. The method used is ion doping, ion implantation, and p Methods include razma immersion ion implantation.

[0259] Furthermore, when using ion implantation as a method for adding oxygen, even if oxygen atomic ions are used... Yes, or you may use oxygen molecular ions. When oxygen molecular ions are used, the added film will Damage can be reduced. Oxygen molecular ions are added to the film surface to which the oxygen is added. It is separated and added as oxygen atom ions. Because energy is used, when oxygen molecular ions are added to the membrane to which the oxygen is added The energy per oxygen atom ion in is the energy of the oxygen atom ion when the oxygen is added. The effect is lower compared to when added to a membrane. Therefore, it reduces damage to the membrane to which the oxygen is added. It can be reduced.

[0260] Furthermore, when implanting oxygen molecular ions, compared to when implanting oxygen atomic ions, the acid The energy per elementary atom ion is low. Therefore, it is implanted using oxygen molecular ions. This makes it possible to increase the acceleration voltage and thus increase throughput. Furthermore, by using oxygen molecular ions for implantation, compared to the case using oxygen atomic ions, It is possible to halve the dose required to add the same amount of oxygen atoms and ions. As a result, it is possible to increase the throughput of the manufacturing process.

[0261] Furthermore, when adding oxygen to the membrane to which the oxygen is added, the oxygen source in the membrane to which the oxygen is added Using conditions such that the peak of the concentration profile of the child ions is located, the oxygen is added. It is preferable to add oxygen to the membrane. As a result, compared to when oxygen atomic ions are implanted... In general, this reduces the acceleration voltage during injection, thereby reducing damage to the membrane to which the oxygen is added. It is possible to do so. That is, the amount of defects in the membrane to which the oxygen is added can be reduced. It is possible to suppress fluctuations in the electrical characteristics of the transistor. As a result, when the oxygen is added... This reduces damage to the film being treated and suppresses fluctuations in the transistor's electrical characteristics. It can be controlled.

[0262] Furthermore, a plasma is generated in an oxygen-containing atmosphere, and the film to which the oxygen is added is exposed to the plasma. By plasma immersion ion implantation, oxygen is added to the film to which the oxygen is added. This is also acceptable. As an oxygen-containing atmosphere, oxygen, ozone, nitrous oxide, nitrogen dioxide, and other acids are also acceptable. There is an atmosphere containing chemical gases. This occurs when a bias is applied to the substrate 100 side. By exposing the film to which the oxygen is added to the plasma, the oxygen is added to the film. It is possible and preferable to increase the amount added. An example of a device for performing such plasma processing. One example is the ashing device.

[0263] For example, if the acceleration voltage is 5kV and the dose is 1 × 10⁻¹⁰ 16 / cm 2 The oxygen molecular ions It can be added to the first oxide semiconductor film by on-implantation.

[0264] By combining the above steps and subsequent heat treatment, the semiconductor layer 122 is oxygen-deficient. Losses can be reduced. Furthermore, the membrane with added oxygen is different from the membrane before oxygen was added. In comparison, the membrane density becomes lower.

[0265] Next, a third heat treatment may be performed. Typically, the third heat treatment involves heating to 150°C or higher. Below the plate strain point, preferably 250°C to 500°C, more preferably 300°C to 45°C The temperature can be set to 0°C or below. This heat treatment causes the added oxygen 172 to diffuse, and half It moves to the conductive layer 122 and replenishes the oxygen vacancies present in the semiconductor layer 122 with oxygen. This is possible (see Figure 14).

[0266] For example, using the sputtering method, with an aluminum oxide (AlOx) target, The insulating layer 170 is formed by adding 50% by volume of oxygen gas as the gas used during sputtering. This can be done. The thickness can be 20 nm to 40 nm. Also, a third heating treatment In theory, it can be heat-treated at 400°C for 1 hour under an oxygen atmosphere.

[0267] Through the above process, the localized energy level density of the semiconductor film is reduced, resulting in a transistor with excellent electrical properties. It is possible to fabricate a zista. Furthermore, it is possible to observe the changes in electrical properties due to aging and stress testing. It is possible to manufacture a small number of highly reliable transistors.

[0268] (Embodiment 2) In this embodiment, a transistor with a different structure from the transistor 10 described in Embodiment 1 is used. The method for fabricating sta 11 and transistor 12 will be described.

[0269] <Variation 1 of transistor 10: Transistor 11> Regarding transistor 11, which has a different shape from transistor 10 shown in Figure 1, use Figure 15. explain.

[0270] Figures 15(A), 15(B), and 15(C) show the top view and cross-sectional view of transistor 11. Figure 15(A) is a top view of transistor 11, and Figure 15(B) is a top view of transistor 11. The dashed line shows the section between A1 and A2, and Figure 15(C) shows the section between A3 and A4.

[0271] The transistor 11 consists of an insulating layer 170, an insulator 121, a semiconductor layer 122, and a source electrode layer 13 0, Transition having a region in contact with the side surface of the drain electrode layer 140 and the insulating layer 175 It is different from Sta10.

[0272] Furthermore, as will be described later, the transistor 11 consists of an insulator 121, a semiconductor layer 122, and a source electrode. The fact that layer 130, drain electrode layer 140, and insulating layer 175 are formed in the same process, and each process The manufacturing method of transistor 10 differs in that planarization is not performed at this stage.

[0273] <Method for fabricating transistor 11> The method for fabricating transistor 11 will be explained using Figures 16 to 23. Note that this is Embodiment 1. For the process similar to that described for transistor 10, refer to that explanation.

[0274] As shown in Figures 16(A) and 16(B), the first insulating layer 110 and the insulating body 121 Edge film 121a, semiconductor film 122a which becomes semiconductor layer 122, source electrode layer 130 and A conductive film 130a that will become the rain electrode layer 140, and an insulating film 175a that will become the insulating layer 175 A film is formed, and a resist mask 176 is formed on the insulating film 175a using lithography.

[0275] Next, using the resist mask 176, a portion of the insulating film 175a and the conductive film 130a is removed. This process forms grooves 174, an insulating layer 175b, and a conductive layer 130b (see Figure 17).

[0276] Next, using a resist mask, the insulating layer 175b, conductive layer 130b, semiconductor film 122a, and The insulating film 121a is partially etched, leaving the insulator 121, semiconductor layer 122, and source electrode. Layer 130, drain electrode layer 140, and insulating layer 175 are formed (see Figure 18).

[0277] Next, a second insulating film 123a that will become the insulator 123, and an insulating film 1 that will become the gate insulating layer 150. 50a and a conductive film 160a, which will become the gate electrode layer 160, are sequentially deposited (see Figure 19).

[0278] Next, using the resist mask formed by lithography, the conductive film 160a and the insulating film are formed. A portion of film 150a and a portion of the second insulating film 123a are etched, and the insulator 123 and ging An insulating layer 150 and a gate electrode layer 160 are formed (see Figure 20).

[0279] Note that the insulator 123, gate insulating layer 150, and gate electrode layer 160 do not need to be formed all at once. Alternatively, as shown in Figures 21 and 22, the insulating film 150a is not etched and the insulator 123 A gate electrode layer 160 may be formed. Also, the end of the insulator 123 and the gate insulating layer 1 The edges of the 50 and the gate electrode layer 160 may be formed so as not to overlap.

[0280] Next, an insulating layer 170 is formed and heat treatment is performed to spread oxygen 172 to the semiconductor layer 122. This allows for dispersion and reduces oxygen vacancies in the semiconductor layer 122 (see Figure 23).

[0281] By following the above steps, transistor 11 can be manufactured.

[0282] In the method for fabricating transistor 11, an insulating film 175a which will become the insulating layer 175 is made of source electrode layer 1 30. The conductive film 130a, which will become the drain electrode layer 140, can be formed before processing. Therefore, the thickness of the insulating film 175a can be made uniform within the substrate surface, and the groove portion 174 is formed. The switching processing time can be stabilized. This allows the transistor 11 to be stabilized. It can be manufactured and the shape of the transistor can be stabilized. Therefore, This allows for stabilization of the transistor characteristics.

[0283] <Variation 2 of transistor 10: transistor 12> Regarding transistor 12, which has a different shape from transistor 10 shown in Figure 1, use Figure 24. explain.

[0284] Figures 24(A), 24(B), and 24(C) show the top view and cross-sectional view of transistor 12. Figure 24(A) is a top view of transistor 12, and Figure 24(B) is a top view of transistor 12. The dashed line in Figure 24(C) shows a cross-section between A1 and A2, and Figure 24(C) shows a cross-section between A3 and A4.

[0285] Transistor 12 differs from transistor 10 in that it has an insulating layer 177.

[0286] Furthermore, as will be described later, the first insulating film 121a which becomes the insulator 121, and the semiconductor layer 122 A conductive film 1 which forms a semiconductor film 122a, a source electrode layer 130, and a drain electrode layer 140. 30a, insulating film 175a which becomes insulating layer 175, and insulating film 177a which becomes insulating layer 177 This differs from the manufacturing method of transistor 10 in that each film is formed before processing.

[0287] <Method for fabricating transistor 12> The method for fabricating transistor 12 will be explained with reference to Figures 25 to 32. Note that this is Embodiment 1. For the process similar to that described for transistor 10, refer to that explanation.

[0288] A first insulating film 121a, which will become an insulator 121, and a semiconductor layer 122, are placed on the insulating layer 110. Conductive film 122a, conductive film 130a which forms the source electrode layer 130 and drain electrode layer 140 Each of the films consists of an insulating film 175a which becomes the insulating layer 175, and an insulating film 177a which becomes the insulating layer 177. The films are deposited sequentially before processing (see Figure 25).

[0289] Furthermore, the insulating layer 177 can be formed using the same material and method as the insulating layer 170. Cut.

[0290] Next, using a resist mask, we have insulating film 177a, insulating film 175a, conductive film 130a, and semiconductor film. The body film 122a and a portion of the first insulating film 121a are etched, forming the insulator 121 and semiconductor layer. 122, a conductive layer 130b, an insulating layer 175b, and an insulating layer 171b are formed (see Figure 26). In addition, the insulating layer 110 may be partially etched at this time.

[0291] Next, an insulating film 173a, which will become the insulating layer 173, is formed (see Figure 27). Plasma CVD, thermal CVD (MOCVD, ALD), sputtering, or spi It can be formed by a coating method or the like.

[0292] Next, the insulating film 173a is subjected to planarization treatment by CMP until the insulating layer 171b is exposed. This process is performed to form the insulating layer 173 (see Figure 28). Note that insulating layer 171b is the insulating layer 173 Under the same CMP processing conditions, the polishing rate is low, i.e., the machine acts as a stopper. It is preferable that it has the ability.

[0293] Next, a resist mask is applied to the insulating layer 173 and the insulating layer 171b by lithography. Formed, and further using the insulating layer 171b as a hard mask, until the semiconductor layer 122 is exposed. This selectively etches a portion of the conductive layer 130b. This removes the source electrode layer 130 and A drain electrode layer 140 and an insulating layer 175 are formed (see Figure 29).

[0294] Next, the second insulating film 123a, insulating film 150a, and conductive film 160a are sequentially deposited (Figure 3). (See reference 0).

[0295] Next, the conductive film 160a, the insulating film 150a, and the second insulating film 123a are subjected to a planarization treatment. This process forms the insulator 123, gate insulating layer 150, and gate electrode layer 160 (see Figure 31). (see).

[0296] Next, an insulating layer 170 is formed and heat treatment is performed to allow oxygen 172 to reach the semiconductor layer 122. This allows for diffusion and reduces oxygen vacancies in the semiconductor layer 122 (see Figure 32).

[0297] By following the above steps, transistor 12 can be manufactured.

[0298] In the method for fabricating transistor 12, an insulating film 175a which will become the insulating layer 175 is made of source electrode layer 1 30. The conductive film 130a, which will become the drain electrode layer 140, can be formed before processing. Therefore, the thickness of the insulating film 175a can be made uniform within the substrate surface, and the groove portion 174 is formed. The switching processing time can be stabilized. This allows the transistor 12 to be stabilized. It can be manufactured and the shape of the transistor can be stabilized. Therefore, Rangitor characteristics (e.g., threshold, reliability, etc.) can also be stabilized.

[0299] This embodiment can be appropriately combined with other embodiments shown herein. .

[0300] (Embodiment 3) <Oxide semiconductor structure> This embodiment describes the structure of an oxide semiconductor.

[0301] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors (such as ke Oxide Semiconductors).

[0302] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. They can be divided into conductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC-O Examples include S, polycrystalline oxide semiconductors, and nc-OS.

[0303] Generally, an amorphous structure is defined as a structure that is not fixed in a metastable state and is isotropic. It is known that it does not have a heterogeneous structure. Also, the bond angles are flexible and short distance It can also be described as a structure that possesses order but lacks long-range order.

[0304] Conversely, in the case of oxide semiconductors, which are inherently stable, a completely amorphous (complete) semiconductor is possible. It cannot be called an oxide semiconductor (ely amorphous). Furthermore, it is not isotropic. For example, an oxide semiconductor (having a periodic structure in a minute region) is made of a completely amorphous oxide It cannot be called a semiconductor. However, a-like OS exhibits periodicity in a minute region. Although it has a structure, it is unstable due to its porous (also called void) nature. Therefore, In terms of physical properties, it can be said to be similar to an amorphous oxide semiconductor.

[0305] <caac-os> First, let me explain CAAC-OS.

[0306] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0307] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS occurs at the grain boundaries. This means that a decrease in electron mobility due to this is less likely to occur.

[0308] The following describes CAAC-OS as observed by TEM. Figure 33(A) shows, This shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The Corrector function was used. High-resolution TEM images using spherical aberration correction were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM images is, for example, done in Japan. This is performed using an atomic-resolution analytical electron microscope, such as the JEM-ARM200F, manufactured by this electronics company. It is possible.

[0309] Figure 33(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 33(A). Figure 33(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is such that the surface forming the CAAC-OS film (also called the surface to be formed) Alternatively, it reflects the irregularities of the upper surface and is parallel to the surface or upper surface of the CAAC-OS that is formed.

[0310] As shown in Figure 33(B), CAAC-OS has a characteristic atomic arrangement. Figure 33(C) The characteristic atomic arrangement is shown with auxiliary lines. Figures 33(B) and 33(C) Furthermore, the size of a single pellet can be 1 nm or larger, or 3 nm or larger. It can be seen that the size of the gap created by the tilt between the pellet and the material is approximately 0.8 nm. Therefore, pellets can also be called nanocrystals (nc). Also, CAAC-OS is CANC(C-Axis Aligned nanocry It can also be called an oxide semiconductor containing stals.

[0311] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the To 5100 can be schematically represented as a structure resembling stacked bricks or blocks. (See Figure 33(D).) The tilt between the pellets observed in Figure 33(C) The area where the condensation is occurring corresponds to region 5161 shown in Figure 33(D).

[0312] Furthermore, Figure 34(A) shows the Cs in the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 34(A). Magnified Cs-corrected high-resolution TEM images are shown in Figures 34(B), 34(C), and 34(C), respectively. As shown in 34(D). From Figures 34(B), 34(C), and 34(D), the pellets are It can be confirmed that metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0313] Next, the CA was analyzed by X-ray diffraction (XRD). Let's discuss AC-OS. For example, CAAC-OS, which has an InGaZnO4 crystal. In contrast, when structural analysis is performed using the out-of-plane method, as shown in Figure 35(A)... In some cases, a peak may appear at a diffraction angle (2θ) near 31°. This peak is in InGaZ Since it is attributed to the (009) plane of the nO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0314] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31°. In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak indicates that some of the crystals in CAAC-OS do not have c-axis orientation. This indicates that the more preferable CAAC-OS is the structural solution by the out-of-plane method. Analysis revealed a peak around 31° for 2θ, but no peak around 36° for 2θ.

[0315] On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 35(B). Furthermore, if it is a single-crystal oxide semiconductor of InGaZnO4, then fixing 2θ to around 56°, φs If this occurs, the crystal plane is assigned to the equivalent of the (110) plane, as shown in Figure 35(C). Six lines are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0316] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe with a diameter of 300 nm is placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern like the one shown in Figure 36(A) (limited field transmission electron diffraction) is produced. Sometimes a pattern (also called a diffraction pattern) may appear. This diffraction pattern is indicative of InGaZnO4. The spot originates from the (009) plane of the crystal. Therefore, electron diffraction also reveals... The pellets contained in CAAC-OS have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be seen that it is oriented in a vertical direction. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. Figure 36(B) shows the diffraction pattern when an electron beam with a diameter of 300 nm is incident on the surface. Figure 36 (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also shows that It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. Note that the first ring in Figure 36(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be caused by the (100) surface, etc. Also, the second ring in Figure 36(B) is (110) This is thought to be caused by the surface, etc.

[0317] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity can decrease due to the inclusion of impurities or the formation of defects, so the opposite perspective is needed. CAAC-OS can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0318] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0319] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers It can become a source of emissions. Furthermore, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, it may act as a carrier source by capturing hydrogen.

[0320] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than, More preferably 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 The above career It can be made into a high-density oxide semiconductor. Such an oxide semiconductor can be made into a high-purity intrinsic or It is essentially a high-purity, intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and defects. It has a low energy level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0321] <nc-os> Next, I will explain nc-OS.

[0322] nc-OS is a region in which the crystalline part can be confirmed in high-resolution TEM images, and is clearly It has regions where the crystalline portion cannot be confirmed. The crystalline portion contained in nc-OS is They are often between 1 nm and 10 nm in size, or between 1 nm and 3 nm. Oxide semiconductors with a crystal size greater than 10 nm and less than or equal to 100 nm are subjected to microcrystalline oxidation. It is sometimes called a solid semiconductor. nc-OS, for example, in high-resolution TEM images, shows grain boundaries. It may not be possible to confirm this clearly. Furthermore, nanocrystals are the pellets in CAAC-OS. They may share the same origin. Therefore, in the following, the crystalline portion of nc-OS will be referred to as a pellet. There are cases where this happens.

[0323] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS can be classified as a-like OS or amorphous oxide semiconductor. In some cases, it may be difficult to distinguish between them. For example, with nc-OS, X has a larger diameter than the pellet. When using lines, out-of-plane analysis detects peaks that indicate crystal planes. It is not released. Also, for nc-OS, a probe diameter larger than the pellet (e.g., 50n) is required. When electron diffraction is performed using an electron beam (of m or greater), a diffraction pattern similar to a halo pattern can be observed. It is measured. On the other hand, compared to nc-OS, the size is close to or smaller than the pellet size. When nanobeam electron diffraction is performed using an electron beam of a certain diameter, spots can be observed. When nanobeam electron diffraction is performed on c-OS, a high-brightness ring-shaped pattern is observed. A region may be observed. Furthermore, multiple spots may be observed within a ring-shaped region. There are cases where this is the case.

[0324] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ).

[0325] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0326] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0327] a-like OS may exhibit porosity in high-resolution TEM images. In the high-resolution TEM image, there are regions where the crystalline structure can be clearly identified, and regions where the crystalline structure cannot be identified. It has areas that cannot be accessed.

[0328] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0329] The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS ( Prepare Sample B (referred to as Sample B) and CAAC-OS (referred to as Sample C). The sample is also an In-Ga-Zn oxide.

[0330] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts.

[0331] The determination of which part should be considered a single crystal can be made as follows. For example, The unit cell of an InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which 6 layers, totaling 9 layers, are stacked in layers along the c-axis. The spacing between adjacent layers is approximately the same as the spacing between grid planes (also called the d value) of the (009) plane. Yes, and its value has been determined to be 0.29 nm from crystal structure analysis. Therefore, the lattice fringes Areas with a spacing of 0.28 nm or more and 0.30 nm or less are considered to be the crystalline regions of InGaZnO4. This can be done. Note that the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0332] Figure 37 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 37, a-lik It can be seen that the crystalline portion of eOS increases in proportion to the cumulative amount of electron irradiation. As shown in (1) in Figure 37, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the initial nucleus), which was initially 4.2 × 10¹⁶ in size, changed when the cumulative irradiation dose reached 4.2 × 10¹⁶. 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS And CAAC-OS has a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. Specifically, Figure As shown in (2) and (3) of 37, regardless of the cumulative dose of electrons, nc-OS and The size of the crystalline portion of CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively. It becomes clear that...

[0333] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It can be seen that it cannot be seen. That is, a-like OS is nc-OS and CAAC-O Compared to S, it is clear that it has an unstable structure.

[0334] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0335] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0336] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, the density equivalent to that of a single crystal at a desired composition can be estimated. This is possible. The density corresponding to a single crystal of the desired composition can be obtained by combining single crystals of different compositions. The proportion can be estimated using a weighted average. However, the density should be as small as possible. It is preferable to estimate by combining different types of single crystals.

[0337] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0338] (Embodiment 4) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. I will explain by referring to it.

[0339] <Cross-sectional structure> Figure 38(A) shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention. In Figure 38(A), X The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. Figure 38(A) The semiconductor device shown has a transistor 2200 made of a first semiconductor material at the bottom, and above The part has a transistor 2100 using a second semiconductor material. In Figure 38(A), As a transistor 2100 using a second semiconductor material, the transistor exemplified in the previous embodiment is An example of applying a transistor is shown. Note that the part to the left of the dashed line is the transistor channel. The image shows a cross-section in the longitudinal direction, with the right side representing a cross-section in the channel width direction.

[0340] It is preferable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). Germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide (e.g., gallium phosphate, indium phosphide, gallium nitride, organic semiconductors), and the second semiconductor The main material can be an oxide semiconductor. Other materials besides oxide semiconductors include single-crystal silicon Transistors using materials such as semiconductors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors By applying the transistor exemplified in the previous embodiment, an excellent sub A threshold characteristic is obtained, making it possible to create a miniature transistor. The fast switch speed enables high-speed operation, and the low off-current results in low leakage current.

[0341] Transistor 2200 is an n-channel type transistor or a p-channel type transistor. Either type of transistor is acceptable, and the appropriate transistor should be used depending on the circuit. Aside from using a transistor according to one embodiment of the present invention that uses a synthetic semiconductor, the materials and structure used are as follows: However, it is not necessary to limit the specific configuration of the semiconductor device shown here to what is presented.

[0342] In the configuration shown in Figure 38(A), an insulator 2201 and an insulator are placed on top of the transistor 2200. Transistor 2100 is provided via 2207. Also, transistor 2200 Multiple wires 2202 are provided between the transistor 2100 and the transistor. Multiple plugs 2203 embedded in the rim allow wiring to be provided in the upper and lower layers, respectively. The electrodes are electrically connected. Also, the insulator 2204 covering the transistor 2100 and Wiring 2205 and a sintered material are provided on the insulator 2204.

[0343] In this way, by stacking two types of transistors, the circuit footprint is reduced. Multiple circuits can be arranged at a higher density.

[0344] In this case, if a silicon-based semiconductor material is used for the transistor 2200 located in the lower layer, Hydrogen in the insulator placed near the semiconductor film of transistor 2200 is in the silicon dung. This terminates the ring bond and improves the reliability of transistor 2200. On the other hand, When an oxide semiconductor is used for the transistor 2100 located in the upper layer, transistor 21 Hydrogen in the insulator placed near the semiconductor film generates carriers in the oxide semiconductor. This can be one of the contributing factors, and therefore can reduce the reliability of transistor 2100. Therefore, an oxide layer is found on the upper layer of the transistor 2200 using silicon-based semiconductor material. When stacking transistors 2100 made of solid semiconductor material, hydrogen diffusion occurs between them. It is particularly effective to provide an insulator 2207 that has the function of preventing this. As a result of step 7, the reliability of transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, which affects transistor 2100. Reliability can also be improved at the same time.

[0345] Examples of insulators 2207 include aluminum oxide, aluminum oxide nitride, and gallium oxide. M, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, acid Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0346] Furthermore, the transistor 2100, which is composed of an oxide semiconductor film, is covered by the transistor It is preferable to form a blocking film on the sta 2100 that has the function of preventing hydrogen diffusion. i. The block film can be made of the same material as the insulator 2207, and is particularly acidic. It is preferable to apply an aluminum oxide film. The aluminum oxide film is resistant to hydrogen, moisture, etc. It has a high blocking effect, preventing both impurities and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the block film covering the transistor 2100. This prevents the desorption of oxygen from the oxide semiconductor film contained in transistor 2100. Furthermore, it is possible to prevent the contamination of the oxide semiconductor film with water and hydrogen. The block film may be used by laminating insulator 2204, or under insulator 2204 It may be placed on the side.

[0347] Note that the 2200 transistor is not only a planar type transistor, but also various types It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of the cross-sectional view in that case is shown in FIG. 38(D). An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not have to be thin at the tip. For example, it may be a substantially rectangular parallelepiped convex portion or a thick convex portion at the tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. Although an example in which the semiconductor substrate 2211 has a convex portion has been shown here, the semiconductor device according to one aspect of the present invention is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0348] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0349] <CMOS inverter circuit> The circuit diagram shown in FIG. 38(B) is a so-called CMO in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. This shows the configuration of the S-inverter.

[0350] <CMOSアナログスイッチ> Furthermore, the circuit diagram shown in Figure 38(C) shows the relationship between transistor 2100 and transistor 2200. This shows a configuration where the source and drain are connected. With this configuration, It can function as a so-called CMOS analog switch.

[0351] <Example of a storage device> Using a transistor according to one aspect of the present invention, the stored contents can be preserved even when power is not supplied. Figure 39 shows an example of a semiconductor device (memory device) that can be stored and has no limit on the number of write cycles. This will be shown.

[0352] The semiconductor device shown in Figure 39(A) comprises a transistor 3200 using a first semiconductor material and a second It has a transistor 3300 and a capacitive element 3400 made of two semiconductor materials. Note that the transistor 3300 is one of the transistors described in Embodiments 1 and 2. It is possible to be there.

[0353] Figure 39(B) shows a cross-sectional view of the semiconductor device shown in Figure 39(A). Now, the configuration shown has a back gate added to transistor 3300, but the back gate A configuration without this feature is also acceptable.

[0354] Transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. The 3300 transistor has a low off-current, so by using it... It is possible to retain memory content for a long period of time. In other words, it does not require a refresh operation. To avoid this, or to create a semiconductor memory device with an extremely low refresh frequency. This makes it possible to significantly reduce power consumption.

[0355] In Figure 39(A), the first wiring 3001 is connected to the source electrode of transistor 3200 and electrical The second wire 3002 is electrically connected to the drain electrode of transistor 3200. It is continued. Also, the third wiring 3003 is the source electrode or of transistor 3300. Electrically connected to one of the rain electrodes, the fourth wire 3004 is connected to the gate of transistor 3300. It is electrically connected to the electrode. And the gate electrode of transistor 3200 is The source electrode or drain electrode of the transistor 3300, and the other of the capacitive element 3400 The fifth wire 3005 is electrically connected to one of the electrodes, and the other electrode of the capacitive element 3400 is connected to the other electrode. They are electrically connected.

[0356] In the semiconductor device shown in Figure 39(A), the potential of the gate electrode of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, retain, and read information in the following ways: ru.

[0357] This section will explain how to write and retain information. First, the potential of the fourth wiring 3004 is set to the traction control. The potential is set to the ON state for transistor 3300, thereby turning on transistor 3300. As a result, the potential of the third wiring 3003 is the same as the gate electrode of transistor 3200, and And is supplied to the capacitance element 3400. That is, the gate electrode of transistor 3200 is A predetermined charge is applied (written). Here, a charge that gives two different potential levels. (Hereafter referred to as Low-level charge and High-level charge) Then, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is in an off state, and by turning off the transistor 3300, the charge applied to the gate electrode of the transistor 3200 is held (retained). Since the off-current of the transistor 3300 is extremely small, the charge on the gate of the transistor 3200 is retained for a long time.

[0358]

[0359] Next, information reading will be described. When a predetermined potential (constant potential) is applied to the first wiring 3001 and an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring 3002 takes on different potentials according to the amount of charge held on the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold value V when a High-level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold value V when a Low-level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage is defined as the potential of the fifth wiring 3005 required to turn the transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between V and V th_H th_L the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, if a High-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 becomes "on". If a Low-level charge was applied, the potential of the fifth wiring 3005 th_L th_H ​ The rank is V0( <V th_L Even if this happens, transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the information being held can be read. It can be released.

[0360] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output. For example, in a memory cell that does not read information, the gate electric current Regardless of the polarity, the potential at which transistor 3200 is in the "off state" is, that is, V th_H By applying a smaller potential to the fifth wiring 3005, the desired information of the memory cell is obtained. The configuration should allow only the data to be read. Alternatively, in memory cells from which no information is read... Regardless of the gate electrode state, the potential at which transistor 3200 is in the "on state" , in other words, V th_L By applying a higher potential to the fifth wiring 3005, the desired memory The system should be configured to allow only the cell's information to be read.

[0361] The semiconductor device shown in Figure 39(C) is different from the one shown in Figure 39(A) in that it does not have transistor 3200. ) is different. In this case as well, the information writing and retention operations are performed in the same manner as above. It is possible.

[0362] Next, we will explain how to read the information. When transistor 3300 is turned on, floating The third wiring 3003, which is in a free state, and the capacitive element 3400 are electrically connected, and the third wiring 3003 and Charge is redistributed among the capacitive elements 3400. As a result, the potential of the third wiring 3003 changes. The change in the potential of the third wiring 3003 is the same as the potential of one electrode of the capacitive element 3400. Alternatively, it takes on different values ​​depending on the charge stored in the capacitive element 3400.

[0363] For example, let V be the potential of one electrode of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and the third The capacitance component of wiring 3003 is CB, and the charge of the third wiring 3003 before redistribution is CB If the potential is VB0, then the potential of the third wiring 3003 after the charge has been redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, the state of the memory cell is the capacity element If one of the electrodes of the child 3400 takes on two states, V1 and V0 (V1 > V0), then The potential of the third wiring 3003 when position V1 is maintained is (=(CB×VB0+C×V1)) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=(C) It can be seen that this is higher than B × VB0 + C × V0) / (CB + C)).

[0364] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information is read out. It is possible.

[0365] In this case, the first semiconductor material described above was applied to the drive circuit for driving the memory cell. A transistor is used, and a second semiconductor material is applied to transistor 3300. The zistas can be stacked on top of the drive circuit.

[0366] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0367] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0368] In this specification, active elements (transistors, diodes, etc.), passive elements ( For all terminals of capacitive elements, resistive elements, etc., the destination of their connection is not specified. However, a person skilled in the art may be able to constitute one aspect of the invention. In other words, connection Even without specifying the destination, one aspect of the invention can be said to be clear. And the connection destination is specified. If the content is described in this specification, etc., then one aspect of the invention that does not specify the connection destination is described in this specification. In some cases, it can be determined that this is stated in the document or other documentation. In particular, multiple terminals are used as connection destinations. When multiple cases are possible, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistors) are distinct. By specifying the connection destination for only some of the terminals (such as those on an element), It may be possible to constitute one aspect of the invention.

[0369] Furthermore, in this specification, etc., if a certain circuit is specified, then at least the connection destination is identified, and this applies to our business. If you are an expert, you may be able to identify the invention. Or, regarding a certain circuit, However, if the function is specified, a person skilled in the art may be able to specify the invention. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even without specifying the function of a certain circuit, if the connection destination is specified, it constitutes an invention. It is disclosed as such and can constitute one aspect of the invention. Regarding a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. This has been disclosed and can constitute one aspect of the invention.

[0370] In this specification, etc., the figures or text described in a particular embodiment may differ from the actual figures or text. Therefore, it is possible to take a part of it and constitute one aspect of the invention. If a diagram or text describing a part is included, remove a portion of that diagram or text. The information provided is disclosed as one aspect of the invention and constitutes one aspect of the invention. It is assumed that this is possible. For example, active elements (transistors, diodes) (etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings that describe one or more materials, inorganic materials, parts, devices, operating methods, manufacturing methods, etc. Alternatively, it is possible to extract a part of a document and use it to constitute one aspect of the invention. It is assumed that, for example, there are N (N is an integer) circuit elements (transistors, capacitor elements, etc.). From a circuit diagram constituted by having M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) extracted from a circuit diagram constituted by having N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to constitute one aspect of the invention. As another example, from a cross-sectional view constituted by having N (N is an integer) layers, it is possible to constitute one aspect of the invention by extracting M (M is an integer, M < N) layers. As yet another example, from a flowchart constituted by having N (N is an integer) elements, it is possible to constitute one aspect of the invention by extracting M (M is an integer, M < N ) elements. (N is an integer).

[0371] <Imaging device> Hereinafter, an imaging device according to one aspect of the present invention will be described.

[0372] FIG. 40(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 has a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel section 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 each have a function of connecting to a plurality of pixels 211 and supplying signals for driving the plurality of pixels 211. In the present specification and the like, all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as a "peripheral circuit" or a "driving circuit". For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0373] Furthermore, it is preferable that the imaging device 200 has a light source 291. The light source 291 is a detection light P It can emit 1.

[0374] Furthermore, the peripheral circuits include at least logic circuits, switches, buffers, amplification circuits, or converters. It has one of the circuits. Furthermore, the peripheral circuits may be formed on the substrate forming the pixel section 210. Furthermore, semiconductor devices such as IC chips may be used in part or all of the peripheral circuits. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 290. You may omit one or more of the following:

[0375] Furthermore, as shown in Figure 40(B), in the pixel section 210 of the imaging device 200, Pixels 211 may be arranged at an angle. By arranging pixels 211 at an angle, the row direction and The pixel spacing (pitch) in the column direction can be shortened. This allows the imaging device 200 to This allows for a further improvement in the quality of the images being captured.

[0376] <Example of pixel configuration 1> The imaging device 200 has one pixel 211 which is composed of multiple sub-pixels 212, and each sub A filter (color filter) that transmits light in a specific wavelength range is combined with pixel 212. This allows us to obtain the information necessary to display color images.

[0377] Figure 41(A) is a plan view showing an example of pixels 211 for acquiring a color image. Pixel 211 shown in 41(A) is equipped with a color filter that transmits light in the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") emits light in the green (G) wavelength band. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. Sub-pixel 212 is provided with a color filter that transmits light in the wavelength bands of (u) and blue (B). It has (hereinafter also referred to as "sub-pixel 212B"). The sub-pixel 212 is a photosensor It can be made to work.

[0378] Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are connected to wiring 23 1. It is electrically connected to wires 247, 248, 249, and 250. Pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected by independent wiring 25 It is connected to 3. Also, in this specification, for example, the nth row (where n is an integer between 1 and p). Wirings 248 and 249 connected to pixel 211 of ) are respectively wired 248[n] And it is written as wiring 249[n]. Also, for example, the mth column (where m is an integer between 1 and q) The wiring 253 connected to pixel 211 is denoted as wiring 253[m]. Note that in Figure 41(A In this case, wiring 253 is connected to the sub-pixel 212R of the m-th pixel 211. Wiring 253[m]G connects to sub-pixel 212G, and sub-pixel 53[m]R, wiring 253[m]G, and sub-pixel The wiring 253 connected to element 212B is described as wiring 253[m]B. Sub-pixel 212 is It is electrically connected to the surrounding circuitry via the above wiring.

[0379] Furthermore, the imaging device 200 transmits light of the same wavelength band to adjacent pixels 211. The sub-pixels 212, each equipped with a filter, are electrically connected to each other via a switch. Figure 41(B) shows the sub-pixels 212 of the pixel 211 arranged in n rows and m columns, and the pixel 2 This shows an example of the connection of subpixels 212 of pixel 211, which is located in row n+1 and column m adjacent to pixel 11. In Figure 41(B), subpixels 212R are arranged in row n and column m, and subpixels are arranged in row n+1 and column m. The sub-pixels 212R are connected via switch 201. Also, arranged in n rows and m columns The sub-pixel 212G placed and the sub-pixel 212G arranged in row n+1 and column m are switched 202 They are connected via [a certain method]. Also, the subpixels 212B are located in n rows and m columns, and the subpixels are located in n+1 rows and m columns. The sub-pixel 212B located there is connected via switch 203.

[0380] Furthermore, the color filters used for sub-pixel 212 are limited to red (R), green (G), and blue (B). Color film that transmits cyan (C), yellow (Y), and magenta (M) light respectively. A LUTA may be used. A sub-pixel detects light of three different wavelength bands in one pixel 211. By adding 212, it is possible to acquire a full-color image.

[0381] Alternatively, color filters that transmit red (R), green (G), and blue (B) light, respectively, are provided. In addition to the sub-pixels 212 that have been cut off, a sub-pixel with a color filter that transmits yellow (Y) light is provided. A pixel 211 having pixel 212 may be used. Alternatively, cyan (C) and yellow (Y) may be used, respectively. In addition to sub-pixels 212 equipped with a color filter that transmits ) and magenta (M) light, A pixel 21 has a sub-pixel 212 that is provided with a color filter that transmits blue (B) light. 1 may be used. Sub-pixels 2 detect light of four different wavelength bands in one pixel 211. By adding 12, the color reproduction accuracy of the acquired image can be further improved.

[0382] Furthermore, for example, in Figure 41(A), sub-pixel 212 detects the red wavelength band, and the green wavelength The ratio of the number of sub-pixels 212 that detect the bandwidth and the sub-pixels 212 that detect the blue wavelength bandwidth ( The pixel ratio (or light-receiving area ratio) does not have to be 1:1:1. For example, the pixel ratio (light-receiving area ratio) Alternatively, a Bayer array with red:green:blue = 1:2:1 may be used. Or, the pixel ratio (received The light area ratio can also be set to red:green:blue = 1:6:1.

[0383] Note that while one sub-pixel 212 may be provided in pixel 211, two or more are preferable. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the 200 unit.

[0384] Furthermore, IR (Infrared) absorbs or reflects visible light and transmits infrared light. By using a filter, an imaging device 200 that detects infrared light can be realized.

[0385] Also, an ND (Neutral Density) filter (light-reducing filter) is used. This is because when a large amount of light is incident on a photoelectric conversion element (light-receiving element), the output saturation occurs. This can prevent this. By using a combination of ND filters with different light reduction amounts, the imaging device This allows for a wider dynamic range in the image.

[0386] In addition to the filter mentioned above, a lens may also be provided at pixel 211. Here, Figure 42 An example of the arrangement of pixels 211, filter 254, and lens 255 will be explained using a cross-sectional diagram. By providing the 255 element, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in Figure 42(A), a lens 255 and a filter 25 are formed on the pixel 211. 4 (filters 254R, 254G, and 254B), and pixel circuit 2 The structure can be configured to allow light 256 to be incident on the photoelectric conversion element 220 through 30, etc.

[0387] However, as shown in the area enclosed by the dashed line, a portion of the light 256 indicated by the arrow is connected to wiring 257. It may be partially blocked by something. Therefore, as shown in Figure 42(B), the photoelectric The lens 255 and filter 254 are placed on the side of the conversion element 220, and the photoelectric conversion element 220 A structure that efficiently receives light 256 is preferred. Light 256 is received from the photoelectric conversion element 220 side. By injecting the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. It is possible.

[0388] As shown in Figure 42, the photoelectric conversion element 220 has a pn-type junction or a pin-type junction formed on it. Photoelectric conversion elements may also be used.

[0389] Furthermore, the photoelectric conversion element 220 uses a material that has the function of absorbing radiation and generating electric charge. It may be formed by absorbing radiation and generating an electric charge. Len, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy These include:

[0390] For example, if selenium is used in the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 having an optical absorption coefficient across a wide wavelength range, including X-rays and gamma rays. We can achieve 20.

[0391] Here, one pixel 211 of the imaging device 200 is, in addition to the sub-pixel 212 shown in Figure 41, Furthermore, it may have a sub-pixel 212 having a first filter.

[0392] <Example of pixel configuration 2> Below, we will discuss transistors using silicon and transistors using oxide semiconductors. An example of how pixels are constructed using this method will be explained.

[0393] Figures 43(A) and 43(B) are cross-sectional views of the elements that make up the imaging device.

[0394] The imaging device shown in Figure 43(A) is a silicon-based transistor provided on a silicon substrate 300. Transistor 351, Transistor 351 with an oxide semiconductor stacked on top of it Transistor 352 and transistor 353, and provided on the silicon substrate 300, Includes a photodiode 360 ​​having an anode 361 and a cathode 362. The sta and photodiode 360 ​​are electrically connected to various plugs 370 and wiring 371. It has a connection. Also, the anode 361 of the photodiode 360 ​​has a low resistance region 363. It has an electrical connection to plug 370 via this.

[0395] The imaging device also includes a transistor 351 and a photodie provided on the silicon substrate 300. A layer 310 having an ore 360, and a layer 3 provided in contact with the layer 310 and having wiring 371 20 is provided in contact with layer 320 and has transistors 352 and 353. A layer 330, and a layer 330 provided in contact with the layer 330, having wiring 372 and wiring 373. It has 40.

[0396] In addition, in the example cross-sectional view in Figure 43(A), transistor 3 is located on the silicon substrate 300. The configuration includes a photodiode 360 ​​with a light-receiving surface on the side opposite to the surface where 51 is formed. This configuration ensures that the optical path is not affected by various transistors, wiring, etc. This allows for the formation of pixels with a high aperture ratio. The light-receiving surface of D360 can also be the same as the surface on which transistor 351 is formed.

[0397] Furthermore, when constructing pixels using only transistors made of oxide semiconductors, layer 31 Layer 0 can be a layer containing a transistor made of oxide semiconductor. Alternatively, layer 310 can be omitted. In short, pixels may be constructed using only transistors made of oxide semiconductors.

[0398] Furthermore, in the cross-sectional view of Figure 43(A), the photodiode 360 ​​provided in layer 310 and layer The transistors provided at 330 can be formed to overlap with the pixels. This allows for an increase in the integration density, that is, an increase in the resolution of the imaging device.

[0399] Furthermore, Figure 43(B) shows that the imaging device has a photodiode 365 on the layer 340 side and a transistor It can be a structure placed on top of. In Figure 43(B), for example, layer 310 is It has a silicon transistor 351 and a silicon transistor 352, and layer 320 has wiring 3 71 has a transistor 352 and transistor 35, which use an oxide semiconductor in layer 330. It has 3, and layer 340 has a photodiode 365, and the photodiode 365 is It consists of semiconductor layer 366, semiconductor layer 367, and semiconductor layer 368, and wiring 373 and It is electrically connected to wiring 374 via lug 370.

[0400] By using the element configuration shown in Figure 43(B), the aperture ratio can be increased.

[0401] Furthermore, the photodiode 365 uses amorphous silicon film, microcrystalline silicon film, etc. A pin-type diode element may also be used. The photodiode 365 is an n-type semiconductor. A configuration in which layer 368, i-type semiconductor layer 367, and p-type semiconductor layer 366 are stacked in order. It has. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. Also, The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are given their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a carboxylate can be used. Photodiode 365, which uses silicon as its photoelectric conversion layer, has sensitivity in the visible light wavelength range. It is highly sensitive and can easily detect weak visible light.

[0402] This embodiment can be appropriately combined with other embodiments shown herein. .

[0403] (Embodiment 5) <RFタグ> In this embodiment, an RF including a transistor or memory device as described in the previous embodiment is used. Tags will be explained with reference to Figure 44.

[0404] The RF tag in this embodiment has a memory circuit inside, and stores the necessary information in the memory circuit. Furthermore, it uses non-contact means, such as wireless communication, to exchange information with the outside world. Due to its characteristics, RF tags are used to identify items by reading individual information about those items. It can be used in body recognition systems, etc. However, in order to use it for these purposes, For the first time, a high level of reliability is required.

[0405] The configuration of an RF tag will be explained using Figure 44. Figure 44 shows an example of an RF tag configuration. This is a lock diagram.

[0406] As shown in Figure 44, the RF tag 800 is connected to the communicator 801 (also known as an interrogator, reader / writer, etc.). Antenna 8 receives a radio signal 803 transmitted from antenna 802 connected to ( It has 04. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit 8 It has a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the reverse current in the rectifying transistor included in the demodulation circuit 807 is sufficiently suppressed. A configuration may be made using a material capable of doing so, for example, an oxide semiconductor. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This can be prevented. In other words, the output of the demodulation circuit can be made more linear with respect to the input of the demodulation circuit. It is possible. Furthermore, the data transmission format involves a pair of coils positioned opposite each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that use induced electromagnetic fields for communication, and methods that use radio waves for communication. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment uses any of these methods. It can also be used for this purpose.

[0407] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. This is a circuit for generating input potential by converting it. Furthermore, the input side of the rectifier circuit 805 is also A limiter circuit may be provided on the output side. A limiter circuit is a circuit that limits the amplitude of the input AC signal. When the internally generated voltage is large, do not input power exceeding a certain level to the subsequent circuit. This is a circuit for controlling sea urchins.

[0408] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80. This is a circuit for generating a reset signal for number 9.

[0409] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation.

[0410] Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose.

[0411] Furthermore, the circuits described above can be selected or omitted as appropriate.

[0412] Here, the transistor described in the previous embodiment can be used in the memory circuit 810. A transistor according to one aspect of the present invention can retain information even when the power supply is cut off. Therefore, it can be suitably used in RF tags. Furthermore, a memory circuit according to one aspect of the present invention is Because the power (voltage) required to write data is significantly lower than that of conventional non-volatile memory. It is also possible to avoid any difference in the maximum communication distance between data reading and writing. Furthermore, it suppresses malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible.

[0413] Furthermore, a memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will provide data to ROM811. A separate command is provided for writing the data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Instead of assigning a unique number to every RF tag produced, only the good quality tags that are shipped will have a unique number assigned to them. It becomes possible to assign a unique number, and the unique numbers of products after shipment will not be discontinuous. This eliminates the need for post-shipment customer management, making it easier to handle customer issues related to products after they have been shipped.

[0414] This embodiment can be appropriately combined with other embodiments shown herein. .

[0415] (Embodiment 6) This embodiment describes a CPU including the storage device described in the previous embodiment.

[0416] Figure 45 shows a CPU that uses at least some of the transistors described in the previous embodiment. This is a block diagram showing the example configuration.

[0417] <cpu> The CPU shown in Figure 45 is an ALU1191 (ALU: Arithmet) mounted on board 1190. IC logic unit, arithmetic circuit, ALU controller 1192, instruction Timing decoder 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface 1 It has 198, a rewritable ROM 1199, and a ROM interface 1189. The substrate 1190 uses semiconductor substrates, SOI substrates, glass substrates, etc. ROM1 199 and the ROM interface 1189 may be provided on a separate chip. Of course, The CPU shown in Figure 45 is merely one example of a simplified configuration; an actual CPU is different. They have a wide variety of configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 45. A configuration including this is considered one core, and there are multiple such cores, with each core operating in parallel. This configuration is also acceptable. Furthermore, the number of bits that the CPU can handle in its internal arithmetic circuits and data bus is: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0418] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0419] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal. Also, the interrupt controller 1194 controls the CPU's program. During execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and masking. The system makes a judgment and processes based on the state. The register controller 1197 determines the address of register 1196. It generates a value and reads or writes to register 1196 depending on the CPU state.

[0420] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0421] In the CPU shown in Figure 45, a memory cell is located in register 1196. The transistors shown in Embodiments 1 to 3 can be used as the 1196 memory cells. can.

[0422] In the CPU shown in Figure 45, the register controller 1197 receives information from the ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 11 In the memory cell of 96, data is retained by a flip-flop, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will not occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. .

[0423] <Recording Circuit> Figure 46 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data is lost when the power is cut off, and a memory element 1200 which loses stored data when the power is cut off. A circuit 1202 that prevents data from volatilizing, a switch 1203, a switch 1204, and a logic element It comprises a sub-element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. 1202 consists of the capacitive element 1208, transistor 1209, and transistor 1210. It has a diode, a resistor, an inductor, etc., as needed. It may also have other elements such as a t-axis.

[0424] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 120 of circuit 1202 The gate of transistor 9 is input to ground potential (0V) or a potential that turns off transistor 1209. The configuration will continue to be such that the first gate of transistor 1209 is connected via a load such as a resistor. The configuration will be grounded.

[0425] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to either the source electrode or the drain electrode of transistor 1213, and switch 120 The second terminal of 3 corresponds to the source electrode and the other of the drain electrode of transistor 1213, Switch 1203 is controlled by the control signal RD input to the gate of transistor 1213. Continuity or non-conductivity between terminal 1 and terminal 2 (i.e., the ON state of transistor 1213) The state (on or off) is selected. The first terminal of switch 1204 is connected to transistor 121 Corresponding to either the source electrode or the drain electrode of 4, the second terminal of switch 1204 is the transistor Corresponding to the source electrode and the other drain electrode of the zista 1214, switch 1204 is a transistor The control signal RD input to the gate of the ZISTA 1214 controls the first terminal and the second terminal. The conduction or non-conductivity between them (i.e., the on or off state of transistor 1214) is selected. It will be selected.

[0426] One of the source and drain electrodes of transistor 1209 is connected to a pair of capacitive elements 1208. One of the electrodes is electrically connected to the gate of transistor 1210. The connection point is designated as node M2. One of the source and drain electrodes of transistor 1210 One side is electrically connected to wiring capable of supplying a low power potential (e.g., a GND wire), The other side is the first terminal of switch 1203 (source electrode and drain of transistor 1213). It is electrically connected to the second terminal of switch 1203 (transistor 12). 13 source electrodes and the other drain electrode) are connected to the first terminal (transistor) of switch 1204 It is electrically connected to one of the source and drain electrodes of the 1214. Switch 120 The second terminal of 4 (the other of the source and drain electrodes of transistor 1214) is at the power supply potential. The second end of switch 1203 is electrically connected to wiring capable of supplying VDD. The child (the source electrode and the other drain electrode of transistor 1213) and switch 1204 The first terminal (one of the source and drain electrodes of transistor 1214) and logic element 1 The input terminal 206 and one of the pair of electrodes of the capacitive element 1207 are electrically connected. Here, the connection point is called node M1. Of the pair of electrodes of the capacitive element 1207, the other This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 120 The other of the pair of electrodes in 7 is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to the wire. The other of the pair of electrodes of the capacitive element 1208 is at a constant potential. The configuration can be configured to accept inputs such as low power supply potential (GND, etc.) or high power supply potential. A configuration can be made in which a position (VDD, etc.) is input. The other end of our system is electrically connected to wiring that can supply a low power potential (e.g., a GND wire). It will continue.

[0427] Capacitive elements 1207 and 1208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0428] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal RD than control signal WE. The conduction or non-conduction state between the first terminal and the second terminal is selected by this, and one of the terminals When there is continuity between the first and second terminals of one switch, the first terminal of the other switch and the second terminal The area between terminals 2 becomes non-conductive.

[0429] Note that in transistor 1209 in Figure 46, the second gate (second gate electrode: buck) The diagram shows a configuration having gates. The first gate receives a control signal WE, and the second gate... The control signal WE2 can be input to the terminal. The control signal WE2 is a signal with a constant potential and This should be done. The constant potential can be, for example, the ground potential GND or the potential of transistor 1209. A potential smaller than the potential of the electrode is selected. At this time, the control signal WE2 is transmitted. This is a potential signal used to control the threshold voltage of the ZISTRA 1209, where the gate voltage VG is 0V. The current can be further reduced. Also, the control signal WE2 is the same as the control signal WE. It may also be a positional signal. Note that transistor 1209 is a transistor without a second gate. A transistor can also be used.

[0430] The source electrode and the other drain electrode of transistor 1209 are held by circuit 1201. A signal corresponding to the data is input. In Figure 46, the signal output from circuit 1201 is The example shows the input to the source electrode and the other drain electrode of transistor 1209. The second terminal of transistor 1203 (the other of the source and drain electrodes of transistor 1213) The signal output from ) is an inverted signal whose logic value is inverted by logic element 1206. This signal is then input to circuit 1201 via circuit 1220.

[0431] Note that in Figure 46, the second terminal of switch 1203 (the source electrode of transistor 1213) The signal output from the other side of the drain electrode is used to connect logic element 1206 and circuit 1220. An example of inputting to circuit 1201 via this is shown, but it is not limited to this. The signal output from terminal 2 (the other of the source and drain electrodes of transistor 1213) The number may be input to circuit 1201 without its logical value being inverted. For example, Within path 1201, a signal is held which is the inverted logical value of the signal input from the input terminal. If a do exists, the second terminal of switch 1203 (source power of transistor 1213) The signal output from the pole and the other drain electrode can be input to the node.

[0432] Furthermore, in Figure 46, among the transistors used in the memory element 1200, Transistors other than TA1209 are made of a layer or substrate 119 made of a semiconductor other than an oxide semiconductor. A transistor can be formed where a channel is created at 0. For example, a silicon layer or It can be a transistor in which a channel is formed on a silicon substrate. Also, a memory element. All transistors used in the 1200 are transistors whose channels are formed by an oxide semiconductor layer. It can also be a transistor. Alternatively, the memory element 1200 can be anything other than transistor 1209. It may also include transistors in which the channel is formed by an oxide semiconductor layer, and the remaining A transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be used as a transistor.

[0433] For example, a flip-flop circuit can be used in circuit 1201 in Figure 46. Furthermore, logic elements such as inverters and clocked inverters can be used as logic elements 1206. It is possible.

[0434] In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory element 1200 The data stored in circuit 1201 is transferred to the capacitive element 120 provided in circuit 1202. It can be held by 8.

[0435] Furthermore, transistors in which channels are formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer has crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, memory element 1 Even when no power voltage is supplied to 200, the signal held by the capacitive element 1208 will persist for a long period of time. The memory element 1200 is thus preserved. It is possible to hold data.

[0436] Furthermore, by providing switches 1203 and 1204, pre-charge action Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, the circuit 1201 This can shorten the time it takes to restore the original data.

[0437] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is transmitted to the transistor The signal is input to gate 1210. As a result, the power supply voltage to memory element 1200 is restored. After that, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210 ( It can be converted to an ON state or an OFF state and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal It is possible to read it accurately.

[0438] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed.

[0439] In this embodiment, although the memory element 1200 was described as an example of being used in a CPU, the memory element 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SIs and PLDs (Programmable Logic Devices), R This can also be applied to the F (Radio Frequency) tag.

[0440] This embodiment can be appropriately combined with other embodiments shown herein. .

[0441] (Embodiment 7) This embodiment describes an example of the configuration of a display device using a transistor according to one aspect of the present invention. explain.

[0442] <Display device circuit configuration example> Figure 47(A) is a top view of a display device according to one embodiment of the present invention, and Figure 47(B) is an embodiment of the present invention. This describes a pixel circuit that can be used when applying liquid crystal elements to the pixels of a display device in one embodiment. This is a circuit diagram for doing so. Also, Figure 47(C) shows the pixels of a display device according to one aspect of the present invention. This is a circuit diagram illustrating a pixel circuit that can be used when applying an EL element. .

[0443] The transistors placed in the pixel area can be formed according to Embodiments 1 to 3. Furthermore, since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A part of the drive circuit, which can be constructed using channel-type transistors, is made up of transistors in the pixel section. They are formed on the same substrate. In this way, the pixel portion and the drive circuit are formed in the transient as shown in the above embodiment. By using STA, a highly reliable display device can be provided.

[0444] An example of a top view of an active-matrix display device is shown in Figure 47(A). The display device's substrate. On 700 are a pixel section 701, a first scan line drive circuit 702, and a second scan line drive circuit 70 3. It has a signal line driving circuit 704. Multiple signal lines are connected to the signal line driving circuit in the pixel section 701. Extending from 704, multiple scan lines are arranged to drive the first scan line drive circuit 702 and the second It is arranged as an extension from the scan line drive circuit 703. Note the intersection region of the scan line and signal line. Each of these has pixels, each having a display element, arranged in a matrix. The board 700 is a connection part for FPC (Flexible Printed Circuit), etc. It is connected to the timing control circuit (also called a controller or control IC) via this.

[0445] Figure 47(A) shows the first scan line drive circuit 702, the second scan line drive circuit 703, and the signal line The drive circuit 704 is formed on the same substrate 700 as the pixel unit 701. Therefore, it is not externally installed. Since the number of components such as drive circuits is reduced, costs can be reduced. Also, the circuit board 7 If the drive circuit is located outside of 00, it becomes necessary to extend the wiring, increasing the number of connections between wires. It is possible to reduce the number of connections between the wiring when the drive circuit is placed on the same circuit board 700. This can improve reliability or yield. Circuit 702, the second scan line drive circuit 703, or the signal line drive circuit 704 are located on board 70 The configuration may be implemented on 0 or provided outside the circuit board 700.

[0446] <Liquid crystal display device> Furthermore, an example of the pixel circuit configuration is shown in Figure 47(B). Here, as an example, a VA-type liquid crystal display... This shows a pixel circuit that can be applied to the pixels of a display device.

[0447] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow this to happen. This allows for the individual pixels of a multi-domain designed pixel to be... The signals applied to the electrode layer can be controlled independently.

[0448] The scan line 712 of transistor 716 and the scan line 713 of transistor 717 are different. It is separated so that a gate signal can be applied. On the other hand, signal line 714 is a transistor It is used in common with the transistor 716 and the transistor 717. The transistor 717 can be any transistor as described in Embodiments 1 to 3. This makes it possible to provide a highly reliable liquid crystal display device.

[0449] Furthermore, the first pixel electrode layer is electrically connected to transistor 716, and transistor 7 17 is electrically connected to the second pixel electrode layer. The layers are separated from each other. Note the shape of the first pixel electrode layer and the second pixel electrode layer. There are no particular limitations. For example, the first pixel electrode layer can be V-shaped.

[0450] The gate electrode of transistor 716 is connected to scan line 712, and the gate electrode of transistor 717 The gate electrode is connected to scan line 713. Different gate signals are connected to scan line 712 and scan line 713. By assigning different numbers, the operating timings of transistors 716 and 717 are made different, and the liquid crystal The orientation can be controlled.

[0451] Furthermore, the capacitive wiring 710, the gate insulating layer which functions as a dielectric, and the first pixel electrode layer A retention capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0452] In a multi-domain design, each pixel is equipped with a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. It can be done.

[0453] Note that the pixel circuit shown in Figure 47(B) is not limited to this. For example, as shown in Figure 47(B) The pixel circuit now includes switches, resistors, capacitives, transistors, sensors, or logic You may add circuits or other components.

[0454] Figures 48(A) and 48(B) are examples of a top view and a cross-sectional view of a liquid crystal display device. In Figure 48(A), the display device 20, display area 21, peripheral circuit 22, and FPC (F A typical configuration having a flexible printed circuit board (42) is shown in the diagram.

[0455] Figure 48(B) shows cross-sectional views of the dashed lines A-A', B-B', and C-C' in Figure 48(A). The section between A and A' indicates the peripheral circuitry, the section between B and B' indicates the display area, and the section between C and C' indicates the FPC and This shows the connection point.

[0456] The display device 20 includes, in addition to the transistor 11, a conductive layer 190, a conductive layer 195, an insulating layer 420, Liquid crystal layer 490, liquid crystal element 80, capacitive element 60, insulating layer 430, spacer 440, coloring layer 4 60, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 473, adhesive layer 474, adhesive layer 475, adhesive layer 476, polarizing plate 103, polarizing plate 403, protective substrate 105, It has a protective substrate 402 and an anisotropic conductive layer 510.

[0457] <Organic EL display device> Another example of a pixel circuit configuration is shown in Figure 47(C). Here, a display using an organic EL element is shown. The pixel structure of the device is shown.

[0458] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected into layers containing luminescent organic compounds, and an electric current flows. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0459] Figure 47(C) shows an example of an applicable pixel circuit. Here, an n-channel type An example is shown where two transistors are used for one pixel. Furthermore, this pixel circuit is a digital time scale. A controlled drive can be applied.

[0460] Applicable pixel circuit configurations and pixel operation when digital time-gradation driving is applied. I will explain.

[0461] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light-emitting element. It has a sub-element 724 and a capacitive element 723. The switching transistor 721 is a The source electrode layer is connected to scan line 726, and the first electrode (source electrode layer and drain electrode layer) One side is connected to signal line 725, and the second electrode (the other side of the source electrode layer and drain electrode layer) is connected to signal line 725. ) is connected to the gate electrode layer of the drive transistor 722. In 22, the gate electrode layer is connected to the power line 727 via the capacitive element 723, and the first electrode is electrically... The power line 727 is connected, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is identical. It is electrically connected to a common potential line formed on the substrate.

[0462] The switching transistor 721 and the driving transistor 722 are of the same type as in Embodiment 1. Transistors, as described in section 3, can be used as appropriate. This allows for highly reliable organic We can provide an EL display device.

[0463] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to power line 727, for example, GND. The forward threshold of the light-emitting element 724 The high and low power supply potentials are set so that they are equal to or greater than the value voltage, and the potential difference between them is used to power the light-emitting element 724 By applying a current to the light-emitting element 724, an electric current is passed through it, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and at least the forward voltage... Includes high-value voltage.

[0464] Furthermore, the capacitive element 723 is replaced by the gate capacitance of the drive transistor 722, thus saving space. It can be abbreviated.

[0465] Next, we will explain the signal input to the drive transistor 722. Voltage input Voltage drive method In this case, the driving transistor 722 is either fully on or completely off. A video signal like this is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for the drive. It is applied to the gate electrode layer of transistor 722. Additionally, the signal line 725 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 722.

[0466] When performing analog grayscale driving, the gate electrode layer of the driving transistor 722 has an emissive element 72 A voltage greater than or equal to the sum of the forward voltage of transistor 4 and the threshold voltage Vth of the drive transistor 722. Apply the signal. Also, input the video signal so that the drive transistor 722 operates in the saturation region. This forces current to flow through the light-emitting element 724. Furthermore, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, the light-emitting element 724 receives a current corresponding to the video signal. It can perform flow and analog gradation driving.

[0467] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 47(C). For example, Figure 47 (C) The pixel circuit shown contains switches, resistors, capacitives, sensors, transistors or You can add circuits and other components.

[0468] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 47, the low potential The source electrode (first electrode) is on the side with the high potential, and the drain electrode (second electrode) is on the high potential side with the electrical currents. The configuration is designed to connect them precisely. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. The second gate electrode is connected to a potential lower than the potential applied to the source electrode by wiring (not shown). The system should be configured to accept the potentials exemplified above, such as by applying them.

[0469] Figures 49(A) and 49(B) are examples of a top view and a cross-sectional view of the light-emitting device. Figure 49(A) shows the light-emitting device 24, the display area 21, the peripheral circuit 22, and the FPC (flexible printed circuit board). A typical configuration having a resizable printed circuit board (42) is shown in the diagram.

[0470] Figure 49(B) shows cross-sectional views of the dashed lines A-A', B-B', and C-C' in Figure 49(A). The section between A and A' indicates the peripheral circuitry, the section between B and B' indicates the display area, and the section between C and C' indicates the FPC and This shows the connection point.

[0471] The light-emitting device 24 includes, in addition to the transistor 11, a conductive layer 190, a conductive layer 195, a conductive layer 410, Optical adjustment layer 530, EL layer 450, light-emitting element 70, capacitive element 60, spacer 440, coloring Layer 460, adhesive layer 470, conductive layer 480, light-shielding layer 418, substrate 400, anisotropic conductive layer 51 It contains 0.

[0472] For example, in this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having a sub-element and a light-emitting element, can be used in various forms or It can have various elements. Display elements, display devices, light-emitting elements, or light-emitting devices are, for example, EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) (etc.), transistors (transistors that emit light in response to current), electron emission elements, liquid crystal elements Electronic ink, electrophoretic elements, grating light bulbs (GLV), plasma displays PDP (Photographic Display Panel), MEMS (Micro-Electro-Mechanical Systems), Digital Micromirror devices (DMD), DMS (Digital Microshutter), M IRASOL®, IMOD (Interference Modulation) element , electrowetting elements, piezoelectric ceramic displays, carbon nanotubes It has at least one display element that uses electrical or magnetic A display medium having properties such as contrast, brightness, reflectance, and transmittance that change due to atmospheric effects. It is acceptable to have them. An example of a display device using EL elements is an EL display. An example of a display device using an electron emission element is a field emission display ( FED) or SED flat-panel display (SED: Surface-conductive) Examples include liquid crystal elements (e.g., ion Electron-emitter Display). An example of a display device using this method is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCD displays, reflective LCD displays, direct-view LCD displays, projection LCD displays Examples include displays. Examples include electronic paper.

[0473] This embodiment can be appropriately combined with other embodiments shown herein. .

[0474] (Embodiment 8) In this embodiment, a display module to which a semiconductor device according to one aspect of the present invention is applied is shown in Figure We will use 50 to explain.

[0475] <Display Module> The display module 6000 shown in Figure 50 consists of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC6003, and FPC6005 connected Display panel 6006, backlight unit 6007, frame 6009, printed circuit board It has 6010 and battery 6011. Furthermore, it has a backlight unit 6007 and battery Features such as the Lee 6011 and Touch Panel 6004 may not be available.

[0476] One embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. It can be used in integrated circuits that are implemented in [the device].

[0477] The upper cover 6001 and the lower cover 6002 are the touch panel 6004 and the display panel. The shape and dimensions can be appropriately modified to match the size of the 6006.

[0478] The touch panel 6004 is a resistive or capacitive touch panel. It can be used superimposed on 006. Also, the opposing substrate (encapsulation substrate) of the display panel 6006. It is also possible to give the display panel 6 a touch panel function. It is also possible to add an optical touch panel function by providing a light sensor within each pixel of 006. Yes. Alternatively, an electrode for a touch sensor can be provided within each pixel of the display panel 6006, and a capacitive method can be used. It is also possible to add a touch panel function to the model.

[0479] The backlight unit 6007 has a light source 6008. The light source 6008 is used as a backlight. A configuration using a light-diffusing plate, provided at the end of unit 6007, is also possible.

[0480] Frame 6009 provides protection for the display panel 6006, as well as generating signals from the printed circuit board 6010. It functions as an electromagnetic shield to block the generated electromagnetic waves. Also, the frame 600 9 may also function as a heat sink.

[0481] Printed circuit board 6010 is a power supply circuit and a signal for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. This is also fine, or a separate battery 6011 may be used. Battery 6011 can be omitted.

[0482] Furthermore, the display module 6000 includes additional components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided.

[0483] This embodiment can be appropriately combined with other embodiments shown herein. .

[0484] (Embodiment 9) This embodiment describes an example of the use of a semiconductor device according to one aspect of the present invention.

[0485] <Package using a lead frame type interposer> Figure 51(A) shows the cross-sectional structure of a package using a lead frame type interposer. A perspective view is shown. The package shown in Figure 51(A) is a semiconductor device according to one aspect of the present invention. The corresponding chip 2751 is bonded to the interposer 2750 by wire bonding. It is connected to terminal 2752. Terminal 2752 is connected to chip 27 of interposer 2750. 51 is positioned on the surface on which it is mounted. And the tip 2751 is molded in resin The terminals may be sealed by 2753, but a portion of each terminal 2752 may be exposed during sealing. Make it happen.

[0486] The configuration of an electronic device (mobile phone) module with a package mounted on a circuit board is shown in the diagram. This is shown in Figure 51(B). The mobile phone module shown in Figure 51(B) is a printed circuit board 28 Unit 01 contains package 2802 and battery 2804. A printed circuit board 2801 is mounted on panel 2800, which is provided with a child, by FPC2803. It is implemented.

[0487] This embodiment can be appropriately combined with other embodiments shown herein. .

[0488] (Embodiment 10) In this embodiment, an electronic device and a lighting device according to one aspect of the present invention will be described with reference to the drawings. do.

[0489] <Electronic equipment> Electronic devices and lighting devices can be manufactured using a semiconductor device according to one embodiment of the present invention. Using a semiconductor device of one embodiment, highly reliable electronic devices and lighting devices can be manufactured. Electronic devices and lighting with improved touch sensor detection sensitivity using a semiconductor device according to one aspect of the invention We can manufacture the device.

[0490] Examples of electronic devices include television equipment (also known as televisions or television receivers). (u) Monitors for computers, digital cameras, digital video cameras, and other cameras. , digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable game Examples include video games, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. .

[0491] Furthermore, if an electronic device or lighting device according to one aspect of the present invention is flexible, it can be used on the interior walls of houses and buildings. Alternatively, it can be incorporated along the curved surfaces of exterior walls, or the interior or exterior of automobiles. ru.

[0492] Furthermore, an electronic device according to one aspect of the present invention may have a secondary battery and use contactless power transmission. It would be preferable if it could also charge a secondary battery.

[0493] Examples of secondary batteries include lithium polymer batteries (lithium iodine) which use a gel electrolyte. Lithium-ion secondary batteries such as polymer batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic polymer batteries, etc. Examples include zinc batteries, lead-acid batteries, rechargeable air batteries, nickel-zinc batteries, and silver-zinc batteries. .

[0494] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, electronic devices can use secondary batteries. If available, the antenna may be used for contactless power transmission.

[0495] Figure 52(A) shows a portable game console, comprising a casing 7101, casing 7102, display unit 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus It has 7108, etc. A semiconductor device according to one aspect of the present invention is built into a housing 7101 It can be used in integrated circuits, CPUs, etc. Display unit 7103 or display unit 7104 By using a display device according to one aspect of the present invention, the user experience is excellent and quality does not deteriorate. We can provide a portable game console that is less prone to problems. The game console has two display units 7103 and 7104, but the portable game The number of display units the device has is not limited to this.

[0496] Figure 52(B) shows a smartwatch, consisting of a casing 7302, a display unit 7304, and operation buttons. It has 7311, 7312, connection terminal 7313, band 7321, clasp 7322, etc. A semiconductor device according to one aspect of the present invention includes a memory, CPU, etc., built into a housing 7302. It can be used for this purpose.

[0497] Figure 52(C) shows a portable information terminal, which includes a display unit 7502 incorporated into the housing 7501, as well as Control buttons 7503, external connection port 7504, speaker 7505, microphone 7506 It is equipped with the following. A semiconductor device according to one aspect of the present invention is built into a housing 7501. It can be used in mobile memory, CPUs, etc. Note that the display unit 7502 is very Because it can achieve high definition, it can display Full HD, 4K, or 8K resolution despite being small to medium-sized. It can display various values ​​such as k, and produce very clear images.

[0498] Figure 52(D) shows a video camera, consisting of a first housing 7701, a second housing 7702, and a display unit 77 03, it has an operation key 7704, a lens 7705, a connector 7706, etc. Operation key 770 4 and lens 7705 are provided in the first housing 7701, and the display unit 7703 is in the second housing It is located in body 7702. And the first housing 7701 and the second housing 7702 are connected. They are connected by part 7706, and the angle between the first housing 7701 and the second housing 7702 is, The connection part 7706 can be used to change the video displayed in the display unit 7703. A configuration that switches according to the angle between the first housing 7701 and the second housing 7702 in 6. It is permissible to do so. The position at the focal point of lens 7705 may be equipped with an imaging device according to one embodiment of the present invention. This is possible. A semiconductor device according to one aspect of the present invention is a cluster built into the first housing 7701 It can be used in integrated circuits, CPUs, and the like.

[0499] Figure 52(E) shows a digital signage display unit 7922 installed on a utility pole 7921. A semiconductor device according to one aspect of the present invention is used in the control circuit of the display unit 7922. It is possible.

[0500] Figure 53(A) shows a notebook personal computer, consisting of a casing 8121 and a display unit 8122 The present invention includes a keyboard 8123, a pointing device 8124, and the like. The semiconductor device in question is applicable to the CPU and memory built into the housing 8121. Yes, it is possible. Furthermore, the display unit 8122 can be made with very high resolution, and is suitable for medium-sized and compact devices. It can display 8K resolution while simultaneously producing extremely sharp images.

[0501] Figure 53(B) shows the exterior of the automobile 9700. Figure 53(C) shows the driver's seat of the automobile 9700. The car 9700 consists of a body 9701, wheels 9702, dashboard 9703, and lights. It has the T9704, etc. A semiconductor device according to one aspect of the present invention is a display unit of an automobile 9700, and It can be used in integrated circuits for control. For example, the display unit 9710 shown in Figure 53(C) Alternatively, the display unit 9715 may be provided with a display device or semiconductor device according to one aspect of the present invention. ru.

[0502] Display units 9710 and 9711 are display devices installed on the windshield of an automobile, or is an input / output device. A display device or input / output device according to one aspect of the present invention is a display device, or Alternatively, by fabricating the electrodes of the input / output device from a light-transmitting conductive material, To create a display device or input / output device that is transparent, allowing the other side to be seen through, in other words, a see-through state. This is possible. If it is a see-through display device or input / output device, then the operation of the automobile 9700 It does not obstruct the view even when turning. Therefore, a display device or input / output display according to one aspect of the present invention The power device can be installed on the windshield of the automobile 9700. Furthermore, the display device, Alternatively, the input / output device may be equipped with a display device or a transistor for driving the input / output device. In such cases, organic transistors using organic semiconductor materials or transistors using oxide semiconductors are used. It is advisable to use a transmissive transistor, such as a light-transmitting transistor.

[0503] The display unit 9712 is a display device provided on the pillar portion. For example, a camera provided on the vehicle body By displaying the image from the imaging device on the display unit 9712, the field of view obstructed by the pillar is compensated for. It can be completed. The display unit 9713 is a display device provided on the dashboard. For example, by displaying images from an imaging device installed on the vehicle body on the display unit 9713, This can compensate for the view obstructed by the dashboard. In other words, it can be installed on the outside of the vehicle body. By displaying images from the captured imaging device, blind spots are compensated for, and safety is enhanced. This is possible. Furthermore, by displaying images that fill in the gaps in the unseen areas, it becomes more natural and less jarring. Safety checks can be performed.

[0504] Furthermore, Figure 53(D) shows the interior of a car with bench seats for both the driver and passenger. The display unit 9721 is a display device or input / output device provided in the door section. By displaying the image from the imaging means installed on the vehicle body on the display unit 9721, It can compensate for the field of view obstructed by A. Also, the display unit 9722 is provided on the handle. This is a display device. The display unit 9723 is a display provided in the center of the seat surface of the bench seat. It is a device. Furthermore, the display device is installed on the seat or backrest, and the display device is... The heat generated by the display device can also be used as a seat heater.

[0505] Display unit 9714, display unit 9715, or display unit 9722 displays navigation information, speed This includes the odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, and more. It can provide various kinds of information. Also, the display items and layout displayed on the display unit can be customized. These can be changed as needed to suit the user's preferences. The above information is displayed on the display unit 9. It can also be displayed on display units 710 to 9713, display unit 9721, and display unit 9723. Furthermore, the display units 9710 to 9715 and 9721 to 9723 are illuminated. It can also be used as a device. In addition, display units 9710 to 9715, display unit Units 9721 through 9723 can also be used as heating devices.

[0506] Figure 54(A) also shows the external appearance of camera 8000. Camera 8000 is housed in housing 8001 , display unit 8002, operation button 8003, shutter button 8004, coupling unit 8005, etc. It has [a certain feature]. Furthermore, the camera 8000 can be fitted with a lens 8006.

[0507] The coupling portion 8005 has electrodes and, in addition to the viewfinder 8100 described later, also a strobe device, etc. It can be connected.

[0508] Here, we'll use camera 8000 and replace lens 8006 by removing it from housing 8001. Although this configuration allows for this, the lens 8006 and the housing 8001 may be integrated into a single unit.

[0509] By pressing the shutter button 8004, an image can be taken. Also, the display unit 80 Unit 02 functions as a touch panel, and by touching the display unit 8002, imaging is performed. It is also possible to do so.

[0510] A display device or semiconductor device according to one aspect of the present invention can be applied to the display unit 8002. ru.

[0511] Figure 54(B) shows an example of the camera 8000 with the viewfinder 8100 attached. It is.

[0512] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0513] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000, The viewfinder 8100 can be attached to the camera 8000. Furthermore, the connection point is electrically powered. It has electrodes, and displays images and other data received from camera 8000 via these electrodes on display unit 8102. It can be made to happen.

[0514] Button 8103 functions as a power button. Button 8103 activates the display unit 8 You can switch the display of 102 on or off.

[0515] A semiconductor device according to one aspect of the present invention is applied to the integrated circuit and image sensor located inside the housing 8101. It can be used.

[0516] Note that in Figures 54(A) and (B), the camera 8000 and the viewfinder 8100 are connected to separate electronic devices. The container was designed to be detachable, but the housing 8001 of the camera 8000 is the present invention. A viewfinder equipped with a display device or input / output device of one form may be incorporated.

[0517] Figure 54(C) also shows the external appearance of the head-mounted display 8200.

[0518] The head-mounted display 8200 consists of the mounting part 8201, the lens 8202, and the main body 820 3. It has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has a battery It has a built-in TERI 8206 chip.

[0519] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 820 3 is equipped with a wireless receiver and displays received video information such as image data on the display unit 8204. It is possible to do so. In addition, the camera installed in the main unit 8203 can capture the movement of the user's eyeballs and eyelids. Capture it and calculate the coordinates of the user's perspective based on the information, thereby inputting the user's perspective It can be used as a force means.

[0520] In addition, a plurality of electrodes may be provided at positions where the user is touched on the mounting portion 8201. The main body 8203 may have a function of recognizing the user's perspective by detecting the current flowing through the electrodes as the user's eyeballs move. Also, by detecting the current flowing through the electrodes, it may have a function of monitoring the user's pulse. In addition, the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Also, by detecting the movement of the user's head etc., the video displayed on the display portion 8204 may be changed according to the movement. It is also possible to detect the movement of the user's head and change the video displayed on the display portion 8204 according to the movement.

[0521] The semiconductor device of one aspect of the present invention can be applied to the integrated circuit inside the main body 8203.

[0522] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0523] (Embodiment 11) In this embodiment, an example of using an RF tag using the semiconductor device according to one aspect of the present invention will be described while using FIG. 55.

[0524] <Example of using an RF tag> The uses of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates documents (driver's licenses, resident cards, etc., see FIG. 55(A)), vehicles (bicycles, etc., FIG. 55(B) (See reference), packaging containers (wrapping paper, bottles, etc., see Figure 55(C)), recording media (DVDs and video) Deodorant tape, etc. (see Figure 55(D)), personal belongings (bags, glasses, etc.), food products, plants, animals Items such as human bodies, clothing, household goods, medicines and drugs, or electronic devices (liquid crystal display devices) Items such as EL display devices, television equipment, or mobile phones, or items attached to each item. It can be attached to luggage tags (see Figures 55(E) and 55(F)) and used in this way.

[0525] An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one aspect of the present invention to the same type of object, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching RF tags related to the configuration, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This enhances security against theft and other crimes.

[0526] As described above, an RF tag using a semiconductor device according to one aspect of the present invention is provided in this embodiment. By using it for each of the listed applications, the operating power, including information writing and reading, can be reduced. Therefore, it becomes possible to extend the maximum communication range. Also, even when the power is cut off Because it can retain information for extremely long periods, it is also suitable for applications where the frequency of writing and reading is low. It can be used suitably.

[0527] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of Symbols]

[0528] 10 transistors 11 transistors 12 transistors 20 Display device 21 Display area 22 Peripheral Circuits 24 Light-emitting device 60 Capacitive elements 70 light-emitting elements 80 liquid crystal elements 100 circuit boards 103 Polarizing plate 105 Protective substrate 110 Insulating layer 120 Semiconductor Layers 121 Insulator 121a Insulator film 122 Semiconductor layer 122a Semiconductor film 123 Insulator 123a Insulator film 130 Source electrode layer 130a conductive film 130b conductive layer 140 Drain electrode layer 150 Gate Insulation Layer 150a insulating film 160 Grid Unit Layer 160a conductive film 165 Conductive layer 166 Conductive layer 167 Conductive layer 170 Insulating layer 170a insulating film 171 Mixed layer 171b Insulating layer 172 Oxygen 173 Insulating layer 173a Insulating Film 174 Groove 175 Insulating layer 175a insulating film 175b Insulating layer 176 Resist Mask 177 Insulating layer 177a Infield 190 conductive layer 195 Conductive layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 pixel section 211 pixels 212 subpixels 212B subpixels 212G sub-pixels 212R sub-pixels 220 Photoelectric conversion element 230-pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrates 310 layers 320 layers 330 layers 340 layers 351 transistors 352 transistors 353 transistors 360 Photodiodes 361 Anodes 362 Cathode 363 Low resistance region 365 Photodiodes 366 Semiconductor Layers 367 Semiconductor layer 368 Semiconductor Layers 370 plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 400 circuit boards 402 Protective substrate 403 Polarizing plate 410 Conductive layer 418 Light blocking layer 420 Insulating layer 430 Insulating layer 440 Spacer 450 EL layer 460 Colored layer 470 Adhesive layer 473 Adhesive layer 474 Adhesive layer 475 Adhesive layer 476 Adhesive layer 480 Conductive layer 490 liquid crystal layer 510 Anisotropic conductive layer 530 Optical adjustment layer 601 Precasa 602 Precasa 700 circuit boards 701 pixel section 702 Scan Line Drive Circuit 703 Scan line drive circuit 704 Signal Line Drive Circuit 710 Capacitance wiring 712 scan lines 713 scan lines 714 signal line 716 transistors 717 transistors 718 Liquid crystal elements 719 Liquid crystal elements 720 pixels 721 Switching Transistors 722 Driver Transistor 723 Capacitive element 724 Light-emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistors 1214 Transistors 1220 Circuit 1700 Substrate to be coated 1701 Chamber 1702 Road Room 1703 Pre-processing room 1704 Chamber 1705 Chamber 1706 Unloading Room 1711a Raw material supply section 1711b Raw material supply section 1712a High-speed valve 1712b High-speed valve 1713a Raw material inlet 1713b Raw material inlet 1714 Raw material discharge port 1715 Exhaust system 1716 PCB holder 1720 Transport Room 2100 transistors 2200 transistors 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2207 Insulator 2211 Semiconductor substrate 2212 Insulator 2213 Terminal 2214 Gate Insulator 2215 Source area and drain area 2750 Interposer 2751 chips 2752 terminal 2753 Mold resin 2800 panels 2801 Printed Wiring Board 2802 Package 2803 FPC 2804 Battery 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitive element 4000 RF tags 5100 pellets 5120 circuit board 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight Unit 6008 Light source 6009 Frame 6010 Printed Circuit Board 6011 Battery 7101 enclosure 7102 enclosure 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation Keys 7108 Stylus 7302 enclosure 7304 Display section 7311 Operation Buttons 7312 Operation Buttons 7313 Connection terminal 7321 Band 7322 Clasp 7501 enclosure 7502 Display section 7503 Operation Buttons 7504 External connection port 7505 Speaker 7506 Mike 7701 enclosure 7702 Casing 7703 Display section 7704 Operation Keys 7705 Lens 7706 Connection part 7921 Utility pole 7922 Display section 8000 Camera 8001 enclosure 8002 Display section 8003 Operation Buttons 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 enclosure 8102 Display section 8103 button 8121 enclosure 8122 Display section 8123 Keyboard 8124 Pointing device 8200 Head-Mounted Display 8201 Mounting part 8202 Lens 8203 Main Unit 8204 Display section 8205 Cable 8206 Battery 9700 automobiles 9701 Car body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section< / cpu>

Claims

[Claim 1] It has a transistor and a capacitive element, A semiconductor device in which one of the source electrode or drain electrode of the transistor is electrically connected to one of the electrodes of the capacitive element, The first insulating layer, An oxide semiconductor layer having a region above the first insulating layer and having a channel formation region for the transistor, A first conductive layer having a region above the oxide semiconductor layer and functioning as either a source electrode or a drain electrode, A second insulating layer having a region in contact with the side surface of the first insulating layer and a region in contact with the side surface of the oxide semiconductor layer, A third insulating layer having a region above the first conductive layer and having grooves, A fourth insulating layer having a region above the third insulating layer and having grooves, A fifth insulating layer having the function of a gate insulating layer formed along the inner wall of the groove, The device has a third conductive layer having a region on the inside of the groove that is in contact with the fifth insulating layer and that functions as a gate electrode, A semiconductor device in which the upper surface of the second insulating layer, the upper surface of the fourth insulating layer, the upper surface of the fifth insulating layer, and the upper surface of the third conductive layer are on the same plane.

Images