A pair of display devices and display systems

Abstract

To suppress the difference in chromaticity between images displayed on a pair of display devices when the same image is displayed on each of them. [Solution] The pair of display devices 1 comprises a first display device 2a and a second display device 2b arranged along the X1 direction. The arrangement of multiple sub-pixels S in the display area DA of the first display device 2a and the arrangement of multiple sub-pixels S in the display area DA of the second display device 2b are symmetric with respect to a virtual line Lv perpendicular to the X1 direction. The arrangement of multiple signal lines Lb of the first display device 2a and the arrangement of multiple signal lines Lb of the second display device 2b are symmetric with respect to a virtual line Lv.

Description

Technical Field

[0001] The present invention relates to a pair of display devices and a display system.

Background Art

[0002] Patent Document 1 discloses a display system including two display panels. Each of the two display panels includes a plurality of pixels arranged along directions Vx and Vy in a display area, and a plurality of signal lines. The signal lines are arranged between two adjacent pixels in the direction Vx and extend along the direction Vy. In other words, one pixel is sandwiched between two signal lines in the direction Vx. A pixel signal is transmitted to the pixel via the signal line, and a holding capacitance corresponding to the pixel signal is formed. The gradation of the pixel is determined by the holding capacitance.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the display system of Patent Document 1 is applied to, for example, a head-mounted display (hereinafter sometimes referred to as an HMD), the size of the pixel may be determined to be relatively small. In this case, the interval between two adjacent signal lines in the direction Vx also becomes relatively narrow. As a result, the holding capacitance formed in the pixel may be affected by the potentials of the two signal lines. That is, the holding capacitance may change depending on the potentials of the two signal lines.

[0005] When the retention capacity of any pixel on a display panel changes as described above, the gradation of that pixel changes. Therefore, depending on the arrangement of multiple pixels, when displaying the same image on two display panels (a pair of display devices), the difference between the gradation of any pixel on one display device and the gradation of the corresponding pixel on the other display device may be relatively large. In this case, the difference in chromaticity between any pixel on one display device and the corresponding pixel on the other display device will be relatively large. In other words, even when displaying the same image on each of the pair of display devices, the difference in chromaticity between the images displayed on the pair of display devices may be relatively large.

[0006] This disclosure aims to suppress differences in chromaticity between images displayed on a pair of display devices when the same image is displayed on each of the two display devices. [Means for solving the problem]

[0007] A pair of display devices according to the present disclosure comprises a first display device and a second display device arranged along the array direction, the first display device and the second display device each comprising: a display panel having a display area in which a plurality of subpixels are arranged in a matrix along the row direction and the column direction; a plurality of gate lines disposed on the display panel and extending along the row direction and arranged along the column direction; a plurality of signal lines disposed on the display panel and extending along the column direction and arranged along the row direction; and a drive circuit that outputs subpixel signals to the subpixels via the signal lines to display an image in the display area and drives the subpixels via the gate lines, wherein the plurality of subpixels each comprises a plurality of first subpixels, second subpixels and third subpixels, each having a different color from one another, and the In the display area of ​​the first display device, the plurality of first subpixels, the plurality of second subpixels, and the plurality of third subpixels are arranged such that the first subpixels, second subpixels, and third subpixels are repeated in this order along the row direction, and the first subpixels, second subpixels, and third subpixels are also arranged such that the first subpixels, second subpixels, and third subpixels are repeated in this order along the column direction, and the arrangement of the plurality of subpixels in the display area of ​​the first display device and the arrangement of the plurality of subpixels in the display area of ​​the second display device are line-symmetric with respect to a virtual line orthogonal to the arrangement direction, and the arrangement of the plurality of signal lines in the first display device and the arrangement of the plurality of signal lines in the second display device are line-symmetric with respect to the virtual line.

[0008] The display system of this disclosure comprises the above-described pair of display devices and a lens. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a front view of a pair of display devices according to the present disclosure. [Figure 2] Figure 2 is a side view of the display device. [Figure 3] Figure 3 shows the circuit configuration of the display panel. [Figure 4] Figure 4 shows the circuit configuration of the sub-pixel. [Figure 5]Figure 5 is a cross-sectional view of the display panel. [Figure 6] Figure 6 shows the arrangement of subpixels and signal lines in the second display device. [Figure 7] Figure 7 is a time chart showing the operation of the display device. [Figure 8] Figure 8 is a partially enlarged view of the circuit configuration of the display panel of the first display device. [Figure 9] Figure 9 is a partially enlarged view of the circuit configuration of the display panel of the second display device. [Figure 10] Figure 10 is a partially enlarged view of the circuit configuration of the display panel of the second display device in the comparative example pair of display devices. [Figure 11] Figure 11 is a diagram showing the circuit configuration of the display panel of the first display device in a pair of display devices according to a modified embodiment of the present disclosure. [Figure 12] Figure 12 is a diagram showing the circuit configuration of the display panel of the second display device in a pair of display devices according to a modified embodiment of the present disclosure. [Figure 13] Figure 13 shows a pair of display devices according to a modified embodiment of the present disclosure, in which the drive circuit of the display device outputs a sub-pixel signal by a second column inversion drive method. [Figure 14] Figure 14 is a perspective view of a display system according to an embodiment of this disclosure. [Figure 15] Figure 15 is a schematic diagram showing the configuration of the display system. [Figure 16] Figure 16 shows the arrangement of a pair of display devices in the mounting section. [Modes for carrying out the invention]

[0010] The embodiments of this disclosure will be described below with reference to the drawings. This disclosure is not limited to the embodiments described below. Furthermore, the components described below include those that are readily conceivable to those skilled in the art, and those that are substantially the same. In addition, the components described below can be combined as appropriate.

[0011] Note that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the present disclosure, they are naturally included in the scope of the present disclosure. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but it is merely an example and does not limit the interpretation of the present disclosure. Also, in this specification and each drawing, the same reference numerals may be assigned to the same elements as those described above for the previously shown drawings, and detailed descriptions may be omitted as appropriate.

[0012] FIG. 1 is a front view of a pair of display devices 1 according to an embodiment of the present disclosure. The X1 direction (corresponding to the "arrangement direction"), Y1 direction, and Z1 direction shown in the drawing are orthogonal to each other and indicate the directions of the pair of display devices 1. Note that the X1 direction, Y1 direction, and Z1 direction are examples, and the present disclosure is not limited to these directions.

[0013] The pair of display devices 1 displays an image based on an image signal transmitted from an external device. The pair of display devices 1 includes a first display device 2a and a second display device 2b. The first display device 2a and the second display device 2b are arranged along the X1 direction.

[0014] The first display device 2a and the second display device 2b are configured in the same manner except for the arrangement of sub-pixels S and the arrangement of signal lines Lb described later. Hereinafter, when the first display device 2a and the second display device 2b are described without distinction, they are simply referred to as "display device 2".

[0015] Figure 2 is a side view of the display device 2. The X2, Y2, and Z2 directions shown in the figure are orthogonal to each other and represent the directions of the display device 2. The X2 and Y2 directions correspond to directions parallel to the main surface of the substrate included in the display device 2. The Z2 direction corresponds to a direction perpendicular to the main surface of the substrate included in the display device 2. The Z2 direction also corresponds to the thickness direction of the display device 2, and the +Z2 side of the Z2 direction (the side indicated by the arrow) corresponds to the front side of the display device 2 where the image is displayed, and the -Z2 side of the Z2 direction (the side opposite to the side indicated by the arrow) corresponds to the back side of the display device 2. Viewing the display device 2 along the Z2 direction is referred to as a "plan view". Note that the X2, Y2, and Z2 directions are examples, and this disclosure is not limited to these directions.

[0016] The display device 2 comprises a display panel 10 and a lighting device 20. The display panel 10 is a transmissive liquid crystal display.

[0017] As shown in Figure 1, the display panel 10 has a display area DA on its front surface where an image is displayed. The front surface of the display panel 10 is perpendicular to the Z2 direction. The display area DA is polygonal in plan view, but may also be rectangular.

[0018] In the display area DA, multiple subpixels S are arranged in a matrix. In a plan view, the multiple subpixels S are arranged in a matrix along the row direction D1 and the column direction D2. The row direction D1 and the column direction D2 are orthogonal to each other. The row direction D1 is parallel to the X2 direction. The column direction D2 is parallel to the Y2 direction. Note that the row direction D1 may be tilted with respect to the X2 direction, and the column direction D2 may be tilted with respect to the Y2 direction. Also, the row direction D1 and the column direction D2 may be tilted without being orthogonal to each other. Details of the subpixels S will be described later.

[0019] As shown in Figure 2, the lighting device 20 is positioned on the back side of the display panel 10 and emits light toward the display panel 10. The lighting device 20 is a so-called direct-lit backlight. The lighting device 20 includes, for example, multiple light-emitting diodes.

[0020] Figure 3 shows the circuit configuration of the display panel 10. The display panel 10 includes the drive circuit 11 shown in Figure 3.

[0021] The drive circuit 11 displays an image in the display area DA. As shown in Figure 3, the drive circuit 11 includes a signal processing circuit 11a, a signal output circuit 11b, and a scanning circuit 11c.

[0022] The signal processing circuit 11a generates a plurality of sub-pixel signals, described later, based on the image signal transmitted from an external device, and outputs the generated plurality of sub-pixel signals to the signal output circuit 11b. The signal processing circuit 11a also outputs a clock signal to the signal output circuit 11b and the scanning circuit 11c to synchronize the operation of the signal output circuit 11b and the operation of the scanning circuit 11c.

[0023] The signal output circuit 11b outputs each of the multiple sub-pixel signals to the corresponding sub-pixel S. The signal output circuit 11b and the multiple sub-pixels S are electrically connected via multiple signal lines Lb extending along the column direction D2 (details will be described later). Multiple signal lines Lb are arranged along the row direction D1. In the row direction D1, the signal lines Lb and sub-pixels S are arranged alternately.

[0024] Furthermore, the signal output circuit 11b outputs sub-pixel signals using a column inversion drive method in which the polarity of the sub-pixel signals differs between two adjacent signal lines Lb in the row direction D1, and the polarity of the sub-pixel signals is periodically reversed (for example, every frame F).

[0025] For example, as shown by the symbols in parentheses in Figure 3, if the polarity of the sub-pixel signal corresponding to the signal line Lb furthest to -D1 is positive (+), then the polarity of the sub-pixel signal corresponding to the adjacent signal line Lb is negative (-). In other words, the polarities of the sub-pixel signals corresponding to multiple signal lines Lb alternate between positive and negative in the row direction D1.

[0026] The scanning circuit 11c scans multiple sub-pixels S in synchronization with the output of the sub-pixel signal by the signal output circuit 11b. The scanning circuit 11c and the multiple sub-pixels S are electrically connected via multiple gate lines Lc extending along the row direction D1. One gate line Lc is electrically connected to multiple sub-pixels S aligned in the same row along the row direction D1. Multiple gate lines Lc are arranged along the column direction D2.

[0027] The drive circuit 11 outputs a sub-pixel signal to the sub-pixel S via the signal line Lb to display an image in the display area DA, and drives the sub-pixel S via the gate line Lc.

[0028] In a plan view, a region demarcated by two adjacent signal lines Lb in the row direction D1 and two adjacent gate lines Lc in the column direction D2 corresponds to one sub-pixel S.

[0029] Figure 4 shows the circuit configuration of the sub-pixel S. The display panel 10 includes a switching element SW, a sub-pixel electrode PE, a common electrode CE, and a liquid crystal capacitor LC, each of the multiple sub-pixels S.

[0030] A switching element SW is composed of, for example, a thin-film transistor (TFT). In a switching element SW, the source electrode and the signal line Lb are electrically connected, and the gate electrode and the gate line Lc are electrically connected.

[0031] The sub-pixel electrode PE is connected to the drain electrode of the switching element SW. The common electrode CE is positioned corresponding to the sub-pixel electrode PE. Both the sub-pixel electrode PE and the common electrode CE are translucent.

[0032] The liquid crystal capacitance LC is the capacitance component of the liquid crystal material in the liquid crystal layer 13, which will be described later, located between the sub-pixel electrode PE and the common electrode CE. A retaining capacitance CS is formed between the electrode at the same potential as the common electrode CE and the electrode at the same potential as the sub-pixel electrode PE.

[0033] Figure 5 is a cross-sectional view of the display panel 10. The display panel 10 comprises a first substrate 12, a liquid crystal layer 13, and a second substrate 14.

[0034] The first substrate 12, the liquid crystal layer 13, and the second substrate 14 are all translucent and are arranged in this order along the Z2 direction from the -Z2 side to the +Z2 side. The IC chip Ti that constitutes the drive circuit 11 is placed on the first substrate 12 (Figures 1 and 2).

[0035] The main surface 12a, which corresponds to the front surface of the first substrate 12, has signal lines Lb and gate lines Lc (not shown in Figure 5) arranged on it. A color filter CF is also arranged on the main surface 12a of the first substrate 12. The color filter CF is rectangular in plan view and one is placed for each of the multiple sub-pixels S.

[0036] The color filter CF is light-transmitting, and the spectral peaks of the light it transmits are predetermined. The spectral peaks are one of three spectral peaks corresponding to three distinct colors. The three colors are red, green, and blue, but it goes without saying that the number and types of colors are not limited to these. Hereinafter, the color corresponding to the spectral peak of the light transmitted by the color filter CF will be referred to as the color of the color filter CF. The color of the color filter CF corresponds to the color of the sub-pixel S.

[0037] Furthermore, on the first substrate 12, a sub-pixel electrode PE is positioned on the +Z2 side in the Z2 direction from the color filter CF and signal line Lb, via an insulating layer IL1. The sub-pixel electrode PE overlaps with the color filter CF in the Z2 direction.

[0038] Furthermore, on the first substrate 12, a light-shielding film SM, a common electrode CE, and an alignment film AL are arranged on the +Z2 side in the Z2 direction from the sub-pixel electrode PE, via an insulating layer IL2.

[0039] The light-shielding film SM has light-shielding properties. The light-shielding film SM overlaps with the signal line Lb and the gate line Lc in the Z2 direction. In other words, the light-shielding film SM partitions multiple sub-pixels S. To put it another way, the light-shielding film SM overlaps in the Z2 direction with the boundary between two sub-pixels S that are adjacent to each other in the row direction D1 and the column direction D2.

[0040] The common electrode CE is laminated on the light-shielding film SM and has a slit SL, positioned to straddle two adjacent sub-pixel electrodes PE in a plan view. Thus, the common electrode CE and sub-pixel electrodes PE are arranged on the first substrate 12. In other words, the display panel 10 is a transverse electric field type liquid crystal display.

[0041] The liquid crystal layer 13 contains multiple liquid crystal molecules LM. The liquid crystal layer 13 is located between two alignment films AL that face each other in the Z2 direction. The orientation of the liquid crystal molecules LM is restricted by the two alignment films AL. The alignment films AL are positioned on the back side of the second substrate 14.

[0042] Furthermore, the display panel 10 also includes a first polarizing plate 15 positioned on the back side of the first substrate 12, and a second polarizing plate 16 positioned on the front side of the second substrate 14.

[0043] The first polarizing plate 15 has a transmission axis perpendicular to the Z2 direction. The second polarizing plate 16 has a transmission axis perpendicular to the transmission axis of the first polarizing plate 15 and the Z2 direction.

[0044] As shown in Figure 1, in a pair of display devices 1, the display device 2 is positioned such that the X2 direction and the X1 direction are parallel, the Y2 direction and the Y1 direction are parallel, and the Z2 direction and the Z1 direction are parallel. Furthermore, if we define a virtual line Lv that lies between the first display device 2a and the second display device 2b and is orthogonal to the X1 direction, then the periphery of the display area DA of the first display device 2a and the periphery of the display area DA of the second display device 2b are symmetrical with respect to the virtual line Lv as the axis of symmetry.

[0045] Next, the arrangement of sub-pixels S and the arrangement of signal lines Lb in the first display device 2a will be described.

[0046] Figure 3 shows the arrangement of subpixels S and the arrangement of signal lines Lb in the first display device 2a. As described above, the multiple subpixels S are arranged in a matrix along the row direction D1 and the column direction D2, respectively, in a plan view.

[0047] Multiple subpixels S have multiple first subpixels Sα, multiple second subpixels Sβ, and multiple third subpixels Sγ. In the first subpixels Sα, second subpixels Sβ, and third subpixels Sγ, the color of the color filter CF, i.e., the color of the subpixels S, are different from each other. The color of the first subpixel Sα is red. The color of the second subpixel Sβ is green. The color of the third subpixel Sγ is blue. In other words, the first subpixel Sα is a red subpixel. The second subpixel Sβ is a green subpixel. The third subpixel Sγ is a blue subpixel.

[0048] In Figure 3 and Figure 6 (described later), the first sub-pixel Sα is shown as "R", the second sub-pixel Sβ as "G", and the third sub-pixel Sγ as "B". It goes without saying that the color of sub-pixel S is not limited to these. Hereafter, when the first sub-pixel Sα, second sub-pixel Sβ, and third sub-pixel Sγ are not distinguished, they may simply be referred to as "sub-pixel S".

[0049] The arrangement of multiple subpixels S shown in Figure 3 is a so-called mosaic arrangement. Specifically, in a plan view, the first subpixel Sα, second subpixel Sβ, and third subpixel Sγ are repeatedly arranged in this order along the row direction D1, from the -D1 side (opposite side to the side indicated by the arrow) to the +D1 side (the side indicated by the arrow), and the first subpixel Sα, second subpixel Sβ, and third subpixel Sγ are repeatedly arranged in this order along the column direction D2, from the -D2 side (opposite side to the side indicated by the arrow) to the +D2 side (the side indicated by the arrow).

[0050] In Figure 3, the multiple subpixels S are arranged in ascending order from the 1st column to the mth column (where m is a natural number) along the row direction D1, from one end (the -D1 side) to the other end (the +D1 side), and arranged in ascending order from the 1st row to the nth row (where n is a natural number) along the column direction D2, from one end (the -D2 side) to the other end (the +D2 side). In this embodiment, the subpixel S in the 1st row and 1st column is the second subpixel Sβ, but the subpixel S in the 1st row and 1st column may be the first subpixel Sα or the third subpixel Sγ.

[0051] In the stripe array, one of the sub-pixel S arrays, the first sub-pixel Sα, second sub-pixel Sβ, and third sub-pixel Sγ are repeatedly arranged in this order along the row direction D1 from the -D1 side to the +D1 side, and sub-pixels S of the same color are arranged consecutively in the column direction D2. The spacing between two adjacent sub-pixels S in both the row direction D1 and the column direction D2 can be made smaller in the mosaic array than in the stripe array. Therefore, a more detailed image can be obtained with the mosaic array compared to the stripe array.

[0052] As described above, multiple signal lines Lb extend along the column direction D2 and are arranged along the row direction D1. In the row direction D1, signal lines Lb and subpixels S are arranged alternately. When the total number of subpixels S arranged in ascending order from the 1st column to the mth column (where m is a natural number) along the row direction D1 from one end (the -D1 side) to the other end (the +D1 side) is M, the total number of signal lines Lb is M.

[0053] The m-th signal line Lb is positioned on the -D1 side of the multiple subpixels S arranged in the m-th column. The m-th signal line Lb branches out and is electrically connected to the multiple subpixels S arranged in the m-th column. Alternatively, the m-th signal line Lb may be positioned on the +D1 side of the subpixels S in the m-th column.

[0054] Next, the arrangement of sub-pixels S and the arrangement of signal lines Lb in the second display device 2b will be described.

[0055] Figure 6 shows the arrangement of subpixels S and the arrangement of signal lines Lb in the second display device 2b. Similar to the first display device 2a, in the second display device 2b, multiple subpixels S consist of multiple first subpixels Sα, multiple second subpixels Sβ, and multiple third subpixels Sγ. The arrangement of multiple subpixels S in the second display device 2b also corresponds to a mosaic arrangement. The number of subpixels S in the second display device 2b is equal to the number of subpixels S in the first display device 2a.

[0056] The arrangement of the subpixels S of the second display device 2b differs from the arrangement of the subpixels S of the first display device 2a. Specifically, the arrangement of the subpixels S in the display area DA of the first display device 2a and the arrangement of the subpixels S in the display area DA of the second display device 2b differ in that they are symmetrical with respect to a virtual line Lv that is orthogonal to the X1 direction.

[0057] In the arrangement of multiple subpixels S in the second display device 2b, in a plan view, the first subpixel Sα, the third subpixel Sγ, and the second subpixel Sβ are repeatedly arranged in this order along the row direction D1 from the -D1 side to the +D1 side, and the first subpixel Sα, the second subpixel Sβ, and the third subpixel Sγ are repeatedly arranged in this order along the column direction D2 from the -D2 side to the +D2 side.

[0058] Furthermore, in the second display device 2b, as in the first display device 2a, multiple signal lines Lb extend along the column direction D2 and are arranged along the row direction D1. The number of signal lines Lb in the second display device 2b and the number of signal lines Lb in the first display device 2a are equal. In the row direction D1, the signal lines Lb and sub-pixels S are arranged alternately. When the total number of sub-pixels S arranged in ascending order from the 1st column to the mth column (where m is a natural number) along the row direction D1 from one end (-D1 side) to the other end (+D1 side) is M, the number of signal lines Lb is M.

[0059] The arrangement of the multiple signal lines Lb of the second display device 2b differs from the arrangement of the multiple signal lines Lb of the first display device 2a in the following respects. Specifically, the arrangement of the multiple signal lines Lb of the first display device 2a and the arrangement of the multiple signal lines Lb of the second display device 2b differ in that they are symmetrical with respect to the virtual line Lv as the axis of symmetry.

[0060] The m-th signal line Lb is positioned on the +D1 side of the multiple subpixels S arranged in the m-th column. The m-th signal line Lb branches out and is electrically connected to the multiple subpixels S arranged in the m-th column.

[0061] Furthermore, if the first signal line Lb in the first display device 2a is positioned +D1 side from the sub-pixel S of the first row, then in the second display device 2b, the first signal line Lb is positioned -D1 side from the sub-pixel S of the first row.

[0062] As shown in Figure 6 by the symbols in parentheses, when the polarity of the sub-pixel signal corresponding to the signal line Lb furthest to -D1 is negative (-) using the above column inversion drive method, the polarity of the sub-pixel signal corresponding to the adjacent signal line Lb is positive (+). In other words, the polarities of the sub-pixel signals corresponding to multiple signal lines Lb will alternate between positive and negative in the row direction D1.

[0063] Next, we will explain the operation of the display device 2.

[0064] Figure 7 is a time chart showing the operation of the display device 2. In Figure 7, the horizontal axis represents time, and the vertical axis represents the positions of multiple subpixels S in the column direction D2 within the display area DA. The display device 2 receives an image signal for each frame F and displays the image.

[0065] The signal processing circuit 11a generates a sub-pixel signal based on the image signal. The sub-pixel signal contains information about the grayscale of the sub-pixel S. The grayscale information of the sub-pixel S is included in the image signal. A single frame F contains the scanning period TS and the emission period TL in that order.

[0066] The scanning circuit 11c scans multiple sub-pixels S during the scanning period TS. The scanning circuit 11c scans sequentially along the column direction D2 from the sub-pixel S furthest to the +D2 side to the sub-pixel S furthest to the -D2 side. In the scanning period TS, the solid line moving from the +D2 side to the -D2 side as time progresses indicates that the scanning circuit 11c is scanning the sub-pixels S.

[0067] During the scanning period TS, the signal output circuit 11b outputs sub-pixel signals corresponding to multiple sub-pixels S via multiple signal lines Lb. The potential of the signal lines Lb fluctuates due to the sub-pixel signals. When a sub-pixel signal is output to a sub-pixel S, a retention capacitance CS corresponding to the gradation indicated by the sub-pixel signal is formed in the sub-pixel S, and the liquid crystal molecule LM tilts due to the electric field generated between the sub-pixel electrode PE and the common electrode CE. The degree of tilt of the liquid crystal molecule LM changes according to the gradation indicated by the sub-pixel signal. When the scanning period TS ends, the potential of the signal line Lb becomes the reference potential (e.g., 0V).

[0068] Furthermore, during the light emission period TL, the illumination device 20 emits light. The light from the illumination device 20 is incident on the display panel 10. The light incident on the display panel 10 is colored by passing through the color filter CF and then incident on the liquid crystal layer 13. Due to the tilt of the liquid crystal molecules LM, the light transmitted through the liquid crystal layer 13 is modulated to the gradation indicated by the sub-pixel signal. Furthermore, the light transmitted through the liquid crystal layer 13 is emitted from the display panel 10. As a result, an image is displayed in the display area DA.

[0069] In such a pair of display devices 1, the retention capacitance CS formed in a sub-pixel S sandwiched between two adjacent signal lines Lb is affected by the potential of those two signal lines Lb. For example, if the pitch of two adjacent sub-pixels S is set to be relatively small in order to obtain a fine image, the distance between the two adjacent signal lines Lb is set to be relatively small, and the influence of the potential of those two signal lines Lb on the retention capacitance CS becomes relatively large.

[0070] Figure 8 is a partially enlarged view of the circuit configuration of the display panel 10 of the first display device 2a. In Figure 8, the second sub-pixel Sβ and the third sub-pixel Sγ, which are electrically connected to the same gate line Lc and are adjacent to each other, are shown.

[0071] In the first display device 2a, the signal line Lb electrically connected to the second subpixel Sβ is located -D1 side of the second subpixel Sβ, and the signal line Lb located +D1 side of the second subpixel Sβ is electrically connected to the third subpixel Sγ adjacent to the second subpixel Sβ.

[0072] For example, when the display device 2 displays cyan in a single color across the entire display area DA, during the scanning period TS (Figure 7), the potential of the signal line Lb corresponding to the first subpixel Sα (red) is 0V, the potential of the signal line Lb corresponding to the second subpixel Sβ (green) is +2V (or -2V: the sign is reversed by the column inversion control method), and the potential of the signal line Lb corresponding to the third subpixel Sγ (blue) is 5V (or -5V). Furthermore, from the end of the scanning period TS to the end of the emission period TL (Figure 7), the potential of the signal line Lb is 0V.

[0073] In other words, as shown in Figure 8, in the first display device 2a, the potential of the signal line Lb on the -D1 side of the second sub-pixel Sβ changes from +2V to 0V (or from -2V to 0V). Then, a first capacitance C1 is formed between the signal line Lb and the second sub-pixel Sβ.

[0074] Furthermore, in the first display device 2a, the potential of the signal line Lb on the +D1 side of the second sub-pixel Sβ changes from +5V to 0V (or from -5V to 0V). As a result, a second capacitance C2 is formed between the signal line Lb and the second sub-pixel Sβ.

[0075] The retention capacitance CS formed in the second sub-pixel Sβ fluctuates under the influence of the first capacitance C1 and the second capacitance C2. When the retention capacitance CS fluctuates, the gradation of the sub-pixel S changes. If the degree of change in the gradation of the sub-pixel S differs between the first display device 2a and the second display device 2b, the difference in chromaticity between the image displayed by the first display device 2a and the image displayed by the second display device 2b may become relatively large.

[0076] Therefore, in the first display device 2a and the second display device 2b, the arrangement of sub-pixels S and the arrangement of signal lines Lb are defined as described above.

[0077] Figure 9 is a partially enlarged view of the circuit configuration of the display panel 10 of the second display device 2b. In Figure 9, the second sub-pixel Sβ and the third sub-pixel Sγ, which are electrically connected to the same gate line Lc and are adjacent to each other, are shown.

[0078] In the second display device 2b, the signal line Lb electrically connected to the second sub-pixel Sβ is located +D1 side of the second sub-pixel Sβ, and the signal line Lb located -D1 side of the second sub-pixel Sβ is electrically connected to the third sub-pixel Sγ adjacent to the second sub-pixel Sβ.

[0079] When the display device 2 displays cyan in monochrome across the entire display area DA, in the second display device 2b, the potential of the signal line Lb on the +D2 side of the second sub-pixel Sβ changes from +2V to 0V (or from -2V to 0V). As a result, a first capacitance C1 is formed between the signal line Lb and the second sub-pixel Sβ. Also in the second display device 2b, the potential of the signal line Lb on the -D1 side of the second sub-pixel Sβ changes from +5V to 0V (or from -5V to 0V). As a result, a second capacitance C2 is formed between the signal line Lb and the second sub-pixel Sβ.

[0080] Therefore, the retention capacitance CS formed in the second sub-pixel Sβ in the second display device 2b fluctuates under the influence of the first capacitance C1 and the second capacitance C2. Similarly, as described above, the retention capacitance CS formed in the second sub-pixel Sβ in the first display device 2a fluctuates under the influence of the first capacitance C1 and the second capacitance C2. In other words, the second sub-pixel Sβ of the first display device 2a and the second sub-pixel Sβ of the second display device 2b fluctuate under the influence of the first capacitance C1 and the second capacitance C2.

[0081] Thus, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the second sub-pixel Sβ is affected by the potential of the signal line Lb corresponding to the second sub-pixel Sβ and the potential of the signal line Lb corresponding to the third sub-pixel Sγ. Therefore, the gradation of the second sub-pixel Sβ fluctuates similarly in both the first display device 2a and the second display device 2b.

[0082] Furthermore, in the first display device 2a shown in Figure 3, the signal line Lb electrically connected to the third sub-pixel Sγ is located -D1 side of the third sub-pixel Sγ, and the signal line Lb located +D1 side of the third sub-pixel Sγ is electrically connected to the first sub-pixel Sα adjacent to the third sub-pixel Sγ. On the other hand, in the second display device 2b shown in Figure 6, the signal line Lb electrically connected to the third sub-pixel Sγ is located +D1 side of the third sub-pixel Sγ, and the signal line Lb located -D1 side of the third sub-pixel Sγ is electrically connected to the first sub-pixel Sα adjacent to the third sub-pixel Sγ.

[0083] In other words, similar to the case of the second sub-pixel Sβ described above, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the third sub-pixel Sγ is affected by the potential of the signal line Lb corresponding to the third sub-pixel Sγ and the potential of the signal line Lb corresponding to the first sub-pixel Sα. Therefore, the gradation of the third sub-pixel Sγ fluctuates similarly in both the first display device 2a and the second display device 2b.

[0084] Furthermore, in the first display device 2a shown in Figure 3, the signal line Lb electrically connected to the first subpixel Sα is located -D1 side of the first subpixel Sα, and the signal line Lb located +D1 side of the first subpixel Sα is electrically connected to the second subpixel Sβ adjacent to the first subpixel Sα. On the other hand, in the second display device 2b shown in Figure 6, the signal line Lb electrically connected to the first subpixel Sα is located +D1 side of the first subpixel Sα, and the signal line Lb located -D1 side of the first subpixel Sα is electrically connected to the second subpixel Sβ adjacent to the first subpixel Sα.

[0085] In other words, similar to the case of the second sub-pixel Sβ described above, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the first sub-pixel Sα is affected by the potential of the signal line Lb corresponding to the first sub-pixel Sα and the potential of the signal line Lb corresponding to the second sub-pixel Sβ. Therefore, the gradation of the first sub-pixel Sα fluctuates similarly in both the first display device 2a and the second display device 2b.

[0086] Thus, in the first display device 2a and the second display device 2b, the gradation of the first sub-pixel Sα, the gradation of the second sub-pixel Sβ, and the gradation of the third sub-pixel Sγ vary similarly. Therefore, when the same image is displayed on each of the pair of display devices 1, the difference in chromaticity between the images displayed on the pair of display devices 1 can be suppressed.

[0087] Next, a comparative example pair of display devices 1a will be described. The comparative example pair of display devices 1a includes a first display device 2a, similar to the pair of display devices 1 in the embodiment described above. The comparative example pair of display devices 1a differs from the pair of display devices 1 in the embodiment described above in that it includes a second display device 2ba instead of a second display device 2b. In other words, the comparative example pair of display devices 1a includes a first display device 2a and a second display device 2ba.

[0088] The comparative example's second display device 2ba is configured similarly to the second display device 2b of the above embodiment, except that the arrangement of the signal lines Lb is different. In other words, in the comparative example's pair of display devices 1a, the arrangement of multiple sub-pixels S in the display area DA of the first display device 2a and the arrangement of multiple sub-pixels S in the display area DA of the second display device 2ba are symmetrical with respect to the virtual line Lv orthogonal to the X1 direction, but the arrangement of multiple signal lines Lb in the first display device 2a and the arrangement of multiple signal lines Lb in the second display device 2ba are not symmetrical with respect to the virtual line Lv.

[0089] Specifically, the arrangement of the multiple signal lines Lb in the comparative example's second display device 2ba is the same as the arrangement of the multiple signal lines Lb in the first display device 2a of the above embodiment (Figure 3). That is, in the comparative example's second display device 2ba, the m-th signal line Lb is positioned on the -D1 side of the multiple sub-pixels S arranged in the m-th column. The m-th signal line Lb branches off and is electrically connected to the multiple sub-pixels S arranged in the m-th column.

[0090] Figure 10 is a partially enlarged view of the circuit configuration of the display panel 10 of the second display device 2ba in the comparative example pair of display devices 1a. In Figure 10, the second sub-pixel Sβ and the first sub-pixel Sα are shown, which are electrically connected to the same gate line Lc and are adjacent to each other.

[0091] As shown in Figure 10, the signal line Lb electrically connected to the second subpixel Sβ is located -D1 side of the second subpixel Sβ, and the signal line Lb located +D1 side of the second subpixel Sβ is electrically connected to the first subpixel Sα adjacent to the second subpixel Sβ. In other words, in the comparative example second display device 2ba, the holding capacitance CS of the second subpixel Sβ is affected by the potential of the signal line Lb corresponding to the second subpixel Sβ and the potential of the signal line Lb corresponding to the first subpixel Sα.

[0092] On the other hand, the comparative example pair of display devices 1a includes a first display device 2a, similar to the pair of display devices 1 in the above embodiment. Therefore, in the first display device 2a of the comparative example pair of display devices 1a, the retention capacitance CS of the second sub-pixel Sβ is affected by the potential of the signal line Lb corresponding to the second sub-pixel Sβ and the potential of the signal line Lb corresponding to the third sub-pixel Sγ.

[0093] Therefore, in the comparative example pair of display devices 1a, the retention capacitance CS of the second sub-pixel Sβ is affected by the potential of the signal line Lb corresponding to different sub-pixels S between the first display device 2a and the second display device 2ba. In this case, the gradation of the second sub-pixel Sβ may not fluctuate similarly in the first display device 2a and the second display device 2ba of the comparative example pair of display devices 1a. The same applies to the first sub-pixel Sα and the third sub-pixel Sγ. Thus, the difference in chromaticity between the images displayed by the comparative example pair of display devices 1a may be greater than the difference in chromaticity between the images displayed by the pair of display devices 1 of the above embodiment.

[0094] Figure 11 shows the circuit configuration of the display panel 10 provided in the first display device 2a in a pair of display devices 1 according to a modified embodiment of the present disclosure.

[0095] The first display device 2a of this modified example and the first display device 2a of the above embodiment are configured similarly except for the arrangement of the multiple signal lines Lb.

[0096] The multiple signal lines Lb1 in the first display device 2a of this modified example extend along the column direction D2 and are arranged along the row direction D1, similar to the first display device 2a of the above embodiment. In the row direction D1, the signal lines Lb1 and sub-pixels S are arranged alternately.

[0097] Unlike the signal lines Lb of the first display device 2a in the above embodiment, the multiple signal lines Lb1 provided in the modified first display device 2a are M+1 when the total number of sub-pixels S arranged in ascending order from the 1st column to the mth column (where m is a natural number) along the row direction D1 from one end (the -D1 side) to the other end (the +D1 side) is M. The first signal line Lb1 is located on the -D1 side of the multiple sub-pixels S arranged in the 1st column. The mth signal line Lb1 branches off and connects to sub-pixels S arranged in the m-1 column of even-numbered rows, and to sub-pixels S arranged in the mth column of odd-numbered rows.

[0098] Figure 12 shows the circuit configuration of the display panel 10 of the second display device 2b in a pair of display devices 1 according to a modified embodiment of the present disclosure.

[0099] The second display device 2b of this modified example and the second display device 2b of the above embodiment are configured similarly except for the arrangement of the multiple signal lines Lb.

[0100] The multiple signal lines Lb1 in the second display device 2b of this modified example extend along the column direction D2 and are arranged along the row direction D1, similar to the second display device 2b of the above embodiment. In the row direction D1, the signal lines Lb1 and sub-pixels S are arranged alternately.

[0101] The multiple signal lines Lb1 in the modified second display device 2b differ from the signal lines Lb of the second display device 2b in the above embodiment in that the first signal line Lb1 is located on the -D1 side of the multiple sub-pixels S arranged in the first column. Furthermore, when M is the total number of sub-pixels S arranged in ascending order from the first column to the mth column (where m is a natural number) along the row direction D1 from one end (the -D1 side end) to the other end (the +D1 side end), the total number of signal lines Lb1 is M+1. In addition, the mth signal line Lb1 branches off and connects to the sub-pixels S arranged in the (m-1)th column of odd-numbered rows, and to the sub-pixels S arranged in the mth column of even-numbered rows.

[0102] With the arrangement of multiple signal lines Lb1 in this manner, the arrangement of multiple signal lines Lb1 in the first display device 2a of the modified example and the arrangement of multiple signal lines Lb1 in the second display device 2b of the modified example are symmetrical with respect to the virtual line Lv.

[0103] Furthermore, with multiple signal lines Lb1 arranged in this way, in the first display device 2a shown in Figure 11, the signal line Lb1 electrically connected to the first subpixel Sα of an odd-numbered row is located -D1 side of the first subpixel Sα, and the signal line Lb1 located +D1 side of the first subpixel Sα is electrically connected to the second subpixel Sβ adjacent to the first subpixel Sα. On the other hand, in the second display device 2b shown in Figure 12, the signal line Lb1 electrically connected to the first subpixel Sα of an odd-numbered row is located +D1 side of the first subpixel Sα, and the signal line Lb1 located -D1 side of the first subpixel Sα is electrically connected to the second subpixel Sβ adjacent to the first subpixel Sα.

[0104] In other words, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the first sub-pixel Sα in odd-numbered rows is affected by the potential of the signal line Lb1 corresponding to the first sub-pixel Sα and the potential of the signal line Lb1 corresponding to the second sub-pixel Sβ. Therefore, in both the first display device 2a and the second display device 2b, the gradation of the first sub-pixel Sα in odd-numbered rows fluctuates similarly.

[0105] Furthermore, in the first display device 2a shown in Figure 11, the signal line Lb1 electrically connected to the first subpixel Sα of an even row is located +D1 side of the first subpixel Sα, and the signal line Lb1 located -D1 side of the first subpixel Sα is electrically connected to the third subpixel Sγ adjacent to the first subpixel Sα. On the other hand, in the second display device 2b shown in Figure 12, the signal line Lb1 electrically connected to the first subpixel Sα of an even row is located -D1 side of the first subpixel Sα, and the signal line Lb1 located +D1 side of the first subpixel Sα is electrically connected to the third subpixel Sγ adjacent to the first subpixel Sα.

[0106] In other words, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the first sub-pixel Sα in even-numbered rows is affected by the potential of the signal line Lb1 corresponding to the first sub-pixel Sα and the potential of the signal line Lb1 corresponding to the third sub-pixel Sγ. Therefore, in both the first display device 2a and the second display device 2b, the gradation of the first sub-pixel Sα in even-numbered rows fluctuates similarly.

[0107] Furthermore, with multiple signal lines Lb1 arranged in this way, in the first display device 2a shown in Figure 11, the signal line Lb1 electrically connected to the second subpixel Sβ of an odd-numbered row is located -D1 side of the first subpixel Sα, and the signal line Lb1 located +D1 side of the second subpixel Sβ is electrically connected to the third subpixel Sγ adjacent to the second subpixel Sβ. On the other hand, in the second display device 2b shown in Figure 12, the signal line Lb1 electrically connected to the second subpixel Sβ of an odd-numbered row is located +D1 side of the first subpixel Sα, and the signal line Lb1 located -D1 side of the second subpixel Sβ is electrically connected to the third subpixel Sγ adjacent to the second subpixel Sβ.

[0108] In other words, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the second sub-pixel Sβ in odd-numbered rows is affected by the potential of the signal line Lb1 corresponding to the second sub-pixel Sβ and the potential of the signal line Lb1 corresponding to the third sub-pixel Sγ. Therefore, in both the first display device 2a and the second display device 2b, the gradation of the second sub-pixel Sβ in odd-numbered rows fluctuates similarly.

[0109] Furthermore, in the first display device 2a shown in Figure 11, the signal line Lb1 electrically connected to the second subpixel Sβ of an even row is located +D1 side of the second subpixel Sβ, and the signal line Lb1 located -D1 side of the first subpixel Sα is electrically connected to the first subpixel Sα adjacent to the first subpixel Sα. On the other hand, in the second display device 2b shown in Figure 12, the signal line Lb1 electrically connected to the second subpixel Sβ of an even row is located -D1 side of the second subpixel Sβ, and the signal line Lb1 located +D1 side of the second subpixel Sβ is electrically connected to the first subpixel Sα adjacent to the second subpixel Sβ.

[0110] In other words, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the second sub-pixel Sβ in even-numbered rows is affected by the potential of the signal line Lb1 corresponding to the second sub-pixel Sβ and the potential of the signal line Lb1 corresponding to the first sub-pixel Sα. Therefore, in both the first display device 2a and the second display device 2b, the gradation of the second sub-pixel Sβ in even-numbered rows fluctuates similarly.

[0111] Furthermore, with multiple signal lines Lb1 arranged in this way, in the first display device 2a shown in Figure 11, the signal line Lb1 electrically connected to the third subpixel Sγ of an odd-numbered row is located -D1 side of the third subpixel Sγ, and the signal line Lb1 located +D1 side of the third subpixel Sγ is electrically connected to the first subpixel Sα adjacent to the third subpixel Sγ. On the other hand, in the second display device 2b shown in Figure 12, the signal line Lb1 electrically connected to the third subpixel Sγ of an odd-numbered row is located +D1 side of the third subpixel Sγ, and the signal line Lb1 located -D1 side of the third subpixel Sγ is electrically connected to the first subpixel Sα adjacent to the third subpixel Sγ.

[0112] In other words, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the third sub-pixel Sγ in odd-numbered rows is affected by the potential of the signal line Lb1 corresponding to the third sub-pixel Sγ and the potential of the signal line Lb1 corresponding to the first sub-pixel Sα. Therefore, in both the first display device 2a and the second display device 2b, the gradation of the third sub-pixel Sγ in odd-numbered rows fluctuates similarly.

[0113] Furthermore, in the first display device 2a shown in Figure 11, the signal line Lb1 electrically connected to the third subpixel Sγ of an even row is located +D1 side of the third subpixel Sγ, and the signal line Lb1 located -D1 side of the third subpixel Sγ is electrically connected to the second subpixel Sβ adjacent to the third subpixel Sγ. On the other hand, in the second display device 2b shown in Figure 12, the signal line Lb1 electrically connected to the third subpixel Sγ of an even row is located -D1 side of the third subpixel Sγ, and the signal line Lb1 located +D1 side of the third subpixel Sγ is electrically connected to the second subpixel Sβ adjacent to the third subpixel Sγ.

[0114] In other words, in both the first display device 2a and the second display device 2b, the retention capacitance CS of the third sub-pixel Sγ in even-numbered rows is affected by the potential of the signal line Lb1 corresponding to the third sub-pixel Sγ and the potential of the signal line Lb1 corresponding to the second sub-pixel Sβ. Therefore, in both the first display device 2a and the second display device 2b, the gradation of the second sub-pixel Sβ in even-numbered rows fluctuates similarly.

[0115] Thus, in the first display device 2a and the second display device 2b, the gradation of the first sub-pixel Sα, the gradation of the second sub-pixel Sβ, and the gradation of the third sub-pixel Sγ vary similarly. Therefore, even in this modified example of a pair of display devices 1, when the same image is displayed on each of the pair of display devices 1, the difference in chromaticity between the images displayed on the pair of display devices 1 can be suppressed.

[0116] Furthermore, in the display device 2 of the above embodiment, the drive circuit 11 may output sub-pixel signals using a second column inversion control method, which will be described below, instead of the column inversion drive method described above.

[0117] Figure 13 shows a state in which a drive circuit 11 of a display device 2 outputs a sub-pixel signal by a second column inversion drive method in a pair of display devices 1 according to a modified embodiment of the present disclosure.

[0118] Multiple signal lines Lb include multiple signal line pairs C. Each signal line pair C consists of two signal lines Lb that are adjacent to each other in the row direction D1. Multiple signal line pairs C are arranged consecutively, adjacent to each other along the row direction D1.

[0119] The second column inversion driving method is a driving method for subpixels S in which the polarity of the subpixel signal is the same in two signal lines Lb included in signal line set C, and the polarity of the subpixel signal is different in two adjacent signal line sets C in the row direction D1, and the polarity of the subpixel signal is periodically inverted. The symbols in parentheses in Figure 13 indicate the polarity of the subpixel signal at any given timing.

[0120] Even when the drive circuit 11 outputs a sub-pixel signal using the second column inversion drive method, the gradation of the first sub-pixel Sα, the gradation of the second sub-pixel Sβ, and the gradation of the third sub-pixel Sγ in the first display device 2a and the second display device 2b fluctuate similarly. Therefore, even in this modified example of a pair of display devices 1, when the same image is displayed on each of the pair of display devices 1, the difference in chromaticity between the images displayed on the pair of display devices 1 can be suppressed.

[0121] <Display System 100> Figure 14 is a perspective view of a display system 100 according to an embodiment of the present disclosure. Figure 15 is a schematic diagram showing the configuration of the display system 100. The display system 100 is, for example, a head-mounted display. The display system 100 displays images such as computer graphics and 360-degree live-action video.

[0122] The display system 100 comprises a mounting unit 3, a video signal source 4, two lenses 5, and the pair of display devices 1 described above.

[0123] The wearable part 3 is, for example, a headset, goggles, helmet, and mask. The wearable part 3 comprises a main body 3a and a belt 3b. The main body 3a houses a video signal source 4, two lenses 5, and a pair of display devices 1. The belt 3b is wrapped around the user's head to secure the main body 3a to the user's head. The wearable part 3 is worn on the user's head with the main body 3a covering both of the user's eyes.

[0124] The video signal source 4 outputs an image signal containing image information to a pair of display devices 1. The image signal includes two distinct images that utilize the parallax between the user's two eyes. These two images are for the user's right eye and the user's left eye, and are substantially the same. The video signal source 4 outputs images pre-stored internally to the pair of display devices 1. The video signal source 4 includes, for example, an HDD (Hard Disk Drive) and flash memory. The video signal source 4 may be located outside the mounting unit 3. In this case, the video signal source 4 is a computer (e.g., a server) electrically connected to the pair of display devices 1 by wire or wireless means.

[0125] The two lenses 5 are positioned opposite the user's eyes E. The lenses 5 are, for example, convex lenses made of glass. The two lenses 5 correspond to both of the user's eyes. The lenses 5 are positioned between the pair of display devices 1 and the user's eyes E. Due to the lenticular action of the lenses 5, the light emitted from the pair of display devices 1 is focused towards the user's eyes E. The user then views an enlarged image of the image displayed on the pair of display devices 1.

[0126] The pair of display devices 1 are positioned on the opposite side of the user's eyes E, with two lenses 5 in between.

[0127] Figure 16 shows the arrangement of a pair of display devices 1 in the mounting section 3. The X1 direction of the pair of display devices 1 corresponds to the left-right direction of the user's eyes.

[0128] The first display device 2a acquires an image for the left eye from the video signal source 4. The display area DA of the first display device 2a faces the user's left eye and displays the image for the left eye. The second display device 2b acquires an image for the right eye from the video signal source 4. The display area DA of the second display device 2b faces the user's right eye and displays the image for the right eye.

[0129] In such a display system 100, the distance between the display area DA and the eye is relatively small, and it is desirable to display a fine image in the display area DA. Therefore, the pitch of two adjacent subpixels S in a pair of display devices 1 is set to be relatively small. Even in this case, by determining the arrangement of the number of subpixels S and the arrangement of multiple signal lines Lb as described above, it is possible to suppress the difference in chromaticity between the images displayed on the pair of display devices 1 when the same image is displayed on each of the pair of display devices 1.

[0130] While preferred embodiments of this disclosure have been described above, this disclosure is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure.

[0131] For example, one end of the row direction D1 may be the +D1 end, or one end of the column direction D2 may be the +D2 end. In this case, in a plan view of the display area DA of the first display device 2a, the first subpixel Sα, the second subpixel Sβ, and the third subpixel Sγ are repeatedly arranged in this order along the row direction D1 from the +D1 side to the -D1 side, and the first subpixel Sα, the second subpixel Sβ, and the third subpixel Sγ are repeatedly arranged in this order along the column direction D2 from the +D2 side to the -D2 side.

[0132] Furthermore, the display panel 10 may be a vertical electric field type liquid crystal display in which a common electrode CE is arranged on the second substrate 14 so as to face multiple sub-pixel electrodes PE. Alternatively, the display panel 10 may be a reflective type liquid crystal display.

[0133] Furthermore, the X2 direction of the display device 2 may be tilted with respect to the X1 direction of the pair of display devices 1. Also, the X2 direction of the first display device 2a may be tilted with respect to the X2 direction of the second display device 2b.

[0134] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally provided by this disclosure. [Explanation of Symbols]

[0135] 1 Display device 2a 1st display device 2b 2nd display device 5 lenses 10 Display Panel 11 Drive Circuit 100 Display Systems C signal wire set D1 row direction D2 column direction DA display area Lb signal line Lc gate line Lv virtual line S subpixel SL Slit Sα (First subpixel) Sβ Second Subpixel Sγ (third subpixel) X1 Array direction

Claims

1. It comprises a first display device and a second display device arranged along the direction of arrangement, The first display device and the second display device are, respectively, A display panel having a display area in which multiple subpixels are arranged in a matrix along the row and column directions, The display panel is arranged with a plurality of gate lines that extend along the row direction and are aligned along the column direction, The display panel comprises a plurality of signal lines, which are arranged along the column direction and aligned along the row direction, The system includes a drive circuit that outputs a sub-pixel signal to the sub-pixel via the signal line to display an image in the display area, and drives the sub-pixel via the gate line, Each of the aforementioned subpixels has multiple first subpixels, second subpixels, and third subpixels, each having a different color from the others. In the display area of ​​the first display device, the plurality of first subpixels, plurality of second subpixels, and plurality of third subpixels are arranged such that the first subpixels, second subpixels, and third subpixels are repeated in this order along the row direction, and the first subpixels, second subpixels, and third subpixels are repeated in this order along the column direction. The arrangement of the plurality of subpixels in the display area of ​​the first display device and the arrangement of the plurality of subpixels in the display area of ​​the second display device are symmetrical with respect to a virtual line perpendicular to the arrangement direction. The arrangement of the plurality of signal lines of the first display device and the arrangement of the plurality of signal lines of the second display device are symmetrical with respect to the virtual line as the axis of symmetry. A pair of display devices.

2. When M is the total number of subpixels arranged in ascending order from the 1st column to the mth column (where m is a natural number) along the row direction, The total number of signal lines is M. In the first display device and the second display device, the m-th signal line is electrically connected to a plurality of sub-pixels arranged in the m-th column. A pair of display devices according to claim 1.

3. When M is the total number of subpixels arranged in ascending order from the 1st column to the mth column (where m is a natural number) along the row direction, The total number of signal lines is M+1. In the first display device, the m-th signal line is connected to the sub-pixels arranged in the m-1 column of even-numbered rows, and to the sub-pixels arranged in the m-th column of odd-numbered rows. In the second display device, the m-th signal line is connected to the sub-pixels arranged in the (m-1)th column of odd-numbered rows, and to the sub-pixels arranged in the (m)th column of even-numbered rows. A pair of display devices according to claim 1.

4. The drive circuit outputs the sub-pixel signal by a column inversion drive method in which the polarities of the sub-pixel signals are different in two adjacent signal lines in the row direction, and the polarity of the sub-pixel signals is periodically reversed. A pair of display devices according to claim 1.

5. The plurality of signal lines include a plurality of signal line sets, each set containing two signal lines adjacent to each other in the row direction. The multiple signal line sets are arranged in a continuous line adjacent to each other along the row direction. The drive circuit outputs the sub-pixel signal by a second column inversion drive method in which the polarity of the sub-pixel signal is the same for two of the signal lines included in the signal line set, and the polarity of the sub-pixel signal is different for two adjacent signal line sets in the row direction, and the polarity of the sub-pixel signal is periodically inverted. A pair of display devices according to claim 1.

6. The first sub-pixel is a red sub-pixel, The aforementioned second subpixel is a green subpixel, The aforementioned third sub-pixel is a blue sub-pixel. A pair of display devices according to claim 1.

7. A pair of display devices according to claim 1, Equipped with a lens, Display system.

Images