Semiconductor modules and semiconductor module systems
The semiconductor module addresses surge voltage reduction by optimizing frame configurations and incorporating snubber capacitors to minimize parasitic inductance, enhancing switching performance and safety.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2024-11-28
- Publication Date
- 2026-06-09
AI Technical Summary
Existing semiconductor modules do not adequately address the reduction of surge voltage when switching elements are turned off, despite successful reduction of switching loss through increased switching speed.
The semiconductor module design includes multiple semiconductor chip groups with specific frame configurations and terminal arrangements that minimize parasitic inductance by arranging frames parallel to current flow directions, incorporating snubber capacitors, and optimizing terminal protrusions to reduce surge voltage.
The design effectively reduces surge voltage by canceling out magnetic flux and parasitic inductance, allowing for improved switching performance and safety.
Smart Images
Figure 2026093694000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor module, and more particularly to a semiconductor module with reduced surge voltage.
Background Art
[0002] When driving a semiconductor device at high frequency, reduction of switching loss is essential. To reduce switching loss, it is necessary to increase the switching speed.
[0003] For example, in FIG. 1C of Patent Document 1, in a semiconductor module equipped with a switching element, in order to reduce the switching loss when the switching element is turned on, the path members through which the reverse recovery current and the gate current flow are arranged so that a mutual induction current is generated, and a configuration for increasing the switching speed when turned on is disclosed.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] In Patent Document 1, although the switching loss when the switching element is turned on can be reduced, reduction of the surge voltage when the switching element is turned off is not considered.
[0006] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor module with reduced surge voltage when a switching element is turned off.
Means for Solving the Problems
[0007] The semiconductor module according to this disclosure comprises a plurality of semiconductor chip groups, each having a first semiconductor chip and a second semiconductor chip connected in series between a first power line to which a first voltage is applied and a second power line to which a second voltage lower than the first voltage is applied, and which switch complementaryly, wherein each of the semiconductor chip groups includes a first frame connected to the lower electrode of the first semiconductor chip and having a first terminal which is a portion that protrudes outward from the semiconductor module, a second frame connected to the upper electrode of the second semiconductor chip and having a second terminal which is a portion that protrudes outward from the semiconductor module, and a portion connected to the upper electrode of the first semiconductor chip and the lower electrode of the second semiconductor chip, and the semiconductor chip group. The semiconductor chip has a third frame having a third terminal which is a portion protruding outward from the conductor module, a fourth terminal connected to the gate electrode of the first semiconductor chip and protruding outward from the semiconductor module, and a fifth terminal connected to the gate electrode of the second semiconductor chip and protruding outward from the semiconductor module, and the second frame and the third frame each have first opposing portions arranged parallel to the direction of current flow, and in adjacent semiconductor chip groups among the plurality of groups, at least one of the first frame of one semiconductor chip group and the second frame of the other semiconductor chip group each have second opposing portions arranged parallel to the direction of current flow. [Effects of the Invention]
[0008] The semiconductor module according to this disclosure has at least one of a first opposing portion and a second opposing portion, so that the surge voltage during the turn-off of the first semiconductor chip and the second semiconductor chip, which are switching elements, can be reduced. [Brief explanation of the drawing]
[0009] [Figure 1] Figure 1 is a plan view showing the configuration of the semiconductor module of Embodiment 1. [Figure 2] Figure 2 is a plan view visually showing the first opposing portion in the semiconductor module of Embodiment 1. [Figure 3] Figure 3 is a plan view visually showing the extended portion of the frame in the semiconductor module of Embodiment 1. [Figure 4] Figure 4 is a plan view visually showing the second opposing portion in the semiconductor module of Embodiment 1. [Figure 5] Figure 5 is a plan view showing an example of snubber capacitor arrangement in the semiconductor module of Embodiment 1. [Figure 6] Figure 6 is a plan view showing an example of the arrangement of snubber capacitors in the semiconductor module of Embodiment 1. [Figure 7] Figure 7 shows an example of an external circuit when a snubber capacitor is installed for each phase. [Figure 8] Figure 8 shows an example of an external circuit when using one snubber capacitor in a three-phase system. [Figure 9] Figure 9 shows an example of an external circuit when one semiconductor module is used as a single-phase semiconductor module. [Figure 10] Figure 10 is a conceptual diagram showing an example of two semiconductor modules connected in parallel. [Figure 11] Figure 11 is a plan view showing the configuration of a semiconductor module of a modified example 1 of Embodiment 1. [Figure 12] Figure 12 is a block diagram showing the configuration of the semiconductor module system of Embodiment 2 according to this disclosure. [Modes for carrying out the invention]
[0010] <Embodiment 1> Figure 1 is a plan view showing the configuration of the semiconductor module 100 of Embodiment 1 according to this disclosure, and for convenience, the resin package PG is partially omitted to show the internal configuration.
[0011] As shown in FIG. 1, a plurality of semiconductor chips SC1 and a plurality of semiconductor chips SC2 are mounted on a plurality of frames provided on an insulating material BS in a semiconductor module 100.
[0012] FIG. 1 illustrates a circuit that can be used as a three-phase full-bridge inverter. The inverters of the U-phase, V-phase, and W-phase all have the same configuration.
[0013] For example, the U-phase inverter is composed of a semiconductor chip SC1 (the first semiconductor chip) and a semiconductor chip SC2 (the second semiconductor chip) connected in series between a power line (the first power line) connected to the positive terminal of a DC power supply (not shown) to supply a positive voltage (the first voltage) and a power line (the first power line) connected to the negative terminal to supply a negative positive voltage (the second voltage).
[0014] The semiconductor chip SC1 is mounted on a frame 2 (the first frame) constituting a circuit pattern, and the semiconductor chip SC2 is mounted on a frame 9 (the third frame). The upper surface electrodes of the semiconductor chips SC1 and SC2 are the emitter electrodes 6 and 3 respectively, and the lower surface electrodes are the collector electrodes.
[0015] One end of the frame 2 protrudes outward from the resin package PG as an upper arm collector terminal 1 (the first terminal), and one end of the frame 9 protrudes outward from the resin package PG as an upper arm emitter terminal / lower arm collector terminal 8 (the third terminal), which serves as the output terminal of the U-phase inverter. The upper arm collector terminal 1 and the upper arm emitter terminal / lower arm collector terminal 8 protrude from opposite sides of the resin package PG.
[0016] The emitter electrode 6 of the semiconductor chip SC1 is electrically connected to the frame 9 (the third frame) via a wire WR, and the emitter electrode 3 of the semiconductor chip SC2 is electrically connected to the frame 5 (the second frame) via a wire WR.
[0017] Frame 5 has a portion parallel to frame 2, and one end of frame 5 protrudes outward from the resin package PG as the lower arm emitter terminal 4 (second terminal). The lower arm emitter terminal 4 protrudes from the same side of the resin package PG as the upper arm collector terminal 1.
[0018] Frame 5 has a portion parallel to frame 2 and a portion parallel to frame 9, and in the portion parallel to frame 9, it is electrically connected to the emitter electrode 3 of semiconductor chip SC2 via wire WR.
[0019] The semiconductor chip SC1 has a gate electrode GT on its upper surface, and the gate electrode GT is electrically connected to the control terminal 10 (the fourth terminal) via a wire WR.
[0020] The semiconductor chip SC2 has a gate electrode GT on its upper surface, and the gate electrode GT is electrically connected to the control terminal 11 (the fifth terminal) via a wire WR.
[0021] One end of each control terminal 10 and 11 protrudes from the side of the same resin package PG as the upper arm emitter terminal / lower arm collector terminal 8. In the above description, semiconductor chips SC1 and SC2 are assumed to be reverse conducting IGBTs (RC-IGBTs), in which an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FWD) are provided on a common semiconductor substrate. However, semiconductor chips SC1 and SC2 are not limited to RC-IGBTs and can also be IGBTs and MOSFETs (MOS Field Effect Transistors), etc. Furthermore, the semiconductor substrate is not limited to a silicon substrate and can also be a silicon carbide (SiC) substrate.
[0022] The configuration of the U-phase inverter described above is the same for the V-phase and W-phase inverters. The same reference numerals are used for identical components, and redundant explanations are omitted. The following describes the features of the semiconductor module 100 shown in Figure 1.
[0023] <Feature 1> The upper arm collector terminal 1 (first terminal) and lower arm emitter terminal 4 (second terminal) of the multiple semiconductor chip groups constituting the inverter of each phase protrude alternately from one side of the semiconductor module 100, while the upper arm emitter terminal / lower arm collector terminal 8 (third terminal), control terminal 10 (fourth terminal), and control terminal 11 (fifth terminal) protrude alternately from the other side of the semiconductor module 100 opposite to the one side.
[0024] As shown in Figure 1, in each semiconductor chip group of the semiconductor module 100, frame 5 (second frame) and frame 9 (third frame) have opposing portions that are arranged parallel to the direction of current flow.
[0025] This part is visually represented in Figure 2. Figure 2 shows the same semiconductor module 100 as in Figure 1, but it is simplified by showing only the relevant reference numerals. In Figure 2, frames 5 and 9 in the area indicated by the border line FL are opposing parts (first opposing parts) arranged parallel to the direction of current flow. There, the direction of current flow indicated by the arrows, in this case the current flowing from the upper arm collector terminal 1 to the lower arm emitter terminal 4, is opposite to each other. As a result, the magnetic flux generated by the current flow cancels each other out, and parasitic inductance can be reduced. Therefore, the surge voltage generated by parasitic inductance can be reduced.
[0026] <Features 2> In Figure 2, in the area indicated by the border line FL, an extended portion has been intentionally added to frame 9 so that the opposing portion between frame 5 and frame 9 is as long as possible. This portion is visually represented in Figure 3.
[0027] In Figure 3, the frame 9 in the area indicated by the border line FL is the extended portion EX, which extends parallel to frame 5 from the mounting portion of the semiconductor chip SC2 in frame 9. Compared to the case without the extended portion EX, the effect of canceling each other's magnetic flux is increased, and the effect of reducing parasitic inductance is enhanced.
[0028] <Feature 3> As shown in Figure 1, in adjacent semiconductor chip groups, frame 2 (first frame) of one semiconductor chip group and frame 5 (second frame) of the other adjacent semiconductor chip group have opposing portions arranged parallel to each other with respect to the direction of current flow.
[0029] This part is visually illustrated in Figure 4. Figure 4 shows the same semiconductor module 100 as in Figure 1, but it is simplified by showing only the relevant reference numerals. In Figure 4, frames 2 and 5 in the area indicated by the border line FL are opposing parts (second opposing parts) arranged parallel to the direction of current flow. There, the currents indicated by the arrows, that is, the directions of the currents flowing in each part, are opposite to each other, and the magnetic fluxes generated by the current flow cancel each other out, thus reducing parasitic inductance. As a result, the surge voltage generated by parasitic inductance can be reduced.
[0030] <Feature 4> As explained using Figures 2 and 4, in opposing sections where frames are arranged parallel to the direction of current flow, the distance between opposing frames is set to be as narrow as possible.
[0031] Figure 2 schematically shows the spacing between opposing frames with arrows AR. Specifically, the distances indicated by arrows AR between frame 5 and frame 9 of one semiconductor chip group, between frame 9 and frame 2, and between frame 2 of one semiconductor chip group and frame 5 of the adjacent semiconductor chip group are set to the shortest possible distance so as to ensure sufficient insulation distance to meet the voltage rating required by the semiconductor module 100.
[0032] For example, if the withstand voltage of semiconductor module 100 is 600-1200V, the shortest distance should be set to about 1-5mm. By making the distance between opposing frames as narrow as possible, the effect of canceling out the magnetic flux generated by the flow of current can be further enhanced.
[0033] <Feature 5> As shown in Figure 1, there are no other terminals between the upper arm collector terminal 1 (first terminal) and the lower arm emitter terminal 4 (second terminal) of the semiconductor chip group, and they are positioned adjacent to each other. By adopting this configuration, a snubber capacitor can be placed between frame 2 (first frame) and frame 5 (second frame), or between the upper arm collector terminal 1 and the lower arm emitter terminal 4. By placing a snubber capacitor, parasitic inductance can be further reduced, and surge voltage can be further reduced.
[0034] Figure 5 shows an example in which a snubber capacitor SC is placed between frame 2 and frame 5 within the resin package PG. The distance between frame 2 and frame 5 is set to be as narrow as possible, but the insulation distance is set to ensure that the voltage withstand voltage required by the voltage rating of the semiconductor module 100 is secured.
[0035] Figure 6 shows an example in which a snubber capacitor SC is placed between the upper arm collector terminal 1 and the lower arm emitter terminal 4. The distance between the upper arm collector terminal 1 and the lower arm emitter terminal 4 is set to be as narrow as possible, but is set to an insulation distance sufficient to ensure the withstand voltage required by the voltage rating of the semiconductor module 100.
[0036] In both examples, it becomes possible to place the surge-protection snubber capacitor SC in close proximity to the semiconductor chip.
[0037] <Feature section 6> As shown in Figure 1, the upper arm collector terminal 1 and the lower arm emitter terminal 4 protrude outward from one side of the resin package PG individually for each phase, thus ensuring sufficient terminal width and internal wiring width, and reducing the wiring inductance inside the semiconductor module 100.
[0038] Furthermore, as explained using Figures 5 and 6, it becomes possible to mount a snubber capacitor for each phase, thereby reducing the capacitance of each snubber capacitor. Reducing the snubber capacitor capacitance allows for a reduction in the size of the snubber capacitor.
[0039] Figure 7 shows an example of an external circuit when a snubber capacitor is installed for each phase. As shown in Figure 7, a snubber capacitor SC is connected between the upper arm collector terminal 1 and the lower arm emitter terminal 4 of each phase. The upper arm collector terminal 1 of each phase is connected to the positive terminal of the DC power supply PW, and the lower arm emitter terminal 4 of each phase is connected to the negative terminal of the DC power supply PW. The upper arm emitter terminal / lower arm collector terminal 8, which is the output terminal of each phase, is connected to the wiring of each phase of the motor MT, which is the load, and the control terminals 10 and 11 of each phase are connected to the drive circuit DC of the semiconductor chip.
[0040] Furthermore, instead of using a snubber capacitor for each phase, it is possible to use one snubber capacitor for all three phases. Figure 8 shows an example of an external circuit when using one snubber capacitor for all three phases. As shown in Figure 8, the snubber capacitor SC is connected in parallel with the DC power supply PW. The other configurations are the same as in Figure 7. This reduces the number of snubber capacitors and simplifies the external circuit.
[0041] Furthermore, it is possible to use one semiconductor module 100 as a single-phase semiconductor module. Figure 9 shows an example of the external circuit when one semiconductor module 100 is used as a single-phase semiconductor module. As shown in Figure 9, the three upper arm emitter terminals / lower arm collector terminals 8 are connected in common to the wiring of one phase of the load motor MT, and all control terminals 10 and all control terminals 11 are connected in common to the semiconductor chip drive circuit DC. The other configurations are the same as in Figure 8. By using multiple semiconductor chip groups within the semiconductor module 100 as a single-phase semiconductor chip, the amount of usable power can be increased.
[0042] Furthermore, by making the upper arm collector terminal 1 and the lower arm emitter terminal 4 protrude to the outside for each phase, parallel connection of multiple semiconductor modules 100 becomes easier.
[0043] Figure 10 is a conceptual diagram showing an example of two semiconductor modules 100 connected in parallel. As shown in Figure 10, the two semiconductor modules 100 can be connected in parallel by electrically connecting the upper arm collector terminals 1 of each phase of the two semiconductor modules 100, the lower arm emitter terminals 4 of each phase, and the upper arm emitter terminals / lower arm collector terminals 8 of each phase with external wiring OW, thereby reducing wiring inductance.
[0044] <Example 1> In the semiconductor module 100 shown in Figure 1, as explained using Figure 2, in the opposing portions where frames 5 and 9 are arranged parallel to the direction of current flow, the directions of current flow are opposite to each other. The emitter electrode 6 of semiconductor chip SC1 is electrically connected to frame 9 (the third frame) via wire WR. By changing the position where wire WR is connected to frame 9, the current path of frame 9 can be lengthened. Similarly, by changing the position of wire WR that electrically connects the emitter electrode 3 of semiconductor chip SC2 to frame 5, the current path of frame 5 can be lengthened.
[0045] Figure 11 is a plan view showing the configuration of a semiconductor module 100A of a modified example 1 of Embodiment 1. In Figure 11, components identical to those of the semiconductor module 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted.
[0046] As shown in Figure 11, the wire WR that electrically connects the emitter electrode 6 of semiconductor chip SC1 to frame 9 is connected to the end of the extended portion of frame 9 furthest from the upper arm emitter terminal / lower arm collector terminal 8 (third terminal). Similarly, the wire WR that electrically connects the emitter electrode 3 of semiconductor chip SC2 to frame 5 is connected to the end of frame 5 furthest from the lower arm emitter terminal 4 (second terminal). As a result, as indicated by the arrows in Figure 11, the current path between the opposing portions of frame 5 and frame 9 can be lengthened, further reducing parasitic inductance. Therefore, surge voltage generated by parasitic inductance can be further reduced.
[0047] <Modification 2> In the semiconductor module 100 shown in Figure 1, the upper arm collector terminal 1 (first terminal), lower arm emitter terminal 4 (second terminal), and upper arm emitter terminal / lower arm collector terminal 8 (third terminal) are shown protruding horizontally from the side of the resin package PG. However, by bending the frame shape at a right angle, they can also protrude in directions other than horizontal from inside the resin package PG. For example, they can protrude from one side of the top or bottom surface of the resin package PG. The same applies to the control terminal 10 (fourth terminal) and control terminal 11 (fifth terminal). By changing the direction of terminal protrusion, the variations in the usage configuration of the semiconductor module 100 can be increased.
[0048] <Embodiment 2> This embodiment relates to a semiconductor module system in which the semiconductor module according to Embodiment 1 described above is applied to a power factor correction circuit, and Figure 12 is a block diagram showing the configuration of the semiconductor module system of Embodiment 2.
[0049] The semiconductor module system shown in Figure 12 consists of a three-phase AC power supply 1000, a power factor correction circuit 2000, and a DC / DC converter 3000. The power factor correction circuit 2000 is a circuit that brings the power factor of the AC power supply 1000 closer to 1 and is called a PFC (power factor correction) circuit.
[0050] By using the semiconductor module 100 described in Embodiment 1 as the three-phase full-bridge converter for the power factor correction circuit 2000, the internal inductance can be reduced. Furthermore, by using a single semiconductor module 100 as the three-phase full-bridge converter, the routing of the wiring around the power factor correction circuit 2000 can be optimized, making it possible to reduce the overall system inductance. This reduces surge voltage and improves the overall safety of the system.
[0051] Furthermore, within the scope of this disclosure, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.
[0052] The above-described disclosure is summarized below as an appendix.
[0053] (Note 1) A semiconductor module comprising a plurality of semiconductor chip groups, each having a first semiconductor chip and a second semiconductor chip connected in series between a first power line to which a first voltage is supplied and a second power line to which a second voltage lower than the first voltage is supplied, and which switch complementaryly, Each of the aforementioned semiconductor chip groups is A first frame having a first terminal which is connected to the lower electrode of the first semiconductor chip and protrudes outward from the semiconductor module, A second frame having a second terminal which is connected to the upper electrode of the second semiconductor chip and is a portion that protrudes from the semiconductor module to the outside, A third frame having a third terminal which is a portion that protrudes from the semiconductor module to the outside, connected to the upper electrode of the first semiconductor chip and the lower electrode of the second semiconductor chip, A fourth terminal connected to the gate electrode of the first semiconductor chip and protruding from the semiconductor module to the outside, It has a fifth terminal connected to the gate electrode of the second semiconductor chip and protruding from the semiconductor module to the outside, The second frame and the third frame have first opposing portions arranged parallel to the direction of current flow, A semiconductor module in which, among the plurality of groups, adjacent semiconductor chip groups have at least one of the first frame of one semiconductor chip group and the second frame of the other semiconductor chip group, which are arranged parallel to the direction of current flow.
[0054] (Note 2) The aforementioned third frame is, The semiconductor module according to Appendix 1, wherein the first opposing portion has an extended portion that extends parallel to the second frame from the portion on which the second semiconductor chip is mounted.
[0055] (Note 3) The distance between the second frame and the third frame in the first opposing portion is, The semiconductor module described in Appendix 2, which is set to the shortest distance that ensures the voltage withstand capability required by the voltage rating of the semiconductor module.
[0056] (Note 4) The aforementioned multiple groups are The first terminal and the second terminal are arranged alternately on the first side of the semiconductor module. The semiconductor module according to Appendix 1, wherein the third terminal, the fourth terminal, and the fifth terminal are arranged alternately on the second side of the semiconductor module opposite to the first side of the semiconductor module.
[0057] (Note 5) The semiconductor module as described in Appendix 1, wherein the first terminal and the second terminal within the semiconductor chip group are arranged adjacent to each other.
[0058] (Note 6) Each of the aforementioned semiconductor chip groups is A semiconductor module according to any one of Appendix 1 to Appendix 5, wherein the first terminal and the second terminal each protrude from the semiconductor module to the outside.
[0059] (Note 7) The top electrode of the first semiconductor chip is electrically connected to the end of the third frame furthest from the third terminal. The semiconductor module according to any one of Appendix 1 to Appendix 5, wherein the upper electrode of the second semiconductor chip is electrically connected to the end of the second frame furthest from the second terminal.
[0060] (Note 8) AC power supply and A power factor correction circuit connected to the aforementioned AC power supply and equipped with a semiconductor module described in any one of the appendices 1 to 5, A semiconductor module system comprising a DC / DC converter connected to the power factor correction circuit. [Explanation of Symbols]
[0061] 1 Upper arm collector terminal, 2, 5, 9 Frame, 3, 6 Emitter electrodes, 4 Lower arm emitter terminal, 8 Upper arm emitter terminal / lower arm collector terminal, 10, 11 Control terminals, GT Grid gate, SC1, SC2 Semiconductor chips.
Claims
1. A semiconductor module comprising a plurality of semiconductor chip groups, each having a first semiconductor chip and a second semiconductor chip connected in series between a first power line to which a first voltage is supplied and a second power line to which a second voltage lower than the first voltage is supplied, and which switch complementaryly, Each of the aforementioned semiconductor chip groups is A first frame having a first terminal which is connected to the lower electrode of the first semiconductor chip and protrudes outward from the semiconductor module, A second frame having a second terminal which is a portion that is connected to the upper electrode of the second semiconductor chip and protrudes outward from the semiconductor module, A third frame having a third terminal which is connected to the upper electrode of the first semiconductor chip and the lower electrode of the second semiconductor chip, and which is a portion that protrudes from the semiconductor module to the outside, A fourth terminal connected to the gate electrode of the first semiconductor chip and protruding from the semiconductor module to the outside, It has a fifth terminal connected to the gate electrode of the second semiconductor chip and protruding from the semiconductor module to the outside, The first opposing portion of the second frame and the third frame is arranged parallel to the direction of current flow, A semiconductor module in which, among the plurality of groups, adjacent semiconductor chip groups have at least one of the first frame of one semiconductor chip group and the second frame of the other semiconductor chip group, which are arranged parallel to the direction of current flow.
2. The third frame described above is The semiconductor module according to claim 1, wherein the first opposing portion has an extended portion that extends parallel to the second frame from the portion on which the second semiconductor chip is mounted.
3. The distance between the second frame and the third frame in the first opposing portion is, The semiconductor module according to claim 2, wherein the distance is set to the shortest distance that can ensure the withstand voltage required by the voltage rating of the semiconductor module.
4. The aforementioned multiple groups are The first terminal and the second terminal are arranged alternately on the first side of the semiconductor module. The semiconductor module according to claim 1, wherein the third terminal, the fourth terminal, and the fifth terminal are arranged alternately on the second side of the semiconductor module opposite to the first side of the semiconductor module.
5. The semiconductor module according to claim 1, wherein the first terminal and the second terminal within the semiconductor chip group are arranged adjacent to each other.
6. Each of the aforementioned semiconductor chip groups is The semiconductor module according to any one of claims 1 to 5, wherein the first terminal and the second terminal each protrude from the semiconductor module to the outside.
7. The top electrode of the first semiconductor chip is electrically connected to the end of the third frame furthest from the third terminal. The semiconductor module according to any one of claims 1 to 5, wherein the upper electrode of the second semiconductor chip is electrically connected to the end of the second frame furthest from the second terminal.
8. AC power supply and A power factor correction circuit connected to the AC power supply and equipped with a semiconductor module according to any one of claims 1 to 5, A semiconductor module system comprising a DC / DC converter connected to the power factor correction circuit.