Photonic integrated circuits

Abstract

This relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. [Solution] The apparatus includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is positioned above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50K or about 20K. In some embodiments, the monolithic photonic apparatus includes a thermal separation structure and an optical separation structure. Techniques for manufacturing the monolithic photonic apparatus including the thermal separation structure and the optical separation structure are also described.

Description

Technical Field

[0001] Cross-reference to Other Applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 039,840, filed on Jun. 16, 2020, for "Photonic Integrated Circuit", which is hereby incorporated by reference in its entirety for all purposes.

Background Art

[0002]

[0001] Photonic integrated circuits, such as photonic integrated circuits in photonic quantum computing systems, may include various integrated optical components such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, delay lines, etc. Integrating different types of integrated optical components onto a single chip can be difficult because the processes and materials used in the manufacture of these integrated optical components are different.

[0003]

[0002] Integrating different types of integrated optical components onto a single chip can also adversely affect the performance of the photonic integrated circuit, for example, due to noise caused by heat dissipation from stray light or heat-generating components to other components. For example, highly sensitive photodetectors, such as single photon detectors, can be used in many optical quantum technologies such as quantum cryptography and quantum computing. Because these photodetectors are highly sensitive, they can be very susceptible to the effects of noise, such as unwanted ambient light or stray light, that can reach the photodetector via direct or indirect paths. Certain thermo-optical components, such as thermal tuners for adjusting filters, may use heaters. The heat generated by the heater can dissipate to other areas of the photonic integrated circuit, reducing the efficiency of the thermo-optical component and / or raising the temperature of other components that need to operate at low temperatures, such as cryogenic temperatures.

Summary of the Invention

[0004]

[0003] This disclosure relates to photonic integrated circuits in general. More specifically, this disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. Monolithic photonic integrated circuits include optical and / or thermal isolation structures. For example, a monolithic photonic integrated circuit may include optical isolation structures to prevent background light from reaching a highly sensitive photodetector (e.g., a superconducting nanowire single-photon detector) within the photonic integrated circuit (PIC) in order to achieve high sensitivity and a high signal-to-noise ratio (SNR). A monolithic photonic integrated circuit may also include thermal isolation structures to reduce or prevent heat dissipation from some thermo-optic devices to other areas of the photonic integrated circuit. Monolithic photonic integrated circuits having optical and / or thermal isolation structures may be manufactured using a combination of semiconductor processing techniques. Various embodiments of the invention, including methods, processes, systems, and apparatus, are described herein.

[0005]

[0004] According to certain embodiments, the photonic integrated circuit may include a photonic integrated circuit for optical quantum computing. The photonic integrated circuit may include various combinations of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, and delay lines. For example, the photonic integrated circuit may include a single-photon generator for generating individual photons, filters and switches which can be tuned or controlled by a thermo-optic device or other tuner, and a single-photon detector for detecting individual photons. Different types of integrated optical components may operate at different temperatures. For example, a single-photon detector may include a superconducting nanowire single-photon detector which can operate at low temperatures, while a thermo-optic device can operate at much higher temperatures.

[0006]

[0005] According to certain embodiments, the photonic integrated circuit may include isolation structures manufactured using a CMOS back-end-of-line (BEOL) process to prevent ambient light or stray light from reaching the photodetector directly or indirectly. The isolation structures may include, for example, metal layers, arrays of vias, air gaps, trenches filled with reflective or absorbing materials. The isolation structures may provide local and / or global isolation to the photodetector and / or waveguide at different locations, including the input and output ports of the photonic integrated circuit and the photodetector, so as to partially or completely block light scattered, reflected, diffused, or otherwise leaked from either the light source or the photonic integrated circuit, thereby preventing it from reaching the photodetector.

[0007]

[0006] The systems, apparatus, and methods disclosed herein can improve the signal-to-noise ratio of a photodetector by preventing unwanted light from reaching a highly sensitive photodetector. In this way, the photodetector may achieve high sensitivity and have minimal dead time. The isolation structure may be manufactured using a standard CMOS back-end-of-line (BEOL) process or a CMOS-compatible BEOL process. Some isolation may be local isolation, which does not require additional global layers or materials in the stack-up, thus avoiding the addition of an additional thermal load to the circuit or apparatus.

[0008]

[0007] According to certain embodiments, the photonic integrated circuit may include thermal isolation structures such as trenches and large undercut regions adjacent to heat generators. Thermal isolation structures may be manufactured using CMOS or other semiconductor processing techniques such as photolithography and wet / dry etching. Thermal isolation structures may retain heat in localized areas to improve the efficiency of the thermo-optic device and reduce the burden on cooling regions that may require operation at low temperatures.

[0009]

[0008] The embodiments of this disclosure are provided as examples. Non-limiting and non-exclusive embodiments are described with reference to the following figures, and similar reference numbers refer to the same parts throughout the various figures unless otherwise specified. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a simplified block diagram showing an example of an optical device including a photonic integrated circuit (PIC) and a high-sensitivity photodetector according to one embodiment. [Figure 2] Figure 2 shows an example of stray light isolation at the input and / or output ports of a photonic integrated circuit according to one embodiment. [Figure 3] Figure 3 shows an example of locally separating a photodetector using various separation structures according to one embodiment. [Figure 4A] Figures 4A to 4D show another example of locally separating a photodetector using various separation structures in an optical device according to one embodiment. Figure 4A is a cross-sectional view of an optical device including a photodetector and an optical separation structure. [Figure 4B] Figure 4B is a perspective view of the optical apparatus shown in Figure 4A. [Figure 4C] Figure 4C is a top view of the optical apparatus shown in Figure 4A. [Figure 4D] Figure 4D is a top view of the cross-section of the optical device shown in Figure 4A. [Figure 5] Figure 5 is a flowchart showing an example of a method for manufacturing various optical separation structures in a photonic integrated circuit according to one embodiment. [Figure 6] Figure 6 is a cross-sectional view of an example of a photonic integrated circuit including a photodetector, manufactured using a line process front end according to one embodiment. [Figure 7] Figure 7 is a cross-sectional view of an example of a photonic integrated circuit having vias or trenches etched into an oxide layer using a line process backend according to one embodiment. [Figure 8]Figure 8 is a cross-sectional view of an example of a photonic integrated circuit having etched vias or trenches in an oxide layer filled with a reflective or absorbent material (e.g., metal) according to one embodiment. [Figure 9] Figure 9 is a cross-sectional view of an example of a photonic integrated circuit with a metal cover fabricated on a metal layer for locally isolating a photodetector according to one embodiment. [Figure 10] Figure 10 is a cross-sectional view of an example of a photonic integrated circuit after an additional BEOL process according to one embodiment. [Figure 11] Figure 11 is a cross-sectional view of an example of a photonic integrated circuit including deep trenches etched into a substrate according to one embodiment of the photonic integrated circuit. [Figure 12] Figure 12 is a cross-sectional view of an example of a photonic integrated circuit, which includes deep trenches filled with reflective or absorbent material within a substrate of the photonic integrated circuit according to one embodiment. [Figure 13] Figure 13 is a cross-sectional view of an example of a photonic integrated circuit showing optical separation by various separation structures in a photonic integrated circuit according to one embodiment. [Figure 14] Figure 14 is a flowchart showing an example of a method for manufacturing a photonic integrated circuit according to one embodiment. [Figure 15] Figure 15 shows an example of a base PIC type according to one embodiment. [Figure 16] Figure 16 shows an example of an additional layer that can be deposited for use in a three-layer lithography process according to one embodiment. [Figure 17] Figure 17 shows an example of an etched PIC structure according to one embodiment. [Figure 18] Figure 18 shows an example of an oxide layer on an etched PIC according to one embodiment. [Figure 19] Figure 19 shows an example of an etching process that forms a trench structure in a thermally separated region according to one embodiment. [Figure 20]FIG. 20 shows an example of an etching process for forming an undercut structure according to an embodiment. [Figure 21] FIG. 21 shows an example of an undercut structure according to an embodiment. [Figure 22] FIG. 22 shows an example of a process for forming an oxide layer that seals a trench structure and an undercut structure according to an embodiment. [Figure 23] FIG. 23 shows an example of an additional layer that can be deposited for use in a three-layer lithography process according to a particular embodiment. [Figure 24] FIG. 24 shows an example of a contact hole for forming an electrical contact according to an embodiment. [Figure 25] FIG. 25 shows an example of an additional layer that can be deposited for use in a three-layer lithography process according to an embodiment. [Figure 26] FIG. 26 shows an example of a contact hole for forming an electrical contact for a photodetector according to an embodiment. [Figure 27] FIG. 27 shows an example of an electrical contact for a photonic integrated circuit according to an embodiment. [Figure 28] FIG. 28 shows an example of a scattering mitigation structure according to an embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]

[0037] The technology disclosed herein generally relates to photonic integrated circuits. More specifically, the present disclosure relates to techniques for integrating different types of components on a monolithic photonic integrated circuit. A monolithic photonic integrated circuit includes optical and / or thermal isolation structures. Various invention embodiments including methods, processes, systems, devices, etc. are described herein.

[0012]

[0038] According to certain embodiments, a photonic integrated circuit may include various combinations of different types of integrated optical components, such as waveguides, couplers, photon generators, filters, switches, detectors, interferometers, and delay lines. For example, a photonic integrated circuit may include a photonic integrated circuit for optical quantum computing, which may include a single-photon generator for generating individual photons, filters and switches that can be tuned or controlled by a thermo-optic device or other tuner, and a single-photon detector for detecting individual photons. Different types of integrated optical components may operate at different temperatures. For example, a single-photon detector may include a superconducting nanowire single-photon detector that can operate at low temperatures, while a thermo-optic device can operate at much higher temperatures.

[0013]

[0039] Monolithic photonic integrated circuits may include optical isolation structures to prevent background light within the photonic integrated circuit (PIC) from reaching a highly sensitive photodetector (e.g., a single-photon detector) in order to achieve high sensitivity and a high signal-to-noise ratio (SNR). Monolithic photonic integrated circuits may also include thermal isolation structures to reduce or prevent heat dissipation from one thermo-optical device to other areas of the photonic integrated circuit. Monolithic photonic integrated circuits having optical and / or thermal isolation structures may be manufactured using a combination of semiconductor processing techniques.

[0014]

[0040] Single-photon detectors used in many photonic quantum technologies (e.g., highly photosensitive photodetectors such as superconducting nanowire SPDs (SNSPDs)) can be very sensitive to many types of light radiation. Often, highly sensitive photodetectors cannot achieve the sensitivity or signal-to-noise ratio they are capable of achieving due to various noise sources, such as background light including stray light in the system and ambient light entering the system. The techniques disclosed herein can reduce or prevent undesirable background light (such as stray light or ambient light) reaching highly sensitive photodetectors (e.g., superconducting nanowire single-photon detectors) in photonic integrated circuits in order to achieve high sensitivity and a high signal-to-noise ratio.

[0015]

[0041] According to certain embodiments, to improve the sensitivity and SNR of the photodetector, a photodetector (e.g., SNSPD) may be optically isolated from background radiation (e.g., ambient light or stray light) using a reflective or absorbing structure surrounding the photodetector. In some embodiments, additional isolation structures may be added at any other location within the PIC where background light may propagate before reaching the photodetector, in order to reduce the number of stray photons that may reach the region of the photodetector. For example, since one of the main sources of background light or stray light in a photonic integrated circuit is light reflected, scattered, or diffused at the optical input and / or optical output ports to the PIC (e.g., input or output waveguide couplers) due to incomplete coupling of light into or from the PIC (e.g., waveguide), isolation structures may be used at the optical input and / or optical output ports to prevent stray light from entering the interior of the PIC. Thus, the probability of stray light or ambient light entering the waveguide or reaching the region of the photodetector can be significantly reduced. Furthermore, even if background light reaches the region where the photodetector is located, the local isolation structure surrounding the photodetector can block the background light from being detected by the photodetector. In various embodiments, the light isolation structure can be manufactured using a standard CMOS back-end obline (BEOL) process or other CMOS-compatible manufacturing process.

[0016]

[0042] According to one embodiment, the photonic integrated circuit may include heaters for tuning several integrated optical components, such as optical filters, optical switches, and optical interferometers. The photonic integrated circuit may also include thermal isolation structures, such as trenches and large undercut regions adjacent to the heaters. The thermal isolation structures may retain heat in localized areas to improve the efficiency of the thermo-optic device and reduce the burden on cooling areas, including devices that need to operate at low temperatures, such as SNSPDs. The thermal isolation structures may also be fabricated using CMOS or other semiconductor processing techniques such as photolithography or wet / dry etching.

[0017]

[0043] Several exemplary embodiments are described with reference to the accompanying drawings that form part of this specification. The following description provides only embodiments and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of embodiments will provide a useful description for those skilled in the art to carry out one or more embodiments. It will be understood that various modifications can be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are given for illustrative purposes to provide a complete understanding of a particular embodiment of the invention. However, it will be apparent that various embodiments can be carried out without these specific details. The figures and descriptions are not intended to limit. In this specification, the terms “example” or “exemplary” are used to mean “serving as an example, illustration, or demonstration.” Any embodiment or design described herein as “exemplary” or “example” should not necessarily be construed as being preferable or advantageous over other embodiments or designs.

[0018]

[0044] Figure 1 is a simplified block diagram showing an example of an optical device 100 including a photonic integrated circuit (PIC) 120 and a high-sensitivity photodetector 130 according to one embodiment. The PIC 120 may include a photonic circuit formed by waveguides and other active or passive optical components, such as filters, resonators, splitters, and optical amplifiers. The optical device may include a light source, such as a laser 110, which may be an ultrafast (e.g., picosecond or femtosecond) pulsed laser. In some embodiments, the light source may be an external light source, which may be connected to the PIC 120, for example, via one or more optical fibers. Light from the light source may be coupled to waveguides in the PIC 120 via couplers such as lattice couplers and edge couplers. However, achieving very high coupling efficiencies can be difficult. For example, the coupling efficiency may often be less than 90%, less than 75%, less than 60%, or less than 50%. Therefore, a large amount of light from the light source may not enter the waveguides in the PIC 120, but instead be reflected, scattered, or diffused to become stray light 140. Stray light 140 may be reflected, refracted, diffracted, or otherwise deflected by structures or components within the optical device 100, such as metal layers or interfaces between dissimilar materials. Thus, some of the stray light 140 may eventually reach the photodetector 130. In addition, some of the PIC 120 may leak light away from its desired path. For example, instead of being guided into the photonic circuit to reach the photodetector 130, light may be coupled from the waveguide, for example, when the waveguide has a sharp bend or when there is a defect in the waveguide or other photonic circuit. Light leaked from the photonic circuit may become stray light 150, which may also be deflected, at least partially, towards the photodetector 130. In some embodiments, ambient light may also enter the PIC 120, for example, through an oxide layer and / or be reflected by a metal layer.

[0019]

[0045] The photodetector 130 may be a highly sensitive photodetector, such as a single-photon detector. For example, in some embodiments, the photodetector 130 may include a superconducting nanowire single-photon detector capable of detecting individual photons. In one embodiment, the photodetector 130 may include a waveguide coupled to a superconducting nanowire, such as a niobium-germanium nanowire, which may have ultra-low resistance in a superconducting state. The superconducting nanowire may be photosensitive or photoactive, such as by absorbing photons. For example, a photon passing through the waveguide may be absorbed by the superconducting nanowire, causing the superconducting nanowire to become non-superconducting (i.e., changing its resistance or impedance). The change in resistance or impedance in the nanowire can be converted into an electrical detection signal (e.g., a current or voltage signal) indicating that one or more photons have been detected.

[0020]

[0046] If at least some of the stray light 140, 150 reaches the photodetector 130, it may alter the state of the superconducting nanowire, causing the photodetector 130 to generate a detection signal indicating that one or more photons have been detected even if no photons have reached the superconducting nanowire from the waveguide, or the magnitude of the detection signal may not accurately reflect the number of photons reaching the photodetector from the waveguide. Consequently, the photodetector 130 may generate a false or incorrect (e.g., noisy) detection signal, which may reduce the effective sensitivity or SNR of the photodetector 130.

[0021]

[0047] According to certain embodiments, light isolation structures may be added to different locations in the optical device 100 to block stray light or ambient light from reaching the photodetector 130. For example, an isolation structure 160 may be added to the input port of the PIC 120, an isolation structure 170 may be fabricated to surround the photodetector 130, or an isolation structure 180 may be added to any location in the optical device 100 where background light could otherwise propagate. Details of some embodiments of light isolation structures and their fabrication processes are described in the following embodiments.

[0022]

[0048] Figure 2 shows an example of stray light isolation at the input and / or output ports of a photonic integrated circuit 200 according to one embodiment. Figure 2 shows a cross-sectional view of the PIC200, which may include a waveguide 210 fabricated on a substrate 205 (e.g., a silicon handle wafer). The PIC200 may also include an input port 220 for the waveguide 210 and an output port 230 for the waveguide 210. The waveguide 210 may carry light from the input port 220 into the interior of the PIC200 where several photosensitive components may be located, or it may guide light from the PIC200 through the output port 230.

[0023]

[0049] As described above, at the input port 220 or output port 230, the light may not be completely coupled to the waveguide 210. A significant portion of the input or output light may enter the PIC200 through paths other than the waveguide 210. In some cases, approximately 10¹² photons may enter the PIC200 as stray light in each laser pulse. To prevent these photons from reaching the interior of the PIC200, one or more light isolation structures may be fabricated at the input and / or output ports. For example, as shown in Figure 2, the PIC200 may include one or more metal trenches 240 and one or more deep trenches 260 that can act as isolation structures 160 shown in Figure 1. The metal trenches 240 may include a metal layer thick enough to block (e.g., reflect or absorb) incident photons. The metal trench 240 may act as a mirror-like barrier, for example, extending from metal 1 (M1, which may be about 1 μm above waveguide 210) to substrate 205 (which may be about 2-3 μm below waveguide 210) to block light that could propagate within the cladding of waveguide 210 from reaching the interior of PIC200. The deep trench 260 may extend through substrate 205 of PIC200, may be empty (i.e., an air gap), or may be filled with a reflective or absorbing material to at least partially reflect or absorb incident photons that could propagate within substrate 205 or be scattered from substrate 205, so that photons do not enter the cladding of waveguide.

[0024]

[0050] Gap 250 may exist between adjacent metal trenches 240 so that waveguide 210 can pass through the gap between metal trenches 240. Gap 270 may exist between adjacent deep trenches 260 so that waveguide 210 can be supported by the substrate in gap 270. As shown in Figure 2, gaps 250 and 270 may not be aligned and may be offset from each other by a certain distance so that gap 250 does not have to be in the line of sight of stray photons from input port 220, and therefore stray photons from input port 220 may not pass through gap 250 but instead be blocked by the metal trenches 240.

[0025]

[0051] Figure 3 shows an example of locally isolating a photodetector 350 using various isolation structures in a photonic integrated circuit 300 according to one embodiment. The PIC 300 may include a substrate 305 (e.g., a silicon handle wafer). A waveguide 310 may be formed on the substrate 305, where the waveguide 310 may include multiple turns for changing direction. Optical isolation structures such as an upper metal cover 320, a metal trench 330, and a deep trench 340 may be fabricated within the PIC 300 to surround and isolate the waveguide 310 and the photodetector 350. The optical isolation structures shown in Figure 3 may be specific embodiments of the isolation structure 170 in Figure 1, or they may form isolation structures comparable to castle-like structures.

[0026]

[0052] As illustrated in Figure 3, the waveguide 310 may carry signal light from the photonic circuit in the PIC 300 to the photodetector 350 (e.g., SNSPD), where the signal light can be detected. Similar to the deep trench 260, the deep trench 340 may include an air gap that completely passes through the substrate 305, or it may be filled with a reflective or absorbing material. In some embodiments, the deep trench 340 may partially pass through the substrate 305. The deep trench can isolate the photodetector 350 from light that may propagate within the substrate 305 or be scattered from the substrate 305. The metal trench 330 may be similar to the metal trench 240 and may create a mirror-like barrier that extends from M1 to the substrate 305, as described above with respect to Figure 2. In some embodiments, the metal trench 330 may include a plurality of nesting rings centered on the photodetector 350, where the inner ring may be surrounded by one or more outer rings. Each ring may include an opening through which the waveguide 310 can pass. The openings in each ring may be on a different side (e.g., opposite or adjacent) to the openings in adjacent rings. The metal trench 330 can block light that may propagate within the cladding of the waveguide 310 from reaching the photodetector 350. The upper metal cover 320 may function as a roof of a light-shielding structure, which may be compared to a castle-like structure, and may prevent light from reaching the photodetector 350 from above the photodetector 350 and PIC300.

[0027]

[0053] Figures 4A to 4D show another example of locally isolating a photodetector 470 using various isolation structures in an optical device 400 according to one embodiment. Figure 4A is a cross-sectional view of the optical device 400 including the photodetector 470 and the optical isolation structure surrounding the photodetector 470. Figure 4B is a perspective view of the optical device 400 shown in Figure 4A. The optical device 400 may include a substrate 410 (e.g., a silicon handle wafer), a barrier oxide (BOX) layer 420 (e.g., silicon dioxide), a waveguide 440 formed on the BOX layer 420, and a low-temperature oxide (LTO) layer 430 covering the waveguide 440. The optical device 400 may also include an array of vias 450 and an upper metal cover 460 which may be formed on a single layer of metal.

[0028]

[0054] Figure 4C is a top view of the optical device 400 shown in Figure 4A. Figure 4C shows an upper metal cover 460 that covers the photodetector 470 from above to prevent background light from reaching the photodetector 470, where the upper metal cover 460 may be part of a single layer of metal.

[0029]

[0055] Figure 4D is a top view of a cross-section of the optical device 400 of Figure 4A. Figure 4D shows the arrangement of the via array 450 and the photodetector 470. As shown, the via array 450 may be arranged in a two-dimensional array, where vias in one row (or column) may be offset from vias in adjacent rows (or columns) so that the via array can effectively form a wall. The photodetector 470 may include photoactive nanowires 480 (e.g., niobium-germanium nanowires) on the waveguide 440.

[0030]

[0056] Figure 5 is a flowchart 500 illustrating an example of a method for fabricating various optical isolation structures in a photonic integrated circuit according to one embodiment. While Figure 5 describes operations in a sequential flow, some operations may be performed in parallel or simultaneously. Some operations may be performed in a different order. Operations may include additional steps not shown in the figure. Some operations may be optional and therefore omitted in various embodiments. Some operations may be performed in conjunction with others.

[0031]

[0057] Optionally, in block 510, the waveguide layer may be formed on a barrier oxide layer of the PIC, such as the BOX layer 420 shown in Figures 4A and 4B. The waveguide layer may be patterned and etched, for example using photolithography techniques, to form waveguide cores and / or input / output couplers. In block 520, a photoactive layer, such as a niobium-germanium layer, may be deposited on top of the waveguide layer. The photoactive layer may be patterned and etched to form nanowires on the waveguide core region. The processing in blocks 510 and 520 may be part of the front end of a line process in a CMOS process.

[0032]

[0058] Figure 6 is a cross-sectional view of an example of a photonic integrated circuit 600 including a photodetector, manufactured using a line process front end in blocks 510 and 520 according to one embodiment. The PIC600 may include a substrate 610 (e.g., a silicon handle wafer), a BOX layer 620 formed on the substrate 610, various devices on the device layer (e.g., an optical input / output coupler 640, a waveguide 650, and a photodetector including a waveguide 660 and nanowires 670 containing photoactive material), and an oxide layer 630 covering the device layer. The optical input / output coupler 640 may include a lattice coupler. The oxide layer 630 and the BOX layer 620 may act as cladding for the waveguide 650. In one example, the oxide layer 630 may have a thickness of about 1 μm.

[0033]

[0059] In block 530, vias or trenches can be etched in the oxide layer down to the substrate. For example, a patterned mask layer may be formed on the oxide layer (e.g., an LTO layer and a BOX layer), and vias (holes) or trenches in the oxide layer may be etched using wet or dry etching techniques, which may have a total thickness of, for example, 3 to 4 μm.

[0034]

[0060] Figure 7 is a cross-sectional view of an example of a photonic integrated circuit 700 having vias or trenches 710 etched into the oxide layer using a back-end-of-line (BEOL) process in block 530 according to one embodiment. The PIC700 may be manufactured from a PIC600. The vias or trenches 710 can be etched through the oxide layer 630 and the BOX layer 620 to the substrate 610.

[0035]

[0061] In block 540, vias or trenches may be filled with reflective or absorbent materials such as metallic materials. For example, a metallic layer may be deposited on an oxide layer and selectively etched over one or more cycles to form a metallic plug within the via or trench.

[0036]

[0062] Figure 8 is a cross-sectional view of an example of a photonic integrated circuit 800 having vias or trenches etched into an oxide layer filled with a reflective or absorbent material (e.g., a metal such as copper, aluminum, cobalt, or tungsten) using a BEOL process in block 540 according to one embodiment. The PIC800 may be manufactured from a PIC700, where the vias or trenches 710 may be filled with metal plugs 810.

[0037]

[0063] In block 550, a metal layer may be deposited on the oxide layer using standard CMOS BEOL processing techniques, and the metal layer may be etched to leave an upper metal cover in the upper region of the photodetector. The upper metal cover may be aligned with vias or trenches filled with a reflective or absorbing material such as metal. Thus, the upper metal cover and vias or trenches can block background light from at least three (e.g., up, left, and right) directions or five (e.g., up, left, right, front, and back) directions.

[0038]

[0064] Figure 9 is a cross-sectional view of an example of a photonic integrated circuit 900, which includes an upper metal cover 910 fabricated as part of a metal layer for locally isolating a photodetector using a BEOL process in block 550 according to one embodiment. PIC900 may be fabricated from PIC800 and may include an additional upper metal cover 910 formed as part of a single metal layer. The upper metal cover 910 may be located above (e.g., above) the photodetector, which includes the waveguide 660 and nanowire 670. The upper metal cover 910 may be in contact with the metal plug 810 in vias or trenches 710 to block light from the top, left, and right directions in a two-dimensional cross-sectional view.

[0039]

[0065] Optionally, other BEOL processes may be performed in block 560 to form additional dielectric (e.g., oxide) layers and upper metal layers (e.g., metal 2, metal 3, etc.). These BEOL processes may include standard CMOS BEOL processes.

[0040]

[0066] Figure 10 is a cross-sectional view of an example of a photonic integrated circuit 1000 after additional BEOL treatment in block 560 according to one embodiment. The PIC1000 may be manufactured from the PIC900 and may include higher-level metal layers such as additional metal layer 1010 and metal layer 1020.

[0041]

[0067] In block 570, the substrate can be etched from the back side to form deep trenches within the substrate. The deep trenches can reflect photons propagating within the substrate at the interface between the substrate material and the air gap. For example, total internal reflection can occur when a photon is incident at a constant angle on the interface from the substrate material to the air gap.

[0042]

[0068] Figure 11 is a cross-sectional view of an example of a photonic integrated circuit 1100, which includes deep trenches 1110 etched into the substrate of the photonic integrated circuit using a BEOL process in block 570 according to one embodiment. The PIC1100 may be manufactured from the PIC1000 and may include deep trenches 1110 in the substrate 610. The deep trenches 1110 may be offset from the metal plugs 810. For example, the deep trenches 1110 may be slightly away from the photodetector than the metal plugs 810 to prevent light from bypassing the metal plugs 810 and reaching the photodetector from the bottom side of the substrate 610 and the BOX layer 620.

[0043]

[0069] Optionally, in block 580, the deep trench may be filled with a reflective or absorbing material that can block light, such as a metallic material.

[0044]

[0070] Figure 12 is a cross-sectional view of an example of a photonic integrated circuit 1200 including deep trenches in a substrate filled with a reflective or absorbent material using a process in block 580 according to one embodiment. The PIC1200 may be manufactured from the PIC1100 and may include a reflective or absorbent material 1210, such as a metallic material, filling the deep trenches 1110.

[0045]

[0071] Figure 13 is a cross-sectional view of a photonic integrated circuit 1200 showing optical separation by various isolation structures in a photonic integrated circuit according to one embodiment. Light from a laser can be sent to the PIC 1200 via an input fiber 1310 which may include a collimator such as a GRIN lens or microlens. The input light 1320 from the input fiber 1310 can propagate through an oxide layer and may be partially coupled to a waveguide in the PIC 1200 by an optical input / output coupler 640 which may include a tilting grating in some embodiments.

[0046]

[0072] Light that is not coupled to the waveguide by the optical input / output coupler 640 can be scattered in various directions. For example, some of the input light 1320 may be reflected as light 1330 at the interface between the substrate 610 and the BOX layer 620, and may be further reflected by the metal layer 1020 as light 1370, which can be blocked by one of the metal plugs 810. Some of the input light 1320 may be scattered as light 1335, propagate toward the metal plug 810, and be blocked by the metal plug. Some of the input light 1320 may be scattered at the bottom surface of the substrate 610, some of the scattered light 1350 may be blocked by the reflective or absorbing material 1210 in the deep trench 1110, and another portion of the scattered light 1340 may be blocked by the metal plug 810.

[0047]

[0073] Light 1360 scattered or otherwise leaked from the waveguide 650 can also be blocked by the metal plug 810 from reaching the photodetector. Ambient light 1380 that may enter the oxide layer from above, or stray light reflected by various metal layers, can be blocked by the upper metal cover 910 located above the photodetector and therefore may not reach the photodetector either. In this way, only photons guided into the waveguide 660 can reach the photodetector, and therefore ambient noise can be greatly reduced or substantially eliminated. Thus, high sensitivity and high SNR can be achieved by the photodetector.

[0048]

[0074] In various embodiments, other dielectric layers used in CMOS processing may be used to replace one or more oxide layers (e.g., silicon dioxide layers) described above. For example, the dielectric layers may include silicon nitride, alkali halides, barium titanate, lead titanate, tantalum oxide, tungsten oxide, zirconium oxide, and the like.

[0049]

[0075] The highly sensitive photodetectors described above can be used to detect individual photons in quantum computing or quantum cryptography. For example, single-photon sources can be used in many photonic quantum technologies. An ideal single-photon source determinsistically generates single photons. One way to realize a deterministic single-photon source is to use a cascaded (or multiplexed) messenger photon source based, for example, spontaneous four-wave mixing (SFWM) or spontaneous parametric down-conversion (SPDC) in a passive nonlinear optical medium. In each messenger photon source (HPS), photons can be nondeterministically generated in pairs (including a signal photon and an idler photon), where one photon (e.g., a signal photon) signals the presence of the other photon in the pair (e.g., an idler photon). Therefore, if a signal photon is detected by a highly sensitive photodetector (e.g., a single-photon detector as described above) in one messenger photon source, the corresponding idler photon can be used as the output of the single-photon source, while other messenger photon sources in a cascaded (or multiplexed) single-photon source can be bypassed or switched off.

[0050]

[0076] Figure 14 is a flowchart 1400 illustrating an example of a method for manufacturing a photonic integrated circuit according to one embodiment. More specifically, Figure 14 shows an example of an integration flow for forming a thermal isolation structure, a scattered light relaxation structure, a photodetector, and metal contacts on and within a base photonic integrated circuit (PIC). Other combinations of elements are possible without departing from the scope of this disclosure. For example, the method does not have to include a step for forming a thermal isolation structure or other structures such as additional photonic structures formed on one or more additional photonic layers.

[0051]

[0077] In step 1401, a base PIC is provided. This base PIC can be any integrated circuit structure, and therefore the examples shown herein are not intended to limit the scope of the disclosure. In some embodiments, the base PIC can be provided as the output of a silicon photonics processing step for processing any sequence prior to the processing step, such as a silicon-on-insulator (SOI) wafer.

[0052]

[0078] Figure 15 shows an example of one type of base PIC that can be provided in step 1401. The base PIC may include a PIC stack 1501. The PIC stack 1501 includes a multilayer photonic integrated circuit stack comprising a substrate 1524 (e.g., a silicon handle wafer), a first oxide layer 1520, a waveguide layer 1521, and a spacer / protective capping layer 1522. In some embodiments, a second oxide layer 1518 may be placed between the waveguide layer 1521 and the spacer / protective capping layer 1522. The waveguide layer 1521 can be patterned to include various photonic components, including one or more input coupler regions 1503, waveguide regions 1505, heater regions 1507, thermal isolation trench regions 1509, photonic switch regions 1511, photon detector regions 1513, photon detector contact regions 1515, and / or scattering relaxation structure regions 1517. Those skilled in the art will understand that the number, order, and location of the various areas and components shown herein are merely illustrative, and any arrangement is possible without departing from the scope of this disclosure.

[0053]

[0079] In some embodiments, the input coupler region 1503 may include any type of photonic input / output structure, such as a lattice coupler 1519. The photonic input / output structure can be pre-formed in the waveguide layer 1521, such as a Si layer, a SiN layer, or any other material suitable for integrated photonics. The waveguide region 1505 may include one or more waveguides 1523 that can become part of one or more photonic structures and / or photonic components. For example, within the waveguide layer 1521, waveguide structures can be used to form input / output structures (such as lattice couplers), optical routing structures (such as linear waveguides and waveguide bends), photogenerating structures (such as coupled microring photon sources), switching structures (such as Mach-Zehnder interferometers (MZI)), coupling structures (such as directional couplers), optical filters (e.g., wavelength division multiplexing (WDM) wavelength filters), photonic delay line structures, and the like.

[0054]

[0080] In the example illustrated in Figure 15, the structure within the waveguide layer is arranged pictorially to facilitate the explanation of the manufacturing process. Those skilled in the art will understand that the exact arrangement of components (and interconnections between components) can vary considerably depending on the application for which the PIC is designed. Thus, the illustrated waveguide layer 1521 is intended to represent any possible combination of photonic components that can be designed using one or more waveguides as building blocks.

[0055]

[0081] The heater region 1507 may also be part of one or more optical components such as filters, microrings, and MZIs (not shown), and can be used to thermally adjust these structures. In some embodiments, a heater 1525 (e.g., a strip heater) may be located in the heater region 1507. In some embodiments, the heater 1525 may be formed within the waveguide layer 1521 and may include a doped silicon (n- or p-doped silicon) layer 1525a and a capping layer 1525b formed of a silicide such as cobalt silicide, nickel silicide, or any other silicide. Although the heater region 1507 is shown adjacent to the waveguide 1523 in Figure 15, other embodiments may employ a silicide and / or metallic heater fabricated on top of the waveguide 1523, and may employ doped Si with a silicide top layer, a metallic material such as TiN, TaN, or any other suitable heater material.

[0056]

[0082] In some embodiments, the thermal isolation trench region 1509 is adjacent to the heater region 1507, thereby allowing trenches and undercuts (not shown) to be formed in the silicon oxide and silicon regions in subsequent processes, as will be described in more detail below with reference to Figures 19-20, providing thermal isolation around the heater region 1525. Such trenches and undercuts not only result in more power-efficient operation of the heater 1525 (by reducing heating of adjacent oxide layers and substrates), but can also provide thermal isolation between the region of the PIC containing the heater 1525 (which may have a local temperature of 150K-200K) and the region of the PIC containing the photon detector (which may be cryogenic, e.g., having a local temperature of 3K-20K, e.g., 4K, 10K). In some embodiments, multiple heaters may be used to tune multiple photonic components (e.g., single-photon sources, filters, MZIs, etc.) that are located in close proximity to each other, and a thermal separation region can prevent crosstalk between the heating of components so that one heater for heating each component only needs to heat adjacent components minimally due to the thermal separation properties of the thermal separation structure formed in the thermal separation region. In some embodiments, thermal tuning may not be necessary, and therefore heaters and heater regions may not be present.

[0057]

[0083] In some embodiments, the photonic switch region 1511 includes any suitable photonic switch 1527, such as a pn switch, a pin switch, a DC Karr switch, a Pockels effect switch, or any other type of optical switch.

[0058]

[0084] In some embodiments, the photon detector region 1513 and the photon detector contact region 1515 can employ any waveguide-integrated photon detection technique. For example, the superconducting nanowire single-photon detector 1529 is shown in the cross-sectional view herein. The photon detector region 1513 and the photon detector contact region 1515 may include, for example, an AlN layer 1530, an NbN layer 1532, an amorphous silicon layer 1534, and a silicon oxide layer 1536. Details of the photon detector region 1513 and the photon detector contact region 1515 are described below.

[0059]

[0085] The area surrounding the photon detector region 1513 can be a scattering relaxation structure region 1517, which can include one or more scattering relaxation structures (not shown) fabricated internally, such as the scattering relaxation structure described above, as shown in Figures 1 to 13.

[0060]

[0086] According to some embodiments, the base PIC can be covered with a spacer / protective cap layer 1522, such as a SiN layer, as shown in Figure 15. The spacer / protective cap layer 1522 can be pre-deposited isometrically on the base PIC wafer. In other embodiments, the base PIC may include a planarized capping layer or any other layer, without departing from the scope of the present disclosure.

[0061]

[0087] Referring back to Figure 14, in step 1403, the base PIC is prepared for the first lithography process. The lithography process referred to herein employs three-layer lithography, but any lithography technique can be used without departing from the scope of this disclosure. Figure 16 shows examples of additional layers that can be deposited for use in a three-layer lithography process. For example, a planarization layer 1603 can be deposited on a pre-formed spacer layer (e.g., a spacer / protective cap layer 1522). Examples of planarization layers 1603 include organic planarization layers such as spin-on hard masks (SOH), organic planarization layers (OPL), or any other layer or material that can be used to planarize the topography of the base PIC. An anti-reflective coating 1605 can be deposited on top of the planarization layer. Examples of anti-reflective coatings 1605 include silicon-based anti-reflective coatings (SiARC), bottom anti-reflective coatings (BARC), and the like. A photoresist layer 1607 can be deposited on the anti-reflective film 1605 and lithographically patterned according to known methods. In the example shown in Figure 16, the photoresist layer 1607 is patterned to protect specific portions of the spacer layer (e.g., a nitride layer) located above the heater contact area, switch contact area, and photon detector contact area, as shown in Figure 16.

[0062]

[0088] In step 1405, a first etching process is performed to pattern the spacer / protective cap layer 1522 (e.g., a nitride layer). For example, the anti-reflective coating 1605 and the planarization layer 1603 are etched in areas that do not contain photoresist (acting as an etching mask), resulting in the etched PIC structure 1701 shown in Figure 17, with the spacer / cap 1705 (e.g., silicon nitride) remaining above the heater contact area, switch contact area, and photon detector contact area. More generally, the photoresist can be lithographically patterned in any way that preserves islands of the SiN layer. These islands can be used, for example, as etching stoppers in subsequent contact formation etching processes.

[0063]

[0089] In step 1407, as shown in Figure 18, an oxide deposition process (e.g., using middle-of-the-line (MOL) SiO2 deposition) is performed to form an oxide layer 1803 on the etched PIC.

[0064]

[0090] In step 1409, the patterned base PIC is prepared for a second lithography process. In this process, as in step 1403, another layer is deposited and lithographic patterning of the photoresist is performed.

[0065]

[0091] In step 1411, as shown in Figure 19, a second etching process is performed to generate a deep trench 1903 in a thermally separated region (e.g., a thermally separated trench region 1509). The deep trench 1903, referred to herein as the “deep trench,” is a trench in the PIC stack that can extend to the substrate 1524. The deep trench can be etched using any suitable etching process. For example, an etching process such as an oxide etching process can be employed without departing from the scope of this disclosure. In some embodiments, the etching can be selective etching that etches the oxide but not the Si substrate. The etching process can be an anisotropic etching process that etches the deep trench 1903.

[0066]

[0092] In step 1413, as shown in Figure 20, an undercut 2003 is etched into the substrate 1524 at the base of the deep trench 1903. Such an undercut is formed using a combination of dry / wet etching processes. Dry etching can be sulfur hexafluoride etching, chlorine etching, or any other dry etching process that is selective etching that etches silicon but not oxide, so that only the silicon at the base of the deep trench 1903 is etched and the overlying oxide layer is preserved. Wet etching can then be performed using, for example, tetramethylammonium hydroxide (TMAH), KOH, or any other suitable etching solution. In some embodiments, the etching of silicon occurs along the 111 crystal plane (e.g., at about 54 degrees). Such etching results in an undercut 2003 with angled walls resulting from the etching of silicon.

[0067]

[0093] Figure 21 shows examples of heaters 2103 and full undercut structures 2105 according to several embodiments. The full undercut structure 2105 may be an example of the undercut 2003 shown in Figure 20, and may be formed using the etching process described above for Figure 20. In some embodiments, the undercut structure 2105 can be located beneath any photonic device 2109 employing the heater. Thermal isolation from the deep trenches and undercut structures 2105 can reduce or prevent heat loss to the surrounding substrate 2107. Examples of photonic devices 2109 include single-photon sources, optical filters, Mach-Zehnder interferometers, microring resonators, or any other structures that may use thermal conditioning and / or switching. Figure 21 shows an example in which two deep trenches 2105a and 2105b are formed on the waveguide and heater sides, respectively, to thermally isolate the heater element from the surrounding region including the substrate (referred to here as the silicon handle) and oxide layer. In some embodiments, a cooling element can be made to thermally contact the substrate to provide a headsink to the PIC during operation. For circuits operating at cryogenic temperatures, the cooling element can be part of a larger cryostat that is cooled to cryogenic temperatures. In such scenarios, without a thermal undercut structure placed between the heater and the cooling structure, much of the heat generated by the heater could be directly shunted to the cooling structure, thereby negatively impacting the heating efficiency of the heater and / or unnecessarily increasing the thermal load on the cryogenic cooling system.

[0068]

[0094] In step 1415, as shown in Figure 22, an oxide layer 2210 is deposited on the PIC stack, which includes deep trenches and undercuts for thermal separation formed internally. The oxide layer 2210 may be planarized, for example, by chemical mechanical polishing (CMP). In some embodiments, the oxide layer 2210 is deposited without breaking the vacuum and thus seals the deep trench undercut regions so that these regions remain sealed under vacuum. Keeping the deep trenches and undercut regions under vacuum can improve the thermal separation capability of the deep trench undercut structure by eliminating the most effective heat transfer mechanism within the void. For example, heat transfer through the deep trenches occurs primarily via radiation, while more efficient processes such as diffusion and convection are minimized.

[0069]

[0095] In step 1417, the patterned photoresist layer 2301 may be formed on the PIC stack for a third lithography process, as shown in Figure 23. In this process, another layer of photoresist is deposited and lithography patterning is performed, similar to step 1403. For example, the patterned photoresist layer 2301 may be formed on the planarization layer 2305 and the anti-reflective coating layer 2303. In this case, patterning is performed to form an etching mask for etching the silicide contact holes.

[0070]

[0096] In step 1419, an oxide etching process is performed to etch the oxide layer 2210, followed by a SiN punching process to etch the spacer / cap 1705, thereby forming silicide contact holes 2401 for contact with the silicide layer (e.g., capping layer 1525b), as shown in Figure 24.

[0071]

[0097] In step 1421, the lithography preparation, lithography, and etching processes are carried out in the same manner as described above. For example, as shown in Figure 25, a patterned photoresist layer 2501 may be formed on the planarization layer 2505 and the anti-reflective coating layer 2503. In this case, the photoresist layer 2501 is patterned to stop at the appropriate layer of the photon detector, e.g., an amorphous silicon layer, and to allow etching of the photon detector contact holes. As shown in Figure 26, the planarization layer 2505 (e.g., an SOH or OPL layer) may be removed to expose the silicide contact hole 2401 and the photon detector contact hole 2601.

[0072]

[0098] In step 1423, a metal silicide contact 2701 is formed as shown in Figure 27. For example, a liner layer 2703 can be deposited first in the contact holes (e.g., silicide contact hole 2401 and photon detector contact hole 2601). In some embodiments, the liner layer 2703 can be formed from tungsten, tungsten carbide, tungsten nitride, or any other suitable liner. After liner layer deposition, an annealing step can be performed to form a silicide region 2705 at the bottom of the metal silicide contact 2701 for detector contact, such as an amorphous silicon layer 1534. Following silicide formation, a metallization process is performed to fill the contact holes with a suitable contact metal 2707, such as tungsten, copper, aluminum, cobalt, etc. In some embodiments, a cleaning process can be performed to clean the amorphous silicon before silicide formation. For example, any suitable cleaning process such as a chemical cleaning step or argon sputtering can be used.

[0073]

[0099] In step 1425, the scattering relaxation structure 2801 is formed using a lithography and etching process, as illustrated in Figure 28. In some embodiments, the scattering relaxation structure 2801 can be formed in a deep trench located on the substrate 1524. In other embodiments, the scattering relaxation structure 2801 can be formed in a through-silicon via (TSV), such as the trench shown in Figure 28. After the trench is etched, an oxide liner 2803 is formed to prevent the filler (which subsequently fills the scattering relaxation structure 2801) from reacting with silicon. Next, a metal liner layer 2805, such as a Ti-Cu barrier and seed layer, may be formed on the oxide liner 2803 before filling the scattering relaxation structure with the filler 2807 (e.g., a metal such as copper). The filler 2807 may have a coefficient of thermal expansion (CTE) similar to that of the substrate 1524 and / or the oxide. In some embodiments, scattering relaxation structures such as TSVs can be on the order of 10 microns in depth, for example, 40-60 microns, and are therefore much deeper than thermal separation trenches (which can be less than one-tenth the depth).

[0074]

[0100] It will be apparent to those skilled in the art that substantial modifications may be made according to specific implementations. For example, customized hardware may be used, and / or certain elements may be implemented in hardware, software (including portable software such as applets), or both. Furthermore, connections to other computing devices, such as network input / output devices, may be employed.

[0075]

[0101] Referring to the attached diagram, components that may include memory may also include non-temporary machine-readable media. As used herein, the terms “machine-readable media” and “computer-readable media” refer to any storage medium involved in providing data that enables a machine to operate in a particular manner. In embodiments provided herein, various machine-readable media may be involved in providing instructions / code to a processor and / or other device for execution. Furthermore, or alternatively, machine-readable media may be used to store and / or carry such instructions / code. In many implementations, computer-readable media are physical and / or tangible storage media. Such media may include, but are not limited to, non-volatile media, volatile media, and transmission media, and can take many forms. Common forms of computer-readable media include, for example, magnetic and / or optical media, punch cards, paper tape, any other physical media having a pattern of holes, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash-EPROM, any other memory chip or cartridge, carriers as described below, or any other media from which a computer can read instructions and / or code.

[0076]

[0102] The methods, systems, and apparatus discussed herein are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For example, features described in relation to one embodiment may be combined in various other embodiments. Different aspects and elements of embodiments may be combined in a similar manner. Various components in the figures provided herein can be embodied in hardware and / or software. Furthermore, technology evolves, and therefore many elements are examples, not limiting the scope of disclosure to those specific examples.

[0077]

[0103] It has sometimes proven convenient, primarily for reasons of common use, to refer to bits, information, values, elements, symbols, characters, variables, terms, numbers, or similar signals. However, it should be understood that all these or similar terms must be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise stated, as will be evident from the above discussion, discussions throughout this specification using terms such as “process,” “calculate,” “compute,” “determine,” “verify,” “identify,” “associate,” “measure,” and “execute” are understood to refer to actions or processes of specific devices, such as special-purpose computers or similar special-purpose electronic computing devices. Thus, in the context of this specification, special-purpose computers or similar special-purpose electronic computing devices can typically manipulate or convert signals that are represented as physical electronic, electrical, or magnetic quantities within memory, registers, or other information storage devices, transmission devices, or display measures of special-purpose computers or similar special-purpose electronic computing devices.

[0078]

[0104] Those skilled in the art will understand that the information and signals used to convey the messages described herein may be represented using any of the various different techniques and technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0079]

[0105] The terms “and,” “or,” and “and / or” as used herein may have a variety of meanings that are expected to depend at least partially on the context in which such terms are used. Typically, when used to relate a list such as A, B, or C, “or” is intended to mean A, B, and C, as used here in an inclusive sense, as well as A, B, or C, as used here in an exclusive sense. In addition, the term “one or more” as used herein may be used to describe any singular feature, structure, or characteristic, or any combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Furthermore, when used to relate a list such as A, B, or C, the term “at least one” may be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABCCC, etc.

[0080]

[0106] Throughout this specification, any reference to “example,” “certain example,” or “exemplary implementation” means that any particular feature, structure, or characteristic described in relation to a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, occurrences of “in an example,” “in an example,” “in a certain example,” “in a certain implementation,” or other similar phrases in various places throughout this specification do not necessarily all refer to the same feature, example, and / or limitation. Furthermore, any particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0081]

[0107] In some implementations, operation or processing may involve the physical manipulation of physical quantities. Typically, but not always, such quantities may take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, or otherwise manipulated. Primarily for reasons of common use, it has been demonstrated that it can be convenient to refer to signals such as bits, data, values, elements, symbols, characters, terms, numbers, and digits. However, it should be understood that all these or similar terms must be associated with the appropriate physical quantities and are merely convenient labels. Unless otherwise stated, as will be evident from the discussion herein, discussions throughout this specification using terms such as “process,” “calculate,” “compute,” and “determine” are understood to refer to the operation or processes of a particular device, e.g., a special-purpose computer, special-purpose computing device, or similar special-purpose electronic computing device. Thus, in the context of this specification, a special-purpose computer or similar special-purpose electronic computing device can typically manipulate or convert signals that are represented as physical electronic or magnetic quantities in memory, registers, or other information storage devices, transmission devices, or within a special-purpose computer or similar special-purpose electronic computing device.

[0082]

[0108] In the preceding detailed description, numerous specific details are given in order to provide a complete understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter can be carried out without these specific details. In other examples, methods and apparatus that would be known to those skilled in the art are not described in detail so as not to obscure the claimed subject matter. Accordingly, the claimed subject matter is not limited to the specific examples disclosed, and such claimed subject matter is intended to include all embodiments included in the appended claims, and their equivalents.

Claims

1. circuit board and The dielectric layer on the substrate, Waveguides within the dielectric layer, A photodetector positioned above the waveguide and monolithically integrated with the substrate, wherein the photodetector is optically coupled to the waveguide and configured to operate at temperatures below 50K. A device equipped with the following features.

2. The apparatus according to claim 1, further comprising a heater positioned in close proximity to the waveguide and configured to thermally adjust a portion of the waveguide.

3. The apparatus according to claim 2, wherein the waveguide and the heater form a single-photon generator, a ring oscillator, an optical filter, an optical switch, or an optical interferometer.

4. The apparatus according to claim 2, further comprising a thermal isolation structure surrounding the heater, the thermal isolation structure including a trench in the dielectric layer and an undercut in the substrate.

5. The apparatus according to claim 4, wherein the undercut extends horizontally within the substrate and is located below the portion of the waveguide.

6. The apparatus according to claim 4, wherein the trench and the undercut form a vacuum region.

7. The apparatus according to claim 4, further comprising a cooling structure disposed so as to be in thermal contact with the substrate, wherein the undercut is disposed between the heater and the cooling structure.

8. The apparatus according to claim 1, further comprising a plurality of light-separating structures on at least one of the substrate or the dielectric layer, wherein the plurality of light-separating structures are configured to prevent photons from reaching the photodetector except through the waveguide.

9. The aforementioned plurality of light separation structures A metal trench in the dielectric layer that partially extends into the substrate, The metal trench in the dielectric layer, The array of metal vias in the dielectric layer, The dielectric layer and the metal cover on top of the photodetector, The apparatus of claim 8, comprising at least one of the deep trenches in the substrate, wherein the deep trench includes an air gap, or the deep trench is filled with a reflective or absorbent material.

10. The apparatus according to claim 9, wherein the metal cover is located within a metal layer and is aligned with or coupled to the metal trench or the array of metal vias to form a continuous structure surrounding the photodetector.

11. The waveguide includes an input port, The apparatus according to claim 9, wherein the metal trench or the array of metal vias is arranged in the region including the input port.

12. The apparatus according to claim 1, wherein the photodetector includes a superconducting nanowire single-photon detector.

13. The apparatus according to claim 1, wherein the dielectric layer includes an oxide layer.

14. A step of receiving a wafer, wherein the wafer is circuit board and The dielectric layer on the substrate, A waveguide formed in the dielectric layer, A photodetector located within the dielectric layer and coupled to the waveguide Steps including, A step of etching a first set of vias or a first trench in the dielectric layer in order to expose a first portion of the substrate, wherein the first set of vias or the first trench surrounds the photodetector. The steps of etching the substrate to form a second set of vias or a second trench in the substrate via the first set of vias or the first trench, The steps include filling the first set of vias or the first trench, and the second set of vias or the second trench with a light-reflective or light-absorbing material. A method that includes this.

15. The method according to claim 14, wherein the wafer further includes a heating structure formed in the dielectric layer and configured to thermally adjust a portion of the waveguide.

16. A step of etching a set of third vias or a third trench in the dielectric layer in order to expose a second portion of the substrate, wherein the set of third vias or the third trench surrounds the heating structure. A step of etching the substrate to form an undercut in the substrate through the third set of vias or the third trench, wherein the undercut is located below the second portion of the substrate, The steps include: depositing an oxide layer on the dielectric layer to seal the third set of vias or the third trench and the undercut; The method according to claim 15, further comprising:

17. The steps include etching the dielectric layer to form contact holes for the heating structure, The steps include filling the contact holes with a conductive material to form electrical contacts for the heating structure, and The method according to claim 15, further comprising:

18. The method according to claim 14, further comprising the step of forming an oxide liner layer in the second set of vias or the second trench before the filling step.

19. The method according to claim 18, further comprising the step of depositing a barrier and a seed layer on the oxide liner layer.

20. The method according to claim 14, further comprising the step of forming an upper metal cover on the dielectric layer and on the upper part of the photodetector.

21. The method according to claim 20, wherein the upper metal cover is made of a single layer of metal.

22. The steps include etching the dielectric layer to form contact holes for the photodetector, The steps include filling the contact holes with a conductive material to form electrical contacts for the photodetector, and The method according to claim 14, further comprising:

23. The method according to claim 22, wherein the step of filling the contact hole includes the step of depositing a liner layer on the side wall of the contact hole.

24. The method according to claim 23, wherein the liner layer comprises tungsten, tungsten carbide, or tungsten nitride.

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