Distributed multi-component synaptic computation structure

Abstract

It provides an energy-efficient spiking neural network. [Solution] A spiking neural network 200 comprises a plurality of presynaptic integrators 209, a plurality of weighting elements 210, and a plurality of output neurons 220, wherein each of the plurality of presynaptic integrators 213 receives a presynaptic pulse signal 204 that causes charge accumulation and generates a synaptic input signal 214 based on the accumulated charge. A first group of weighting elements 211 receive the synaptic input signal 214 from the first presynaptic integrator 213 and apply weight values ​​to the synaptic input signal 214 to generate a synaptic output current 215. The intensity of the synaptic output current is a function of the applied weight values. Each of the plurality of output neurons 222 receives the synaptic output current from a second group of weighting elements and generates a spatiotemporal spike train output signal 223 based on the synaptic output current.

Description

[Technical Field]

[0001] The present invention relates to an automatic signal recognition technology, and more particularly to a system and method for a distributed multi-component synaptic computing structure that enables an area-optimized and energy-efficient processing mechanism in a network. In particular, the computing structure is a spiking neural network. [Background technology]

[0002] Brain-inspired neuromorphic spiking neural network (SNN) emulators form distributed, parallel, event-driven systems that provide capabilities such as adaptation, self-organization, and learning. These emulators implement several concepts, such as activity-dependent short-term and long-term plasticity, which are experimentally demonstrated. C. Mead, "Neuromorphic electronic See "systems," Proceedings of IEEE, vol.78, no.10, pp.1629-1636, October 1990.

[0003] Input information is encoded by patterns of activity occurring across a population of neurons, and synapses (each forming a connection from one neuron to a subsequent neuron) can adapt their function in response to the pulses they receive (e.g., in the form of spatiotemporal spike trains), providing signal transmission energy efficiency as well as flexibility for storing and retrieving information. (R. Douglas, M. Mahowlald, C. Mead, "Neuromorphic Analogue VLSI", Annual Reviews) See Neuroscience, vol. 18, pp. 255-281, 1995.

[0004] Synapses perform a dual function: in addition to functioning as complex nonlinear operators performing distributed computations, they implement memory storage capabilities. The separation of processing elements and memory means that conventional, von Neumann-based computing systems are not optimized for computational tasks involving large amounts of high-dimensional data, such as image processing, object recognition, probabilistic reasoning, or speech recognition. These tasks can be efficiently completed using powerful yet conceptually simple and highly parallel methods, such as SNNs, where memory and processing elements are co-located. Neuromorphic systems are directly driven by input data; that is, at the rate of incoming data, each synapse receives a spike and each neuron generates a spike. As a result, dynamic power consumption occurs only when the circuit is processing data. In applications with sparse spatiotemporal signal activity, most neurons are inactive at each particular moment, leading to minimal power consumption.

[0005] Neuromorphic computing elements, namely neurons and synapses, exhibit a wide range of spiking behavior, typically represented as dynamic systems of varying complexity, representing various trade-offs between biophysical precision and computational power. Several specific hardware implementations of biologically plausible, biologically inspired, and integral firing neuron models incorporate membrane dynamics (modeling charge leakage across membranes); ion channel dynamics (controlling ion flow); axon models (with associated delay components); and dendritic models (modeling the influence of presynaptic and postsynaptic neurons). See CDSchuman, et al., "A survey of neuromorphic computing and neural networks in hardware," arXiv.1705.06963, p.88, 2017.

[0006] Hardware implementations of synaptic models, repurposed for advancements and adoption of new materials, primarily focus on optimizing the synaptic implementation. More complex synaptic models include plasticity mechanisms (e.g., both short- and long-term enhancement and inhibition; see S.-C. Liu, "Analog VLSI circuits for short-term dynamic synapses," EURASIP Journal on Applied Signal Processing, vol.7, pp.620-628, 2003), or, in more biologically inspired neuromorphic networks, synaptic chemical interactions (see FLMaldonado Huayaney, et al., "Implementation of multi-factor synaptic plasticity with calcium-based dynamics," IEEE Transactions on Circuits and Systems-I, vol.63, no.12, pp.2189-2199, 2016). Synapses are also used as homeostatic mechanisms to stabilize network activity (S.-C. Liu, BAMinch, "Silicon synaptic adaptation mechanisms for homeostasis and contrast gain control", IEEE). See Transactions on Neural Networks, vol.13, no.6, pp.1497-1503, 2002.

[0007] Modern deep learning architectures typically consist of multiple layers, each layer comprising vector matrix multiplication implemented by synaptic matrices, the result of which is used as input for a specific nonlinear activation function in a neuron (e.g., sigmoid function, ReLU (rectified linear unit) activation function, or activation function based on membrane potential dynamics). The activation function in a neuron is also called the neuronal activation function. Neurosynaptic arrays employ a hybrid analog-digital signal representation, i.e., a sequence of pulses / spikes transmits analog information at the timing of events, which are converted back to analog signals at the input of the synaptic matrix. Analog crossbar arrays essentially implement dot product operations (which form an essential operation in dense vector matrix multiplication). In the analog domain, the vector of voltage signals is applied to the rows of synaptic crossbars, multiplying with each synapse (weight w) according to Kirchhoff's current law (KCL) rule, and the currents are added together across each column. That is, the output of a synapse is usually in the current domain, since signal summation in the current domain simply wires all the outputs together. This postsynaptic current represents the result of multiplication, and signal summation and nonlinear functionality are provided by neuronal dynamics, which are represented by the neuronal activation function.

[0008] Generally, two specific methods are used to derive weighted inputs, as illustrated by Figures 1A and 1B, respectively.

[0009] Figure 1A discloses a known first method in which every synapse has two symmetric output currents, which are first added separately. Thus, the difference between the two sums is the weighted input. Figure 1A actually shows a partial example of a prior art spiking neural network 100, which includes a synaptic input signal 103, a m-synaptic element 101, a current mirror 106, a synaptic output current 107, a weighted synaptic output 104, an output neuron 102, and a neuron output signal 105. The synaptic element 101 is configured to receive a synaptic input signal 100, which is a spatiotemporal spike train. The synaptic element 101 converts the input spikes in the synaptic input signal 103 into currents, each of which is weighted w 11 ,w 21 ,...,w m1 Applying the formula (where the first index represents the row of the synaptic matrix and the second index represents the column of the synaptic matrix), two synaptic symmetric output currents 107 are generated. The difference between these currents is calculated by the current mirror 106 to generate the final weighted synaptic output 104. The output neuron 102 then generates a neuron output signal 105 based on the weighted synaptic output 104. Note that each of the synaptic elements 101 is configured to perform both the integration of the synaptic input signal 100 to generate a current and the subsequent application of weights to this current to generate the synaptic output current 107.

[0010] Figure 1B discloses a second known technique in which every synapse has one bipolar (positive / negative, excitatory / inhibitory) output current, and therefore the weighted input is the sum of these bipolar output currents. Figure 1B actually shows another example of a portion of a prior art spiking neural network 110, including a synaptic input signal 113, a synaptic element 111, a synaptic output current 114, an output neuron 112, and a neuron output signal 115. Similar to the previous example, the synaptic element 111 takes the integral of the synaptic input signal and the weight w 11 ,w 21 ,...,w m1Execute both functions of subsequent weight application using it. However, in this method, the synaptic element 111 is configured to generate a positive or negative output current 104 corresponding to an excitatory or inhibitory signal so that signal subtraction is not required to generate a correctly weighted output.

[0011] Since each synapse includes a normal current mirror, each synapse requires a larger chip area. However, the wiring in this example is simplified because all building blocks are the same, that is, when implementing neurons using higher- or lower-dimensional input vectors, that is, when the number m of synaptic elements is changed, there is no need to redesign the current mirror.

[0012] FIG. 1C discloses a known neuro-synaptic array consisting of a neural network matrix connecting m×n programmable synapses to n neurons. The neuro-synaptic computing element can generate complex spatio-temporal dynamics that can be extended towards specific features of the target signal processing function. The spiking characteristics of neurons are controlled through a specific set of parameters. In fact, FIG. 1C shows a neural network matrix 130 that connects multiple groups of programmable synaptic elements 121 to an array 140 of n output neurons 122 including neurons N1, N2,..., N n to form a part of a spiking neural network. Here, the synaptic element 121 receives a synaptic input signal 123 and generates a synaptic output current 124, and the output neuron 122 is configured to generate a neuron output signal 125. Each of the neurons 122 is connected to a different column of the synaptic elements 121, and the synaptic input signals 123 received by each row of the synaptic elements 213 are the same, but different weight values w i1 , w i2 ,..., w inHowever, this can be applied by different synaptic elements 211 within the same row at row index i. Finally, the neuron can be composed of one or more neuron control signals 127. These neuron control signals 127 can control the neuron dynamics represented by the neuron activation function, for example, by changing the parameters of the neuron activation function. In this case as well, each of the synaptic elements 121 is configured to perform both the integration of the synaptic input signal and the subsequent weight application function.

[0013] In a fully connected network, synaptic integral capacitance is the largest contributor to the total area of ​​the array. Capacitors occupy a lot of space and consume a relatively large amount of energy. In conventional hardware implementations of spiking neural networks, capacitors are required for synaptic integrals at synaptic elements. As a result, conventional spiking neural networks, which consist of many layers of synapses and neurons, are not optimized in terms of area and energy use. Therefore, there is a need in the industry for more efficient spiking neural networks. [Overview of the project]

[0014] In this patent application, the inventors report a novel distributed multi-component synaptic structure that enables area-efficient and power-efficient designs, in which each distributed component can implement unique computational characteristics and be optimized for a given signal processing function specification.

[0015] According to a first aspect of this disclosure, a spiking neural network 100 is disclosed, comprising a plurality of presynaptic integrators 209, a plurality of weighting elements 210, and a plurality of output neurons 220. Each of the plurality of presynaptic integrators 213 receives a presynaptic pulse signal 204 that causes charge accumulation in the presynaptic integrator and is adapted to generate a synaptic input signal 214 based on the accumulated charge such that the synaptic input signal has a predetermined time dynamics. A first group of weighting elements 211 of the plurality of weighting elements 210 is connected to receive the synaptic input signal 214 from the first of the plurality of presynaptic integrators 213. Each weighting element 211 of the first group of weighting elements is adapted to apply weight values ​​to the synaptic input signal 214 to generate a synaptic output current 215, the intensity of which is a function of the applied weight values. Each of the multiple output neurons 222 is connected to receive a synaptic output current 214 from a second group of weight-applying elements among the multiple weight-applying elements, and to generate a spatiotemporal spike train output signal 223 based on one or more of the received synaptic output currents.

[0016] Thus, instead of using a single circuit to reproduce synaptic dynamics for area-optimized design (and subsequent energy-efficient design), the present invention reproduces synaptic dynamics using two dedicated circuits: a presynaptic integrator and a weighted application element. Each implements a clearly defined function; the first circuit performs pulse (spike) integration, and the second circuit performs weighted application. As a result, only a single spike integrator (and therefore a single capacitor rather than one capacitor per synapse) is required for each input signal. This thus results in an area-efficient design, as the preintegration is shared per row of the weighted application element 211. Furthermore, since only a single preintegration is now required instead of n preintegrations, the present invention provides a more power-efficient implementation of the synaptic matrix.

[0017] According to one embodiment, each of the weight application elements includes a synaptic input receiver configured to receive a synaptic input signal from a presynaptic integrator and generate a synaptic input current based on the synaptic input signal, a weight storage element configured to store a weight value, and a correction element configured to apply the weight value stored in the weight storage element to the synaptic input current to generate a synaptic output current. The weight value is preferably stored in digital form and is converted to the analog domain via a current-mode digital-to-analog converter. The current-mode digital-to-analog converter is preferably based on an R-2R architecture and preferably applies a predetermined coefficient to attenuate the synaptic input current and generate a synaptic output current based on the attenuated synaptic input current.

[0018] In one embodiment, the weight value stored in the weight storage element is adjustable, and preferably, the weight value stored in the weight storage element is adjusted based on a learning rule.

[0019] In one embodiment, the network further includes a row spike decoder configured to supply a presynaptic pulse signal based on a presynaptic input spike such that the presynaptic pulse signal is assigned to the presynaptic integrator based on the configuration of the spiking neural network.

[0020] In one embodiment, the spiking neural network includes an input neuron that generates a presynaptic pulse signal, and the presynaptic integrator multiplexes temporal spikes arising from different input neurons.

[0021] In one embodiment, the predetermined temporal dynamics of the synaptic input signal generated by the presynaptic integrator are the temporal dynamics of AMPA, NMDA, GABA A , or GABA B .

[0022] In one embodiment, the presynaptic integrator generates an adjustable gain independent of an adjustable time constant, where the time constant determines a leakage current that separates the accumulated charge within the presynaptic integrator and characterizes the temporal dynamics of the synaptic input signal of the presynaptic integrator.

[0023] In one embodiment, the presynaptic integrator is configurable by a control signal, and preferably, the control signal controls the temporal shape of the synaptic input signal.

[0024] In one embodiment, the output neuron is controlled by a neuron control signal, such as for controlling neuron dynamics.

[0025] In one embodiment, the spiking neural network includes a plurality of first groups of weight application elements, and each one of the weight application elements within each first group of weight application elements is connected to receive the same synaptic input signal from a respective presynaptic integrator, and each first group of weight application elements is connected to receive synaptic input signals from different ones of the plurality of presynaptic integrators.

[0026] In one embodiment, the spiking neural network includes a plurality of input neurons, and each one of the input neurons is connected to provide a presynaptic pulse signal to a respective one of the presynaptic integrators to provide a synaptic input signal to a respective first group of weight application elements.

[0027] In one embodiment, the spiking neural network includes a plurality of second groups of weight application elements, and each second group of weight application elements is connected to provide a synaptic output signal to a different one of the plurality of output neurons.

[0028] In one embodiment, the spiking neural network exhibits various pattern activity in use, including complete synchronization, clustering or asynchronous states, heterogeneity in the input pattern, spatiotemporal dynamics of neurosynaptic elements, nonlinear spiking behavior, and / or frequency adaptability.

[0029] A second aspect of the present disclosure discloses a presynaptic integrator configured to generate synaptic input currents for input to a plurality of weight-applying elements. The presynaptic integrator comprises an input element configured to receive a presynaptic pulse signal, preferably a presynaptic pulse voltage, wherein the presynaptic pulse signal is a spatiotemporal spike train; a capacitor configured to store charge in response to the presynaptic pulse signal; a leakage element configured to discharge at least a portion of the charge stored by the capacitor; and an output element configured to generate synaptic input signals based on the charge stored by the capacitor for supply to a plurality of weight-applying elements.

[0030] In one embodiment, the presynaptic integrator further comprises a control element adapted to control the time dynamics of a synaptic input signal, the control element being configured to receive a control signal, preferably a control voltage, and to adjust the maximum amplitude of the synaptic input signal by adjusting the accumulation of charge by a capacitor based on the control signal and controlling the maximum charge on the capacitor.

[0031] A third aspect of this disclosure discloses a presynaptic integrator circuit configured to generate a synaptic input signal for subsequent weight application. The presynaptic integrating circuit comprises: an input element configured to receive a presynaptic pulse signal, preferably a presynaptic pulse voltage, wherein the presynaptic pulse signal is a spatiotemporal spike train; a capacitor configured to accumulate charge based on spikes in the spatiotemporal spike train; a leakage element configured to discharge at least a portion of the charge accumulated by the capacitor; an output element configured to generate a synaptic input signal based on the charge accumulated by the capacitor; an output control element configured to control the generation of a synaptic input signal performed by the output element based on the presynaptic pulse signal, wherein the generation of the synaptic input signal is controlled by the spatiotemporal spike train, wherein the synaptic input signal is preferably not generated during spikes in the spatiotemporal spike train; and a control element configured to receive a control signal, preferably a control voltage, and to adjust the temporal shape and maximum amplitude of the synaptic input signal by adjusting the accumulation of charge by the capacitor and controlling the maximum charge on the capacitor, such that the amount of charge accumulated by the capacitor does not depend on the duration of spikes in the spatiotemporal spike train and the capacitance value of the capacitor, preferably manufacturing variations of the capacitor.

[0032] The amount of charge stored by a capacitor is independent of the duration of the spikes in the spatiotemporal spike train and the capacitance value of the capacitor; therefore, the function and performance of the presynaptic integrator circuit are independent of variations in the manufacturing of the capacitor.

[0033] In one embodiment, the output control element comprises a field-effect transistor and an inverter, the inverter configured to apply a gate-source voltage to the field-effect transistor of the output control element based on a presynaptic input signal, preferably the gate-source voltage is applied when the presynaptic input signal is not spiking, and the synaptic input signal is generated by a drain-source current flowing through the field-effect transistor of the output control element.

[0034] In the second or third embodiment, the leakage element is controlled by a time constant, preferably the time constant is AMPA, NMDA, GABA A or GABA B This characterizes the time dynamics of [the system].

[0035] In the second or third embodiment, the leakage element comprises a field-effect transistor, the time constant is the gate-source voltage of the field-effect transistor of the leakage element, and the capacitor is discharged by the drain-source current of the field-effect transistor of the leakage element.

[0036] In the second or third embodiment, the input element comprises a field-effect transistor, the presynaptic pulse signal is the gate-source voltage of the field-effect transistor of the input element, and the drain-source current flowing through the field-effect transistor of the input element charges a capacitor.

[0037] In one embodiment of the second or third aspect, the output element comprises a field-effect transistor, where the charge stored by the capacitor generates a gate-source voltage of the field-effect transistor of the output element, and the drain-source current flowing through the field-effect transistor of the output element generates a synaptic input signal.

[0038] In one embodiment of the second or third aspect, the control element comprises a field-effect transistor, the control signal is the gate-source voltage of the field-effect transistor of the control element, and the capacitor is charged by the drain-source current flowing through the field-effect transistor of the control element.

[0039] In one embodiment of the second or third aspect, the output element further comprises an output current mirror configured to generate a synaptic input signal in the voltage domain, or an output cascode current mirror configured to generate a synaptic input signal in the voltage domain, wherein the resulting synaptic input signal includes two voltage signals.

[0040] In the second or third embodiment, the synaptic input signal decreases exponentially when the capacitor is discharged.

[0041] A fourth aspect of the present disclosure discloses a polarity selection circuit configured to duplicate or invert a synaptic output current. The polarity selection circuit comprises a polarity input element configured to receive a synaptic output current; a polarity selection terminal configured to select a sourcing or thinking current mirror based on a polarity input signal, wherein the sourcing current mirror is configured to duplicate the synaptic output current and the thinking current mirror is configured to invert the synaptic output current; and a polarity output element that generates a polarity output current based on the duplicated or inverted synaptic output current.

[0042] According to one embodiment of the first aspect of the present invention, each weight-applying element further comprises a polarity-selecting element, the polarity-selecting element comprising a polarity-selecting circuit according to the fourth aspect of the present invention, thereby the synaptic output signal from the first aspect of the present invention is used by the polarity-selecting circuit to generate a polar output current, preferably an input neuron receives the polar output current, the replicated synaptic output current corresponds to an excitatory synaptic output signal, and the inverted synaptic output current corresponds to an inhibitory synaptic output signal.

[0043] In one embodiment of the first aspect, the presynaptic integrator comprises a presynaptic integrating circuit according to the second or third aspect.

[0044] A fifth aspect of this disclosure discloses a method for presynaptic integration and weight application for a spiking neural network. The spiking neural network comprises a plurality of presynaptic integrators 209, a plurality of weight application elements 210, and a plurality of output neurons 220. The method includes: each of a plurality of presynaptic integrators 213 receiving a presynaptic pulse signal 204 that causes charge accumulation in the presynaptic integrator; each of the plurality of presynaptic integrators 213 generating a synaptic input signal 214 based on the accumulated charge such that the synaptic input signal has a predetermined time dynamics; receiving the synaptic input signal 214 from the first of the plurality of presynaptic integrators 213 by a first group of weighted elements 211 of a plurality of weighted elements 210; applying weight values ​​to the synaptic input signal 214 by each weighted element 211 of the first group of weighted elements to generate a synaptic output current 215, wherein the intensity of the synaptic output current is a function of the applied weight values; and each of a plurality of output neurons 222 receiving a synaptic output current 214 from a second group of weighted elements and generating a spatiotemporal spike train output signal 223 based on one or more received synaptic output currents.

[0045] In one embodiment, each weight application element comprises a weight application circuit adapted to receive a synaptic input signal from a presynaptic integrator, generate a synaptic input current based on the synaptic input signal, store weight values, and apply the stored weight values ​​to the synaptic input current to generate a synaptic output current.

[0046] In one embodiment, the presynaptic integrator generates a tunable gain independent of a tunable time constant, the time constant determining a leakage current that isolates the accumulated charge within the presynaptic integrator and characterizing the time dynamics of the synaptic input signal to the presynaptic integrator.

[0047] In one embodiment, the spiking neural network comprises a plurality of first groups of weighted elements, where each weighted element in each first group is connected to receive the same synaptic input signal from its respective presynaptic integrator, and each weighted element in each first group is connected to receive the synaptic input signal from one of a plurality of different presynaptic integrators.

[0048] In one embodiment, the spiking neural network includes a plurality of input neurons, each of which is connected to provide a presynaptic pulse signal to each of the presynaptic integrators in order to provide a synaptic input signal to each of the first group of weight-applying elements.

[0049] A sixth aspect of the present disclosure discloses a method for presynaptic integration for a spiking neural network. The method includes providing a presynaptic integration circuit configured to generate synaptic input currents for input to a plurality of weight-applying elements, receiving a presynaptic pulse signal, preferably a presynaptic pulse voltage, preferably the presynaptic pulse signal being a spatiotemporal spike train, receiving, accumulating charge in response to the presynaptic pulse signal, discharging at least a portion of the accumulated charge through a leakage element, and generating synaptic input signals based on the accumulated charge to supply to the plurality of weight-applying elements.

[0050] A seventh aspect of this disclosure discloses a method for presynaptic integration for a spiking neural network. The method includes providing a presynaptic integrating circuit configured to generate a synaptic input signal for subsequent weight application; receiving a presynaptic pulse signal, preferably a presynaptic pulse voltage, wherein the presynaptic pulse signal is a spatiotemporal spike train; accumulating charge in a capacitor based on spikes in the spatiotemporal spike train; discharging at least a portion of the charge accumulated in the capacitor through a leakage element; generating a synaptic input signal based on the charge accumulated in the capacitor; controlling the generation of a synaptic input signal, performed by an output element based on a presynaptic pulse signal, such that the generation of the synaptic input signal is controlled by the spatiotemporal spike train, preferably so that the synaptic input signal is not generated during spikes in the spatiotemporal spike train; and providing a control element configured to receive a control signal, preferably a control voltage, and to adjust the temporal shape and maximum amplitude of the synaptic input signal by adjusting the accumulation of charge and controlling the maximum charge on the capacitor, such that the amount of charge accumulated in the capacitor does not depend on the duration of spikes in the spatiotemporal spike train and the capacitance value of the capacitor, preferably manufacturing variability of the capacitor.

[0051] An eighth aspect of this disclosure discloses a method for polarity selection. The method includes providing a polarity selection circuit configured to duplicate or invert a synaptic output current, receiving a synaptic output current, selecting a sourcing or thinking current mirror based on a polarity input signal, duplicating and / or inverting a synaptic output current, and generating a polarity output current based on the duplicated or inverted synaptic output current.

[0052] A ninth aspect of this disclosure discloses a method for classifying an input signal using a spiking neural network according to the first aspect.

[0053] Next, with reference to the attached schematic diagram, an embodiment will be described as merely an example, where corresponding reference numerals indicate corresponding parts. [Brief explanation of the drawing]

[0054] [Figure 1A] This is a diagram showing at least some examples of conventional spiking neural networks. [Figure 1B] This is a diagram showing at least some examples of conventional spiking neural networks. [Figure 1C] This is a diagram showing at least some examples of conventional spiking neural networks. [Figure 2] This is a diagram of at least a portion of a spiking neural network according to an exemplary embodiment. [Figure 3] This is a figure of at least a portion of a spiking neural network according to another exemplary embodiment. [Figure 4A] This is a diagram of a presynaptic integrating circuit according to an exemplary embodiment. [Figure 4B] This is a diagram of a presynaptic integrating circuit according to another exemplary embodiment. [Figure 5A] This is a diagram of a weight application circuit according to an exemplary embodiment. [Figure 5B] This is a diagram of a weight application circuit according to another exemplary embodiment. [Figure 6] This is a diagram of a polarity selection circuit according to an exemplary embodiment. [Figure 7A] This graph shows the excitatory synaptic output current dynamics according to an exemplary embodiment. [Figure 7B] This graph shows the spatiotemporal spike train dynamics according to an exemplary embodiment. [Figure 7C] This graph shows the spatiotemporal spike train dynamics in another exemplary embodiment. [Modes for carrying out the invention]

[0055] The figures are for illustrative purposes only and do not limit the scope or protection defined by the claims.

[0056] The following describes specific embodiments in further detail. However, it should be understood that these embodiments do not necessarily have to be construed as limiting the scope of protection of this disclosure.

[0057] As described above, in a fully connected network with m × n synapses, the capacitor used for synaptic integration is the largest contributor to the total area of ​​the array. For area-optimized design (and subsequent energy-efficient design), instead of using one circuit to reproduce synaptic dynamics (as shown in Figures 1A-1C), the present invention reproduces synaptic dynamics using two dedicated circuits (Figure 2), each implementing a clearly defined function: the first circuit performs pulse (spike) integration, and the second circuit performs weight application. As a result, only a single spike integrator (and therefore a single capacitor instead of n capacitors) is required for each input signal. Thus, this results in an area-efficient design, and the pre-integration is shared per row of weight application elements 211. Furthermore, since only a single pre-integration is now required instead of n pre-integrations, the present invention provides a more power-efficient implementation of the synaptic matrix.

[0058] Figure 2 shows a portion of a spiking neural network 200 according to an exemplary embodiment, which can form a subnetwork (or ensemble) within a larger neural network comprising multiple subnetworks and can be implemented as a neurosynaptic score. Figure 2 shows output neurons 222 connected to weighted elements 211 connected to a presynaptic integrator 213. An exemplary embodiment includes at least one presynaptic integrator 213, a plurality of weighted elements 211, and a plurality of output neurons 220. In some embodiments, the spiking neural network 200 comprises several layers such that spatiotemporal spike train output signals 223 generated by output neurons 222 can form presynaptic signals 204 received by a presynaptic integrator 213 in the next layer, and that presynaptic pulse signals 204 received by the presynaptic integrator 213 can be generated by input neurons, i.e., output neurons 222 from the previous layer. To avoid confusing the image, only a small number of neurons 222, presynaptic integrators 213, and weight-applying elements 211 are shown, and only a few are labeled with reference numbers.

[0059] Synaptic dynamics are replicated by the presynaptic integrator 213 and the weighting element 211. The presynaptic integrator 213 performs the function of presynaptic pulse (spike) integration so that the presynaptic (fast) pulse signal 204 is converted into a (longer) synaptic input signal 214. In some embodiments, the synaptic input signal 214 may be an exponentially decreasing spike, similar to the signal emitted by an AMPA receptor. In some embodiments, the synaptic input signal 214 may be a synaptic input current. In some embodiments, the synaptic input signal 214 may be a synaptic input voltage. In some embodiments, the presynaptic integrator 213 may be configured by a control signal 203, preferably the control signal 203 controlling the time shape of the synaptic input signal 214 generated by the presynaptic integrator 213.

[0060] Each weight application element 211 performs a typical synaptic function, connecting an input neuron and an output neuron, and applies weight values ​​stored in the corresponding weight memory element 212 to the synaptic input signal 214 to generate a synaptic output current 215. In particular, the applied weight values ​​determine the intensity of the synaptic output current 215. In some embodiments, the weight application element applies a coefficient ranging from 0 to 1 to attenuate the synaptic input signal in order to generate a synaptic output current that includes a selected portion of the synaptic input signal. In some embodiments, the weight values ​​stored by the weight memory element 212 are preferably adjustable according to a learning rule.

[0061] The output neuron 222 is configured to receive at least one synaptic output current 215 from the weighting element 211 and to generate a spatiotemporal spike train output signal based on the one or more synaptic output currents it receives. In some embodiments, the output neuron 222 can be configured by neuron control signals 224. These neuron control signals 127 can control the neuron dynamics represented by the neuron activation function, for example, by changing the parameters of the neuron activation function.

[0062] In an alternative embodiment, the spiking neural network further comprises a row spike decoder 202 configured to decode a presynaptic pulse signal 204 based on a presynaptic input spike 201 and assign it to a corresponding presynaptic integrator 213. Which presynaptic pulse signal is sent to which presynaptic integrator 213 depends on the configuration of the spiking neural network. Decoding the presynaptic input spike 201 is included.

[0063] Figure 3 shows another example of a spiking neural network 300 according to another exemplary embodiment, which can form subnetworks (or ensembles) within a larger neural network comprising multiple subnetworks and can be implemented as neurosynaptic scores. Output neurons 322 are connected to weighted elements 311 connected to presynaptic integrators 313. An exemplary embodiment includes at least one presynaptic integrator 313, a plurality of weighted elements 311, and a plurality of output neurons 320. In some embodiments, the spiking neural network 300 comprises several layers such that spatiotemporal spike train output signals 326 generated by output neurons 322 can form presynaptic signals 204 received by presynaptic integrators 213 in the next layer, and presynaptic pulse signals 307 received by presynaptic integrators 313 can be generated by input neurons, i.e., output neurons 322 from the previous layer. To avoid confusing the image, only a small number of neurons 322, presynaptic integrators 313, and weight-applying elements 311 are shown, and only a few are labeled with reference numbers.

[0064] This embodiment further comprises a neurosynapse score control element 304, a neuron control element 323, a neuron decoder element 321, and a row spike decoder 302 similar to the row spike decoder 202 in Figure 2, such that the row spike decoder 302 decodes a presynaptic pulse signal 307 based on a presynaptic input spike 301 and assigns it to a presynaptic integrator 313.

[0065] Multiple neurosynaptic cores arranged within an array of cores house a high-level architecture for the learning system. Each core contains a network of neurons implemented in hardware, where the neurons are interconnected by synaptic elements. A single core may implement a complete spiking neural network or a portion of a spiking neural network that forms separate subnetworks. In this way, a large spiking neural network may be divided into several smaller subnetworks, each subnetwork being implemented in one of the cores of the array. In one embodiment, a core may implement a spiking neural network having associated input data ports, output ports, and / or control and configuration interfaces, for example, each core may implement one or more subnetworks, including the arrangement shown in Figure 2 or Figure 3.

[0066] By dividing a large spiking neural network into smaller subnetworks and implementing each subnetwork on one or more cores, each with its own required circuitry, some of the non-idealism of the circuitry operating at smaller process geometries and lower operating currents is mitigated, especially for large arrays. Thus, core-based implementation techniques reduce the impact of physical non-idealism.

[0067] Ensembles of neurons that form subnetworks or collaborative groups can, for example, form classifiers, ensembles of classifiers, data transformations, feature coding, or groups of neurons that process classification alone.

[0068] In such a regime, the large network of an ensemble is divided and mapped onto an array of cores, each containing a programmable network of spiking neurons. As a result, each core implements a single ensemble, multiple smaller ensembles (in terms of the number of neurons and synapses within the core), or, in the case of a large ensemble, only a portion of the single ensemble, with the rest implemented on other cores of the array. The modality of how the ensemble is divided and mapped onto the cores is determined by the mapping methodology. The mapping methodology can include constraint-driven division. The constraints can be performance metrics linked to the functionality of each respective subnetwork. The performance metrics may depend on power-area limits, memory structure, memory access, time constants, biases, technical limitations, resilience, acceptable levels of mismatch, and network or physical artifacts.

[0069] The neurosynapscore control element 304 is configured to receive a spike input 306 from the preceding layer of the input neuron, send a presynaptic input spike 301 to the row spike decoder 302, and send a control signal 303 to the presynaptic integrator 303. Furthermore, the neurosynapscore control element 304 is configured to receive and then transmit a neuron spike output signal 325 from the neuron decoder element 321. In addition, the neurosynapscore control element 304 is configured to control both the neuron control element 323 and the neuron decoder element 321. Finally, the neurosynapscore control element is configurable by the configuration signal 305.

[0070] The neuron control element 323 is configured to control a plurality of output neurons 320 via a neuron control signal 324. The neuron decoder element 321 is configured to generate a neuron spike output signal 325 based on at least one spatiotemporal spike train output signal 326 generated by the output neurons 322 based on a synaptic output current 315.

[0071] Therefore, the neurosynaptic score disclosed in this invention can be organized as a repeating array of synaptic circuits and neuronal units, each unit of which can form a cellular assembly. The system can incorporate the presence of electronic synapses at the junctions of the array. The periphery of the array can include rows of synaptic circuits that mimic the action of the cell body and axonal crest of a living neuron.

[0072] Furthermore, each neurosynaptic score in the array may have a local router that communicates with routers in other cores within a dedicated real-time reconfigurable network on-chip. A classifier can be assumed to have, for example, a set of output neurons (one per class) each firing events (spikes) according to its firing probability distribution.

[0073] Next, the presynaptic integrating circuit according to the present invention will be described.

[0074] Figure 4A shows a presynaptic integrator circuit 400 according to an exemplary embodiment of presynaptic integrators 213, 313, which is powered by a positive voltage source 420 (voltage V DD Also called the drain), negative voltage source 440 (voltage V SS The presynaptic integrators 213, 313 include a capacitor 404 (also called a source), several field-effect transistors (FETs), particularly the input FET 401, the leakage FET 403, the output FET 405, and the current mirror 406. The presynaptic integrators 213, 313 operate in the subthreshold region and provide low-area and linear filtering characteristics. The presynaptic integrators 213, 313 convert fast presynaptic pulse signals 204, 307 into (long-lasting) synaptic input signals 214, 314. The synaptic input signals may be shaped, for example, as exponentially decreasing spikes (while preserving the temporal dynamics of receptors such as AMPA). The presynaptic integrators 213, 313 offer the possibility of multiplexing temporal spikes originating from different neurons and provide tunable gains independent of the (tunable) time constant.

[0075] In this embodiment, presynaptic pulse signals 204 and 307 from row spike decoders 213 and 302 form a gate-source voltage across input FET 401. When the gate-source voltage is positive in response to a spike in the presynaptic pulse signal, input FET 401 turns on, allowing drain-source current to flow.

[0076] Some embodiments may further include a control FET 402 configured to control the time dynamics of synaptic input signals 214, 314 based on a control signal, which is a gate-source voltage applied to the control FET 402. In this embodiment, the control signal is a control signal 203, 303 from a row spike decoder 202 or a neurosynapse core control element 304. When the gate-source voltage is positive, for example, the control FET 402 turns on, allowing drain-source current to flow.

[0077] Capacitor 404 is connected to input FET 401 and optionally control FET 402, thereby connecting a positive voltage source 420 to a negative voltage source 440 via capacitor 404, so that when both input FET 401 and control FET 402 are turned on, a closed circuit is formed and capacitor 404 stores charge until the connection is terminated.

[0078] When capacitor 404 has accumulated charge, output FET 405 turns on when its gate-source voltage equals the charge accumulated by capacitor 404. When output FET 405 is on, drain-source current is allowed to flow from positive voltage source 420 to negative voltage source 440 through output FET 405 and current mirror 406. Output FET 405 may be configured to operate in its subthreshold region such that as the charge on capacitor 404 decreases linearly, the drain-source current flowing through output FET 405 decreases exponentially. In some embodiments, output FET 405 operates in its subthreshold region and therefore provides an exponential relationship between its gate-source voltage and its source-drain current. As a result, a linear decrease in charge on capacitor 404 is translated into an exponential decay of the drain-source current.

[0079] The leak FET 403 is configured to discharge capacitor 404 when switched on. Due to the constant current flowing through the leak FET 403, the charge stored by capacitor 404 decreases linearly. In some embodiments, the leak FET 403 is controlled by a time constant, which determines the gate-source voltage of the leak FET 403. The time constant is, for example, AMPA, NDMA, GABA. A or GABA B The time dynamics may be chosen to be realized.

[0080] When current flows through the current mirror 406, a voltage signal is generated in proportion to the intensity of this current. In this embodiment, the synaptic input signals 214, 314 generated by the presynaptic integrators 213, 313 are these voltage signals. In practice, the current flowing through the current mirror 406 is replicated as a voltage signal. Alternatively, or in addition, the current mirror 406 may be a cascode current mirror such that the synaptic input signals 214, 314 include two voltage signals, in order to reduce variability in current replication and improve accuracy. That is, the cascode implementation improves the output drive strength by improving impedance.

[0081] Figure 4B shows a presynaptic integrator circuit 410 according to another exemplary embodiment of the presynaptic integrators 213, 313, which comprises a positive voltage source 430, a negative voltage source 450, a capacitor 414, and several field-effect transistors (FETs), in particular an input FET 411, a control FET 412, a leakage FET 413, an output FET 415, a mirror FET 417, and a cascode current mirror 416. The circuit of Figure 4B is used so that the amount of charge stored by the capacitor does not depend on the capacitance value of the capacitor 414 (which can vary by up to 20% due to manufacturing variations). Thus, the circuit no longer depends on the duration of the spikes in the presynaptic pulse signals 204, 307, as long as it is long enough to stabilize the charge on the capacitor 414. This embodiment further includes output control elements, including an output control FET 419, a current control FET 418, and an inverter 423.

[0082] In this embodiment, the presynaptic pulse signals 204 and 307 are the gate-source voltages applied to the input FET 411. When an input pulse is applied, the gate-source voltage across the input FET 411 increases, causing current to flow through the control FET 412, charging the capacitor 414 to the diode voltage of the Miller FET 417. It is important to note that the gate-source voltage pulse on the input FET 411 must be long enough for the amount of charge stored in the capacitor 414 to reach a certain value.

[0083] The control FET 412 is configured to control the time dynamics of synaptic input signals 214, 314 based on control signals 203, 303. In this embodiment, control signals 203, 303 are gate-source voltages applied to the control FET 412. When the gate-source voltage is positive, the control FET 412 is turned on, allowing drain-source current to flow. In this embodiment, control signals 203, 303 are configured to adjust the time shape and maximum amplitude of the synaptic input signals by regulating the charge accumulation by the capacitor and controlling the maximum charge on the capacitor, such that the amount of charge accumulated by the capacitor does not depend on the duration of the spikes in the spatiotemporal spike train and the capacitance value of the capacitor. In some embodiments, the control FET 412 is a constant current source.

[0084] Capacitor 414 is connected to the input FET 411 and the control FET 412, thereby connecting the positive voltage source 430 to the negative voltage source 450 via capacitor 414 so that when both the input FET 411 and the control FET 412 are turned on, a closed circuit is formed and the capacitor 414 stores charge until the connection is terminated.

[0085] When capacitor 414 is accumulating charge, output FET 415 turns on when its gate-source voltage equals the charge accumulated by capacitor 414. When presynaptic pulse signals 204, 307 go low, the output is activated, and as leakage FET 413 discharges capacitor 414 over time, the drain-source current flowing through output FET 415 decreases accordingly. When both output FET 415 and output control FET 419 are turned on, the drain-source current can flow from positive voltage source 430 to negative voltage source 450, through output FET 415, output control FET 419, and cascode current mirror 416. Output FET 415 may be configured to operate in its subthreshold region such that the drain-source current across output FET 415 decreases exponentially as the charge on capacitor 414 decreases linearly.

[0086] The output stage may employ a cascode current mirror 416 to reduce variations in current replication and improve accuracy. When current flows through the cascode current mirror 416, two voltage signals are generated in proportion to the intensity of this current. In this embodiment, the synaptic input signals 214, 314 generated by the presynaptic integrators 213, 313 thus include two voltage signals. In practice, the current flowing through the cascode current mirror 416 is replicated as two voltage signals. Alternatively, the cascode current mirror 416 may be a normal current mirror that generates a single voltage signal instead, as seen in the embodiment of Figure 4A.

[0087] The output control elements, including inverter 423, output control FET 419, and current control FET 418, are configured to regulate the flow of output current. Arrow 421 indicates the direction of the output current flowing drain-source of output FET 415. However, this current flows only when both output FET 415 and output control FET 419 are turned on. Inverter 423 is connected to input FET 411 such that a positive voltage is generated at its output when the presynaptic input signals 204, 307 are negative, and a negative voltage is generated at the output of inverter 423 when the presynaptic input signals 204, 307 are positive. As a result, output control FET 419 is turned on only when the presynaptic input signal is negative, i.e., when the presynaptic input signal is not spiking. Therefore, output current flowing through FETs 415 and 419 is only possible after a spike in the spatiotemporal spike train has ended. Furthermore, current control FET 418 is turned on only when the presynaptic pulse signals 204, 307 are spiking. As a result, discharge of capacitor 414 due to drain-source current flowing through either FET 418 or 411 is impossible after the spike has subsided, ensuring that the discharge of capacitor 414 is controlled by the leakage FET 413.

[0088] The leak FET 413 is configured to discharge capacitor 414 through its drain-source current (current direction indicated by arrow 422) when it is turned on. When the presynaptic pulse signals 204, 307 go low and the charging circuit is closed, capacitor 414 discharges through the leak FET 413 with a constant current. In some embodiments, the leak FET 413 is controlled by a time constant, which determines the gate-source voltage of the leak FET 413. The time constant is determined by AMPA, NDMA, GABA A or GABA B The time dynamics may be chosen to be realized.

[0089] The mirror FET 417 is coupled to the output FET 415, thereby forming a current mirror between the two, ensuring that the drain-source current flowing through the output FET 415 is identical to the drain-source current flowing through the mirror FET 417. Consequently, the voltage induced by the capacitor in the pre-integration circuit is no longer important to the function of the pre-integration circuit.

[0090] Next, we will perform the weight application circuit according to the present invention.

[0091] The weight application (multiplication) circuits in Figures 2 and 3 are fully distributed, perform typical synaptic functions, connect input and output neurons, and apply stored weights. The linearity of the multiplier should be preserved to avoid degrading learning. The digitally stored weights are converted to the analog domain via a current-type D / A converter based on the R-2R architecture shown in Figures 5A and 5B. The weight application element can apply coefficients ranging from 0 to 1 to its input current, attenuate it, and send a selected portion of the input current to its output.

[0092] Having a small transconductance is advantageous to minimize sensitivity to weighting errors. Since this design is based on current-type D / A conversion, the outputs of multiple weighting elements can be simply added together.

[0093] Figure 5A shows a weight application circuit 500 according to an exemplary embodiment of weight application elements 211 and 311. To avoid confusion in the image, only some elements are numbered, and repeating elements are shown only a limited number of times. The weight application circuit 500 comprises a positive voltage source 520, a negative voltage source 540, a first synaptic input receiver 507, a second synaptic input receiver 508, an output terminal 509, and a ladder of output selection elements 550, each output selection element including a double-resistance FET 503, a single-resistance FET 504, a positive output FET 501, and a negative output FET 502. FETs 505 and 506 may also be connected to the positive voltage source 520.

[0094] The synaptic input receivers 507 and 508 are configured to receive synaptic input signals 214 and 314 in the form of gate-source voltages. Referring to Figure 4A, the synaptic input signals 214 and 314 may be provided by the output current mirror 406. The gate-source voltages applied to the synaptic input receivers 507 and 508 cause current to flow through the rest of the weighted application circuit 500, particularly along the ladder of the output selection element 550 toward the output terminal 509.

[0095] The output selection elements 550 are connected sequentially so that the current flowing through the synaptic input receiver 507 is distributed among the output selection elements 550. Each of the output selection elements 550 includes a single-resistance transistor 504 and a double-resistance transistor 503, which are arranged so that the current from the synaptic input receiver 507 is divided into two for each output selection element 550 it passes through. Thus, the first output selection element 550 receives half of the synaptic input current, the second output selection element 550 receives one-quarter of the synaptic input current, the third output selection element 550 receives one-eighth of the synaptic input current, and so on. The more output selection elements 550 included, the higher the accuracy that can be achieved in weight application.

[0096] Each of the output selection elements 550 includes a positive output FET 501 and a negative output FET 502. The gate-source voltage across these FETs is determined by digitally stored weight values ​​stored in the weight memory element 212. The weight values ​​are stored as bits, and the number of bits is equal to the number of output control elements 550. Each bit of the stored weight value determines the setting of the output control element so that either the positive output FET 501 or the negative output FET 502 is turned on. When the positive output FET 501 is turned on, the portion of the synaptic input current assigned to the corresponding output selection element is connected to the output terminal 509. When the negative output FET 502 is turned on, the selected portion of the synaptic input current does not contribute to the synaptic output current. In this way, weight application based on stored binary weight values ​​is realized.

[0097] Figure 5B shows a weighting application circuit 500 according to another exemplary embodiment of the weighting application elements 211, 311. In this circuit, the synaptic input receivers 507, 508 include two field-effect transistors, each configured to receive synaptic input signals 214, 314 in the form of two gate-source voltages. Referring to Figure 5B, the synaptic input signals 214, 314 may be provided by an output cascode current mirror 416.

[0098] Next, the polarity selection circuit according to the present invention will be described.

[0099] Figure 6 shows a polarity selection circuit 600 according to an exemplary embodiment of the present invention, including polarity selection. The polarity of the outputs of the weighting application elements 211, 311 can be configured to generate inhibitory spikes corresponding to the behavior of GABA receptors. The polarity selection circuit 600 uses a sourcing current mirror 632 that discharges current and a thinking current mirror 642 that absorbs current. The polarity selection circuit further includes a positive voltage source 610, a negative voltage source 620, a polarity output element 603, a first pass-through FET 631, a second pass-through FET 641, a sourcing selection FET 630, a thinking selection FET 640, and a polarity input element 601 configured to receive synaptic output currents 215, 315. The direction of the synaptic output currents 215, 315 is indicated by arrows 604. Depending on whether the voltage applied to the polarity selection terminal 602 is set to high or low, a sourcing current mirror or a thinking current mirror is activated, corresponding to an excitatory synapse or an inhibitory synapse, respectively.

[0100] The polarity input element 601 is configured to receive the synaptic output current as a drain-source current and convert this current into a gate-source voltage. This gate-source voltage is applied to the gate terminal of either the sourcing current mirror 632 or the sourcing current mirror 642.

[0101] The through-FETs 631 and 632 are configured, where applicable, to pass the signal received by the polar input element 601 through the thinking current mirror. When a voltage is applied to the gate of the first through-FET 631, a drain-source current begins to flow. This drain-source current determines the drain-source current flowing through the second through-FET 641, which determines the gate-source voltage of the second through-FET 641. Then, when the thinking selection FET 640 is turned on, this gate-source voltage applied to the through-FET 641 can be applied to the thinking current mirror 642. The gate-source voltage across the second through-FET 641 is identical to the gate-source voltage generated by the polar input element 601.

[0102] When either a high voltage or a low voltage is applied to the polarity selection terminal 602, the sourcing selection FET 630 or the thinking selection FET 640 is turned on.

[0103] When the sourcing select FET 630 is turned on, the drain-source current flowing through the sourcing select FET 630 becomes active. As a result, the gate-source voltage applied to the polarity input element 601 is also applied to the sourcing current mirror 632, turning on the sourcing current mirror 632. When the sourcing current mirror 632 is turned on, current begins to flow from the positive voltage source 610 to the polarity output element 603, and this current is identical to the synaptic output current received by the polarity input element 601.

[0104] When the thinking selection FET 640 is turned on, the drain-source current flowing through the thinking selection FET 640 becomes active. As a result, the gate-source voltage applied to the polar input element 601 is also applied to the thinking current mirror 642, turning it on. When the thinking current mirror 642 is turned on, current begins to flow from the polar output element 603 to the negative voltage source 620. Therefore, a current equal to the inverted synaptic input current received by the polar input element 601 flows through the polar output element 603.

[0105] Through the use of polarity selection circuits, spiking neural networks can be implemented without loss of generality as conductance-based integral firing models, which is one possible implementation of generalized integral firing models.

[0106] Next, we will describe the signal patterns that can potentially be achieved by the present invention.

[0107] The spiking neural network according to the present invention can exhibit a wide range of pattern activity, such as fully synchronous, clustered, or asynchronous states, depending on the excitatory / inhibitory network interaction conditions, heterogeneity in the input pattern, and spatiotemporal dynamics implemented in the presynaptic integrator.

[0108] Figure 7A shows a graph 700 plotting the excitatory synaptic output current (or excitatory postsynaptic current, i.e., synaptic EPSC current) 701 in amperes as a function of time 702 in seconds, where the excitatory synaptic output current 701 is one exemplary embodiment of the synaptic output currents 215, 315.

[0109] Figures 7B and 7C show graphs 710 and 720 plotting the voltage (volts) of spatiotemporal spike trains 711 and 721 as a function of time (seconds) 712 and 722, where the spatiotemporal spike trains are exemplary embodiments of spatiotemporal spike trains 204 and 307. In particular, Figure 7B shows that the accumulation of charge on the membrane of neurons (nodes) leads to spike generation. Figure 7C shows the nonlinear spiking behavior and frequency adaptability.

[0110] The present invention can be implemented on an integrated circuit, particularly on a microcontroller integrated circuit. For example, cores in a core array can form a network-on-chip on a microcontroller integrated circuit. The network-on-chip improves the scalability and power efficiency of the microcontroller integrated circuit. The network-on-chip may be reconfigurable in real time or may be statically defined during the production stage. If the network-on-chip is reconfigurable in real time, the configuration of the cores in the core array and their interconnection structure can be changed. This change can be made, for example, based on changes in the inputs or outputs of the microcontroller integrated circuit, different requirements for classification accuracy or stability, network evolution based on learning rules, and changes in communication protocols.

[0111] This invention provides an implementation of a distributed multi-component hardware structure that enables optimal area and power design of synaptic processing functions. This implementation can increase the number of synaptic structure dimensions by enabling component-wise optimization of individual signal processing characteristics and functions within a spiking neural network.

[0112] The present invention provides an area- and power-efficient implementation of a presynaptic adaptation mechanism that is robust to array heterogeneity, requiring only a single spike integrator (rather than n) per input neuron.

[0113] The present invention provides an implementation of a presynaptic adaptation (presynaptic integration and current generation) mechanism that minimizes the effects of synaptic capacitance fluctuations. Furthermore, the present invention provides an efficient mechanism for converting digitally stored weights into an analog domain by applying a ranged coefficient to its input current and sending a selected portion of the input current to its output.

[0114] Furthermore, the present invention provides an implementation of a mechanism for selecting between excitatory and inhibitory outputs in a synaptic element. This provides an implementation of a synaptic element that can generate complex dynamics that can be extended to specific functions, such as changes in time characteristics, in order to perform time-dependent calculations.

[0115] Two or more of the above embodiments may be combined in any suitable manner.

Claims

1. Multiple presynaptic integrators (209), multiple weight application elements (210), and multiple output neurons (220) A spiking neural network (100) comprising, Each of the plurality of presynaptic integrators (213) is adapted to receive a presynaptic pulse signal (204) that causes charge accumulation in the presynaptic integrator, and to generate the synaptic input signal (214) based on the accumulated charge such that the synaptic input signal has a predetermined time dynamics. A first group of weight-applying elements (211) among the plurality of weight-applying elements (210) is connected to receive the synaptic input signal (214) from the first of the plurality of presynaptic integrators (213), Each weighting element (211) of the first group of weighting elements is adapted to apply a weight value to the synaptic input signal (214) in order to generate a synaptic output current (215), wherein the intensity of the synaptic output current is a function of the applied weight value. A spiking neural network (100) in which each of the plurality of output neurons (222) is connected to receive a synaptic output current (214) from a second group of weight-applying elements among the plurality of weight-applying elements, and to generate a spatiotemporal spike train output signal (223) based on one or more of the received synaptic output currents.

2. Each of the aforementioned weight application elements is A synaptic input receiver configured to receive the synaptic input signal from the presynaptic integrator and generate a synaptic input current based on the synaptic input signal, A weight storage core configured to store the aforementioned weight values, A modification element configured to apply the weight values ​​stored in the weight memory element to the synaptic input current in order to generate the synaptic output current, It includes a weight application circuit, The aforementioned weight values ​​are preferably stored in digital format and converted to the analog domain via a current-type digital-to-analog converter. The current-type digital-to-analog converter is preferably based on an R-2R architecture. The spiking neural network according to claim 1, wherein a current-type digital-to-analog converter preferably applies a predetermined coefficient to attenuate the synaptic input current and generates the synaptic output current based on the attenuated synaptic input current.

3. The spiking neural network according to claim 2, wherein the weight values ​​stored in the weight memory element are adjustable, and preferably the weight values ​​stored in the weight memory element are adjusted based on a learning rule.

4. The spiking neural network according to any one of claims 1 to 3, further comprising a row spike decoder configured to supply the presynaptic pulse signal based on presynaptic input spikes such that the presynaptic pulse signal is assigned to the presynaptic integrator based on the configuration of the spiking neural network.

5. The spiking neural network according to any one of claims 1 to 4, wherein the spiking neural network includes input neurons that generate the presynaptic pulse signals, and the presynaptic integrator multiplexes time spikes originating from different input neurons.

6. The predetermined time dynamics of the synaptic input signal generated by the presynaptic integrator are AMPA, NMDA, GABA Ａ , or GABA Ｂ A spiking neural network according to any one of claims 1 to 5, wherein the time dynamics are as follows.

7. The spiking neural network according to any one of claims 1 to 6, wherein the presynaptic integrator generates a tunable gain independent of a tunable time constant, the time constant determines a leakage current that isolates the accumulated charge within the presynaptic integrator, and characterizes the time dynamics of the synaptic input signal of the presynaptic integrator.

8. The spiking neural network according to any one of claims 1 to 7, wherein the presynaptic integrator can be configured by a control signal, preferably the control signal controls the time shape of the synaptic input signal.

9. The spiking neural network according to any one of claims 1 to 8, wherein the output neurons are controlled by neuronal control signals, such as to control the neuronal dynamics.

10. The spiking neural network comprises a plurality of first groups of weight-applying elements, Each of the weight-applying elements in each first group is connected to receive the same synaptic input signal from each presynaptic integrator. The spiking neural network according to any one of claims 1 to 9, wherein each weight-applying element of the first group is connected to receive a synaptic input signal from one of the plurality of presynaptic integrators.

11. The spiking neural network according to claim 10, wherein the spiking neural network includes a plurality of input neurons, and one of each of the input neurons is connected to provide a presynaptic pulse signal to each of the presynaptic integrators in order to provide a synaptic input signal to each of the first group of weight-applying elements.

12. The spiking neural network according to any one of claims 1 to 11, wherein the spiking neural network comprises a plurality of second groups of weight-applying elements, each second group of weight-applying elements being connected to provide a synaptic output signal to one of the plurality of output neurons.

13. The spiking neural network according to any one of claims 1 to 12, wherein the spiking neural network exhibits various pattern activity in use, including complete synchronization, clustering or asynchronous states, heterogeneity in the input pattern, spatiotemporal dynamics of neurosynaptic elements, nonlinear spiking behavior and / or frequency adaptability.

14. A presynaptic integrator circuit configured to generate synaptic input currents for input to multiple weight-applying elements, An input element configured to receive a presynaptic pulse signal, preferably a presynaptic pulse voltage, wherein the presynaptic pulse signal is a spatiotemporal spike train, A capacitor configured to accumulate charge in response to the presynaptic pulse signal, A leakage element configured to discharge at least a portion of the charge accumulated by the capacitor, An output element configured to generate the synaptic input signal based on the charge accumulated by the capacitor, in order to supply the plurality of weight-applying elements, A presynaptic integrating circuit equipped with this circuit.

15. The system further comprises a control element adapted to control the time dynamics of the synaptic input signal, wherein the control element Receive control signals, preferably control voltages. Based on the aforementioned control signal, the accumulation of charge by the capacitor is adjusted. By controlling the maximum charge on the capacitor, the maximum amplitude of the synaptic input signal is adjusted. The presynaptic integrator circuit according to claim 14, configured as described above.

16. A presynaptic integrator circuit configured to generate a synaptic input signal for subsequent weight application, An input element configured to receive a presynaptic pulse signal, preferably a presynaptic pulse voltage, wherein the presynaptic pulse signal is a spatiotemporal spike train. A capacitor configured to accumulate charge based on the spikes in the aforementioned spatiotemporal spike train, A leakage element configured to discharge at least a portion of the charge accumulated by the capacitor, An output element configured to generate the synaptic input signal based on the charge accumulated by the capacitor, An output control element configured to control the generation of the synaptic input signal, which is performed by the output element based on the presynaptic pulse signal, such that the generation of the synaptic input signal is controlled by the spatiotemporal spike train, preferably an output control element in which the synaptic input signal is not generated during the spikes of the spatiotemporal spike train. Receive control signals, preferably control voltages. The amount of charge accumulated by the capacitor is adjusted so that it does not depend on the duration of the spikes in the spatiotemporal spike train and the capacitance value of the capacitor, preferably on the manufacturing variations of the capacitor. By controlling the maximum charge on the capacitor, the time shape and maximum amplitude of the synaptic input signal are adjusted. A control element configured as follows: A presynaptic integrating circuit equipped with this circuit.

17. The presynaptic integrator circuit according to claim 16, wherein the output control element comprises a field-effect transistor and an inverter, the inverter is configured to apply a gate-source voltage to the field-effect transistor of the output control element based on the presynaptic input signal, preferably the gate-source voltage is applied when the presynaptic input signal is not spiking, and the synaptic input signal is generated by the drain-source current flowing through the field-effect transistor of the output control element.

18. The leakage element is controlled by a time constant, preferably the time constant is AMPA, NMDA, GABA Ａ Or GABA Ｂ A presynaptic integrating circuit according to any one of claims 14 to 17, which characterizes the time dynamics of the circuit.

19. The presynaptic integrator circuit according to claim 18, wherein the leakage element comprises a field-effect transistor, the time constant is the gate-source voltage of the field-effect transistor of the leakage element, and the capacitor is discharged by the drain-source current of the field-effect transistor of the leakage element.

20. The presynaptic integrator circuit according to any one of claims 14 to 19, wherein the input element comprises a field-effect transistor, the presynaptic pulse signal is the gate-source voltage of the field-effect transistor of the input element, and the drain-source current flowing through the field-effect transistor of the input element charges the capacitor.

21. The presynaptic integrator circuit according to any one of claims 14 to 20, wherein the output element comprises a field-effect transistor, the charge accumulated by the capacitor generates the gate-source voltage of the field-effect transistor of the output element, and the drain-source current flowing through the field-effect transistor of the output element generates the synaptic input signal.

22. The presynaptic integrator circuit according to any one of claims 14 to 20, wherein the control element comprises a field-effect transistor, the control signal is the gate-source voltage of the field-effect transistor of the control element, and the capacitor is charged by the drain-source current flowing through the field-effect transistor of the control element.

23. The output element is an output current mirror configured to generate the synaptic input signal in the voltage domain, or An output cascode current mirror configured to generate the synaptic input signal in the aforementioned voltage domain, wherein the resulting synaptic input signal includes two voltage signals. A presynaptic integrator according to any one of claims 14 to 22, further comprising:

24. The presynaptic integrator circuit according to any one of claims 14 to 23, wherein the synaptic input signal decreases exponentially when the capacitor is discharged.

25. A polarity selection circuit configured to duplicate or invert synaptic output current, A polar input element configured to receive the aforementioned synaptic output current, A polarity selection terminal configured to select a sourcing or thinking current mirror based on a polarity input signal, The sourcing current mirror is configured to replicate the synaptic output current, The thinking current mirror includes a polarity selection terminal configured to reverse the synaptic output current, A polar output element that generates a polar output current based on the replicated or inverted synaptic output current, A polarity selection circuit equipped with this.

26. Each of the weight-applying elements further comprises a polarity-selecting element, the polarity-selecting element comprising the polarity-selecting circuit described in claim 26, thereby using the synaptic output signals from any one of claims 1 to 13 by the polarity-selecting circuit to generate the polarity output current, preferably the input neuron receiving the polarity output current, the replicated synaptic output current corresponding to an excitatory synaptic output signal, and the inverted synaptic output current corresponding to an inhibitory synaptic output signal, in the spiking neural network according to any one of claims 1 to 13.

27. The spiking neural network according to claim 26, wherein the presynaptic integrator comprises a presynaptic integration circuit according to any one of claims 14 to 24.

28. A method for presynaptic integration and weight application for a spiking neural network, wherein the spiking neural network comprises a plurality of presynaptic integrators (209), a plurality of weight application elements (210), and a plurality of output neurons (220), and the method is Each of the plurality of presynaptic integrators (213) receives a presynaptic pulse signal (204) that causes charge accumulation in the presynaptic integrator, Each of the plurality of presynaptic integrators (213) generates the synaptic input signal (214) based on the accumulated charge such that the synaptic input signal has a predetermined time dynamic, The first group of weight-applying elements (211) among the plurality of weight-applying elements (210) receives the synaptic input signal (214) from the first of the plurality of presynaptic integrators (213), To generate a synaptic output current (215), a weight value is applied to the synaptic input signal (214) by each weight application element (211) of the first group of weight application elements, wherein the intensity of the synaptic output current is a function of the applied weight value. Each of the plurality of output neurons (222) receives a synaptic output current (214) from a second group of weight-applying elements among the plurality of weight-applying elements, and generates a spatiotemporal spike train output signal (223) based on one or more of the received synaptic output currents. A method for presynaptic integration and weight application, including the following.

29. Each of the aforementioned weight application elements is The presynaptic integrator receives the synaptic input signal and generates a synaptic input current based on the synaptic input signal. The aforementioned weight values ​​are stored, The stored weight values ​​are applied to the synaptic input current to generate the synaptic output current. The method of presynaptic integration and weight application according to claim 28, comprising a weight application circuit adapted for the purpose.

30. The method for presynaptic integration and weighting according to claim 28 or 29, wherein the presynaptic integrator generates an adjustable gain independent of an adjustable time constant, the time constant determines a leakage current that isolates the accumulated charge within the presynaptic integrator, and characterizes the time dynamics of the synaptic input signal of the presynaptic integrator.

31. The spiking neural network comprises a plurality of first groups of weight-applying elements, Each of the weight-applying elements in each first group is connected to receive the same synaptic input signal from each presynaptic integrator. The method of presynaptic integration and weighting according to any one of claims 28 to 30, wherein each weighting element of the first group is connected to receive a synaptic input signal from one of the plurality of presynaptic integrators.

32. The method of presynaptic integration and weight application according to claim 31, wherein the spiking neural network includes a plurality of input neurons, and one of each of the input neurons is connected to provide a presynaptic pulse signal to one of the presynaptic integrators in order to provide a synaptic input signal to a first group of weight application elements.

33. A method for presynaptic integration for spiking neural networks, To provide a presynaptic integral circuit configured to generate synaptic input currents for input to multiple weight-applying elements, The receiving of a presynaptic pulse signal, preferably a presynaptic pulse voltage, and preferably the presynaptic pulse signal being a spatiotemporal spike train, Accumulating charge in response to the aforementioned presynaptic pulse signal, Discharging at least a portion of the accumulated charge through a leakage element, To supply the aforementioned multiple weight-applying elements, synaptic input signals are generated based on the accumulated charge. Methods that include...

34. A method for presynaptic integration for spiking neural networks, To provide a presynaptic integrator circuit configured to generate a synaptic input signal for subsequent weight application, Receiving a presynaptic pulse signal, preferably a presynaptic pulse voltage, wherein the presynaptic pulse signal is a spatiotemporal spike train. Accumulation of charge by a capacitor based on the spikes in the aforementioned spatiotemporal spike train, Discharging at least a portion of the charge accumulated by the capacitor through a leakage element, The synaptic input signal is generated based on the charge accumulated by the capacitor, Controlling the generation of the synaptic input signal, which is performed by the output element based on the presynaptic pulse signal, so that the generation of the synaptic input signal is controlled by the spatiotemporal spike train, preferably controlling the generation so that the synaptic input signal is not generated during the spikes of the spatiotemporal spike train. Receive control signals, preferably control voltages. The amount of charge accumulated by the capacitor is adjusted so that it does not depend on the duration of the spikes in the spatiotemporal spike train and the capacitance value of the capacitor, preferably on the manufacturing variations of the capacitor. The time shape and maximum amplitude of the synaptic input signal are adjusted by controlling the maximum charge on the capacitor. To provide a control element configured in such a way as Methods that include...

35. To provide a polarity selection circuit configured to duplicate or invert synaptic output current, Receiving the aforementioned synaptic output current, Selecting a sourcing or thinking current mirror based on the polarity input signal, Replicating the synaptic output current and / or inverting the synaptic output current, To generate a polar output current based on the replicated or inverted synaptic output current. A method for polarity selection, including the following.

36. A method for classifying an input signal using a spiking neural network according to any one of claims 1 to 13 or 26 to 27.

Images