Nitride semiconductor device and method for manufacturing a nitride semiconductor device

Abstract

To reduce gate leakage current in nitride semiconductor devices. [Solution] The nitride semiconductor device 10 includes a substrate 40, a buffer layer 42, a mask portion 45, and a nitride semiconductor layer 46. The nitride semiconductor layer 46 includes an electron transport layer 48 and an electron supply layer 50 located on the electron transport layer 48 and having a larger band gap than the electron transport layer 48. The buffer layer 42 is located on the substrate 40. The mask portion 45 is selectively provided on the buffer layer 42. It includes a gate structure 30 located on the nitride semiconductor layer 46. The nitride semiconductor layer 46 includes a high dislocation density region 54 located on the buffer layer 42 and a low dislocation density region 56 located on the mask portion 45 and having a lower dislocation density than the high dislocation density region 54. The gate structure 30 is located on the low dislocation density region 56.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices and methods for manufacturing nitride semiconductor devices. [Background technology]

[0002] Currently, the commercialization of high-electron-mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing. HEMTs use a two-dimensional electron gas (2DEG) generated near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices utilizing HEMTs are recognized as devices that enable high voltage resistance and high-frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a substrate, a buffer layer located on the substrate, an electron transport layer located on the buffer layer, and an electron supply layer located on the electron transport layer. In the electron transport layer, 2DEG occurs near the interface of the heterojunction between the electron transport layer and the electron supply layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-10193

[0005] [overview] In nitride semiconductor devices, layers made of nitride semiconductors (e.g., buffer layers, electron transport layers, electron supply layers) are provided on a substrate made of a different material from the nitride semiconductor. Due to mismatches in lattice constants between the substrate material and the nitride semiconductor, lattice defects, or dislocations, may occur in the nitride semiconductor. Dislocations can cause an increase in leakage current in nitride semiconductor devices.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a buffer layer located on the substrate, a mask portion selectively provided on the buffer layer, and a nitride semiconductor layer. The nitride semiconductor layer includes an electron transport layer and an electron supply layer located on the electron transport layer and having a larger band gap than the electron transport layer. The nitride semiconductor device includes a source electrode and a drain electrode located on the nitride semiconductor layer and extending in a first direction in a plan view, and a gate structure located on the nitride semiconductor layer and positioned between the source electrode and the drain electrode in a second direction intersecting the first direction in a plan view. The nitride semiconductor layer includes a high dislocation density region located on the buffer layer and a low dislocation density region located on the mask portion and having a lower dislocation density than the high dislocation density region. The gate structure is located on the low dislocation density region. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic plan view showing an exemplary planar layout of a nitride semiconductor device. [Figure 2] Figure 2 is a schematic plan view, enlarged, of the area enclosed by the dashed line in Figure 1. [Figure 3] Figure 3 is a schematic cross-sectional view of a nitride semiconductor device cut along the line F3-F3 in Figure 2. [Figure 4] Figure 4 is a schematic plan view showing the planar layout of the mask layer in Figure 3. [Figure 5] Figure 5 is a schematic cross-sectional view showing an enlarged portion of Figure 3. [Figure 6] Figure 6 is a schematic cross-sectional view of the nitride semiconductor device cut along the F6-F6 line in Figure 2. [Figure 7] Figure 7 is a schematic cross-sectional view of the nitride semiconductor device cut along the line F7-F7 in Figure 2. [Figure 8] Figure 8 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device shown in Figure 3. [Figure 9] Figure 9 is a schematic cross-sectional view showing the manufacturing process following Figure 8. [Figure 10]FIG. 10 is a schematic cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing process following FIG. 16. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a modified example of a nitride semiconductor device.

[0008] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Also, for ease of understanding, in the cross-sectional views, the hatching lines may be omitted. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0009] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0010] In this disclosure, the term "plan view" refers to viewing the nitride semiconductor device in the Z direction of the mutually orthogonal XYZ axes shown in Figure 1. For convenience of explanation, the direction along the Z axis is referred to as the "Z direction," the direction along the X axis is referred to as the "X direction," and the direction along the Y axis is referred to as the "Y direction." In this disclosure, the X direction corresponds to the "first direction," and the Y direction corresponds to the "second direction."

[0011] <Embodiment> A nitride semiconductor device 10 according to one embodiment of the present disclosure will be described with reference to Figures 1 to 7. Figure 1 is a schematic plan view showing an exemplary plan layout of the nitride semiconductor device 10. Figure 2 is a schematic plan view enlarged from the portion enclosed by the dashed line in Figure 1. Figure 3 is a schematic cross-sectional view of the nitride semiconductor device cut along the line F3-F3 in Figure 2. Figure 4 is a schematic plan view showing the plan layout of the mask layer 44, which will be described later. Figure 5 is a schematic cross-sectional view showing an enlarged portion of Figure 3. Figure 6 is a schematic cross-sectional view of the nitride semiconductor device cut along the line F6-F6 in Figure 2. Figure 7 is a schematic cross-sectional view of the nitride semiconductor device cut along the line F7-F7 in Figure 2. For ease of understanding of the drawings, the insulating layer 22, which will be described later, is omitted in Figures 1 and 2. Also, in Figure 4, components located above the mask layer 44 are omitted or shown with dashed lines.

[0012] (Description of planar layout of nitride semiconductor device) As shown in Figure 1, the nitride semiconductor device 10 includes a plurality of active regions 12 and boundary regions 14. The plurality of active regions 12 are separated by boundary regions 14. The active regions 12 are the regions where the nitride semiconductor layer 46, which will be described later, is located.

[0013] In this embodiment, multiple active regions 12 are arranged in a matrix along the X and Y directions. In this embodiment, each active region 12 is approximately square in shape when viewed from above.

[0014] The boundary region 14 may include a plurality of first boundary regions 14X extending along the X direction and a plurality of second boundary regions 14Y extending along the Y direction. Two adjacent active regions 12 in the Y direction are separated by one of the plurality of first boundary regions 14X. Each of the plurality of active regions 12 is located between two first boundary regions 14X. Two adjacent active regions 12 in the X direction are separated by one of the plurality of second boundary regions 14Y. Each of the plurality of active regions 12 is located between two second boundary regions 14Y.

[0015] The boundary regions 14 are arranged in a grid pattern along the X and Y directions. More specifically, multiple first boundary regions 14X and multiple second boundary regions 14Y are arranged in a grid pattern. One active region 12 is placed in each of the multiple regions surrounded by the grid-like boundary regions 14.

[0016] The shape, number, and arrangement of the active regions 12 can be arbitrarily changed. Each active region 12 may be rectangular in shape with the X or Y direction as its longitudinal direction in a plan view, or it may be circular, etc. Part or all of the outer perimeter of each active region 12 may be curved. It can also be said that part or all of each boundary region 14 may be curved. The active regions 12 may be arranged along only one of the X or Y directions. There may also be only one active region 12. The shape, number, and arrangement of the boundary regions 14 may be changed according to the shape, number, and arrangement of the active regions 12.

[0017] The nitride semiconductor device 10 includes a plurality of gate wirings 16, a plurality of source wirings 18, and a plurality of drain wirings 20. In this embodiment, each gate wiring 16, each source wiring 18, and each drain wiring 20 extends along the Y direction in a plan view.

[0018] Each gate wire 16 is spaced apart in the X direction from other gate wires 16, multiple source wires 18, and multiple drain wires 20. Each source wire 18 is spaced apart in the X direction from other source wires 18, multiple gate wires 16, and multiple drain wires 20. Each drain wire 20 is spaced apart in the X direction from other drain wires 20, multiple gate wires 16, and multiple source wires 18.

[0019] In this embodiment, the multiple gate wires 16 and the multiple source wires 18 are arranged alternately in the X direction. One of the multiple drain wires 20 is located in each region between the gate wires 16 and the source wires 18.

[0020] At least two of the gate wirings 16, source wirings 18, and drain wirings 20 may be arranged to overlap with a second boundary region 14Y extending along the Y direction in a plan view. In the illustrated example, each gate wiring 16 is arranged to overlap with one of the multiple second boundary regions 14Y in a plan view. Each source wiring 18 is arranged to overlap with one of the multiple second boundary regions 14Y in a plan view. More specifically, each gate wiring 16 and each source wiring 18 overlap with a different second boundary region 14Y in a plan view. The second boundary region 14Y overlapping with the gate wiring 16 and the second boundary region 14Y overlapping with the source wiring 18 are arranged alternately in the X direction.

[0021] Each active region 12 may overlap with one of the gate lines 16, one of the source lines 18, and one of the drain lines 20 in a plan view. In the illustrated example, the central portion of each active region 12 in the X direction overlaps with one of the drain lines 20 in a plan view. The two ends of each active region 12 in the X direction overlap with one of the gate lines 16 and one of the source lines 18, respectively, in a plan view.

[0022] At least two of the gate wirings 16, source wirings 18, and drain wirings 20 may be arranged in a plan view to overlap with two adjacent active regions 12 in the X direction. In the illustrated example, each gate wiring 16 is arranged in a plan view to overlap with two adjacent active regions 12 in the X direction. More specifically, the gate wiring 16 is arranged in a plan view to overlap with the gate structures 30 of two adjacent active regions 12 in the X direction, which will be described later. Each source wiring 18 is arranged in a plan view to overlap with two adjacent active regions 12 in the X direction. More specifically, the source wiring 18 is arranged in a plan view to overlap with the source electrodes 32 of two adjacent active regions 12 in the X direction, which will be described later.

[0023] The multiple gate wires 16, multiple source wires 18, and multiple drain wires 20 may be made of any metallic material. For example, the gate wires 16, source wires 18, and drain wires 20 may contain at least one of aluminum (Al), copper (Cu), and AlCu.

[0024] The nitride semiconductor device 10 includes an insulating layer 22 (see Figure 3) located beneath a plurality of gate wirings 16, a plurality of source wirings 18, and a plurality of drain wirings 20. The insulating layer 22 may contain at least one of the following: silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), and aluminum oxynitride (AlON).

[0025] As shown in Figure 2, the nitride semiconductor device 10 may include a plurality of gate vias 24, a plurality of source vias 26, and a plurality of drain vias 28 that penetrate the insulating layer 22 (see Figure 3). Each gate via 24 is located beneath and connected to each gate wiring 16. Each source via 26 is located beneath and connected to each source wiring 18. The plurality of drain vias 28 are located beneath and connected to each drain wiring 20. Each gate via 24, each source via 26, and each drain via 28 may be made of any metallic material. Each gate via 24, each source via 26, and each drain via 28 may be made of at least one of tungsten (W), Al, Cu, and AlCu, for example.

[0026] The nitride semiconductor device 10 includes a plurality of gate structures 30, a plurality of source electrodes 32, and a plurality of drain electrodes 33. In this embodiment, each gate structure 30 includes a gate layer 34 and a gate electrode 39. Each gate electrode 39 is located on each gate layer 34. Each source electrode 32 and each drain electrode 33 extends in the X direction in a plan view. Each gate structure 30 surrounds each source electrode 32 in a plan view.

[0027] As shown in Figure 3, the insulating layer 22 is located on the gate structure 30, the source electrode 32, and the drain electrode 33. The insulating layer 22 can be said to be located between the gate structure 30, the source electrode 32, and the drain electrode 33 and the gate wiring 16, the source wiring 18, and the drain wiring 20.

[0028] As shown in Figure 2, the gate electrode 39 is electrically connected to the gate wiring 16 located on the insulating layer 22 via one or more gate vias 24 that penetrate the insulating layer 22. The source electrode 32 is electrically connected to the source wiring 18 located on the insulating layer 22 via one or more source vias 26 that penetrate the insulating layer 22. The drain electrode 33 is electrically connected to the drain wiring 20 located on the insulating layer 22 via one or more drain vias 28 that penetrate the insulating layer 22.

[0029] In this embodiment, for the sake of clarity, we will describe in detail two drain electrodes 33 and one gate structure 30 and one source electrode 32 located between them, as well as the components surrounding the multiple gate structures 30, multiple source electrodes 32, and multiple drain electrodes 33.

[0030] As shown in Figure 2, the gate structure 30 includes a first main portion 30A1 and a second main portion 30A2 extending in the X direction between the source electrode 32 and the drain electrode 33. The first main portion 30A1 and the second main portion 30A2 are located on both sides of the source electrode 32 in the Y direction. The gate structure 30 also includes a first connecting portion 30B1 and a second connecting portion 30B2 that extend in the Y direction and connect the first main portion 30A1 and the second main portion 30A2. The first connecting portion 30B1 connects one end of the first main portion 30A1 and the second main portion 30A2 in the X direction to each other. The second connecting portion 30B2 connects the other end of the first main portion 30A1 and the second main portion 30A2 in the X direction to each other.

[0031] The source electrode 32 is located between the first main portion 30A1 and the second main portion 30A2. In a plan view, the source electrode 32 is surrounded by the first main portion 30A1, the second main portion 30A2, the first connecting portion 30B1, and the second connecting portion 30B2.

[0032] The drain electrode 33 includes a first drain electrode 33A and a second drain electrode 33B located on the opposite side of the source electrode 32 from the first drain electrode 33A. The first drain electrode 33A is located on the opposite side of the source electrode 32 from the first main part 30A1 of the gate structure 30. In other words, the first main part 30A1 of the gate structure 30 is located between the first drain electrode 33A and the source electrode 32. The second drain electrode 33B is located on the opposite side of the source electrode 32 from the second main part 30A2 of the gate structure 30. In other words, the second main part 30A2 of the gate structure 30 is located between the second drain electrode 33B and the source electrode 32.

[0033] (Description of the cross-sectional structure of nitride semiconductor devices) The schematic cross-sectional structure of the nitride semiconductor device will be explained with reference to Figures 3 to 7. As shown in Figure 3, the nitride semiconductor device 10 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a substrate 40, a buffer layer 42 located on the substrate 40, and a nitride semiconductor layer 46 located on the buffer layer 42. The nitride semiconductor layer 46 includes an electron transport layer 48 and an electron supply layer 50 located on the electron transport layer 48.

[0034] (Description of the substrate and buffer layer) The substrate 40 may be made of silicon (Si), silicon carbide (SiC), sapphire, or other substrate materials. In one example, the substrate 40 is a Si substrate. The thickness of the substrate 40 can be, for example, 200 μm or more and 1500 μm or less.

[0035] In this disclosure, unless otherwise specified, the term "thickness direction" refers to the thickness direction of the substrate 40. In the example in Figure 3, the thickness direction coincides with the Z direction. In other words, the Z direction coincides with the thickness direction of the substrate 40.

[0036] The buffer layer 42 includes a buffer lower surface 42G in contact with the substrate 40 and a buffer upper surface 42F on the opposite side of the buffer lower surface 42G. The buffer layer 42 may include one or more nitride semiconductor layers. The buffer layer 42 may include layers made of a material that can reduce warping and cracking of the nitride semiconductor device 10 caused by the difference in thermal expansion coefficients between the substrate 40 and layers located on the buffer layer 42 (e.g., electron transport layer 48). The buffer layer 42 may include, for example, at least one of GaN layers, AlN layers, AlGaN layers, and graded AlGaN layers having different Al compositions. For example, the buffer layer 42 may include a single GaN layer, a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0037] In this embodiment, the buffer layer 42 includes a first buffer layer 42A provided on the substrate 40, a second buffer layer 42B provided on the first buffer layer 42A, and a third buffer layer 42C provided on the second buffer layer 42B.

[0038] The first buffer layer 42A may be, for example, an AlN layer having a thickness of 100 nm to 300 nm. The lower surface of the first buffer layer 42A constitutes the buffer lower surface 42G. The second buffer layer 42B may contain a plurality of AlGaN layers with different compositions, each having a thickness of 100 nm to 300 nm. The third buffer layer 42C may be a layer made of the same material as the electron transport layer 48 located on the buffer layer 42. In this embodiment, the third buffer layer 42C is a GaN layer. The upper surface of the third buffer layer 42C constitutes the buffer upper surface 42F.

[0039] Furthermore, in order to reduce the leakage current in the buffer layer 42, an impurity may be introduced into a part of the buffer layer 42 to make it semi-insulating. In that case, the impurity may be, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4 × 10⁻⁶. 16 cm -3This can be done.

[0040] (Explanation of the mask layer) The mask layer 44 will be described with reference to Figures 3 and 4. Figure 4 is a schematic plan view showing the planar layout of the mask layer 44. To facilitate understanding of the drawing, the nitride semiconductor layer 46, insulating layer 22, gate wiring 16, source wiring 18, and drain wiring 20 are omitted in Figure 4. The gate structure 30, source electrode 32, and drain electrode 33 are shown with dashed lines. The mask layer 44 is also given dot hatching.

[0041] As shown in Figure 4, the nitride semiconductor device 10 includes a mask layer 44 selectively provided on a buffer layer 42. The mask layer 44 includes a plurality of boundary masks 44Y and a plurality of main masks 44X. The plurality of boundary masks 44Y extend in the Y direction and are spaced apart from each other in the X direction. The plurality of main masks 44X extend in the X direction and are spaced apart from each other in the Y direction. Each main mask 44X extends in the X direction to connect the plurality of boundary masks 44Y. The plurality of boundary masks 44Y and the plurality of main masks 44X are configured integrally. The plurality of boundary masks 44Y and the plurality of main masks 44X may be configured separately.

[0042] As shown in Figure 3, the mask layer 44 includes a mask lower surface 44G that is in contact with the buffer upper surface 42F, a mask upper surface 44F on the opposite side of the mask lower surface 44G, and a mask side surface 44H that connects the mask lower surface 44G and the mask upper surface 44F. The buffer upper surface 42F includes a covering portion 42F1 on which the mask layer 44 is provided, and an exposed portion 42F2 exposed from the mask layer 44. Note that the mask layer 44 shown in Figure 3 is the main mask 44X.

[0043] As shown in Figure 4, each main mask 44X is rectangular in shape, with the X direction as the longitudinal direction and the Y direction as the transverse direction. Each main mask 44X has a dimension D2 in the Y direction. The dimension D2 of each main mask 44X in the Y direction is equal to the dimension in the Y direction of the covering portion 42F1 of the buffer upper surface 42F. The distance D3 in the Y direction between the main masks 44X is greater than the dimension D2 in the Y direction of each main mask 44X. In this disclosure, the main mask 44X may be referred to as the mask portion 45.

[0044] Each boundary mask 44Y has a constant dimension D1 in the X direction and is a strip extending in the Y direction. Each boundary mask 44Y is located in each boundary region 14. More specifically, each boundary mask 44Y is located in each second boundary region 14Y.

[0045] The nitride semiconductor device 10 includes a window portion 52 surrounded on all sides by two boundary masks 44Y and two main masks 44X. The window portion 52 exposes the exposed portion 42F2 of the buffer upper surface 42F from the mask layer 44. The presence of the window portion 52 means that the mask layer 44 is selectively provided on the buffer layer 42.

[0046] In this embodiment, the window portion 52 is rectangular in shape, with the X direction as the longitudinal direction and the Y direction as the transverse direction. The X-direction dimension of the window portion 52 is equal to the X-direction dimension of the main mask 44X. The Y-direction dimension of the window portion 52 is equal to the Y-direction distance D3 between the main masks 44X. The Y-direction dimension of the window portion 52 is equal to the Y-direction dimension of the exposed portion 42F2 of the buffer upper surface 42F. The window portion 52 is located on both sides of the main mask 44X in the X direction. In other words, the main mask 44X and the window portion 52 are arranged alternately in the Y direction. It can also be said that the main mask 44X is selectively provided on the buffer layer 42.

[0047] The thickness of the mask layer 44 may be, for example, about 100 nm. The Y-direction dimension D2 of each main mask 44X may be, for example, 3 μm or more and 8 μm or less. The Y-direction dimension D2 of each main mask 44X may be smaller than the Y-direction distance D3 between multiple main masks 44X. In other words, the Y-direction dimension D2 of each main mask 44X may be smaller than the Y-direction dimension of the window portion 52. The Y-direction dimension of each window portion 52 may be, for example, 5 μm or more. The X-direction dimension D1 of each boundary mask 44Y may be, for example, 5 μm or more and 20 μm or less.

[0048] The mask layer 44 is made of a material capable of suppressing the epitaxial growth of nitride semiconductors on the mask layer 44. The mask layer 44 may be made of the same material as the insulating layer 22. The mask layer 44 may be made of a material that is relatively easy to etch in order to selectively provide the mask layer 44 on the buffer layer 42. For example, the mask layer 44 may contain at least one of SiO2 and SiN.

[0049] (Explanation of nitride semiconductor layer) As shown in Figure 3, the nitride semiconductor layer 46 is located on the buffer layer 42. More specifically, the electron transport layer 48 of the nitride semiconductor layer 46 is located on the buffer layer 42. The electron transport layer 48 includes a first lower surface 46G1 that is in contact with the buffer layer 42 and a second lower surface 46G2 that is in contact with the mask layer 44. The first lower surface 46G1 is in contact with the buffer upper surface 42F of the buffer layer 42. More specifically, the first lower surface 46G1 is in contact with the exposed portion 42F2 of the buffer upper surface 42F. The second lower surface 46G2 is in contact with the mask upper surface 44F of the main mask 44X. The main mask 44X is located between the second lower surface 46G2 and the buffer upper surface 42F. More specifically, the main mask 44X is located between the second lower surface 46G2 and the covering portion 42F1 of the buffer upper surface 42F. The second lower surface 46G2 can be said to be separated in the Z direction from the buffer upper surface 42F by the main mask 44X.

[0050] The electron transport layer 48 is composed of a nitride semiconductor. The electron transport layer 48 may be, for example, a GaN layer. The thickness of the electron transport layer 48 can be, for example, 10 μm or less. The thickness of the electron transport layer 48 can be 0.5 μm or more and 5 μm or less. The electron transport layer 48 may include one or more nitride semiconductors. The dimension D2 of the mask portion 45 in the Y direction may be larger than the thickness of the electron transport layer 48.

[0051] The electron supply layer 50 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 48. The electron supply layer 50 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 50 which is an AlGaN layer has a larger bandgap than the electron transport layer 48 which is a GaN layer. In one example, the electron supply layer 50 is x Ga 1-x composed of N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 50 can be, for example, 5 nm or more and 20 nm or less.

[0052] The electron transport layer 48 and the electron supply layer 50 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transport layer 48 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 50 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 48 and the electron supply layer 50 and the piezo-polarization caused by the compressive stress received by the hetero-junction portion of the electron transport layer 48, the energy level of the conduction band of the electron transport layer 48 near the hetero-junction interface between the electron transport layer 48 and the electron supply layer 50 becomes lower than the Fermi level. As a result, 2DEG occurs in the electron transport layer 48 at a position close to the hetero-junction interface between the electron transport layer 48 and the electron supply layer 50 (for example, at a distance of about several nm from the interface).

[0053] The electron transport layer 48 and the electron supply layer 50 are made of a material having a hexagonal crystal structure. The electron transport layer 48 and the electron supply layer 50 are made of, for example, a nitride semiconductor having a wurtzite crystal structure. In nitride semiconductors having a wurtzite crystal structure, spontaneous polarization occurs in the c-axis direction due to the arrangement of heterogeneous atoms such as gallium (Ga) atoms and nitrogen (N) atoms. Therefore, nitride semiconductors having a wurtzite crystal structure have a crystal orientation of polar planes in which polarization occurs in the perpendicular direction and a crystal orientation of non-polar planes in which polarization does not occur in the perpendicular direction.

[0054] The polar plane is the c-plane, and the non-polar planes are the m-plane and the a-plane. In the wurtzite crystal structure, the c-plane is the (0001) plane. In the wurtzite crystal structure, the m-plane is the (10-10) plane and other planes equivalent to the (10-10) plane. In the wurtzite crystal structure, the a-plane is the (-2110) plane and other planes equivalent to the (-2110) plane.

[0055] In this disclosure, Miller indices are notated as follows: () indicates each crystal plane. {} indicates a collective term for equivalent crystal planes. [] indicates each crystal axis direction. <> indicates a collective term for equivalent crystal axis directions. For example, the notation [hkil] direction indicates the crystal axis direction perpendicular to the (hkil) plane. <hkil>The notation "direction" indicates the crystal axis direction equivalent to the [hkil] direction. Furthermore, the Miller indices (hkil) of a hexagonal crystal have the relationship h+k=-i. Therefore, (hkil) is sometimes written with three digits as (hkl). Also, the a-axis direction indicates the direction perpendicular to the a-plane. The m-axis direction indicates the direction perpendicular to the m-plane. The c-axis direction indicates the direction perpendicular to the c-plane.

[0056] In this embodiment, the <1-100> direction, which is the m-axis direction of the electron transport layer 48, coincides with the X direction. It can also be said that the <1-100> direction of the electron transport layer 48 coincides with the longitudinal direction of the main mask 44X. It can also be said that the <1-100> direction of the electron transport layer 48 coincides with the direction in which the source electrode 32 and drain electrode 33 extend in a plan view.

[0057] The a-axis direction of the electron transport layer 48, the <11-20> direction, coincides with the Y direction. The <11-20> direction of the electron transport layer 48 can also be said to coincide with the short-side direction of the main mask 44X. The <11-20> direction of the electron transport layer 48 can also be said to coincide with the direction in which the main mask 44X and the window portions 52 are alternately arranged.

[0058] This is the c-axis direction of the electron transport layer 48. <0001> The direction coincides with the Z-direction. It is the c-axis direction of the electron transport layer 48. <0001> The direction is consistent with the stacking direction of the substrate 40, buffer layer 42, and nitride semiconductor layer 46.

[0059] In the nitride semiconductor device 10, buffer layers 42 (e.g., AlN layer, AlGaN layer, GaN layer, etc.) and nitride semiconductor layers 46 (e.g., AlGaN layer, GaN layer, etc.) are sequentially stacked on a substrate 40, having been epitaxially grown. If the crystal structure, lattice constant, and thermal expansion coefficient differ between the substrate 40 and the layers epitaxially grown on the substrate 40, dislocations, which are linear lattice defects, may occur due to these differences. Although dislocations are classified into edge dislocations, helical dislocations, and mixed dislocations, in this disclosure, they are not distinguished and are treated simply as "dislocations."

[0060] As shown in FIG. 5, the nitride semiconductor layer 46 includes a high dislocation density region 54 and a low dislocation density region 56. In the illustrated example, among the nitride semiconductor layer 46, the portion with dot hatching is the high dislocation density region 54. Also, among the nitride semiconductor layer 46, the portion without dot hatching is the low dislocation density region 56. The low dislocation density region 56 has a lower dislocation density than the high dislocation density region 54.

[0061] The dislocation density of the low dislocation density region 56 may be, for example, 1×10 5 cm -2 or less. The dislocation density of the low dislocation density region 56 may be, for example, 1×10 4 cm -2 or less. Also, the dislocation density of the high dislocation density region 54 may be, for example, 1×10 9 cm -2 or more. The dislocation density of the low dislocation density region 56 may be, for example, 1 / 10000 or less of the dislocation density of the high dislocation density region 54. The dislocation density of the low dislocation density region 56 may be, for example, 1 / 100000 or less of the dislocation density of the high dislocation density region 54. The dislocation density can be measured, for example, by a scanning electron microscope (SEM) and CL (Cathode Luminescence). The dislocation density may be, for example, the density of threading dislocations penetrating the interface between the electron transport layer 48 and the electron supply layer 50.

[0062] The high dislocation density region 54 is composed of a part of the electron transport layer 48 and a part of the electron supply layer 50. Specifically, the high dislocation density region 54 is composed of the electron transport layer 48 located on the exposed portion 42F2 and the electron supply layer 50 overlapping the exposed portion 42F2 in plan view. The low dislocation density region 56 is composed of a part of the electron transport layer 48 and a part of the electron supply layer 50. Specifically, the low dislocation density region 56 is composed of the electron transport layer 48 located on the main mask 44X and the electron supply layer 50 overlapping the main mask 44X in plan view.

[0063] The high dislocation density region 54 is located on the buffer layer 42. More specifically, the high dislocation density region 54 is located on the exposed portion 42F2 of the buffer upper surface 42F. The high dislocation density region 54 is in contact with the exposed portion 42F2 of the buffer upper surface 42F via the window portion 52. The lower surface of the high dislocation density region 54 constitutes the first lower surface 46G1.

[0064] The high dislocation density region 54 of the nitride semiconductor layer 46 includes a first high dislocation region 54A and a second high dislocation region 54B. The first high dislocation region 54A is located below the first drain electrode 33A. The second high dislocation region 54B is located below the second drain electrode 33B. The first high dislocation region 54A and the second high dislocation region 54B are located on opposite sides of the main mask 44X in the Y direction.

[0065] The low dislocation density region 56 is located on the main mask 44X. More specifically, the low dislocation density region 56 is in contact with the upper surface 44F of the mask. The lower surface of the low dislocation density region 56 constitutes a second lower surface 46G2. The low dislocation density region 56 is separated from the buffer layer 42 in the Z direction by the main mask 44X. More specifically, the second lower surface 46G2 of the low dislocation density region 56 is separated from the buffer upper surface 42F of the buffer layer 42 by the main mask 44X.

[0066] The low dislocation density region 56 does not necessarily have to be in contact with the main mask 44X. For example, there may be a gap between the low dislocation density region 56 and the main mask 44X. The low dislocation density region 56 may also be separated from the upper surface 44F of the mask in the Z direction.

[0067] The Y-direction dimension of the low dislocation density region 56 may be, for example, 3 μm or more and 8 μm or less. The Y-direction dimension D2 of each main mask 44X may also be the Y-direction dimension of the low dislocation density region 56.

[0068] The Z-direction dimension of the low dislocation density region 56 may be, for example, 2 μm or more and 10 μm or less. The Y-direction dimension D2 of each main mask 44X may be larger than the Z-direction dimension of the low dislocation density region 56.

[0069] The low dislocation density region 56 includes a first low dislocation region 56A and a second low dislocation region 56B. The first low dislocation region 56A is located below the first main portion 30A1. The second low dislocation region 56B is located below the second main portion 30A2. The first low dislocation region 56A and the first high dislocation region 54A are integrally formed. The second low dislocation region 56B and the second high dislocation region 54B are integrally formed.

[0070] The high dislocation density region 54 and the low dislocation density region 56 are arranged alternately in the Y direction. Corresponding to the alternating arrangement of the main mask 44X and the window portion 52 in the Y direction, it can be said that the low dislocation density region 56 and the high dislocation density region 54 are arranged alternately in the Y direction.

[0071] The nitride semiconductor layer 46 may include a boundary region 58 located between a first low dislocation region 56A and a second low dislocation region 56B. The boundary region 58 has a higher dislocation density than the low dislocation density region 56. In this embodiment, the boundary region 58 is located in the center of the main mask 44X in the Y direction.

[0072] As shown in Figures 6 and 7, the nitride semiconductor layer 46 is located in the active region 12. More specifically, the nitride semiconductor layer 46 is located above the buffer layer 42 in the active region 12. In other words, the active region 12 is the region in which the nitride semiconductor layer 46 is located above the buffer layer 42. As shown in Figure 6, the low dislocation density region 56 of the nitride semiconductor layer 46 is located in the part of the active region 12 where the mask layer 44 is located. As shown in Figure 7, the high dislocation density region 54 of the nitride semiconductor layer 46 is located in the part of the active region 12 where the buffer layer 42 is exposed from the mask layer 44.

[0073] As shown in Figures 6 and 7, the nitride semiconductor layer 46 is not located in the boundary region 14. More specifically, the nitride semiconductor layer 46 is not located on the mask layer 44 located in the boundary region 14. In the boundary region 14, the mask layer 44 is exposed from the nitride semiconductor layer 46. More specifically, in the boundary region 14, the boundary mask 44Y of the mask layer 44 is exposed from the nitride semiconductor layer 46. In other words, the boundary region 14 is the region where the nitride semiconductor layer 46 is not located on the mask layer 44 and the mask layer 44 is exposed from the nitride semiconductor layer 46. The nitride semiconductor layer 46 located in each active region 12 is separated from the nitride semiconductor layer 46 located in other active regions 12 by the boundary region 14. In the boundary region 14, the mask layer 44 exposed from the nitride semiconductor layer 46 is covered by the insulating layer 22.

[0074] (Description of gate structure, source electrode, and drain electrode) As shown in Figure 3, the gate structure 30, source electrode 32, and drain electrode 33 are located on the nitride semiconductor layer 46. More specifically, the gate structure 30, source electrode 32, and drain electrode 33 are located on the electron supply layer 50 of the nitride semiconductor layer 46.

[0075] The gate structure 30 is located on the low dislocation density region 56 of the nitride semiconductor layer 46. More specifically, the entire gate structure 30 is located on the low dislocation density region 56 of the nitride semiconductor layer 46. It can also be said that the gate structure 30 overlaps with the main mask 44X in a plan view. As shown in Figure 4, in this embodiment, the entire gate structure 30 overlaps with the main mask 44X in a plan view.

[0076] The gate layer 34 is made of a nitride semiconductor. In one example, the gate layer 34 is made of a nitride semiconductor having a smaller band gap than the electron supply layer 50 and containing acceptor-type impurities. In one example, the gate layer 34 is GaN (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and carbon. The maximum concentration of acceptor-type impurities in the gate layer 34 is, for example, 7 × 10⁻⁶. 18 cm -3 The above 3 x 10 20 cm -3 The following applies:

[0077] The gate electrode 39 comprises one or more metal layers. In one example, the gate electrode 39 may be a titanium nitride (TiN) layer. In another example, the gate electrode 39 may consist of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 39 may be made of a material that has the property of forming a Schottky bond with the gate layer 34, for example. An example of such a material is TiN. The thickness of the gate electrode 39 can be, for example, 50 nm to 200 nm.

[0078] When a voltage exceeding the gate threshold voltage is applied to the gate electrode 39, a channel due to 2DEG is created in the electron transport layer 48. As a result, current can flow between the source electrode 32 and the drain electrode 33. On the other hand, when a voltage below the gate threshold voltage is applied to the gate electrode 39 (including when no voltage is applied to the gate electrode 39), 2DEG is less likely to occur in at least a portion of the region of the electron transport layer 48 located below the gate layer 34. This is because the gate layer 34 contains acceptor-type impurities, which raises the energy levels of the electron transport layer 48 and the electron supply layer 50, resulting in the depletion of 2DEG. Thus, normally-off operation is achieved in the nitride semiconductor device 10 including the gate layer 34.

[0079] The gate layer 34 includes a ridge portion 35 that is in contact with the electron supply layer 50 and includes an upper surface 34F, and a first extension portion 36 and a second extension portion 37 that are in contact with the electron supply layer 50 and extend outward from the ridge portion 35 in a plan view, and are thinner than the ridge portion 35. In this disclosure, the first extension portion 36 and the second extension portion 37 may be collectively referred to as the extension portion 38.

[0080] Since the first extension portion 36 and the second extension portion 37 are thinner than the ridge portion 35, the upper surface 36F of the first extension portion 36 and the upper surface 37F of the second extension portion 37 are located below the upper surface 35F of the ridge portion 35 in the Z direction. The side surface 35H of the ridge portion 35 connects the upper surface 35F of the ridge portion 35 to the upper surface 36F of the first extension portion 36 and the upper surface 37F of the second extension portion 37.

[0081] The first extension portion 36 extends from the ridge portion 35 toward the source electrode 32. In a plan view, the first extension portion 36 partially covers the surface of the electron supply layer 50 between the ridge portion 35 and the source electrode 32. The first extension portion 36 is separated from the source electrode 32.

[0082] The second extension portion 37 extends from the ridge portion 35 toward the drain electrode 33. In a plan view, the second extension portion 37 partially covers the surface of the electron supply layer 50 between the ridge portion 35 and the drain electrode 33. The second extension portion 37 is separated from the drain electrode 33.

[0083] The ridge portion 35 is located between the first extension portion 36 and the second extension portion 37, and is integrally formed with the first extension portion 36 and the second extension portion 37. Due to the presence of the first extension portion 36 and the second extension portion 37, the lower surface 34G of the gate layer 34 has a larger area than the upper surface 34F. In the example shown in Figure 3, the second extension portion 37 may extend longer outward from the ridge portion 35 in a plan view than the first extension portion 36. That is, the second extension portion 37 may have a larger dimension in the X direction than the first extension portion 36. The first extension portion 36 may have a dimension in the X direction of, for example, 0.2 μm or more and 0.3 μm or less. On the other hand, the second extension portion 37 may have a dimension in the X direction of, for example, 0.2 μm or more and 0.6 μm or less.

[0084] The ridge portion 35 corresponds to a relatively thick portion of the gate layer 34. The ridge portion 35 may have a thickness of, for example, 80 nm to 150 nm. In one example, the ridge portion 35 may have a thickness greater than 110 nm. The first extension portion 36 and the second extension portion 37 have a thickness less than the thickness of the ridge portion 35. In other words, the first extension portion 36 and the second extension portion 37 are thinner than the ridge portion 35. In one example, the first extension portion 36 and the second extension portion 37 may have a thickness of half or less the thickness of the ridge portion 35.

[0085] In this embodiment, the entire gate layer 34 is located on a low dislocation density region 56. More specifically, the lower surface 36G of the first extension portion 36, the lower surface 37G of the second extension portion 37, and the lower surface 35G of the ridge portion 35 are in contact with the low dislocation density region 56.

[0086] As shown in Figure 3, the source electrode 32 is in contact with the electron supply layer 50. The source electrode 32 can make ohmic contact with the 2DEG directly beneath the electron supply layer 50 that is in contact with the source electrode 32. In a plan view, the source electrode 32 overlaps with the center of the main mask 44X in the Y direction. The source electrode 32 straddles the first low dislocation region 56A and the second low dislocation region 56B. The source electrode 32 is located on the boundary portion 58.

[0087] The drain electrode 33 is in contact with the electron supply layer 50. The drain electrode 33 can make ohmic contact with the 2DEG directly below the electron supply layer 50 that is in contact with the drain electrode 33. The distance between the drain electrode 33 and the gate layer 34 in the Y direction may be greater than the distance between the source electrode 32 and the gate layer 34 in the Y direction.

[0088] The drain electrode 33 is located on the high dislocation density region 54. The drain electrode 33 is located in the center of the high dislocation density region 54 in the Y direction. In plan view, the drain electrode 33 can be said to overlap with the exposed portion 42F2 of the buffer upper surface 42F. The drain electrode 33 is located in the center of the window portion 52 in the Y direction. It can also be said that the drain electrode 33 is located in the center between the main masks 44X in the Y direction.

[0089] The source electrode 32 and the drain electrode 33 include one or more metal layers. In one example, the source electrode 32 and the drain electrode 33 may be composed of one or any combination of Ti, TiN, Al, AlSiCu, and AlCu. In one example, the source electrode 32 and the drain electrode 33 are composed of a first metal layer in contact with the electron supply layer 50, a second metal layer laminated on the first metal layer, a third metal layer laminated on the second metal layer, and a fourth metal layer laminated on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0090] (Method for manufacturing nitride semiconductor equipment) Next, an example of a manufacturing method for the nitride semiconductor device 10 will be described. Figures 8 to 17 are schematic cross-sectional views showing an exemplary manufacturing process for the nitride semiconductor device 10. For ease of understanding, in Figures 8 to 17, components similar to those in Figure 3 are denoted by the same reference numerals.

[0091] As shown in Figure 8, the manufacturing method of the nitride semiconductor device 10 includes forming a buffer layer 42 on a substrate 40. In one example, the buffer layer 42 can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD).

[0092] The buffer layer 42 may be a multilayer buffer layer. For example, the multilayer buffer layer may include a first buffer layer 42A formed on the substrate 40, a second buffer layer 42B formed on the first buffer layer 42A, and a third buffer layer 42C formed on the second buffer layer 42B.

[0093] In one example, the first buffer layer 42A may be an AlN layer. The second buffer layer 42B may be an AlGaN layer. The third buffer layer 42C may be a GaN layer. Although not shown in the figure, the buffer layer 42 may include a graded AlGaN layer. The graded AlGaN layer can be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0094] As shown in Figure 9, the manufacturing method of the nitride semiconductor device 10 includes selectively forming a mask portion 45 on a buffer layer 42. The mask portion 45 is the main mask 44X of the mask layer 44, as shown in Figure 3. Forming the mask portion 45 may include forming a mask forming layer (not shown) on the buffer layer 42 and selectively removing a part of the mask forming layer. The mask forming layer may contain at least one of SiO2 and SiN. The mask forming layer may cover the entire buffer upper surface 42F, which is the upper surface of the buffer layer 42. Subsequently, the mask portion 45 is formed by selectively removing a part of the mask forming layer. By selectively forming the mask portion 45, a covered portion 42F1 of the buffer upper surface 42F that is covered by the mask portion 45 and an exposed portion 42F2 of the buffer upper surface 42F that is exposed from the mask portion 45 are formed.

[0095] It can also be said that a window portion 52 is formed in which a part of the mask-forming layer is removed. The window portion 52 is located on both sides of the mask portion 45 in the Y direction. In other words, the mask portion 45 and the window portion 52 are formed alternately in the Y direction. For example, a part of the mask-forming layer may be removed by photolithography using a resist. The method for removing the mask-forming layer is not limited to the above and may be any method.

[0096] As shown in Figures 10 to 13, the manufacturing method of the nitride semiconductor device 10 includes forming a nitride semiconductor layer 46 on a buffer layer 42 and a mask portion 45. As shown in Figures 10 to 12, forming the nitride semiconductor layer 46 includes growing the electron transport layer 48 on the buffer layer 42 on the exposed portion 42F2. Furthermore, forming the nitride semiconductor layer 46 also includes growing the electron transport layer 48 on the mask portion 45 so as to cover the mask portion 45.

[0097] As shown in Figure 10, the electron transport layer 48 is grown on the exposed portion 42F2 of the buffer upper surface 42F. The electron transport layer 48 is formed by epitaxial growth from the exposed portion 42F2 of the buffer upper surface 42F to a thickness similar to that of the mask portion 45. The formed electron transport layer 48 constitutes a part of the high dislocation density region 54 (see Figure 3). The mask portion 45 is made of a material that suppresses the epitaxial growth of nitride semiconductors on the mask portion 45. Therefore, the electron transport layer 48 is not formed on the mask portion 45, but on the portion of the buffer layer 42 that is exposed from the mask portion 45.

[0098] Next, as shown in Figure 11, the electron traveling layer 48 is grown in both the Z and Y directions. When the electron traveling layer 48 becomes thicker than the mask portion 45 due to epitaxial growth, the electron traveling layer 48 also begins to grow in the Y direction so as to cover the mask portion 45. The electron traveling layer 48 grown on the exposed portion 42F2 constitutes a part of the high dislocation density region 54 (see Figure 3). The electron traveling layer 48 that has grown to cover the mask portion 45 constitutes a part of the low dislocation density region 56 (see Figure 3). On the mask portion 45, a first low dislocation region 56A is formed closer to one side in the Y direction as viewed from the mask portion 45, and a second low dislocation region 56B is formed closer to the other side in the Y direction.

[0099] In the illustrated example, the side surface 54H1 of the first low dislocation region 56A and the side surface 54H2 of the second low dislocation region 56B are inclined from the Z direction. More specifically, the side surfaces 54H1 and 54H2 have a tapered structure in which the distance between them in the Y direction decreases as they approach the upper surface 44F of the mask portion 45. It can also be said that the side surfaces 54H1 and 54H2 are inclined such that the angle between them and the upper surface 44F of the mask is acute. The side surfaces 54H1 and 54H2 may be the {1-101} plane of the nitride semiconductor constituting the electron transport layer 48.

[0100] The orientation of sides 54H1 and 54H2 is not limited to those described above. For example, sides 54H1 and 54H2 may extend in the Z direction. In other words, sides 54H1 and 54H2 may be approximately perpendicular to the upper surface 44F of the mask.

[0101] Next, as shown in Figure 12, the electron traveling layer 48 is further grown in the Z and Y directions. The first low dislocation region 56A and the second low dislocation region 56B grow toward the center of the mask portion 45 in the Y direction, covering the mask portion 45. The formation of the electron traveling layer 48 is completed when the first low dislocation region 56A and the second low dislocation region 56B combine near the center of the mask portion 45 in the Y direction. In order to improve the flatness of the upper surface of the electron traveling layer 48, epitaxial growth of the electron traveling layer 48 may be continued for a predetermined period even after the first low dislocation region 56A and the second low dislocation region 56B have combined. A boundary portion 58 is formed between the first low dislocation region 56A and the second low dislocation region 56B. The upper surface of the electron traveling layer 48 may be formed flat.

[0102] The electron transport layer 48 may be formed by the MOCVD method. The electron transport layer 48 may be made of GaN. Growth conditions may be set appropriately to promote the growth of the low dislocation density region 56 in the Y direction and to make the upper surface of the electron transport layer 48 flat. For example, the temperature, pressure, carrier gas concentration, and the geometric shape of the carrier gas flow during the formation of the electron transport layer 48 may be set.

[0103] As shown in Figure 13, forming the nitride semiconductor layer 46 includes forming an electron supply layer 50 on the electron transport layer 48. The electron supply layer 50 formed in a position overlapping with the window portion 52 in a plan view constitutes a part of the high dislocation density region 54. The electron supply layer 50 formed in a position overlapping with the mask portion 45 in a plan view constitutes a part of the low dislocation density region 56. The electron supply layer 50 may be made of AlGaN. The electron supply layer 50 may be formed by the MOCVD method. The formation of the electron supply layer 50 completes the formation of the high dislocation density region 54 and the low dislocation density region 56. Furthermore, the formation of the electron supply layer 50 completes the formation of the nitride semiconductor layer 46.

[0104] As shown in Figures 14 to 17, the manufacturing method of the nitride semiconductor device 10 includes forming a gate structure 30 on a nitride semiconductor layer 46. As shown in Figure 14, forming the gate structure 30 (see Figure 3) may include forming a semiconductor layer 100 on an electron supply layer 50. The semiconductor layer 100 may be composed of a nitride semiconductor containing acceptor-type impurities. The semiconductor layer 100 may be composed of, for example, a p-type GaN layer. The semiconductor layer 100 is composed of a nitride semiconductor having a smaller band gap than the electron supply layer 50. The semiconductor layer 100 is a semiconductor layer that constitutes the gate layer 34 (see Figure 3). The semiconductor layer 100 can be epitaxially grown, for example, using the MOCVD method. In one example, a semiconductor layer 100 containing acceptor-type impurities can be formed by doping with Mg while growing a nitride semiconductor layer (for example, a GaN layer) corresponding to the gate layer 34.

[0105] As shown in Figure 15, forming the gate structure 30 (see Figure 3) may include forming a gate electrode 39 on the semiconductor layer 100. Although not shown, the gate electrode 39 may be formed by, for example, forming a first electrode layer on the semiconductor layer 100 by sputtering, and then removing a portion of the first electrode layer. The electrode layer may be formed over the entire upper surface of the semiconductor layer 100. The electrode layer is, for example, a TiN layer. In one example, a protective mask (not shown) is formed on the electrode layer, and the gate electrode 39 is formed by removing the electrode layer exposed from the protective mask. The protective mask is removed after the formation of the gate electrode 39.

[0106] As shown in Figure 16, forming the gate structure 30 may include forming the gate layer 34 by etching the semiconductor layer 100 (see Figure 15). For example, the semiconductor layer 100 is etched by plasma etching. A chlorine-based (Cl2-based) gas can be used for plasma etching. This forms the gate layer 34, which includes a ridge portion 35 directly below the gate electrode 39 and an extended portion 38. The formation of the gate structure 30 is completed by the formation of the gate layer 34 and the gate electrode 39. The gate structure 30 is formed on the low dislocation density region 56. In this embodiment, the gate structure 30 is formed on the low dislocation density region 56 by forming the gate layer 34 on the low dislocation density region 56.

[0107] Alternatively, the gate electrode 39 may be formed after etching the semiconductor layer 100 to form the gate layer 34. In that case, the gate electrode 39 may be formed simultaneously with the source electrode 32 and drain electrode 33, which will be described later.

[0108] As shown in Figure 17, the method for manufacturing the nitride semiconductor device 10 includes forming a source electrode 32 and a drain electrode 33 on a nitride semiconductor layer 46, which extend along the X direction in a plan view. The source electrode 32 and the drain electrode 33 may be formed by etching a second metal layer after forming a second electrode layer (not shown) on the nitride semiconductor layer 46. The second electrode layer can be composed of, for example, one or more metal layers (for example, any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and / or an AlCu layer).

[0109] The source electrode 32 may be formed on the low dislocation density region 56. More specifically, the source electrode 32 may be formed in the center of the low dislocation density region 56 in the Y direction. The source electrode 32 may be formed spanning a first low dislocation region 56A and a second low dislocation region 56B of the low dislocation density region 56. The source electrode 32 may be formed on a boundary portion 58 located between the first low dislocation region 56A and the second low dislocation region 56B.

[0110] The drain electrode 33 may be formed on the high dislocation density region 54. The drain electrode 33 may be formed in the center of the high dislocation density region 54 in the Y direction. (Effect of the embodiment) The operation of the nitride semiconductor device 10 of this embodiment will be described below.

[0111] The nitride semiconductor device 10 of this embodiment includes a substrate 40, a buffer layer 42 located on the substrate 40, a mask portion 45 selectively provided on the buffer layer 42, an electron transport layer 48, and a nitride semiconductor layer 46 including an electron supply layer 50 located on the electron transport layer 48 and having a larger band gap than the electron transport layer 48. The nitride semiconductor layer 46 includes a high dislocation density region 54 located on the buffer layer 42 and a low dislocation density region 56 located on the mask portion 45 and having a lower dislocation density than the high dislocation density region 54.

[0112] In the nitride semiconductor device 10, a mask portion 45 is selectively provided on the buffer layer 42. This suppresses the growth of the nitride semiconductor in the Z direction on the mask portion 45 in the nitride semiconductor device 10. Consequently, a high dislocation density region 54 grows on the exposed portion 42F2 of the buffer upper surface 42F.

[0113] On the mask portion 45, an electron transport layer 48 grows so as to cover the mask portion 45. More specifically, on the mask portion 45, an electron transport layer 48 grows from the electron transport layer 48 that constitutes the high dislocation density region 54 so as to cover the mask portion 45. The electron transport layer 48 that has grown to cover the mask portion 45 constitutes a low dislocation density region 56.

[0114] The dislocation density of the electron traveling layer 48 grown to cover the mask portion 45 is lower than that of the electron traveling layer 48 grown on the exposed portion 42F2. In other words, the dislocation density of the electron traveling layer 48 constituting the low dislocation density region 56 is lower than that of the electron traveling layer 48 constituting the high dislocation density region 54.

[0115] Incidentally, one reason why the dislocation density in the low dislocation density region 56 is lower than that in the high dislocation density region 54 is that the inheritance of dislocations in the buffer layer 42 is hindered by the mask portion 45 in the low dislocation density region 56. Dislocations that extend in the Z direction within the buffer layer 42 and reach the boundary between the buffer layer 42 and the high dislocation density region 54 may be inherited from the buffer layer 42 to the high dislocation density region 54. On the other hand, the low dislocation density region 56 and the buffer layer 42 are separated in the Z direction by the mask portion 45. Therefore, dislocations that extend in the Z direction within the buffer layer 42 and reach the upper surface of the buffer layer 42 located below the low dislocation density region 56 are blocked by the mask portion 45 and are not inherited to the low dislocation density region 56. As a result, the dislocation density in the low dislocation density region 56 tends to be lower than that of the high dislocation density region 54.

[0116] Subsequently, an electron supply layer 50 grows on the electron transport layer 48 in the Z direction. The electron supply layer 50 grown on the electron transport layer 48 that has grown to cover the mask portion 45 has a lower dislocation density than the electron supply layer 50 grown on the electron transport layer 48 that has grown on the exposed portion 42F2. In other words, the electron supply layer 50 in the low dislocation density region 56 has a lower dislocation density than the electron supply layer 50 in the high dislocation density region 54.

[0117] In nitride semiconductor devices, dislocations are a cause of leakage current flowing through them. In particular, in nitride semiconductor devices where a large number of dislocations are present under the gate structure, including the gate electrode, gate leakage current is more likely to flow. The generation of gate leakage current can lead to a decrease in the gate breakdown voltage of nitride semiconductor devices.

[0118] In this regard, in the nitride semiconductor device 10 of this embodiment, the gate structure 30 is located on a low dislocation density region 56. By locating the gate structure 30 on a low dislocation density region 56 where the dislocation density is low, the gate leakage current is reduced in the nitride semiconductor device 10.

[0119] (Effects of the embodiment) The nitride semiconductor device 10 of this embodiment has the following advantages. (1) The nitride semiconductor device 10 includes a substrate 40, a buffer layer 42, a mask portion 45, and a nitride semiconductor layer 46. The buffer layer 42 is located on the substrate 40. The mask portion 45 is selectively provided on the buffer layer 42. The nitride semiconductor layer 46 includes a high dislocation density region 54 located on the buffer layer 42 and a low dislocation density region 56 located on the mask portion 45, where the dislocation density is lower than that of the high dislocation density region 54. The gate structure 30 is located on the low dislocation density region 56.

[0120] In this configuration, as described above, the gate structure 30 is located in a low dislocation density region 56 where the dislocation density is lower than that of the high dislocation density region 54. This reduces the gate leakage current from the gate structure 30.

[0121] (2) The gate structure 30 includes a gate layer 34 containing acceptor-type impurities and a gate electrode 39 located on the gate layer 34. The entire gate layer 34 is located on a low dislocation density region 56.

[0122] In this configuration, the nitride semiconductor device 10 has a normally-off characteristic where the gate threshold voltage is a positive value, due to the gate layer 34 containing acceptor-type impurities. The gate layer 34 is epitaxially grown on the nitride semiconductor layer 46. When the dislocation density of the nitride semiconductor layer 46 beneath the gate layer 34 is relatively high, the dislocation density of the gate layer 34 tends to be relatively high as well. In this respect, in the nitride semiconductor device 10 of this embodiment, the gate layer 34 is located on a low dislocation density region 56, resulting in a low dislocation density of the gate layer 34. This further reduces the gate leakage current.

[0123] (3) The gate structure 30 is superimposed on the mask portion 45 in a plan view. In this configuration, the nitride semiconductor layer 46 directly beneath the gate structure 30 is entirely a low dislocation density region 56. This reduces the gate leakage current from the gate structure 30. In addition, a mask portion 45 made of an insulating material is located entirely beneath the gate structure 30. This further reduces the gate leakage current from the gate structure 30.

[0124] (4) The source electrode 32 is aligned with the center of the mask portion 45 in the second direction in a plan view. The area above the center of the mask portion 45 in the Y direction tends to have a higher dislocation density than the low dislocation density region 56. In this regard, in the nitride semiconductor device 10 of this embodiment, the source electrode 32 is located above the center of the mask portion 45. As a result, the gate structure 30 is located away from the center above the mask portion 45. By positioning the gate structure 30 to avoid the high dislocation density region, the gate leakage current from the gate structure 30 can be reduced.

[0125] (5) The gate structure 30 includes a first main portion 30A1 and a second main portion 30A2. The first main portion 30A1 is located between the first drain electrode 33A and the source electrode 32. The second main portion 30A2 is located between the second drain electrode 33B and the source electrode 32. The low dislocation density region 56 includes a first low dislocation region 56A located below the first main portion 30A1 and a second low dislocation region 56B located below the second main portion 30A2. The source electrode 32 straddles the first low dislocation region 56A and the second low dislocation region 56B.

[0126] The dislocation density is higher near the boundary between the first low dislocation region 56A and the second low dislocation region 56B compared to the low dislocation density region 56. If the gate structure 30 is located near the boundary between the first low dislocation region 56A and the second low dislocation region 56B, there is a risk that gate leakage current will be more likely to occur due to dislocations.

[0127] In this regard, in the nitride semiconductor device 10 of this embodiment, the source electrode 32 spans the first low dislocation region 56A and the second low dislocation region 56B. Therefore, the gate structure 30 is positioned to avoid regions with high dislocation density. Specifically, the first main part 30A1 of the gate structure 30 is located on the first low dislocation region 56A of the low dislocation density region 56. The second main part 30A2 of the gate structure 30 is located on the second low dislocation region 56B of the low dislocation density region 56. This reduces the gate leakage current from the gate structure 30.

[0128] (6) The nitride semiconductor layer 46 is located between the first low dislocation region 56A and the second low dislocation region 56B and includes a boundary region 58 in which the dislocation density is higher than that of the low dislocation density region. The source electrode 32 is located on the boundary region 58.

[0129] This configuration allows the gate structure 30 to be positioned while avoiding the boundary region 58 where the dislocation density is higher than that of the low dislocation density region 56. This reduces the gate leakage current from the gate structure 30.

[0130] (7) The dislocation density in the low dislocation density region 56 is 1 × 10 4 cm -2 The following applies: According to this configuration, the dislocation density in the low dislocation density region 56 is 1 × 10⁻⁶ 4 cm -2 The values ​​are as low as below. This makes the effect of reducing gate leakage current from the gate structure 30 more pronounced.

[0131] (8) The electron transport layer 48 has a hexagonal crystal structure. The first direction coincides with the <1-100> direction of the electron transport layer 48. With this configuration, the electron traveling layer 48 tends to grow to cover the mask portion 45. This makes it easier to increase the Y-direction dimension of the low dislocation density region 56. Therefore, it is easier to secure the Y-direction dimension of the low dislocation density region 56 for arranging the gate structure 30.

[0132] (9) The nitride semiconductor device 10 includes a plurality of mask portions 45. The plurality of mask portions 45 are spaced apart in the Y direction. The Y-direction dimension D2 of each of the plurality of mask portions 45 is smaller than the Y-direction distance D3 between the plurality of mask portions 45.

[0133] The low dislocation density region 56 grows toward the center of the mask portion 45 in the Y direction, covering the mask portion 45. With this configuration, the Y-direction dimension of the low dislocation density region 56 in the nitride semiconductor device 10 tends to be relatively small. This makes it easier for the low dislocation density region 56 to cover the entire mask portion 45.

[0134] (10) The mask portion 45 contains at least one of SiO2 and SiN. This configuration suppresses the growth of the nitride semiconductor layer 46 in the Z direction on the mask portion 45. This allows for the creation of a low dislocation density region 56 on the mask portion 45. Furthermore, SiO2 and SiN are relatively easy to etch for selectively creating the mask portion 45. This makes it easy to create the desired shape for the mask portion 45.

[0135] (11) The buffer layer 42 includes a plurality of active regions 12 on which nitride semiconductor layers 46 are arranged, and boundary regions 14 that separate the plurality of active regions 12. The nitride semiconductor layer 46 located in each active region 12 is separated from the nitride semiconductor layer 46 located in other active regions 12 by the boundary regions 14.

[0136] With this configuration, the effects of mismatch in thermal expansion coefficients between the substrate 40 and the nitride semiconductor layer 46 (e.g., electron transport layer 48) can be mitigated by the boundary region 14. Therefore, the occurrence of warping and cracks can be suppressed in the nitride semiconductor device 10.

[0137] Warping and cracking can lead to the generation of dislocations and leakage currents. In this embodiment, warping and cracking of the nitride semiconductor device 10 are suppressed. This makes it possible to suppress the generation of dislocations and leakage currents.

[0138] (12) Multiple active regions 12 are arranged in a matrix along the first and second directions. In this configuration, the multiple active regions 12 and boundary regions 14 are regularly arranged in the X and Y directions. This makes it possible to further suppress the occurrence of warping and cracks in the nitride semiconductor device 10. Consequently, the generation of dislocations and leakage currents can be further suppressed.

[0139] (13) The nitride semiconductor device 10 includes gate wiring 16, source wiring 18, and drain wiring 20. The gate wiring 16 is electrically connected to the gate structure 30. The source wiring 18 is electrically connected to the source electrode 32. The drain wiring 20 is electrically connected to the drain electrode 33. Two of the gate wiring 16, source wiring 18, and drain wiring 20 overlap with the boundary region 14 in a plan view.

[0140] With this configuration, at least two of the gate wiring 16, source wiring 18, and drain wiring 20 can be easily connected to each of two adjacent components in the X direction among the multiple active regions 12. For example, if the gate wiring 16 is positioned so as to overlap in a plan view with two adjacent active regions 12 in the X direction, the gate wiring 16 can be easily connected to the gate structures 30 of the two adjacent active regions 12 in the X direction. More specifically, by positioning the gate wiring 16 so as to overlap in a plan view with the gate structures 30 of the two adjacent active regions 12 in the X direction, the gate wiring 16 and the gate structures 30 can be easily connected. This reduces the number of required wirings compared to the case where gate wiring 16 is placed in each of the two adjacent active regions 12 in the X direction. Therefore, the wiring of the nitride semiconductor device 10 can be simplified.

[0141] (14) The gate structure 30 includes a gate layer 34 and a gate electrode 39. The gate layer 34 contains acceptor-type impurities. The gate electrode 39 is located on the gate layer 34. The gate layer 34 includes a ridge portion 35 and an extension portion 38. The ridge portion 35 includes an upper surface 35F on which the gate electrode 39 is located and a lower surface 35G in contact with the nitride semiconductor layer 46. The extension portion 38 includes lower surfaces 36G and 37G in contact with the electron supply layer 50 and is thinner than the ridge portion 35.

[0142] In this configuration, the gate layer 34 includes an extension 38 that is thinner than the ridge portion 35. When a voltage is applied to the gate electrode 39, some of the equipotential lines within the ridge portion 35 pass through the extension 38. Therefore, localized electric field concentration near the edge of the ridge portion 35 (e.g., within the electron supply layer 50), which may occur in the absence of the extension 38, can be suppressed. This reduces the gate leakage current.

[0143] (Example of change) This embodiment can be implemented with the following modifications. This embodiment and the following modifications can be implemented individually or in combination with each other to the extent that they do not contradict each other technically.

[0144] As shown in Figure 18, the gate structure 30 of the nitride semiconductor device 10 does not necessarily have to include a gate layer 34. The gate structure 30 may consist only of a gate electrode 39. A nitride semiconductor device 10 without a gate layer 34 will have a negative gate threshold voltage and will perform normally-on operation.

[0145] The gate structure 30 does not have to be located entirely on the low dislocation density region 56. It is sufficient if at least a part of the gate structure 30 is located on the low dislocation density region 56. The gate structure 30 does not have to overlap the mask portion 45 in a plan view.

[0146] The gate structure 30 does not have to surround the source electrode 32 in a plan view. The gate structure 30 does not have to include the first main part 30A1, the second main part 30A2, the first connecting part 30B1, and the second connecting part 30B2. The gate structure 30 only needs to be located between the source electrode 32 and the drain electrode 33.

[0147] The gate layer 34 does not necessarily have to include a ridge portion 35 and an extended portion 38. The cross-sectional shape of the gate layer 34 may be rectangular. The source electrode 32 does not have to overlap with the center of the mask portion 45 in the second direction in a plan view. The source electrode 32 does not have to be located on the boundary portion 58. The drain electrode 33 does not have to be located on the high dislocation density region 54. The drain electrode 33 does not have to be located in the center of the high dislocation density region 54 in the second direction. The drain electrode 33 does not have to be located in the center between the mask portions 45 in the second direction.

[0148] The Y-direction dimension D2 of each of the multiple mask sections may be greater than the Y-direction distance D3 between the multiple mask sections. With this configuration, the Y-direction dimension of the low dislocation density region 56 located on the mask section 45 tends to be larger than the Y-direction dimension of the high dislocation density region 54. Therefore, it is easier to secure the Y-direction dimension of the low dislocation density region 56 for arranging the gate structure 30.

[0149] The shape and material of the mask portion 45 can be arbitrarily changed. The mask portion 45 may be made of materials other than SiO2 and SiN. The mask portion 45 only needs to be made of a material that can suppress the epitaxial growth of nitride semiconductors on the mask portion 45.

[0150] The X direction does not have to coincide with the <1-100> direction of the electron transport layer 48. The crystal orientation of the electron transport layer 48 is such that it grows to cover the mask portion 45 and is arranged to provide a low dislocation density region 56.

[0151] Only one of the gate wiring 16, source wiring 18, and drain wiring 20 may overlap with the boundary region 14 in a plan view. The gate wiring 16, source wiring 18, and drain wiring 20 do not have to overlap with the boundary region 14 in a plan view.

[0152] In this disclosure, the phrase "at least one of A and B" should be understood to mean "A only, B only, or both A and B." As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, for example, the expression “the first element is positioned on the second element” is intended to mean that in one embodiment the first element may be in contact with and directly positioned on the second element, while in other embodiments the first element may be positioned above the second element without contact. In other words, the term “on” does not preclude structures in which other elements are provided between the first and second elements.

[0153] The Z direction used in this disclosure does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures described herein (e.g., the structure shown in Figure 3) are not limited to the Z direction "up" and "down" being the same as the Z direction "up" and "down" being the same as the vertical. For example, the X direction may be vertical, or the Y direction may be vertical.

[0154] [Note] The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0155] [Note 1] Circuit board (40) and A buffer layer (42) located on the substrate (40), A mask portion (45) is selectively provided on the buffer layer (42), A nitride semiconductor layer (46) includes an electron transport layer (48) and an electron supply layer (50) located on the electron transport layer (48) and having a larger band gap than the electron transport layer (48). A source electrode (32) and a drain electrode (33) are located on the nitride semiconductor layer (46) and extend in a first direction (X) in a plan view, A gate structure (30) is located on the nitride semiconductor layer (46) and is positioned between the source electrode (32) and the drain electrode (33) in a second direction (Y) that intersects the first direction (X) in a plan view, Includes, The nitride semiconductor layer (46) is A high dislocation density region (54) located on the buffer layer (42), A low dislocation density region (56) is located on the mask portion (45) and has a lower dislocation density than the high dislocation density region (54), Includes, The gate structure (30) is located on the low dislocation density region (56). Nitride semiconductor device (10).

[0156] [Note 2] The gate structure (30) is A gate layer (34) containing acceptor-type impurities, A gate electrode (39) located on the gate layer (34), Includes, The gate layer (34) is entirely located on the low dislocation density region (56). Nitride semiconductor device (10) as described in Appendix 1.

[0157] [Note 3] The gate structure (30) is such that, in a plan view, it overlaps with the mask portion (45). Nitride semiconductor device (10) as described in Appendix 1 or 2.

[0158] [Note 4] The source electrode (32) is aligned with the center of the mask portion (45) in the second direction (Y) in a plan view. Nitride semiconductor device (10) as described in Appendix 1.

[0159] [Note 5] The drain electrode (33) is the first drain electrode (33A), The nitride semiconductor device (10) further includes a second drain electrode (33B), The second drain electrode (33B) is provided on the opposite side of the source electrode (32) from the first drain electrode (33A), The gate structure (30) is A first main portion (30A1) is located between the first drain electrode (33A) and the source electrode (32), A second main portion (30A2) is located between the second drain electrode (33B) and the source electrode (32), Includes, The low dislocation density region (56) is A first low dislocation region (56A) located below the first main portion (30A1), A second low dislocation region (56B) located below the second main portion (30A2), Includes, The source electrode (32) spans the first low dislocation region (56A) and the second low dislocation region (56B). Nitride semiconductor device (10) as described in any one of the appendices 1 to 3.

[0160] [Note 6] The nitride semiconductor layer (46) includes a boundary region (58) located between the first low dislocation region (56A) and the second low dislocation region (56B), where the dislocation density is higher than that of the low dislocation density region (56). The source electrode (32) is located on the boundary portion (58), Nitride semiconductor device (10) as described in Appendix 5.

[0161] [Note 7] The drain electrode (33) is located on the high dislocation density region (54). Nitride semiconductor device (10) as described in any one of the appendices 1 to 6.

[0162] [Note 8] The drain electrode (33) is located in the center of the high dislocation density region (54) in the second direction (Y). Nitride semiconductor device (10) as described in any one of the appendices 1 to 7.

[0163] [Note 9] The dislocation density in the low dislocation density region (56) is 1 × 10⁻⁶ 4 cm -2 The following is: Nitride semiconductor device (10) as described in any one of the appendices 1 to 8.

[0164] [Note 10] The dislocation density in the low dislocation density region (56) is 1 / 10000 or less of the dislocation density in the high dislocation density region (54). Nitride semiconductor device (10) as described in any one of the appendices 1 to 9.

[0165] [Note 11] The dislocation density is the density of through-dislocations penetrating the interface between the electron transport layer (48) and the electron supply layer (50). Nitride semiconductor device (10) as described in any one of the appendices 1 to 10.

[0166] [Note 12] The low dislocation density region (56) and the high dislocation density region (54) are arranged alternately in the second direction (Y). Nitride semiconductor device (10) as described in any one of the appendices 1 to 11.

[0167] [Note 13] The electron transport layer (48) has a hexagonal crystal structure. The first direction (X) coincides with the <1-100> direction of the electron transport layer (48). Nitride semiconductor device (10) as described in any one of the appendices 1 to 12.

[0168] [Note 14] The dimension (D2) of the mask portion (45) in the second direction (Y) is greater than the thickness of the electron traveling layer (48). Nitride semiconductor device (10) as described in any one of the appendices 1 to 13.

[0169] [Note 15] It includes a plurality of mask portions (45) arranged spaced apart in the second direction (Y), The mask portion (45) is one of the plurality of mask portions (45), The dimension (D2) of each of the plurality of mask portions (45) in the second direction (Y) is smaller than the distance (D3) between the plurality of mask portions (45) in the second direction (Y). Nitride semiconductor device (10) as described in any one of the appendices 1 to 14.

[0170] [Note 16] The drain electrode (33) is located in the center between the mask portions (45) in the second direction (Y). Nitride semiconductor device (10) as described in Appendix 14.

[0171] [Note 17] The mask portion (45) contains at least one of SiO2 and SiN. Nitride semiconductor device (10) as described in any one of the appendices 1 to 16.

[0172] [Note 18] The electron transport layer (48) is a GaN layer, The electron supply layer (50) is an AlGaN layer. Nitride semiconductor device (10) as described in any one of the appendices 1 to 17.

[0173] [Note 19] Multiple active regions (12) are arranged on the buffer layer (42) and the nitride semiconductor layer (46), A boundary region (14) that separates the plurality of active regions (12), Includes, The nitride semiconductor layer (46) located in each of the active regions (12) is separated from the nitride semiconductor layer (46) located in other active regions (12) by the boundary region (14). Nitride semiconductor device (10) as described in any one of the appendices 1 to 18.

[0174] [Note 20] The mask portion (45) is covered by the nitride semiconductor layer (46) in the plurality of active regions (12), and is not covered by the nitride semiconductor layer (46) in the boundary region (14). Nitride semiconductor device (10) as described in Appendix 19.

[0175] [Note 21] The plurality of active regions (12) are arranged in a matrix along the first direction (X) and the second direction (Y). Nitride semiconductor device (10) as described in Appendix 19.

[0176] [Note 22] The gate structure (30) and the gate wiring (16) which is electrically connected, The source electrode (32) and the source wiring (18) are electrically connected, The drain electrode (33) and the drain wiring (20) are electrically connected, Includes, Two of the gate wiring (16), source wiring (18), and drain wiring (20) overlap with the boundary region (14) in a plan view. Nitride semiconductor device (10) as described in Appendix 19.

[0177] [Note 23] At least two of the gate wiring (16), source wiring (18), and drain wiring (20) extend in the second direction (Y) and are arranged to overlap in a plan view with two adjacent active regions (12) in the first direction (X). Nitride semiconductor device (10) as described in Appendix 22.

[0178] [Note 24] At least two of the gate wiring (16), source wiring (18), and drain wiring (20) are arranged so as to overlap in a plan view with the components (30, 32, 33) to which each wiring is electrically connected in two adjacent active regions (12) in the first direction (X). Nitride semiconductor device (10) as described in Appendix 23.

[0179] [Note 25] The gate structure (30) is A gate layer (34) containing acceptor-type impurities, A gate electrode (39) located on the gate layer (34), Includes, The gate layer (34) is The ridge portion (35) includes the upper surface on which the gate electrode (39) is located and the lower surface in contact with the nitride semiconductor layer (46), The extended portion (38) includes a lower surface (36G, 37G) in contact with the electron supply layer (50) and is thinner than the ridge portion (35), including, Nitride semiconductor device (10) as described in any one of the appendices 1 to 24.

[0180] [Note 26] Forming a buffer layer (42) on the substrate (40), To selectively form a mask portion (45) on the buffer layer (42), Forming a nitride semiconductor layer (46) on the buffer layer (42) and the mask portion (45), Forming a gate structure (30) on the nitride semiconductor layer (46), A source electrode (32) and a drain electrode (33) are formed on the nitride semiconductor layer (46) in a plan view along a first direction (X). Includes, Forming the nitride semiconductor layer (46) is The electron transport layer (48) is grown on the portion of the buffer layer (42) that is exposed from the mask portion (45). The electron transport layer (48) is grown so as to cover the mask portion (45). Forming an electron supply layer (50) on the electron transport layer (48), including, A method for manufacturing a nitride semiconductor device (10).

[0181] The above description is for illustrative purposes only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of symbols]

[0182] 10. Nitride semiconductor equipment 12…Active area 14...boundary area 14X…first boundary area 14Y…Second boundary area 16…Gate wiring 18…Source wiring 20... Drain wiring 22…Insulating layer 24…Gate Beer 26… Source Beer 28... Drain Via 30…Gate structure 30A1...Main section 1 30A2...Second Main Section 30B1...First connection section 30B2...Second connection section 32…Source electrode 33... Drain electrode 33A...First drain electrode 33B...Second drain electrode 34...Gate Layer 35... Ridge section 36...First extension part 37…Second extension part 38...Extension part 39… Gate stop gate 40... Circuit board 42... Buffer layer 42A...First buffer layer 42B...Second buffer layer 42C...Third buffer layer 42G... Buffer bottom 42F... Buffer top 42F1... Covering part 42F2…Exposed part 44… Mask layer 44G…Underside of mask 44F…Top of the mask 44H…Side of the mask 44X…Main mask 44Y... Boundary Mask 45... Mask section 46… Nitride semiconductor layer 48...Electronic Tracking Layer 48G1…1st bottom surface 48G2…2nd bottom surface 50...electron supply layer 52...Window section 54…High dislocation density region 54A...First high-dislocation region 54B...Second high-dislocation region 56... Low dislocation density region 56A...First low-transition region 56B...Second low-transition region 58... Boundary 100... Semiconductor layer< / hkil>

Claims

1. circuit board and A buffer layer located on the substrate, A mask portion selectively provided on the buffer layer, A nitride semiconductor layer comprising an electron transport layer and an electron supply layer located on the electron transport layer and having a larger band gap than the electron transport layer, A source electrode and a drain electrode are located on the nitride semiconductor layer and extend in a first direction in a plan view, A gate structure located on the nitride semiconductor layer and positioned between the source electrode and the drain electrode in a second direction intersecting the first direction in a plan view, Includes, The nitride semiconductor layer is A high dislocation density region located on the buffer layer, A low dislocation density region located on the mask portion, where the dislocation density is lower than that of the high dislocation density region, Includes, The gate structure is located on the low dislocation density region. Nitride semiconductor equipment.

2. The aforementioned gate structure is A gate layer containing acceptor-type impurities, A gate electrode located on the gate layer, Includes, The gate layer is entirely located on the low dislocation density region. The nitride semiconductor device according to claim 1.

3. The gate structure, in its entirety, overlaps with the mask portion in a plan view. The nitride semiconductor device according to claim 1.

4. The source electrode is aligned with the center of the mask portion in the second direction in a plan view. The nitride semiconductor device according to claim 1.

5. The drain electrode is a first drain electrode, The nitride semiconductor device further includes a second drain electrode, The second drain electrode is provided on the opposite side of the source electrode from the first drain electrode, The aforementioned gate structure is A first main portion located between the first drain electrode and the source electrode, A second main portion located between the second drain electrode and the source electrode, Includes, The aforementioned low dislocation density region is A first low dislocation region located below the first main portion, A second low dislocation region located below the second main portion, Includes, The source electrode spans the first low dislocation region and the second low dislocation region. The nitride semiconductor device according to claim 1.

6. The nitride semiconductor layer includes a boundary region located between the first low dislocation region and the second low dislocation region, where the dislocation density is higher than that of the low dislocation density region. The source electrode is located on the boundary portion, The nitride semiconductor device according to claim 5.

7. The drain electrode is located on the high dislocation density region. The nitride semiconductor device according to claim 1.

8. The drain electrode is located in the center of the high dislocation density region in the second direction. The nitride semiconductor device according to claim 1.

9. The dislocation density is the density of through-dislocations penetrating the interface between the electron transport layer and the electron supply layer. The nitride semiconductor device according to claim 1.

10. The dislocation density in the low dislocation density region is 1 × 10 4 cm －２ The following is: The nitride semiconductor device according to claim 1.

11. The low dislocation density region and the high dislocation density region are arranged alternately in the second direction. The nitride semiconductor device according to claim 1.

12. The electron transport layer has a hexagonal crystal structure. The first direction coincides with the <1-100> direction of the electron transport layer. The nitride semiconductor device according to claim 1.

13. It includes a plurality of mask portions arranged spaced apart in the second direction, The mask portion is one of the plurality of mask portions, The dimension of each of the plurality of mask portions in the second direction is smaller than the distance between the plurality of mask portions in the second direction. The nitride semiconductor device according to claim 1.

14. The drain electrode is located in the center between the mask portions in the second direction. The nitride semiconductor device according to claim 13.

15. The mask portion is made of SiO ２ and including at least one of SiN, The nitride semiconductor device according to claim 1.

16. Multiple active regions in which the nitride semiconductor layer is disposed on the buffer layer, A boundary region that separates the multiple active regions, Includes, Each of the nitride semiconductor layers located in the active region is separated from the nitride semiconductor layers located in other active regions by the boundary region. A nitride semiconductor device according to any one of claims 1 to 15.

17. The plurality of active regions are arranged in a matrix along the first and second directions. The nitride semiconductor device according to claim 16.

18. The gate structure and the gate wiring electrically connected thereto The source electrode and the source wiring electrically connected, The drain electrode and the drain wiring electrically connected, Includes, Two of the source wiring, drain wiring, and gate wiring overlap with the boundary region in a plan view. The nitride semiconductor device according to claim 16.

19. The aforementioned gate structure is A gate layer containing acceptor-type impurities, A gate electrode located on the gate layer, Includes, The aforementioned gate layer is A ridge portion including the upper surface on which the gate electrode is located and the lower surface in contact with the nitride semiconductor layer, An extended portion that includes a lower surface in contact with the electron supply layer and is thinner than the ridge portion, including, The nitride semiconductor device according to claim 1.

20. Forming a buffer layer on the substrate, To selectively form a mask portion on the buffer layer, Forming a nitride semiconductor layer on the buffer layer and the mask portion, Forming a gate structure on the nitride semiconductor layer, A source electrode and a drain electrode are formed on the nitride semiconductor layer, extending along a first direction in a plan view. Includes, Forming the nitride semiconductor layer is Growing an electron transport layer on the portion of the buffer layer exposed from the mask portion, To grow the electron transport layer so as to cover the mask portion, Forming an electron supply layer on the electron transport layer, including, A method for manufacturing nitride semiconductor devices.

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