Nitride semiconductor device and method for manufacturing the same

Abstract

To provide a highly reliable nitride semiconductor device with a wide gate drive area. [Solution] A first nitride semiconductor layer 13 constituting a channel layer, a second nitride semiconductor layer 14 having a larger band gap than the first nitride semiconductor layer 13 and constituting a carrier supply layer, a third nitride semiconductor layer 21 containing acceptor-type impurities, and a fourth nitride semiconductor layer 22 containing donor-type impurities are sequentially stacked, with the third nitride semiconductor layer 21 and the fourth nitride semiconductor layer 22 having a ridge shape. The fourth nitride semiconductor layer 22 is a low-temperature grown layer and has a microcrystalline structure.

Description

[Technical Field]

[0001] The present invention relates to a normally-off operating nitride semiconductor device, and more particularly to a technique for reducing gate leakage current and increasing the gate's breakdown voltage. [Background technology]

[0002] Switching elements in power semiconductor devices are required to have high breakdown voltage and low on-resistance. Therefore, power MOSFETs (Metal Oxide Semiconductor FETs) using Si, and IGBTs (Insulated Gate Bipolar Transistors), which combine bipolar transistors and MOSFETs, are used as switching elements. In addition, devices using SiC (Silicon Carbide) and Group III nitride semiconductors are known to have high breakdown voltage and low on-resistance. Among these, GaN-based power transistors using Group III nitride semiconductors have high breakdown voltage and low on-resistance, and are particularly capable of high-speed switching. Devices with a normally-off HEMT (High Electron Mobility Transistor) structure that take advantage of these strengths have been put into practical use.

[0003] Figure 4 is a cross-sectional view of a conventional normally-off nitride semiconductor device, a p-GaN gate HEMT. As shown, a buffer layer 112, a GaN channel layer 113, an AlGaN carrier supply layer 114, and a p-type GaN gate layer 121 are sequentially stacked on a substrate 111. The p-type GaN gate layer 121 is partitioned so that it remains only in the gate formation region 120, with a gate electrode 124 positioned on top. Figure 5 shows the energy band diagram of the semiconductor device shown in Figure 4, where EF represents the Fermi level, Ev represents the valence band level, and Ec represents the conduction band level. As shown in Figure 5, by connecting the p-type GaN gate layer 121 to the AlGaN carrier supply layer 114, the Fermi level is lowered and the region directly beneath the gate is depleted. That is, the channel disappears due to the depletion layer extending from the p-type GaN gate layer 121, achieving a normally-off state.

[0004] However, p-GaN gate HEMTs have a relatively low gate breakdown voltage, with the maximum gate drive voltage (Vg-max) typically remaining at 6-8V. The threshold voltage (Vth) is typically 1-2V, and the optimal on-operation gate voltage is usually 5-6V. This small gate voltage amplitude imposes significant constraints on gate drive design and can lead to reduced reliability. Therefore, increasing Vg-max and widening the gate drive region is desirable.

[0005] Structures for realizing normally-off nitride semiconductor devices and further widening the gate drive region have been proposed, for example, in Non-Patent Documents 1 and 2. The HEMT disclosed therein, as shown in Figure 6, has an n-GaN / p-GaN / AlGaN / GaN epitaxial structure in which the Schottky junction is replaced with a metal-np junction to improve gate reliability. In this figure, 122 is an n-type GaN layer.

[0006] Furthermore, another proposal for a similar purpose is presented in Patent Document 1. The HEMT disclosed therein has an n-GaN / i-GaN / p-GaN / AlGaN / GaN epitaxial structure in which the Schottky junction is replaced with a metal-nip junction, as shown in Figure 7. In this figure, 123 is an undoped i-type GaN layer. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] C. Wang et al., ``E-Mode pn Junction / AlGaN / GaN (PNJ) HEMTs'' IEEE Electron Device Lett., Vol. 41, No. 4, pp-545-548, April 2020. [Non-Patent Document 2] C. Wang et al., ``E-Mode pn Junction / AlGaN / GaN HEMTs with Enhanced Gate Reliability'' Proc. of ISPSD 2020, pp.14-17. [Patent Documents]

[0008] [Patent Document 1] U.S. Publication No. 11,721,751 [Overview of the project] [Problems that the invention aims to solve]

[0009] The nitride semiconductor devices disclosed in Non-Patent Documents 1 and 2 form a pn junction by depositing an n-type GaN layer 122 on a p-type GaN gate layer 121 on an AlGaN carrier supply layer 114, thereby reducing gate leakage current and increasing gate breakdown voltage. However, it is necessary to add a long-duration high-temperature activated annealing process to remove hydrogen from the sidewalls of the p-type GaN gate layer 121 after exposing them. This annealing process is performed after the surface of the AlGaN carrier supply layer 114 is exposed by dry etching, and there was a possibility that the relaxation of AlGaN strain could have a detrimental effect on the two-dimensional electron gas 115 at the AlGaN / GaN interface.

[0010] Furthermore, the nitride semiconductor device disclosed in Patent Document 1 reduces current leakage by depositing an i-type GaN layer 123 between the p-type GaN gate layer 121 and the n-type GaN layer 122, thereby avoiding electric field concentration between the gate electrode 124 and the n-type GaN layer 122. However, this also requires the addition of a long-duration high-temperature activated annealing process to remove hydrogen from the sidewalls of the p-type GaN gate layer 121.

[0011] In view of the above issues, one objective of the present invention is to provide a nitride semiconductor device that has a wide gate drive region and is highly reliable. [Means for solving the problem]

[0012] To solve the above problems, a nitride semiconductor device according to one embodiment is a normally-off operating nitride semiconductor device comprising: a first nitride semiconductor layer constituting a channel layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, having a larger band gap than the first nitride semiconductor layer and constituting a carrier supply layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing acceptor-type impurities; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and containing donor-type impurities; and a gate electrode that makes ohmic contact with the fourth nitride semiconductor layer, wherein the fourth nitride semiconductor layer is a low-temperature grown layer and has a microcrystalline structure.

[0013] In another embodiment, the nitride semiconductor device further comprises a fifth nitride semiconductor layer, which is a low-temperature grown layer and has a microcrystalline structure, between the third nitride semiconductor layer and the fourth nitride semiconductor layer in the above embodiment, providing high resistance.

[0014] A method for manufacturing a nitride semiconductor device according to one embodiment is a method for manufacturing a normally-off nitride semiconductor device, comprising the steps of: growing a first nitride semiconductor layer constituting a channel layer on a substrate or buffer layer; growing a second nitride semiconductor layer on the first nitride semiconductor layer, which has a larger band gap than the first nitride semiconductor layer and constitutes a carrier supply layer; growing a third nitride semiconductor layer containing acceptor-type impurities on the second nitride semiconductor layer; growing a fourth nitride semiconductor layer containing donor-type impurities on the third nitride semiconductor layer; selectively etching the third nitride semiconductor layer and the fourth nitride semiconductor layer to form a ridge shape; depositing a metal film over the entire surface, heat-treating and then forming a pattern, forming an ohmic contact source electrode and drain electrode on the first nitride semiconductor layer, and forming an ohmic contact gate electrode on the fourth nitride semiconductor layer, wherein the fourth nitride semiconductor layer is grown at a lower temperature than the third nitride semiconductor layer to form a microcrystalline structure.

[0015] In another embodiment, the method for manufacturing a nitride semiconductor device further includes a step of growing a high-resistance fifth nitride semiconductor layer between the step of growing the third nitride semiconductor layer and the step of growing the fourth nitride semiconductor layer in the above embodiment, wherein the fifth nitride semiconductor layer is grown at a lower temperature than the third nitride semiconductor layer to form a microcrystalline structure and is formed in a ridge shape together with the third nitride semiconductor layer and the fourth nitride semiconductor layer. [Effects of the Invention]

[0016] According to the present invention, a nitride semiconductor device with low gate leakage current and high gate breakdown voltage can be obtained. [Brief explanation of the drawing]

[0017] [Figure 1] It is a diagram schematically showing a cross section of a nitride semiconductor device according to the first embodiment. [Figure 2] It is a diagram showing the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 3] It is a diagram schematically showing a cross section of a nitride semiconductor device according to the second embodiment. [Figure 4] It is a diagram schematically showing a cross section of a conventional nitride semiconductor device having a p-GaN layer. [Figure 5] It is an energy band diagram of the nitride semiconductor device of FIG. 4. [Figure 6] It is a diagram schematically showing a cross section of a conventional nitride semiconductor device having an n-GaN layer. [Figure 7] It is a diagram schematically showing a cross section of a conventional nitride semiconductor device having an i-GaN layer.

Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals and described.

[0019] (First Embodiment) FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to the first embodiment of the present invention. The nitride semiconductor device of this embodiment includes a substrate 11, a buffer layer 12 formed on the surface of the substrate 11, and a first nitride semiconductor layer 13 and a second nitride semiconductor layer 14 sequentially epitaxially grown on the buffer layer 12. And a gate formation region 20 is formed on the second nitride semiconductor layer 14.

[0020] Furthermore, the nitride semiconductor device of this embodiment includes a source electrode 16 and a drain electrode 17 that are ohmic-contact with the second nitride semiconductor layer 14. The source electrode 16 and the drain electrode 17 are arranged at intervals.

[0021] The substrate 11 is, for example, a low-resistivity p-type Si substrate with a resistivity of about 0.02 Ω mm. In addition to a Si substrate, the substrate 11 may also be a SiC substrate, a GaN substrate, a sapphire substrate, etc. The thickness of the substrate 11 during the semiconductor process is, for example, about 675 μm to 1150 μm, and it is polished to about 300 μm before being formed into a chip. The substrate 11 is electrically connected to the source electrode 16, although this is not shown in the diagram.

[0022] The buffer layer 12, the first nitride semiconductor layer 13, the second nitride semiconductor layer 14, the third nitride semiconductor layer 21, and the fourth nitride semiconductor layer 22 are each formed by epitaxial growth on the substrate using the MOCVD method.

[0023] The buffer layer 12 is constructed by stacking multiple nitride semiconductor films, including a film having a superlattice structure. This buffer layer 12 is composed of, for example, a first buffer layer (not shown) consisting of an AlN film in contact with the surface of the substrate 11 and an AlGaN film on top of it, and a second buffer layer (not shown) consisting of an AlN / GaN superlattice layer stacked on this surface. The thickness of the first buffer layer is about 100 nm to 300 nm, and the thickness of the second buffer layer is about 500 nm to 2 μm. However, the buffer layer 12 is not limited to this and may be composed of a single AlGaN film or a composite film of AlGaN in which the Al composition is intermittently or continuously changed.

[0024] The first nitride semiconductor layer 13 is a channel layer made of GaN layers, with a thickness of approximately 500 nm to 1 μm. Furthermore, to suppress leakage current flowing through the first nitride semiconductor layer 13, impurities such as carbon may be added to make the region other than the surface semi-insulating. In that case, the concentration would be 1 × 10⁻⁶. 17 cm -3 That's all for 1 x 10 19 cm -3 It is preferable that it be to a certain degree.

[0025] The second nitride semiconductor layer 14 has a larger band gap than the first nitride semiconductor layer 13 and constitutes a carrier (electron) supply layer made of an AlGaN layer with a high Al composition. Its Al composition is approximately 15% to 30%, and its thickness is approximately 5 nm to 20 nm.

[0026] Thus, the first nitride semiconductor layer 13, which acts as a channel layer, and the second nitride semiconductor layer 14, which acts as a carrier supply layer, are composed of nitride semiconductors with different band gaps (Al composition), resulting in lattice mismatch. Due to the spontaneous polarization of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14, and the piezoelectric polarization due to lattice mismatch, the energy level of the conduction band of the first nitride semiconductor layer 13 at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 becomes lower than the Fermi level. Therefore, a two-dimensional electron gas (2DEG) 15 is generated within the first nitride semiconductor layer 13 at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14.

[0027] A third nitride semiconductor layer 21 and a fourth nitride semiconductor layer 22, epitaxially grown on the second nitride semiconductor layer 14, are formed in a ridge shape and, together with the gate electrode 24, constitute a gate formation region 20. The gate electrode 24 faces the second nitride semiconductor layer 14 with the third nitride semiconductor layer 21 and the fourth nitride semiconductor layer 22 in between, and the entire gate formation region 20 is positioned closer to the source electrode 16.

[0028] The third nitride semiconductor layer 21 consists of a p-type GaN layer, doped with Mg (magnesium) as an acceptor-type impurity, and its thickness is approximately 60 nm to 120 nm. The concentration of the acceptor-type impurity injected into the third nitride semiconductor layer 21 is 1 × 10⁻⁶ 19 cm -3 The above 3 x 10 19 cm -3The following are preferred. Note that the dopant of the p-type GaN layer may be other acceptor-type impurities such as Zn (zinc) instead of Mg. Immediately after growth, p-type formation is inactivated by simultaneously doped hydrogen, so annealing is performed in a nitrogen atmosphere at about 800 °C for 3 to 10 minutes to achieve p-type formation. The third nitride semiconductor layer 21 has a role of canceling out the two-dimensional electron gas 15 generated near the interface between the first nitride semiconductor layer 13 (electron traveling layer) and the second nitride semiconductor layer 14 (carrier supply layer) in the region directly below the gate formation region 20.

[0029] The fourth nitride semiconductor layer 22 is composed of a low-temperature grown n-type GaN layer (n-type LT-GaN layer) with a microcrystalline structure, doped with Si (silicon) as a donor-type impurity, and its thickness is about 20 nm to 50 nm. The microcrystalline structure can be realized, for example, by growing at a low temperature of 550 °C. This is a growth temperature about 500 °C lower than that of the first to third nitride semiconductor layers. The concentration of the donor-type impurity implanted into the fourth nitride semiconductor layer 22 is preferably 1×10 19 cm -3 or more. Note that the dopant of the n-type LT-GaN layer may be other donor-type impurities such as Ge (germanium) instead of Si.

[0030] The source electrode 16 and the drain electrode 17 in this embodiment may be composed of a multilayer metal film. This multilayer metal film is composed of, for example, a first metal layer (ohmic metal layer) in contact with the second nitride semiconductor layer 14, a second metal layer (main electrode metal layer) laminated on the first metal layer, and a third metal layer (barrier metal layer) laminated on the second metal layer. The first metal layer may be a Ti layer with a thickness of about 5 nm to 20 nm, the second metal layer may be an Al layer with a thickness of about 100 nm to 200 nm, and the third metal layer may be a TiN layer with a thickness of about 20 nm to 50 nm.

[0031] The gate electrode 24 may be a multilayer metal film similar to the source electrode 16 and the drain electrode 17, and is in contact with the fourth nitride semiconductor layer 22 in the gate formation region 20.

[0032] In the gate formation region 20, the gate electrode 24 is in ohmic contact with the surface layer of the fourth nitride semiconductor layer 22, and a potential is generated near the interface of the pn junction between the fourth nitride semiconductor layer 22 and the third nitride semiconductor layer 21 due to depletion.

[0033] The ionization acceptors contained in the third nitride semiconductor layer 21 raise the energy levels of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 below the third nitride semiconductor layer 21. As a result, the energy level of the conduction band at the heterojunction interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 becomes higher than the Fermi level. Therefore, a two-dimensional electron gas 15 is not formed directly below the gate formation region 20 due to spontaneous polarization of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14, as well as piezoelectric polarization due to their lattice mismatch.

[0034] Therefore, when no bias is applied to the gate electrode 24 (at 0V), the channel formed by the two-dimensional electron gas 15 is blocked directly below the gate formation region 20, and a normally-off HEMT is realized. When an appropriate on-voltage (for example, 3V to 6V) is applied to the gate electrode 24, a channel is induced in the first nitride semiconductor layer 13 directly below the second nitride semiconductor layer 14 in the gate formation region 20, and the two-dimensional electron gases 15 on both sides of the gate formation region 20 are connected. As a result, the source and drain become conductive. For use, for example, a predetermined voltage is applied between the source electrode 16 and the drain electrode 17, with the drain electrode 17 being positive. In this state, with the source electrode 16 as the reference potential (0V), an off voltage (0V) and an on voltage (5V) are applied to the gate electrode 24.

[0035] Figure 2 is a cross-sectional view illustrating an example of the manufacturing process of a nitride semiconductor device according to the first embodiment, and shows the cross-sectional structure at multiple stages in the manufacturing process.

[0036] In this process, a buffer layer 12, a first nitride semiconductor layer 13 (channel layer), a second nitride semiconductor layer 14 (carrier supply layer), and a third nitride semiconductor layer 21 (p-type GaN layer) are sequentially formed on the substrate 11. These layers are formed by epitaxial growth at a temperature of approximately 1050°C using the MOCVD (Metal Organic Chemical Vapor Deposition) method. Subsequently, the third nitride semiconductor layer 21 is annealed in a nitrogen atmosphere at approximately 800°C for 3 to 20 minutes to activate it. Then, the growth temperature is lowered to 550°C, and a fourth nitride semiconductor layer 22, consisting of an n-type LT-GaN layer, is grown (Figure 2a).

[0037] Subsequently, an etching mask 25, such as a photoresist or SiO2 film, is patterned only in the area corresponding to the gate formation region 20, and the fourth nitride semiconductor layer 22 and the third nitride semiconductor layer 21 are selectively etched away by dry etching containing a chlorine-based gas (Figure 2b). As a result, the fourth nitride semiconductor layer 22 and the third nitride semiconductor layer 21 remain only in the gate formation region 20, and a two-dimensional electron gas 15 is generated at the interface of the first nitride semiconductor layer 13 (channel layer) and the second nitride semiconductor layer 14 (carrier supply layer) other than below the gate formation region 20.

[0038] In this embodiment, the growth of the fourth nitride semiconductor layer 22, which is made of an n-type LT-GaN layer, does not deactivate the third nitride semiconductor layer 21, which is made of a p-type GaN layer. Therefore, the conventional process that was required, namely the long-duration high-temperature activation annealing process (for example, an annealing process at approximately 800°C for 30 minutes in a nitrogen atmosphere) to remove hydrogen from the sidewalls of the p-type GaN layer, can be omitted.

[0039] Subsequently, a metal film is deposited over the entire surface by a conventional sputtering or vapor deposition method. As described above, this metal film may consist of a multilayer titanium (Ti) / aluminum (Al) metal film. Next, the metal film is subjected to RTA treatment at 550°C or higher, and then a pattern is formed by a conventional photolithography method to form the source electrode 16, drain electrode 17, and gate electrode 24 (Figure 2c). The source electrode 16 and drain electrode 17 make ohmic contact with the second nitride semiconductor layer 14 (carrier supply layer), and the gate electrode 24 makes ohmic contact with the fourth nitride semiconductor layer 22. Although not shown, the source electrode 16 is electrically connected to the substrate 11.

[0040] In this case, the source electrode 16 and drain electrode 17 may be formed after partially or completely removing the second nitride semiconductor layer 14 (carrier supply layer) below the source electrode 16 and drain electrode 17 in advance. In this case, the ohmic contact resistance of the source electrode 16 and drain electrode 17 tends to decrease further because they are closer to the two-dimensional electron gas 15 at the interface between the first nitride semiconductor layer 13 (channel layer) and the second nitride semiconductor layer 14 (carrier supply layer).

[0041] When the IG-VG characteristics of the nitride semiconductor device fabricated in this embodiment were evaluated as described above, it showed a low gate leakage current and a high gate breakdown voltage, achieving characteristics equivalent to those of the AlGaN / GaN HEMT with a pn junction described in Non-Patent Documents 1 and 2.

[0042] (Second Embodiment) Figure 3 is a cross-sectional view illustrating the configuration of a nitride semiconductor device according to a second embodiment of the present invention. It is basically the same as the first embodiment except for the changes relating to the fifth nitride semiconductor layer 23.

[0043] The fifth nitride semiconductor layer 23 is formed between the third nitride semiconductor layer 21 and the fourth nitride semiconductor layer 22, and is formed by epitaxial growth, similar to the first to fourth nitride semiconductor layers. However, the fifth nitride semiconductor layer 23 is a high-resistance, low-temperature grown layer. The third nitride semiconductor layer 21, the fifth nitride semiconductor layer 23, and the fourth nitride semiconductor layer 22, which is an n-type LT-GaN layer, are sequentially epitaxially grown on the second nitride semiconductor layer 14 and are formed in a ridge shape, constituting a gate formation region 20 together with the gate electrode 24. The gate electrode 24 faces the second nitride semiconductor layer 14 with the third nitride semiconductor layer 21, the fifth nitride semiconductor layer 23, and the fourth nitride semiconductor layer 22 in between, and the entire gate formation region 20 is positioned closer to the source electrode 16.

[0044] In this embodiment, the fifth nitride semiconductor layer 23 consists of a microcrystalline GaN layer grown at 550°C, which is about 500°C lower than the first to third nitride semiconductor layers 21, and is not intentionally doped. That is, it is an i-type LT-GaN layer, and its thickness is about 5 nm to 30 nm. Furthermore, the fourth nitride semiconductor layer 22 also has a microcrystalline structure grown at 550°C, which is about 500°C lower than the first to third nitride semiconductor layers 21, and its thickness, dopant, and other details are the same as those described in the first embodiment.

[0045] Therefore, in this embodiment, neither the growth of the fifth nitride semiconductor layer 23, which is made of an i-type LT-GaN layer, nor the growth of the fourth nitride semiconductor layer 22, which is made of an n-type LT-GaN layer, deactivates the third nitride semiconductor layer 21, which is made of a p-type GaN layer. As a result, the conventional process that was previously required, namely the long-duration high-temperature activation annealing process (for example, an annealing process at approximately 800°C for 30 minutes in a nitrogen atmosphere) to remove hydrogen from the sidewalls of the p-type GaN layer, can be omitted.

[0046] When the IG-VG characteristics of the nitride semiconductor device fabricated as described above were evaluated, we were able to obtain characteristics superior to those of the AlGaN / GaN HEMT having a pn junction disclosed in Non-Patent Document 1 and Non-Patent Document 2.

[0047] While embodiments of the present invention have been described above, various modifications are possible based on the spirit of the invention. For example, in the above embodiments, a buffer layer was provided on the substrate, but this can be omitted by setting an appropriate substrate and growth conditions.

[0048] Furthermore, in the above embodiment, the source electrode, drain electrode, and gate electrode were made of the same material, but it is not necessarily required that they be made of the same material. However, by using the same material as in the above embodiment, it is possible to form them simultaneously.

[0049] Furthermore, in the above embodiment, the source electrode, drain electrode, and gate electrode were formed simultaneously, but the source electrode may be provided later. In this case, the source electrode is formed after depositing a passivation film (not shown) made of a SiN film, SiO2 film, or the like, so as to cover the surface of the carrier supply layer and the sides and surface of the gate formation region, thereby forming an opening. By arranging the source electrode pattern to cover the gate formation region, it is possible to provide a field plate effect. However, forming the source electrode, drain electrode, and gate electrode simultaneously can reduce the number of steps involved. [Explanation of symbols]

[0050] 11, 111: Circuit board 12, 112: Buffer layer 13: First nitride semiconductor layer 14: Second nitride semiconductor layer 15, 115: Two-dimensional electron gas 16, 116: Source electrode 17, 117: Drain electrode 20, 120: Gate formation region 21: Third nitride semiconductor layer 22: Fourth nitride semiconductor layer 23: Fifth nitride semiconductor layer (high-resistance low-temperature grown GaN layer) 24, 124: Gate plate 25: Etching mask 113: GaN channel layer 114: AlGaN carrier supply layer 121: p-type GaN gate layer 122:n-type GaN layer 123: i-type GaN layer

Claims

1. A normally off nitride semiconductor device, The first nitride semiconductor layer constituting the channel layer, A second nitride semiconductor layer is formed on the first nitride semiconductor layer, has a larger band gap than the first nitride semiconductor layer, and constitutes a carrier supply layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer and contains acceptor-type impurities, A fourth nitride semiconductor layer is formed on the third nitride semiconductor layer and contains donor-type impurities, The device comprises a gate electrode that makes ohmic contact with the fourth nitride semiconductor layer, The nitride semiconductor device is characterized in that the fourth nitride semiconductor layer is a low-temperature grown layer and has a microcrystalline structure.

2. A high-resistance fifth nitride semiconductor layer is further provided between the third nitride semiconductor layer and the fourth nitride semiconductor layer. The nitride semiconductor device according to claim 1, characterized in that the fifth nitride semiconductor layer is a low-temperature grown layer and has a microcrystalline structure.

3. A method for manufacturing a nitride semiconductor device that operates normally off, A step of growing a first nitride semiconductor layer that constitutes a channel layer on a substrate or buffer layer, A step of growing a second nitride semiconductor layer on the first nitride semiconductor layer, the second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer and constituting a carrier supply layer, A step of growing a third nitride semiconductor layer containing acceptor-type impurities on the second nitride semiconductor layer, A step of growing a fourth nitride semiconductor layer containing donor-type impurities on the third nitride semiconductor layer, A step of selectively etching the third nitride semiconductor layer and the fourth nitride semiconductor layer to form a ridge shape, The process includes the steps of depositing a metal film over the entire surface, forming a pattern after heat treatment, forming an ohmic contact source electrode and drain electrode on the first nitride semiconductor layer, and forming an ohmic contact gate electrode on the fourth nitride semiconductor layer, A method for manufacturing a nitride semiconductor device, characterized in that the fourth nitride semiconductor layer is grown at a lower temperature than the third nitride semiconductor layer to form a microcrystalline structure.

4. The process further includes a step of growing a high-resistance fifth nitride semiconductor layer between the step of growing the third nitride semiconductor layer and the step of growing the fourth nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to claim 3, characterized in that the fifth nitride semiconductor layer is grown at a lower temperature than the third nitride semiconductor layer to form a microcrystalline structure, and is formed in a ridge shape together with the third nitride semiconductor layer and the fourth nitride semiconductor layer.

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