Electro-optical devices and electronic equipment

Abstract

This helps to suppress the deterioration of display quality caused by differences in initialization conditions. [Solution] When the scan line block of the (i-1)th Y block Bly(i-1) is "primarily selected", the scan line block of the i-th Y block Bly(i) is "secondarily selected". In "primarily selected", the initialization period (A), compensation period (B), write period (C), and initialization period (D) are executed, but in "secondarily selected", only the initialization periods (A) and (D) are executed. As a result, the initialization period (A) for the first horizontal scan when the i-th scan line block is "primarily selected" is executed.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] An electro-optical device using, for example, an OLED as a display element is known. OLED is an abbreviation for Organic Light Emitting Diode. In this type of electro-optical device, high definition and miniaturization are required. To achieve high definition, it is necessary to increase the number of scanning lines and the number of data lines. However, when the number of data lines increases, a large number of output signal lines are required from the drive circuit. Therefore, a technique has been proposed in which a liquid crystal element is used as a display element, and one output signal line is branched by a distribution circuit and supplied to a data line (see, for example, Patent Document 1).

[0003] When, for example, an OLED is used as a display element, initialization may be performed to apply an initial voltage to a data line or the like before supplying a data signal of a voltage corresponding to gradation to the OLED (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, if the initialization conditions differ, display unevenness or the like may occur, leading to a deterioration in display quality.

Means for Solving the Problems

[0006] To solve the above problems, an electro-optical apparatus according to one aspect of the present disclosure includes a data trunk, a first data branch group and a second data branch group consisting of a plurality of data branch lines, a first pixel circuit group consisting of a first pixel circuit provided corresponding to a first scan line and the first data branch group, a second pixel circuit group consisting of a second pixel circuit provided corresponding to a second scan line and the second data branch group, a first distribution circuit for distributing a data signal supplied to the data trunk to a plurality of data branch lines included in the first data branch group, a second distribution circuit for distributing the data signal supplied to the data trunk to a plurality of data branch lines included in the second data branch group, and a control circuit, wherein the control circuit operates during the first horizontal scanning period of the first scan line. The system controls the following: a first initialization which applies an initial voltage to the first data branch line group; a first write which supplies the data signal to the first pixel circuit group via the first data branch line after the first initialization; a second initialization which applies the initial voltage to the first data branch line group and the second data branch line group after the first write; a third initialization which applies the initial voltage to the second data branch line group during the second horizontal scanning period of the second scan line; a second write which supplies the data signal to the second pixel circuit group via the second data branch line after the third initialization; and a fourth initialization which applies the initial voltage to the second data branch line group after the second write, such that the second initialization and the third initialization are temporally continuous. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing the configuration of the electro-optical device according to the first embodiment. [Figure 2] This is a diagram showing the electrical configuration of an electro-optical device. [Figure 3] This diagram shows the configuration of a pixel block in an electro-optical device. [Figure 4] This diagram shows a pixel circuit in an electro-optical device. [Figure 5] This figure shows a scanning line drive circuit in an electro-optical device. [Figure 6]This diagram shows the Y block in a scan line drive circuit. [Figure 7] This is a timing chart showing the operation of an electro-optical device. [Figure 8] This is a diagram illustrating the operation of an electro-optical device. [Figure 9] This is a diagram illustrating the operation of an electro-optical device. [Figure 10] This is a diagram illustrating the operation of an electro-optical device. [Figure 11] This is a diagram illustrating the operation of an electro-optical device. [Figure 12] This is a diagram illustrating the operation of an electro-optical device. [Figure 13] This diagram shows the initialization timing in an electro-optical device. [Figure 14] This diagram shows the control signal for initialization in an electro-optical device. [Figure 15] This figure shows the initialization timing in the electro-optical device according to the second embodiment. [Figure 16] This is a perspective view showing a head-mounted display using an electro-optical device. [Figure 17] This figure shows the optical configuration of a head-mounted display. [Figure 18] This figure shows the initialization timing in an electro-optical device related to a comparative example. [Figure 19] This figure shows the control signal for initialization in an electro-optical device relating to a comparative example. [Modes for carrying out the invention]

[0008] Hereinafter, an electro-optical apparatus according to an embodiment will be described with reference to the drawings. Note that the dimensions and scale of each part in each drawing have been appropriately changed from those of the actual parts. Furthermore, the embodiments described below are preferred examples and are subject to various technically preferred limitations, but the scope of this disclosure is not limited to these forms unless otherwise stated in the following description to specifically limit this disclosure.

[0009] FIG. 1 is a perspective view showing an electro-optical device 10. The electro-optical device 10 is a microdisplay panel that displays an image in, for example, a head-mounted display. The electro-optical device 10 includes a plurality of pixel circuits and a driving circuit that drives the pixel circuits. The pixel circuit and the driving circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be other semiconductor substrates.

[0010] As shown in this figure, the electro-optical device 10 is housed in a frame-shaped case 192 having an opening 191. One end of an FPC (Flexible Printed Circuits) substrate 194 is connected to the electro-optical device 10. A plurality of terminals 196 are provided at the other end of the FPC substrate 194. The plurality of terminals 196 are connected to a host device (not shown). The host device supplies video data to the electro-optical device 10. The video data is data indicating a video to be displayed by the electro-optical device 10.

[0011] In the figure, the X direction indicates the horizontal direction of the image displayed on the electro-optical device 10, and the Y direction indicates the vertical direction of the image. The two-dimensional plane defined by the X direction and the Y direction is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X direction and the Y direction, and indicates the light emission direction of light emitted from a light-emitting element described later.

[0012] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a scanning line driving circuit 40, a data signal output circuit 50, and a display area 100.

[0013] In the display area 100, in this embodiment, 56 scanning lines 12 blocked every 56 are provided extending in the X direction, and a plurality of pairs of data trunks 14a and 14b are provided extending in the Y direction. Pixel blocks BLp are provided in a matrix corresponding to the intersection of the 56 blocked scanning lines 12 and one pair of data trunks 14a and 14b.

[0014] In this embodiment, for example, the total number of scan lines 12 is 1960. If we refer to the 56 block-shaped scan lines 12 as scan line blocks, there will be 35 (=1960 ÷ 56) scan line blocks. Pixel blocks BLp correspond to scan line blocks, so there will be 35 of them arranged in a single row along the Y direction. Multiple pixel circuits are arranged within each pixel block BLp, as will be described later.

[0015] The control circuit 30 controls each part based on the video data Vid and the synchronization signal Sync supplied from the host device. The video data Vid is supplied in synchronization with the synchronization signal Sync, and specifies the grayscale level of each pixel in the image to be displayed by the electro-optical device 10, for example, using 8 bits for each RGB component. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data Vid. The control circuit 30 controls the driving of the pixel circuit via the scan line drive circuit 40 and the data signal output circuit 50. For this reason, the control circuit 30, the scan line drive circuit 40, and the data signal output circuit 50 together are sometimes referred to as a broad control circuit that controls the electro-optical device 10.

[0016] The control circuit 30 outputs a control signal Ctr-Y to drive the scan line drive circuit 40 based on the vertical synchronization signal included in the synchronization signal Sync, and outputs a control signal Ctr-X to drive the data signal output circuit 50 based on the horizontal synchronization signal.

[0017] The scan line driving circuit 40 is a circuit that, during the vertical scanning period, selects 1960 scan lines 12 for each scan line block, sequentially selects 56 scan lines 12 in the selected scan line block one by one, and sequentially selects the pixel circuits located on the selected scan lines 12 as scanning targets.

[0018] The scan line drive circuit 40 outputs scan signals / Gwr(1) to / Gwr(1960) sequentially to scan lines 12 from 1 to 1960. To distinguish between the 35 scan line blocks, an integer i between 1 and 35 is used. The scan line drive circuit 40 then sequentially supplies scan signals / Gwr(56i-55)~ / Gwr(56i) to the 56 scan lines 12 corresponding to the i-th scan line block. The prefix " / " in the signal code indicates negative logic. Furthermore, the scan line driving circuit 40 outputs a control signal / Gini(i) to control initialization corresponding to the i-th scan line block, and outputs control signals / Sel_1(i)~ / Sel_4(i) to sequentially select the pixel circuits located on the selected scan line 12 as scanning targets. Although omitted in Figure 2, the scan line driving circuit 40 also outputs a control signal / Gset(i) corresponding to the i-th scan line block.

[0019] An integer j between 1 and 1960 is used to distinguish the scan lines 12. Although not shown in Figure 2, the scan line drive circuit 40 also outputs control signals / Gcmp(j) and / Gel(j) corresponding to the j-th scan line 12.

[0020] i and j are related in that j is the result of subtracting 1 from j, dividing that value by 56, and adding 1 to the integer part of the quotient. For example, if j is 112, then i is 2, which is the result of subtracting 1 from j to get 111, dividing that by 56, and adding 1 to the integer part of the quotient (1). In other words, the 112th scan line 12 belongs to the second scan line block.

[0021] The data signal output circuit 50 is a circuit that outputs a data signal with a voltage corresponding to the grayscale of the pixel circuit to be scanned in the pixel block BLp to the data trunk lines 14a and 14b. Specifically, the data signal output circuit 50 is provided with a latch circuit L and DA conversion circuits 52a and 52b. A latch circuit L is provided in a one-to-one correspondence with one pair of data trunk lines 14a and 14b. The latch circuit L sequentially transfers the video data Vdata supplied from the control circuit 30 and latches one row at a time. One latch circuit L latches the video data Vdata corresponding to eight pixel circuits in one row of the pixel block BLp, and outputs the latched video data Vdata as video data Vta and Vtb in a time-division manner in accordance with the timing when the control signals / Sel_1(i) to / Sel_4(i) sequentially reach the L level. In this explanation, voltage refers to the voltage between two points, and unless otherwise specified, it is based on the L level, which is the ground potential.

[0022] The DA conversion circuit 52a is provided in a one-to-one correspondence with the data trunk line 14a. The DA conversion circuit 52a converts the video data Vta output from the latch circuit L into an analog voltage data signal Vda and outputs it to the data trunk line 14a. Similarly, the DA conversion circuit 52b is provided in a one-to-one correspondence with the data trunk line 14b. The DA conversion circuit 52a converts the video data Vtab analog voltage output from the latch circuit L into a data signal Vdb and outputs it to the data trunk line 14b.

[0023] The timing and specific video data Vta and Vtb output by the DA conversion circuits 52a and 52b, as well as the voltage data signals Vda and Vdb output, will be described later.

[0024] Figure 3 shows the configuration of pixel blocks BLp in the display area 100. As described above, pixel blocks BLp are provided corresponding to the intersections of the 56 blocked scan lines 12 and one pair of data trunk lines 14a and 14b. In other words, for the 56 blocked scan lines 12, there are as many pixel blocks BLp along the X direction as there are pairs of data trunk lines 14a and 14b. Here, we will describe the pixel block BLp provided in response to the intersection of the 56 scan lines 12 corresponding to the i-th block and any pair of data trunk lines 14a and 14b.

[0025] In pixel block BLp, the data trunk 14a branches into four data branch lines 14c, 14d, 14g, and 14h, respectively, via transistors 62c, 62d, 62g, and 62h. Similarly, in pixel block BLp, the data trunk 14b branches into four data branch lines 14e, 14f, 14i, and 14j, respectively, via transistors 62e, 62f, 62i, and 62j. Data branch lines 14c to 14j are provided, each extending in the Y direction.

[0026] The gate nodes of transistors 62c and 62e are supplied with the control signal / Sel_1(i) in common. Similarly, the gate nodes of transistors 62d and 62f are supplied with the control signal / Sel_2(i) in common, and the gate nodes of transistors 62g and 62i are supplied with the control signal / Sel_3(i) in common. Finally, the gate nodes of transistors 62h and 62j are supplied with the control signal / Sel_4(i) in common.

[0027] In the pixel block BLp, the pixel circuits 110 are arranged in a matrix corresponding to the intersections of the 56 scan lines 12 and the 8 data branch lines 14c to 14j. In the pixel block BLp, the pixel circuits 110 are arranged in the order of R1, B1, G1, G2, R2, B2, G3, and G4, which are assigned color codes, when viewed in one row along the X direction. R1 and R2 of the pixel circuit 110 include an OLED that emits red light, B1 and B2 of the pixel circuit 110 include an OLED that emits blue light, and G1, G2, G3 and G4 of the pixel circuit 110 include an OLED that emits green light. Although the pixel circuits 110 emit different colored light from the OLED, their electrical circuit configurations are identical. Therefore, when distinguishing pixel circuits by data branch lines or color, the color code will be added to "110". For example, the code for the red pixel circuit corresponding to data branch line 14c will be "110R1". In cases where pixel circuits are not distinguished by data branch lines or color, the code will be "110".

[0028] In pixel block BLp, the color of one dot is represented by additive color mixing of light emitted from the OLEDs of pixel circuits 110R1, 110B1, 110G1, and 110G2, which are among the eight pixel circuits 110 in one row. Similarly, the color of one dot is represented by additive color mixing of light emitted from the OLEDs of pixel circuits 110R2, 110B2, 110G3, and 110G4. In other words, two dots of adjacent colors in the X direction are represented by the eight pixel circuits 110 in one row of pixel block BLp. On the other hand, in the pixel block BLp, 56 pixel circuits 110 of the same color are arranged in the Y direction. Therefore, in this embodiment, the pixel block BLp represents a 2 dot × 56 dot color in the X direction × Y direction.

[0029] In the pixel block BLp, transistors 64a and 64b are provided. For transistor 64a, the source node is connected to the voltage Vini power supply line, and the drain node is connected to the data trunk line 14a. For transistor 64b, the source node is connected to the voltage Vini power supply line, and the drain node is connected to the data trunk line 14b. The gate nodes of transistors 62a and 62b are supplied with a common control signal / Gset(i).

[0030] In pixel block BLp, transistors 66c to 66j are provided in a one-to-one correspondence with data branches 14c to 14j. The source nodes of transistors 66c to 66j are connected to the power supply line of voltage Vini, and the gate nodes are supplied with the control signal / Gini(i). The drain nodes of transistors 66c to 66j are connected in order to data branches 14c to 14j.

[0031] Here, we have described the pixel block BLp corresponding to the intersection of the 56 scan lines 12 corresponding to the i-th block and an arbitrary pair of data trunk lines 14a and 14b, but the configuration is similar for other pixel blocks BLp that share the same 56 scan lines 12.

[0032] Figure 4 shows the configuration of the pixel circuit 110. Although the light emitted from the OLED, which is the light-emitting element, differs in color, the electrical configuration of the pixel circuits 110 is the same for all of them. For this reason, the pixel circuit 110 will be explained using as an example the pixel circuit 110R1 that corresponds to the intersection of an arbitrary k-th scan line 12 and a data branch line 14c among the 56 scan lines 12 corresponding to the i-th block.

[0033] Note that k is an integer between 1 and 56. In the i-th scanline block, the k-th scanline 12 is related to the j-th scanline when viewed as a whole, by subtracting (55-(k-1)) from the product of i multiplied by 56. For example, in the second scanline block, the third scanline 12 is related to the 59th scanline when viewed as a whole, by subtracting (55-3+1) from 112, which is the product of 2 multiplied by 56.

[0034] As shown in the figure, the pixel circuit 110R1 includes P-channel MOS type transistors 121-124, an OLED 130, and a capacitive element 140. In addition, the scan signal / Gwr(k), as well as control signals / Gcmp(k) and / Gel(k), are supplied to the pixel circuit 110 of the kth row in the i-th scan line block from the scan line drive circuit 40.

[0035] OLED130 is an example of a light-emitting element, in which a light-emitting layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The pixel electrode 131 is light-reflective, and the common electrode 133 is both light-reflective and light-transmitting. In OLED130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting layer 132 to generate excitons, and white light is produced.

[0036] In this embodiment, when a color display is achieved, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective, semi-transparent layer (not shown), and is emitted at a resonant wavelength set to correspond to one of the colors R (red), G (green), or B (blue). A color filter (not shown) is provided on the light emission side of the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and color filter before being visible to the observer. Furthermore, if the electro-optical device 10 simply displays a monochrome image consisting only of light and dark areas, the above-mentioned color filter is omitted.

[0037] In the k-th row, the transistor 121 of the pixel circuit 110 has its gate node g connected to the drain node of transistor 122 and one end of the capacitive element 140, its source node s connected to the voltage Vel wiring 116, and its drain node d connected to the source node of transistor 123 and the source node of transistor 124. The other end of the capacitive element 140 is connected to wiring 116 with a constant voltage, for example, voltage Vel. Therefore, the capacitive element 140 maintains the voltage between the gate node g and the source node s in the transistor 121. The capacitive element 140 may be formed by sandwiching an insulating film between electrodes made of different wiring layers on a semiconductor substrate, or a capacitance parasitic on the gate node g of the transistor 121 may be used.

[0038] In the transistor 122 of the pixel circuit 110 in the kth row, the gate node is connected to the scan line 12 of the kth row to which the scan signal / Gwr(k) is supplied, and the source node is connected to the data branch line 14c. In the transistor 123 of the pixel circuit 110 in the kth row, a control signal / Gcmp(k) is supplied to the gate node, and the drain node is connected to the data branch line 14c. In the transistor 124 of the pixel circuit 110 in the kth row, a control signal / Gel(k) is supplied to the gate node, and the drain node is connected to the pixel electrode 131, which is the anode of the OLED 130. The common electrode 133, which functions as the cathode of the OLED130, is connected to the power supply line for voltage Vct.

[0039] Although the pixel circuit 110R1 is used as an example here, other pixel circuits 110 located on the k-th scan line 12 in the i-th scan line block have a similar electrical configuration, differing only in the data branch line 14c to which they are connected. Similarly, other pixel circuits located on scan lines 12 other than the k-th line also have a similar configuration.

[0040] Figure 5 shows the scan line drive circuit 40 in the electro-optical device 10. As shown in the figure, the scan line drive circuit 40 is provided with Y blocks Bly(1) to Bly(35) in order, corresponding one-to-one to the 35 scan line blocks. The Y block corresponding to the i-th scan line block is denoted as Bly(i).

[0041] The Y block Bly(i) outputs the scan signals / Gwr(56i-55)~ / Gwr(56i) sequentially to scan lines 12 from line (56i-55) to line (56i) in the corresponding scan line block. Furthermore, the Y block Bly(i) outputs the following control signals to the i-th scanline block: / Gini(i) for initialization, / Gset(i) for pre-sampling preparation, and / Sel_1(i)~ / Sel_4(i) for sampling.

[0042] Figure 6 shows the configuration of the i-th Y block Bly(i) in the scan line drive circuit 40. As shown in the figure, block Y Bly(i) includes a 56-stage shift register 420 and an auxiliary circuit 430 that outputs control signals / Gini(i), / Gset(i), and / Sel_1(i) to / Sel_4(i). Although not shown in Figures 5 and 6, Y block BLY(i) further outputs control signals / Gcmp(56i-55)~ / Gcmp(56i) and / Gel(56i-55)~ / Gcmp(56i) corresponding to scan line 12 from line (56i-55) to line (56i).

[0043] In this scan line driving circuit 40, during the duration of one frame, one Y block from Bly(1) to Bly(35) is selected in order, and within the selected Y block, the 56 scan lines 12 are horizontally scanned sequentially for each horizontal scan period. In other words, the period during which one Y block is selected is 56 horizontal scan periods, and the 56 scan lines 12 belonging to one scan line block are horizontally scanned for each horizontal scan period. In this explanation, the duration of one frame refers to the period required to display one frame of the image specified by the video data Vid. The length of one frame is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz. The horizontal scan period is the period required to horizontally scan one line.

[0044] Furthermore, when the i-th Y block Bly(i) is selected, the Y block Bly(i) outputs the control signals / Gset(i) and / Sel_1(i) to / Sel_4(i) for each horizontal scanning period. In this embodiment, the i-th Y block Bly(i) outputs the control signal / Gini(i) not only when its own Y block Bly(i) is selected, but also when the previous block, the (i-1)th Y block Bly(i-1), is selected for each horizontal scanning period. In this explanation, "outputting a signal during a certain period" means that the signal is at an active level or a significant level during part or all of that period. For example, when a negative logic signal is output during a certain period, it means that the signal is at an L level during part or all of that period, and at an H level outside of that period.

[0045] Figure 7 is a timing chart illustrating the operation of the electro-optical device 10. In the electro-optical device 10, horizontal scanning is performed in the order of rows 1, 2, 3, ..., 1959, 1960 during one frame (V). Note that in Figure 7, the vertical scale indicating voltage is not necessarily aligned across all signals.

[0046] The operation of the pixel circuit 110 during the horizontal scanning period (H) in each row is roughly the same. Furthermore, the operation of the pixel circuit 110 in each column of a row scanned during a given horizontal scanning period (H) is also roughly the same. Therefore, the following explanation will focus on the pixel circuit 110R1 in the kth row of the i-th scan line block, which corresponds to the data branch line 14c.

[0047] In the electro-optical device 10, the horizontal scanning period (H) is divided into four periods in order of time: initialization period (A), compensation period (B), writing period (C), and initialization period (D). In addition, the operation of the pixel circuit includes an additional light emission period (E) to the above four periods. Note that the light emission period (E) in the k-th row is the period in Figure 7 when the control signal / Gel(k) is at the L level.

[0048] The initialization period (A) is the period during which a voltage Vini is applied to the gate node g of transistor 121 to turn on transistor 121 at the start of the next compensation period (B).

[0049] In detail, during the initialization period (A) of the horizontal scanning period (H) in the i-th scan line block where the k-th row is selected, the control signal / Gini(i) is at the L level and the control signal / Gset(i) is at the H level. Also, during the initialization period (A), the control signals / Sel_1(i)~ / Sel_4(i) are at the H level. Therefore, in the pixel block BLp corresponding to the i-th scan line block, transistors 66c~66j are turned on, and transistors 64a and 64b are turned off. Also, transistors 62c~62j are turned off.

[0050] In this explanation, the "on state" of a transistor refers to a state where the source node and drain node are electrically closed, resulting in a low impedance state. Conversely, the "off state" of a transistor refers to a state where the source node and drain node are electrically open, resulting in a high impedance state.

[0051] Furthermore, during the initialization period (A) of the horizontal scanning period (H) in which the k-th row is selected, the scan signal / Gwr(k) is at the L level, the control signal / Gcmp(k) is at the H level, and the control signal / Gel(k) is at the H level. Therefore, in the pixel circuit 110R1 of the kth row, transistors 121 and 122 are turned on, and transistors 123 and 124 are turned off.

[0052] Therefore, during the initialization period (A), as shown in Figure 8, the voltage Vini is applied to the data branch line 14c via transistor 66c. Furthermore, in the k-th row pixel circuit 110R1, this voltage Vini is applied to one end of the capacitive element 140 and the gate node g of transistor 121, sequentially via the data branch line 14c and transistor 122. During the initialization period (A), transistor 121 is in the ON state, but transistor 124 is in the OFF state, so no current flows through the OLED 130.

[0053] After the initialization period (A), the compensation period (B) begins. The compensation period (B) is the period during which the gate node g of transistor 121 is brought to its threshold voltage.

[0054] In detail, during the compensation period (B) of the horizontal scanning period (H) in which the k-th row of the i-th scan block is selected, the control signal / Gini(i) is at the H level, and the control signal / Gset(i) is at the H level. Also, during the compensation period (B), the control signals / Sel_1(i)~ / Sel_4(i) are at the H level. Therefore, in the pixel block BLp corresponding to the i-th scan line block, transistors 66c~66j change to the off state, and transistors 64a and 64b remain in the off state. Transistors 62c~62j also remain in the off state.

[0055] Furthermore, during the compensation period (B) of the horizontal scanning period (H) in which the k-th row is selected, the scan signal / Gwr(k) remains at a low level, the control signal / Gcmp(k) becomes low, and the control signal / Gel(k) remains at a high level. Therefore, in the j-th row pixel circuit 110, transistor 122 remains in the ON state, transistor 123 changes to the ON state, and transistor 124 remains in the OFF state.

[0056] During compensation period (B), as shown in Figure 9, the gate node g and drain node d of transistor 121 are connected, meaning transistor 121 is in a diode connection state. As a result, the voltage Vgs between the gate node g and source node s of transistor 121 converges to approach the threshold voltage of transistor 121. If we conveniently denote the threshold voltage as Vth, the gate node g of transistor 121 converges to a threshold equivalent voltage (Vel-Vth) corresponding to the threshold voltage Vth.

[0057] At the start of compensation period (B), current must flow from the source node to the drain node in the diode-connected transistor 121. Therefore, the voltage Vini applied to the gate node g during the initialization period (C) prior to compensation period (B) is: Vini <Vel-Vth This relationship is necessary.

[0058] After the compensation period (B), the writing period (C) begins. The writing period (C) is the period during which the gate node g of transistor 121 holds a voltage corresponding to the gradation. The writing period (C) includes time-isolated sampling periods (C1) to (C4), and a set period is provided before the sampling periods (C1) to (C4). The sampling periods (C1) to (C4) are the periods during which the gate node g of transistor 121 in the pixel circuit 110 samples the data signal two columns at a time. The set period is a period before the sampling periods (C1) to (C4) to align the states of data trunk lines 14a and 14b for sampling.

[0059] In the i-th scan block, during the write period (C) of the horizontal scan period (H) in which row k is selected, the control signal / Gini(i) remains at the H level, so transistors 62c to 62j are in the off state. Also, during the write period (C) of the horizontal scan period (H) in which row k is selected, the control signal / Gcmp(k) changes to the H level, and the control signal / Gel(k) remains at the H level. As a result, in the pixel circuit 110 of row j, transistor 123 changes to the off state, and transistor 124 remains in the off state. During the write period (C), the control signal / Gwr(k) is at the L level, so the transistor 122 in the k-th row pixel circuit 110 remains ON.

[0060] During the set period prior to the sampling period (C1), the control signals / Sel_1(i)~ / Sel_4(i) remain at a high level, and the control signal / Gset(i) changes to a low level. As a result, in the pixel block BLp corresponding to the i-th scan line block, transistors 62c~62j remain in the off state, and transistors 64a and 64b change to the on state. Therefore, during the set period, voltage Vini is applied to data trunks 14a and 14b. The voltage state before the next sampling period (C1) is matched to that of data trunks 14a and 14b. Since transistors 66c to 66j are in the off state, data branch lines 14c to 14j maintain the threshold voltage equivalent to the previous state.

[0061] During the sampling period (C1) of the horizontal scanning period (H) in which the k-th row is selected, the latch circuit L outputs video data Vta, which is the k-th row and corresponds to the pixel circuit 110R1, and video data Vtb, which is the k-th row and corresponds to the pixel circuit 110G1. The DA conversion circuit 52a converts the video data Vta into an analog voltage data signal Vda and outputs it to the data trunk line 14a. Similarly, the DA conversion circuit 52b converts the video data Vtb into an analog voltage data signal Vdb and outputs it to the data trunk line 14b.

[0062] During the sampling period (C1), of the control signals / Sel_1(i) to / Sel_4(i), only the control signal / Sel_1(i) changes to the L level. This turns on transistors 62c and 62e. As a result, data branch line 14c is electrically connected to data main line 14a, and data branch line 14e is electrically connected to data main line 14b.

[0063] Therefore, during the sampling period (C1), in the k-th row pixel circuit 110R1, a data signal Vda with a voltage corresponding to the gradation output to the data trunk 14a is applied sequentially through the data branch 14c and transistor 121 to the gate node g of transistor 121 and one end of capacitive element 140, as shown in Figure 10. Although not specifically shown in the diagram, similarly, for the pixel circuit 110G1 corresponding to the data branch line 14e, a data signal Vdb of voltage corresponding to the grayscale output to the data trunk line 14b is applied to the gate node g of the transistor 121 and one end of the capacitive element 140.

[0064] When the sampling period (C1) ends, the control signal / Sel_1(i) becomes high, causing transistors 62c and 62e to switch to the off state. Furthermore, since the period after the sampling period (C1) and before the sampling period (C2) is the set period, as described above, the data trunk lines 14a and 14b are aligned to the voltage Vini.

[0065] During the sampling period (C2) of the horizontal scanning period (H) in which the k-th row is selected, the latch circuit L outputs video data Vta, which is the k-th row and corresponds to the pixel circuit 110B1, and video data Vtb, which is the k-th row and corresponds to the pixel circuit 110G2. The DA conversion circuit 52a converts the video data Vta into a data signal Vda and outputs it to the data trunk line 14a. Similarly, the DA conversion circuit 52b converts the video data Vtb into a data signal Vdb and outputs it to the data trunk line 14b.

[0066] During the sampling period (C2), of the control signals / Sel_1(i) to / Sel_4(i), only the control signal / Sel_2(i) changes to the L level. This causes transistors 62d and 62f to turn on. Therefore, during the sampling period (C2), although not specifically shown in the diagram, in the pixel circuit 110B1 of the kth row, a data signal Vda with a voltage corresponding to the grayscale output to the data trunk 14a is applied to the gate node g of the transistor 121 and one end of the capacitive element 140. Similarly, in the pixel circuit 110G2, a data signal Vdb with a voltage corresponding to the grayscale output to the data trunk 14b is applied to the gate node g of the transistor 121 and one end of the capacitive element 140.

[0067] Similarly, during the sampling period (C3) following the set period, in the pixel circuit 110R2 of the k-th row, a data signal Vda of voltage corresponding to the grayscale is applied to the gate node g of transistor 121 and one end of the capacitive element 140, and in the pixel circuit 110G3 of the k-th row, a data signal Vdb of voltage corresponding to the grayscale is applied to the gate node g of transistor 121 and one end of the capacitive element 140. Furthermore, during the sampling period (C4) following the set period, in the pixel circuit 110B2 of the k-th row, a data signal Vda of voltage corresponding to the grayscale is applied to the gate node g of the transistor 121 and one end of the capacitive element 140, and in the pixel circuit 110G4 of the k-th row, a data signal Vdb of voltage corresponding to the grayscale is applied to the gate node g of the transistor 121 and one end of the capacitive element 140.

[0068] After the write period (C), the initialization period (D) begins. While the initialization period (A) is a preparation period for the compensation period (B), this initialization period (D) is a supplementary period for the initialization period (A) in the horizontal scan period (H) of the next line.

[0069] In detail, during the initialization period (D) of the horizontal scan period (H) in which the kth row of the i-th scanline block is selected, the control signal / Gini(i) changes back to the L level, and the control signal / Gset(i) remains at the H level. Also, during the initialization period (D), the control signals / Sel_1(i) to / Sel_4(i) are at the H level. Therefore, in the pixel block BLp corresponding to the i-th scan line block, transistors 66c to 66j are turned on, and transistors 64a and 64b are turned off. Also, transistors 62c to 62j are turned off.

[0070] Furthermore, during the initialization period (D) of the horizontal scanning period (H) in which the k-th row is selected, the scanning signal / Gwr(k) changes to an H level, and the control signals / Gcmp(k) and / Gel(k) maintain an H level. Therefore, in the pixel circuit 110R1 of the kth row, transistor 122 changes to the off state, transistor 123 turns on again, and transistor 124 remains in the off state.

[0071] Therefore, during the initialization period (D), as shown in Figure 11, the data branch line 14c is supplied with voltage Vini via transistor 62 to function as an auxiliary for the next line's initialization period (A).

[0072] In the pixel circuit 110R1, the voltage Vini is applied to the drain node d of transistor 121 and the source node of transistor 124 via the data branch line 14c and transistor 123 in sequence. However, since transistor 124 is in the off state, no current flows through the OLED 130.

[0073] After the initialization period (D), the illumination period (E) begins after one or more horizontal scanning periods have elapsed. The illumination period (E) is the period during which a current corresponding to the voltage of the gate node g held during the write period (C) is supplied to the OLED130.

[0074] During the k-th light emission period (E), the control signal / Gel(k) changes to the L level. When the control signal / Gel(k) reaches the L level, as shown in Figure 14, transistor 121 supplies a current Iel to OLED 130 that corresponds to the voltage Vgs and is limited by the resistance between the source node and drain node of transistor 124. Consequently, OLED 130 emits light with a brightness corresponding to the current Iel. Furthermore, the duration of the L level is consistent for all corresponding control signals / Gel(1) to / Gel(1960). Additionally, by increasing the duration of the L level in the control signals / Gel(1) to / Gel(1960), the brightness of the image displayed in display area 100 can be increased, while conversely, by shortening it, the brightness of the image can be decreased.

[0075] Although this explanation focuses on the pixel circuit 110R1 corresponding to data branch line 14c, the pixel circuits corresponding to the other data branch lines 14d to 14g operate similarly. Additionally, rows 1 through 35 of the i-th scan block are horizontally scanned sequentially for each horizontal scan period (H). A similar operation is performed for scan blocks 1 through 35.

[0076] As described above, in this embodiment, the i-th Y block Bly(i) outputs the control signal / Gini(i) not only when its own Y block Bly(i) is selected, but also when the previous (i-1)th Y block Bly(i-1) is selected. This point will be explained.

[0077] Figure 13 shows the relationship between selection and initialization by Y blocks Bly(1) to Bly(35) in the electro-optical device 10 according to this embodiment. Figure 14 shows the control signal / Gini(i) output from the i-th Y block Bly(i) and the control signal / Gini(i-1) output from the previous (i-1)-th Y block Bly(i-1) in this embodiment.

[0078] In Figure 13, during the effective scanning period (Va) of one frame (V), Y blocks Bly(1) to Bly(35) are selected one by one in order, as indicated by the hatching. The selected (hatched) Y blocks are horizontally scanned through 56 scan lines 12 in sequence for each horizontal scanning period (H). During the horizontal scanning period (H), the processes in the initialization period (A), compensation period (B), write period (C), and initialization period (D) are executed in order. That is, the hatched Y blocks are horizontally scanned one line at a time for each of the 56 scan line blocks contained within the Y block, accompanied by a write period (C).

[0079] For the purposes of this explanation, if we refer to the selection of a hatched Y block as the "primary selection," then in this embodiment, a "secondary selection" is performed for only the initialization periods (A) and (D) before the "primary selection" of a given Y block. In other words, as shown in Figure 14, the "dependent selection" Y block performs initialization periods (A) and (D) when horizontally scanning the 56 scan lines 12 sequentially for each horizontal scanning period (H), but does not perform compensation periods (B) and write periods (C). That is, during initialization period (A), the voltage Vini is applied to the data branches 14c to 14j in the (i-1)th Y block Bly(i-1), and also to the data branches 14c to 14j in the ith Y block Bly(i). Similarly, during initialization period (D), the voltage Vini is applied to the data branches 14c to 14j in the (i-1)th Y block Bly(i-1), and also to the data branches 14c to 14j in the ith Y block Bly(i).

[0080] The secondary selection preceding the primary selection of the i-th Y block Bly(i) is executed concurrently with the primary selection of the (i-1)th Y block Bly(i-1), which is one block prior to the i-th block. Furthermore, the "secondary selection" of the first Y block Bly(1) prior to the "primary selection" in the period before a certain frame (V) is executed concurrently with the "primary selection" of the last 35th Y block Bly(35) in the frame period immediately preceding that frame (V), and after the vertical scan retrace period (Vb), it leads to the "primary selection" of Y block Bly(1).

[0081] Here, in order to explain the advantages of the electro-optical apparatus 10 according to this embodiment, a comparative example in which "dependent selection" is not performed will be described.

[0082] Figure 18 shows the relationship between the selection and initialization of Y block Bly(1) to Bly(35) in the comparative example, and unlike Figure 13, "dependent selection" is not provided.

[0083] Figure 19 shows the control signal / Gini(i) output from the i-th Y block Bly(i) and the control signal / Gini(i-1) output from the previous (i-1)th Y block Bly(i-1) in the comparative example. In both the comparative example and this embodiment, for example, in the scan line block of the i-th Y block Bly(i), initialization periods (A) and (D) are executed during the horizontal scanning of each row.

[0084] However, in the comparative example, in the scan line block of Y block Bly(i), the auxiliary initialization period (D) for the scan line block is not executed before the initialization period (A) for that scan line block during the first horizontal scan. More specifically, the initialization period (D) performed before the initialization period (A) in the horizontal scan of the first row in the i-th scan line block is the application of voltage Vini to data branch lines 14c to 14j in the (i-1)-th scan line block, and not the application of voltage Vini to data branch lines 14c to 14j in the i-th scan line block. Therefore, in the i-th scanline block, the initial period (A) is executed after the initialization period (D) in the horizontal scan of lines 2 to 35, whereas in the first horizontal scan of line 1, the initial period (A) is executed without going through the initialization period (D). Therefore, in the comparative example, the initialization of the first horizontal scan in each scan line block is performed in a different state than the initialization of the other 2 to 35 lines in the same scan line block, which raises concerns about a decrease in display quality, such as color unevenness. Specifically, it is anticipated that display inconsistencies may occur due to differences in the load fluctuations of the power supply circuit that outputs voltage Vini between the horizontal scan of the first line and the horizontal scan of lines 2 to 35 within the same scan line block, and differences in the duration for which voltage Vini is applied to data branch lines 14c to 14j before the write period (C).

[0085] In this embodiment, compared to the comparative example, block Y performs "secondary selection" before "primary selection". Specifically, before the initialization period (A) in the first horizontal scan when the i-th scan line block is "primary selected", it is executed immediately before the initialization period (D) in the 35th horizontal scan when the i-th scan line block is "secondary selected". Therefore, in this embodiment, in the i-th scan line block, just as the initialization period (A) is executed after the initialization period (D) in the horizontal scan of lines 2 to 35, the initialization period (A) is also executed in the first horizontal scan of line 1 after the initialization period (D) in the same i-th scan line block. Therefore, in this embodiment, the initialization of the first horizontal scan in each scan line block is performed in the same state as the initialization of the other 2 to 35 lines in the same scan line block, thus suppressing a decrease in display quality such as color unevenness caused by different initializations.

[0086] Next, the electro-optical apparatus 10 according to the second embodiment will be described. Figure 15 shows the relationship between the selection and initialization of Y blocks Bly(1) to Bly(35) in the electro-optical apparatus 10 according to the second embodiment. As shown in this figure, the second embodiment differs from the first embodiment shown in Figure 13 in that only the "secondary selection" prior to the "primary selection" of the first Y block Bly(1) is not provided. In the second embodiment, the "secondary selection" prior to the "primary selection" for the 34 Y blocks Bly(2) to Bly(35) is executed concurrently with the "primary selection" for the previous Y block Bly(1) to Bly(34), as in the first embodiment.

[0087] In the second embodiment, the operation of the scan line drive circuit 40 can be stopped during the retrace period (Vb) of the vertical scan. Therefore, in the second embodiment, when the supply of a clock signal or the like for continuing operation during the retrace period (Vb) is stopped, the power consumed by parasitic capacitance due to the change in the level of the clock signal can be suppressed. Furthermore, in the electro-optical device 10, various sensors for measuring temperature, etc., may be activated during the retrace period (Vb). However, in the second embodiment, the operation of the scan line drive circuit 40 is stopped during the retrace period (Vb), so the influence of the operation of the scan line drive circuit 40 on the detection results of the various sensors can be eliminated.

[0088] In the second embodiment, however, the initialization of the horizontal scan of the first row in the first scan line block is performed differently from the initialization of the other 2 to 1960 rows, which raises concerns about a decrease in display quality, such as color unevenness. However, in the second embodiment, since it is the first row and at the edge of the display pixels, even if a decrease in display quality occurs, it will not be noticeable.

[0089] In the first and second embodiments (hereinafter referred to as "embodiments, etc."), the pixel circuits corresponding to the G color light were divided into 110G1 and 110G2 (110G3 and 110G4), but they may be combined into one. Furthermore, although the embodiment uses two data trunk lines, 14a and 14b, it may use one or three or more. The number of branch lines in the pixel block BLp that branch off to data branch lines 14c etc. via transistor 62c etc. is not limited to "4" but can be "2" or more.

[0090] In the embodiments, OLED130 was used as an example of a light-emitting element, but other light-emitting elements may be used. For example, as the light-emitting element, an element that emits light with brightness corresponding to the current, such as an LED, mini-LED, or micro-LED, may be used. The channel type of the transistor is not limited to the P-channel type, as shown in the embodiments.

[0091] Next, we will describe electronic devices to which the electro-optical device 10 according to the embodiment is applied. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, we will explain using a head-mounted display as an example of an electronic device.

[0092] Figure 16 shows the external appearance of the head-mounted display, and Figure 17 shows its optical configuration.

[0093] First, as shown in Figure 10, the head-mounted display 300 has, externally, the same features as ordinary eyeglasses, including temples 310, a bridge 320, and lenses 301L and 301R. Furthermore, as shown in Figure 17, the head-mounted display 300 is equipped with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320, behind (below in the figure) the lenses 301L and 301R. The image display surface of the electro-optical device 10L is positioned to the left in Figure 17. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is positioned to the right, opposite to the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction.

[0094] In this configuration, the wearer of the head-mounted display 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state, superimposed on the outside environment. Furthermore, in this head-mounted display 300, if the left-eye image is displayed by the electro-optical device 10L and the right-eye image is displayed by the electro-optical device 10R, the wearer can perceive the displayed images as if they had depth and three-dimensionality.

[0095] Furthermore, the electronic device including the electro-optical device 10 can be applied not only to the head-mounted display 300, but also to electronic viewfinders in video cameras and interchangeable-lens digital cameras, smartwatches, display units for wearable devices, and light bulbs for projection projectors.

[0096] From the forms exemplified above, the following aspects can be understood, for example.

[0097] An electro-optical apparatus according to one embodiment 1 includes a data trunk, a first data branch group and a second data branch group consisting of a plurality of data branch lines, a first pixel circuit group consisting of a first pixel circuit provided corresponding to a first scan line and the first data branch group, a second pixel circuit group consisting of a second pixel circuit provided corresponding to a second scan line and the second data branch group, a first distribution circuit for distributing the data signal supplied to the data trunk to a plurality of data branch lines included in the first data branch group, a second distribution circuit for distributing the data signal supplied to the data trunk to a plurality of data branch lines included in the second data branch group, and a control circuit, wherein the control circuit performs the first horizontal scanning period of the first scan line. The system controls a first initialization which applies an initial voltage to a group of data branch lines, a first write which supplies the data signal to the first pixel circuit group via the first data branch line after the first initialization, a second initialization which applies the initial voltage to the first and second data branch line groups after the first write, a third initialization which applies the initial voltage to the second data branch line group during the second horizontal scanning period of the second scan line, a second write which supplies the data signal to the second pixel circuit group via the second data branch line after the third initialization, and a fourth initialization which applies the initial voltage to the second data branch line group after the second write, such that the second and third initializations are time-sequential.

[0098] According to the electro-optical apparatus of Embodiment 1, when the initial voltage is applied in two stages during the horizontal scanning period, the duration for which the initial voltage is applied to the data branch lines can be made uniform. Therefore, a decrease in display quality caused by non-uniformity in the duration for which the initial voltage is applied can be suppressed.

[0099] Furthermore, the pixel block BLp corresponding to the intersection of the scan line 12 included in the Y block BLi(i-1) and the data branch lines 14c~14j is an example of the "first pixel circuit group," and the transistors 62c~62j in the said pixel block BLp are an example of the "first distribution circuit." A pixel block BLp corresponding to the intersection of scan line 12 and data branch lines 14c to 14j in Y block BLY(i) is an example of a "second pixel circuit group," and transistors 62c to 62j in the said pixel block BLp are an example of a "second distribution circuit." Furthermore, during the horizontal scanning period of scan line 12 included in Y block Bly(i-1), the initialization during initialization period (A) is an example of "first initialization," and the initialization during initialization period (D) is an example of "second initialization." During the horizontal scanning period of scan line 12 included in Y block Bly(i), the initialization during initialization period (A) is an example of "third initialization," and the initialization during initialization period (D) is an example of "fourth initialization."

[0100] In an electro-optical apparatus according to a specific embodiment 2 of embodiment 1, the first pixel circuit includes a first light-emitting element and a first transistor that supplies a current to the first light-emitting element corresponding to the voltage of a first gate node, and the second pixel circuit includes a second light-emitting element and a second transistor that supplies a current to the second light-emitting element corresponding to the voltage of a second gate node, wherein during a first compensation period after the first initialization and before the first write, the first transistor is in a diode connection state and the first gate node reaches a threshold voltage, and during a second compensation period after the third initialization and before the second write, the second transistor is in a diode connection state and the second gate node reaches a threshold voltage, and the initial voltage is a voltage that, when applied to the first gate node, turns on the first transistor and when applied to the second gate node, turns on the second transistor.

[0101] According to the electro-optical apparatus of embodiment 2, the initial voltage can be used for preparation during the first compensation period and the second compensation period. Note that OLED130 is an example of the "first light-emitting element" and the "second light-emitting element," and transistor 121 is an example of the "first transistor" and the "second transistor." The compensation period (B) during the horizontal scanning period of scan line 12 included in Y block Bly(i-1) is an example of the "first compensation period," and the compensation period (B) during the horizontal scanning period of scan line 12 included in Y block Bly(i) is an example of the "second compensation period."

[0102] In an electro-optical apparatus according to another specific embodiment 3 of embodiment 1, the control circuit controls the scan line drive circuit to perform the first initialization, the first write, the second initialization, the third initialization, the second write, and the fourth initialization, the first horizontal scanning period being the first horizontal scanning period in one frame period, and the operation of the scan line drive circuit stopping during the retrace period of the vertical scan prior to the first horizontal scanning period. According to the electro-optical apparatus of embodiment 3, the operation of the scanning drive circuit is stopped during the retrace period of vertical scanning. Therefore, the effects of the scanning line drive circuit operating during the retrace period can be suppressed.

[0103] In an electro-optical apparatus according to another specific embodiment 4 of embodiment 1, there are multiple first scanning lines and multiple second scanning lines, the first horizontal scanning period is performed for each of the multiple first scanning lines, and the second horizontal scanning period is performed for each of the multiple second scanning lines.

[0104] Furthermore, in an electro-optical apparatus according to another specific embodiment 5 of embodiment 1, the control circuit controls the distribution of the data signal in the first distribution circuit and the second distribution circuit.

[0105] In an electro-optical apparatus according to another specific embodiment 6 of embodiment 1, the initial voltage is applied to the second data branch line group during the first initialization.

[0106] The electronic device according to embodiment 7 has an electro-optical device according to any of embodiments 1 to 6. [Explanation of symbols]

[0107] 10... Electro-optical device, 30... Control circuit, 50... Data signal output circuit, 110, 110R1, 110B1, 110G1, 110G2, 110R2, 110B2, 110G3, 110G4... Pixel circuit, 120... Scan line drive circuit, 121~124... Transistor, 130... OLED, Bly(1)~BLy(35)... Y block, BLP... Pixel block.

Claims

1. Data trunk lines and A first data branch group and a second data branch group consisting of multiple data branch lines, A first pixel circuit group consisting of a first pixel circuit provided in correspondence with the first scan line and the first data branch line group, A second pixel circuit group consisting of a second pixel circuit provided in correspondence with the second scanning line and the second data branch line group, A first distribution circuit that distributes the data signal supplied to the data trunk to a plurality of data branch lines included in the first data branch line group, A second distribution circuit distributes the data signal supplied to the data trunk to a plurality of data branch lines included in the second data branch line group, Control circuit and Includes, The aforementioned control circuit is A first initialization is performed by applying an initial voltage to the first data branch line group during the first horizontal scanning period of the first scan line, A first write operation is performed after the first initialization, supplying the data signal to the first pixel circuit group via the first data branch line, A second initialization is performed after the first write operation, in which the initial voltage is applied to the first data branch group and the second data branch group. A third initialization is performed by applying the initial voltage to the second data branch line group during the second horizontal scanning period of the second scanning line, After the third initialization, a second write operation is performed, in which the data signal is supplied to the second pixel circuit group via the second data branch line. A fourth initialization is performed after the second write operation, in which the initial voltage is applied to the second data branch line group, Control, The second initialization and the third initialization are consecutive in time. Electro-optical device.

2. The first pixel circuit is, First light-emitting element, A first transistor supplies a current to the first light-emitting element according to the voltage of the first gate node, Includes, The second pixel circuit is, The second light-emitting element, A second transistor supplies a current to the second light-emitting element according to the voltage of the second gate node, Includes, During the first compensation period after the first initialization and before the first write operation, the first transistor enters a diode-connected state. When the first gate node reaches a threshold voltage, During the second compensation period after the third initialization and before the second write operation, the second transistor enters a diode-connected state. When the second gate node reaches a threshold voltage, The aforementioned initial voltage is, When applied to the first gate node, it turns on the first transistor. and, When applied to the second gate node, it turns on the second transistor. It is voltage. The electro-optical apparatus according to claim 1.

3. The aforementioned control circuit is Control the scan line drive circuit, The first initialization, the first write, the second initialization, the third initialization, the second write, and the fourth initialization are executed. The first horizontal scanning period is the first horizontal scanning period in one frame period, The operation of the aforementioned scan line drive circuit is as follows: Stops during the retrace period of the vertical scan prior to the first horizontal scan period. The electro-optical apparatus according to claim 1.

4. The first scan line consists of multiple lines, The aforementioned second scan lines are multiple, The first horizontal scanning period is performed for each of the multiple first scanning lines. The second horizontal scanning period is performed for each of the multiple second scanning lines. The electro-optical apparatus according to claim 1.

5. The aforementioned control circuit is Controlling the distribution of the data signal in the first distribution circuit and the second distribution circuit, The electro-optical apparatus according to claim 1.

6. In the first initialization, the initial voltage is applied to the second data branch line group. The electro-optical apparatus according to claim 1.

7. An electronic device having an electro-optical device according to any one of claims 1 to 6.

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