Calibration circuit

Abstract

This invention provides a calibration circuit that can perform smooth calibration in response to temperature changes. [Solution] A calibration circuit connected to a phase-synchronous circuit 200 which includes a voltage-controlled oscillator 14 that receives a control voltage and generates an oscillation signal with a frequency corresponding to the control voltage, a phase-frequency comparator 11 that receives a reference frequency signal and detects the phase difference between the reference frequency signal and the oscillation signal or a signal obtained by dividing the frequency of the oscillation signal, a charge pump 12 that generates a phase difference signal corresponding to the phase difference, and a loop filter 13 that smooths the voltage level of the phase difference signal and generates a control voltage, wherein the first voltage and the control voltage V CTRL The system includes a first comparator CMPA that compares the first voltage with the second voltage, a second comparator CMPB that compares the control voltage with a second voltage that has a lower voltage value than the first voltage, and a control circuit that changes the gain setting of the voltage-controlled oscillator based on the comparison results from the first and second comparators.

Description

[Technical Field]

[0001] This disclosure relates to a calibration circuit for calibrating a voltage-controlled oscillator. [Background technology]

[0002] Conventionally, to suppress variations in the loop characteristics of PLL (Phase Locked Loop) circuits, VCO (Voltage Controlled Oscillator) calibration has been performed (for example, Patent Document 1). VCO calibration is performed, for example, by stopping the CP (Charge Pump), fixing the VCO input to an arbitrary voltage, measuring the frequency, and increasing the VCO setting one step at a time until the VCO frequency (FVCO) exceeds F1. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-191486 [Summary] By performing the above-described calibration of the VCO, the characteristics of the elements constituting the VCO, the temperature at the time of calibration, and the applied power supply voltage can be calibrated. However, regarding temperature, changes may occur due to changes in the external environment or heat generated by the elements themselves.

[0004] You can recalibrate when the temperature changes, but the above calibration is V CTRL Since the VCO frequency is determined by fixing the control voltage and switching the VCO gain, the PLL and CDR (Clock Data Recovery) loops that use this must be stopped each time. Therefore, calibration has to be performed by repeatedly stopping the circuit, recalibrating, restarting the circuit, and locking, which has the problem of being time-consuming.

[0005] A calibration circuit according to one aspect of the present disclosure is connected to a phase-synchronous circuit that includes: a voltage-controlled oscillator that receives a control voltage and generates an oscillation signal with a frequency corresponding to the control voltage; a phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and the oscillation signal or the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal; a charge pump that generates a phase difference signal corresponding to the phase difference; and a loop filter that smooths the voltage level of the phase difference signal to generate the control voltage, and performs calibration of the voltage-controlled oscillator, comprising: a first comparator that receives a first voltage and compares the first voltage with the control voltage; a second comparator that receives a second voltage with a lower voltage value than the first voltage and compares the second voltage with the control voltage; and a control circuit that changes the gain setting of the voltage-controlled oscillator based on the comparison result of the first comparator and the comparison result of the second comparator. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing the configuration of the calibration circuit according to Embodiment 1 of the present disclosure. [Figure 2] This is a circuit diagram showing the configuration of the calibration voltage generation circuit. [Figure 3A] This figure shows the VF characteristics of a VCO at room temperature. [Figure 3B] This figure shows the VF characteristics of a VCO at low temperatures. [Figure 3C] This figure shows the VF characteristics of a VCO at high temperatures. [Figure 4] This figure shows the relationship between the comparator output and the gain setting. [Figure 5] This is a flowchart showing the processing routine for the calibration operation in Example 1. [Figure 6] This is a time chart showing the changes in control voltage and gain settings during calibration in Example 1. [Figure 7]This diagram shows the configuration when the calibration circuit of Example 1 is applied to a CDR circuit. [Figure 8] This is a circuit diagram showing the configuration of the calibration voltage generation circuit in Example 2. [Figure 9] This figure shows the change in the VF characteristics of the control voltage due to temperature changes. [Figure 10] This is a circuit diagram showing another example of a calibration voltage generation circuit configuration. [Figure 11] This is a flowchart showing the processing routine for the calibration operation in Example 3. [Figure 12] This is a time chart showing the change in control voltage and gain setting during calibration in Example 3. [Detailed Description] Preferred embodiments of the present disclosure are described in detail below. In the following descriptions and accompanying drawings, substantially identical or equivalent parts are denoted by the same reference numerals. [Example 1]

[0007] Figure 1 is a block diagram showing the configuration of a calibration circuit 100 according to an embodiment of the present disclosure. The calibration circuit 100 is connected to a PLL (Phase Locked Loop) circuit 200 and is a circuit that performs calibration of a VCO (Voltage Controlled Oscillator) provided in the PLL circuit 200.

[0008] The PLL circuit 200 includes a PFD (Phase Frequency Detector) 11, a charge pump (CP) 12, a loop filter (LPF) 13, a VCO 14, and a frequency divider (1 / N) 15. These constitute a feedback loop.

[0009] The PLL circuit 200 is equipped with a PFD (Phase Frequency Comparator) 11, which acts as a phase comparator that detects the phase difference between two input signals and outputs a voltage corresponding to the detected phase difference. The PFD 11 is connected to a reference clock signal CLK. REFReceives the supply of , receives the supply of the divided clock signal DIV from the frequency divider 15, and outputs a control signal Up or Down according to these phase differences.

[0010] Based on the control signal Up or Down supplied from the PFD 11, the charge pump 12 outputs a current pulse signal PS corresponding to the phase difference between the reference clock signal CLK REF and the divided clock signal DIV.

[0011] The loop filter 13 smoothes the current pulse signal PS supplied from the charge pump 12 and outputs it as a control voltage V CTRL .

[0012] The VCO 14 is a voltage-controlled oscillator circuit that controls the oscillation frequency based on the control voltage V CTRL . The VCO 14 receives the supply of the control voltage V from the loop filter 13 CTRL and outputs an output clock signal CLK having a frequency corresponding thereto OUT .

[0013] The frequency divider 15 receives the supply of the output clock signal CLK OUT and outputs a divided clock signal DIV obtained by dividing this.

[0014] The calibration circuit 100 includes a calibration voltage (V CALIB ) generation circuit 21, a comparator CMPA, a comparator CMPB, and a control circuit 22.

[0015] The calibration voltage generation circuit 21 generates an initial calibration voltage V CALIB , a calibration upper limit voltage V CALIBH , and a calibration lower limit voltage V CALIBL . Note that the initial calibration voltage V CALIB has a voltage level not less than the calibration lower limit voltage V CALIBL (that is, the relationship of V CALIBL ≤V CALIB ). Also, the initial calibration voltage VCALIB This is the calibration upper voltage V CALIBH The following voltage levels (i.e., V CALIB ≤V CALIBH (The relationship) is such that. Calibration voltage V CALIB Depending on the calibration method, the calibration lower limit voltage V CALIBL Or calibration upper voltage V CALIBH It is also possible that the voltages will be the same, but in this embodiment, the relationship between the voltage values ​​of these voltages is V CALIBL <V CALIB <V CALIBH The following explanation will use this case as an example.

[0016] Figure 2 is a circuit diagram showing the configuration of the calibration voltage generation circuit 21. The calibration voltage generation circuit 21 is composed of a resistive voltage divider circuit consisting of resistors R1, R2, R3, and R4.

[0017] Resistors R1, R2, R3, and R4 are connected in series between the power supply voltage VDD supply line and the ground potential VSS supply line. One end of resistor R1 is connected to the power supply voltage VDD supply line. The calibration upper limit voltage V is measured from the connection node connecting the other end of resistor R1 and one end of resistor R2. CALIBH The following is output. The initial calibration voltage V is output from the connection node that connects the other end of resistor R2 and one end of resistor R3. CALIB The output is as follows: From the connection node connecting the other end of resistor R3 and one end of resistor R4, the calibration lower limit voltage V CALIBL The output is as follows. The other end of resistor R4 is grounded.

[0018] Referring again to Figure 1, the initial calibration voltage V of the calibration voltage generation circuit 21. CALIB A switch SW is provided between the output terminal of the PLL circuit 200 and the input terminals of comparators CMPA and CMPB. The switch SW is controlled to be ON during initial calibration and OFF during normal operation of the PLL circuit 200.

[0019] Comparators CMPA and CMPB are voltage comparison circuits that receive voltage inputs at their first and second input terminals, respectively, and output a signal indicating the comparison result at either a high level (logic level 1) or a low level (logic level 0).

[0020] The first input terminal of the comparator CMPA receives the initial calibration voltage V when the switch SW is ON, i.e., when the initial calibration is performed. CALIB When power is supplied and the switch SW is off, i.e., during normal operation of the PLL circuit 200, the control voltage V CTRL The calibration upper limit voltage V is supplied to the second input terminal of the comparator CMPA. CALIBH It will be supplied.

[0021] The first input terminal of comparator CMPB receives the initial calibration voltage V when switch SW is ON, i.e., when the initial calibration is performed. CALIB When power is supplied and the switch SW is off, i.e., during normal operation of the PLL circuit 200, the control voltage V CTRL The following is supplied: The calibration lower limit voltage V is supplied to the second input terminal of the comparator CMPB. CALIBL It will be supplied.

[0022] The control circuit 22 changes the gain setting of the VCO 14 according to the output of comparators CMPA and CMPB when performing dynamic calibration, which is performed during the normal operation of the PLL circuit 200. This change in gain setting is due to the control voltage V that changes with the temperature of the semiconductor chip on which the PLL circuit 200 is mounted. CTRL This is done in response to changes in [the system / factor]. This will be explained below.

[0023] In semiconductors, electron mobility decreases with increasing temperature, causing the gain Kv (also called modulation sensitivity Kv) of a voltage-controlled oscillator (VCO) to decrease. Conversely, gain Kv increases when the temperature decreases. When gain Kv changes, PLL circuits and CDR circuits attempt to maintain the output frequency, and the control voltage Vv changes accordingly. CTRL The control voltage V changes. The control circuit 22 of this embodiment controls this control voltage VCTRL The change in the control voltage V is detected, and the control voltage V CTRL The gain setting of VCO14 is changed so that if the value exceeds a certain level, the gain setting is increased, and if it falls below a certain level, the gain setting is decreased.

[0024] Figures 3A, 3B, and 3C show the VF characteristics of the VCO at room temperature, low temperature, and high temperature.

[0025] For example, suppose that initial calibration is performed so that the VF characteristics are as shown by the solid line B in Figure 3A at room temperature. From this state, if the temperature of the semiconductor on which the PLL circuit 200 is mounted changes, the VF characteristics will also change accordingly, becoming as shown by the solid line B in Figure 3B at low temperatures and as shown by the solid line B in Figure 3C at high temperatures.

[0026] Control voltage V CTRL In Figures 3A-3C, this is represented by the voltage value at the intersection of the dashed line indicating frequency F1 and the solid line B. As shown in Figure 3A, the control voltage V at room temperature CTRL This is the calibration lower limit voltage V CALIBL and calibration upper voltage V CALIBH Between (that is, V CALIBL <V CTRL <V CALIBH ) is located at ). However, at low temperatures, as shown in Figure 3B, the control voltage V CTRL The calibration lower limit voltage V CALIBL A state below V CTRL <V CALIBL ) Also, at high temperatures, the control voltage V is as shown in Figure 3C. CTRL The calibration upper limit voltage V CALIBH A state exceeding (i.e., V) CALIBH <V CTRL )

[0027] The control circuit 22 controls the control voltage V CTRL The calibration lower limit voltage V CALIBL and calibration upper voltage V CALIBHThe gain setting of VCO14 is changed so that it falls between the two values. Specifically, the control circuit 22 changes the gain setting of VCO14 so that, at low temperatures, the VF characteristic changes in the direction indicated by the arrow in Figure 3B, that is, from the solid line B to the dashed line C. Also, the control circuit 22 changes the gain setting of VCO14 so that, at high temperatures, the VF characteristic changes in the direction indicated by the arrow in Figure 3C, that is, from the solid line B to the dashed line A.

[0028] Figure 4 shows the relationship between the outputs of comparators CMPA and CMPB and the changes in the gain setting of VCO14 by the control circuit 22.

[0029] The output of comparator CMPA is the control voltage V CTRL The calibration upper limit voltage V CALIBH The output of comparator CMPB is H level (logic level 1) when it exceeds the control voltage V, and L level (logic level 0) otherwise. CTRL The calibration lower limit voltage V CALIBL If it falls below a certain level, it becomes L level (logical level 0); otherwise, it becomes H level (logical level 1).

[0030] The control circuit 22 increments the gain setting of VCO14 (+1) when both the output of comparator CMPA and the output of comparator CMPB are at the H level.

[0031] Furthermore, the control circuit 22 decrements the gain setting of VCO14 (-1) when both the output of comparator CMPA and the output of comparator CMPB are at the L level.

[0032] Furthermore, if the output of comparator CMPA is at a low level and the output of comparator CMPB is at a high level, the control circuit 22 does not change the gain setting of VCO14 and maintains that state.

[0033] Next, the operation of the calibration circuit 100 in this embodiment will be explained with reference to the flowchart in Figure 5 and the timing chart in Figure 6.

[0034] First, the calibration circuit 100 turns on the switch SW and starts the initial calibration of the VCO14 (STEP 101).

[0035] During the initial calibration, the control circuit 22 gradually increases the gain setting of the VCO 14 from 1 or an arbitrary value. Figure 6 shows an example of gradually increasing the gain setting from 1. The period indicated as "T1" in the figure is the execution period of the initial calibration. The control circuit 22 determines the final gain setting for the initial calibration to "k" and terminates the initial calibration (STEP 102).

[0036] After the initial calibration is complete, the PLL circuit 200 starts up and begins operation (STEP 103). In Figure 6, "T2" indicates the period after the initial calibration is complete and before the PLL circuit 200 starts operation, and "T3" indicates the period after the PLL circuit 200 starts operation.

[0037] After starting operation, the PLL circuit 200 goes through states such as frequency clock and phase clock before the output frequency stabilizes (STEP 104).

[0038] The calibration circuit 100 detects that the PLL circuit 200 has entered a frequency-locked or phase-locked state and starts dynamic calibration (STEP 105).

[0039] In the time chart of Figure 6, "T4" indicates the period after the calibration circuit 100 started dynamic calibration.

[0040] When the temperature (Temp) of the semiconductor chip containing the PLL circuit 200 rises, the control voltage V increases accordingly. CTRL The voltage value also increases. Control voltage VCTRL The calibration upper limit voltage V CALIBH When this value is exceeded, the output of the comparator CMPA inverts from a low level to a high level.

[0041] In response to the change in the output of comparator CMPA to a high level, control circuit 22 increments the gain setting of VCO14, changing it from "k" to "k+1".

[0042] Subsequently, as the temperature of the semiconductor chip decreases, the control voltage V decreases accordingly. CTRL The voltage value also decreases. Control voltage V CTRL When the voltage falls below the calibration lower limit voltage VCLIBL, the output of the comparator CMPB inverts from a high level to a low level.

[0043] In response to the change in the output of comparator CMPB to an L level, control circuit 22 decrements the gain setting of VCO14, changing it from "k+1" to "k".

[0044] Subsequently, if the temperature continues to rise or fall and the outputs of comparators CMPA and CMPB change, the control circuit 22 will further modify the gain settings accordingly.

[0045] As described above, the calibration circuit 100 of this embodiment controls the control voltage V CTRL Calibration upper limit voltage V CALIBH The comparator CMPA is used for comparison, and the control voltage V CTRL Calibration lower limit voltage V CALIBL The PLL circuit 200 has a comparator CMPB that compares to and performs dynamic calibration by changing the gain setting of VCO14 in response to changes in the outputs of comparators CMPA and CMPB (i.e., inversion of logic levels).

[0046] With this configuration, a temperature change occurs after the PLL circuit 200 starts operating, causing the control voltage V to decrease. CTRLEven when the voltage value fluctuates significantly, the gain setting of VCO14 can be changed to control the voltage V CTRL It becomes possible to adjust the voltage so that it falls within a predetermined voltage range.

[0047] Furthermore, the calibration circuit 100 in this embodiment can be applied not only to PLL circuits but also to CDR (Clock Data Recovery) circuits.

[0048] Figure 7 is a block diagram showing the configuration when the calibration circuit 100 of this embodiment is applied to the CDR circuit 300.

[0049] The CDR circuit 300 is equipped with a PD (Phase Detector) 31 as a phase comparator. The PD 31 receives an input signal which is a mixture of data and clock signals. IN It receives input and converts it into a clock signal and output data DATA. OUT It is separated into two parts. Also, PD31 receives the input signal DATA IN and the output clock signal CLK of VCO14 OUT It receives input and outputs a control signal (Up or Down) corresponding to the phase difference.

[0050] In this configuration as well, the calibration circuit 100 of this embodiment changes the gain setting of the VCO14 in accordance with the change in the output of the comparators CMPA and CMPB, similar to the case of the PLL circuit 200, thereby controlling the control voltage V CTRL It can be adjusted so that it falls within a predetermined voltage range. [Example 2]

[0051] Next, Embodiment 2 of the present disclosure will be described. The calibration circuit of this embodiment differs from the calibration circuit 100 of Embodiment 1 in the configuration of the calibration voltage generation circuit.

[0052] Figure 8 is a circuit diagram showing the configuration of the calibration voltage generation circuit 21A in this embodiment. The calibration voltage generation circuit 21A consists of a current source CS, resistors R11, R12, R13, and transistor NM11.

[0053] The current source CS is a current source that supplies current to a circuit consisting of resistors R11, R12, R13 and transistor NM11. In this embodiment, one end of the current source CS is connected to the power supply voltage VDD supply line. The calibration upper limit voltage V is supplied from the connection node connecting the other end of the current source CS and one end of resistor R11. CALIBH The following is output. The initial calibration voltage V is output from the connection node that connects the other end of resistor R11 and one end of resistor R12. CALIB The output is as follows: From the connection node connecting the other end of resistor R12 and one end of resistor R13, the calibration lower limit voltage V CALIBL The following will be output.

[0054] Transistor NM11 is composed of an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) with its gate and drain connected by a so-called diode. Transistor NM11 is connected in series with the resistor voltage divider circuit, which consists of a current source CS and resistors R11 to R13, and the supply line for the ground potential VSS. The gate and drain of transistor NM11 are connected to the other end of resistor R13. The source of transistor NM11 is grounded.

[0055] According to the calibration voltage generation circuit 21A with this configuration, the threshold voltage V of the NMOS transistor constituting the VI conversion section of VCO14 TH Calibration voltage (V) for fluctuations CALIBH , V CALIB , V CALIBL This allows it to follow. This will be explained below.

[0056] Figure 9 shows the control voltage V in response to temperature changes. CTRLIt is a diagram showing the change in the VF characteristics. Although the gain Kv of VCO14 changes according to the temperature change, when the V-I conversion section of VCO14 is composed of NMOS transistors, the oscillation start point of VCO14 also changes due to the change in the threshold voltage V TH of the NMOS transistor according to the temperature change.

[0057] The calibration upper limit voltage V CALIBH , the initial calibration voltage V CALIB , and the calibration lower limit voltage V CALIBL generated by the calibration voltage generation circuit 21A of this embodiment vary according to the change in the threshold voltage V TH of the transistor NM11. Thereby, the influence of the variation in the threshold voltage V TH of the NMOS transistor in VCO14 can be offset.

[0058] Thus, by generating the calibration voltages (V TH , V CALIBH , V CALIB , V CALIBL ) following the threshold voltage V TH of the NMOS transistor, the voltage comparison by the comparators CMPA and CMPB can be stably performed regardless of the variation in the threshold voltage V

[0059] . Therefore, the change in the gain Kv of VCO14 can be more reliably detected.

[0060] In addition, FIG. 10 is a circuit diagram showing the configuration of a calibration voltage generation circuit 21B which is a modified example of the calibration voltage generation circuit of this embodiment.

[0061] Transistor PM1 is composed of a P-channel MOS transistor (hereinafter referred to as a PMOS transistor). The source of transistor PM1 is connected to the power supply voltage VDD line.

[0062] Resistor R0 has one end connected to the drain of transistor PM1 and the other end connected to ground. Resistor R0 is composed of the same components as resistors R11, R12, and R13.

[0063] The differential amplifier OP receives a reference voltage VREF at its inverting input terminal, and its non-inverting input terminal is connected to a connection node that connects one end of resistor R0 to the drain of transistor PM1. The differential amplifier OP receives the reference voltage VREF and the potential at one end of resistor R0 (i.e., the potential at the connection node connecting resistor R0 and the drain of transistor PM1) as inputs, and supplies a differentially amplified differential signal DS to the gate of transistor PM1.

[0064] Transistor PM2 is a PMOS transistor, and its source is connected to the power supply voltage VDD line along with the source of transistor PM1. The drain of transistor PM2 is connected to one end of resistor R11. Transistor PM2, together with transistor PM1, forms a current mirror circuit.

[0065] The calibration voltage generation circuit 21B with this configuration can suppress the influence of resistance variations in the resistive elements compared to the calibration voltage generation circuit 21A shown in Figure 8. This will be explained below.

[0066] If the resistance value of resistor R0 is R0, then the current IPM1 flowing through transistor PM1 due to the virtual short at the differential input of differential amplifier OP is IPM1 = VREF / R0. Also, if the current mirror ratio of the current mirror circuit is k (where k is an arbitrary coefficient), then the current IPM2 flowing through transistor PM2 is IPM2 = kIPM1.

[0067] If the resistance value of resistor R11 is R11, then the potential difference VR11 across resistor R11 is given by VR11 = IPM2 * R11 = kIPM1 * R11 = kVREF * R11 / R0. As described above, resistors R0, R11, R12, and R13 are composed of the same element, so the resistance ratio R11 / R0 of resistors R0 and R11 is constant regardless of manufacturing variations. Therefore, if the reference voltage VREF is constant, the potential difference VR11 will also be a fixed value. The same applies to resistors R12 and R13.

[0068] By suppressing the effect of resistance variations in the resistive elements in this way, the calibration voltage (V CALIBH , V CALIB , V CALIBL The factors causing the fluctuations are the threshold voltage V of the NMOS transistor. TH This allows us to limit the analysis to only the variation within the given range. Therefore, voltage comparisons using comparators CMPA and CMPB can be performed more stably, and changes in the gain Kv of VCO14 can be detected more reliably. [Example 3]

[0069] Next, Embodiment 3 of the present invention will be described. The calibration circuit of this embodiment has the same configuration as the calibration circuit 100 of Embodiment 1, but differs from the calibration circuit 100 of Embodiment 1 in that it performs dynamic calibration without presupposing the execution of initial calibration.

[0070] The operation of the calibration circuit in this embodiment will be explained with reference to the flowchart in Figure 11 and the timing chart in Figure 12.

[0071] First, prior to starting the PLL circuit 200, the VCO 14 is started (STEP 201). Immediately after the VCO is started, the control circuit 22 is masked for a certain period of time, and the control voltage V CTRLThe system is controlled to prevent the determination of the condition and the change in the gain setting of VCO14. In the time chart of Figure 12, the period when “Mask” is at an H level is the masking period, and the period when it is at an L level is the unmasking period (i.e., the control voltage V based on the comparator output). CTRL This indicates the period during which the determination and gain setting are controlled.

[0072] Next, the control voltage V CTRL Initial calibration voltage V CALIB Charge to a voltage level equivalent to (STEP 202).

[0073] Control voltage V CTRL The initial calibration voltage V CALIB After being charged to a certain extent, the PLL circuit 200 (or CDR circuit 300) is activated (STEP 203).

[0074] After the output of comparator CMPB inverts from L level to H level, the calibration circuit 100 starts dynamic calibration. The control circuit 22 is masked and starts controlling the gain setting of VCO14 (STEP 204).

[0075] As shown in Figure 12, at this point the output frequency F OUT Since the target frequency F1 has not been reached, the control voltage V is controlled by the operation of PFD11. CTRL Charging continues, and the control voltage V CTRL The calibration upper limit voltage V CALIBH When this value is exceeded, the gain setting is changed (in Figure 12, it changes from 1 to 2).

[0076] When the gain of VCO14 is set to an appropriate value (set to 4 in Figure 12), the control voltage V CTRL The calibration lower limit voltage V CALIBL ~Calibration upper limit voltage V CALIBH The circuit then enters a state where the PLL circuit 200 is locked (frequency locked, phase locked) (STEP 205).

[0077] The mask of control circuit 22 is released when the output of comparator CMPB changes from L level to H level, and control circuit 22 enters a state where it awaits the outputs of comparators CMPA and CMPB. Subsequently, when the gain setting is changed in accordance with the inversion of the comparator output, the mask of control circuit 22 transitions back to H level and is released again after a certain period of time.

[0078] As shown in Figure 12, when the mask is released (when Mask is at a low level), the control circuit 22 determines the outputs of comparators CMPA and CMPB and controls the gain setting to increase if both outputs are at a high level, and to decrease the gain setting if both outputs are at a low level (see Figure 4).

[0079] When the gain of VCO14 is set to an appropriate value (4 in the example in Figure 12), and the output of comparator CMPA is at a low level and the output of comparator CMPA is at a high level, the mask of control circuit 22 is maintained in an unlocked state thereafter. In other words, subsequent gain adjustments due to temperature changes are performed in the same manner as in Example 1.

[0080] As described above, according to the operation of the calibration circuit 100 of this embodiment, dynamic calibration is performed without performing initial calibration, and the control voltage V CTRL It becomes possible to adjust the voltage so that it falls within a predetermined voltage range.

[0081] This disclosure is not limited to the embodiments described above. For example, in Embodiment 1, dynamic calibration is initiated by detecting the locked state of the PLL circuit 200. However, if the damping factor (attenuation coefficient) of the PLL circuit 200 is sufficiently large at the design stage, the control voltage V is maintained during the locked operation. CTRL If it is known that the system will not overshoot, the comparator CMPB may be activated at the same time as the PLL circuit 200 is started, and dynamic calibration may be initiated when the output of the comparator CMPB inverts from a low level to a high level.

[0082] Furthermore, while the above embodiment 3 described a case where dynamic calibration is started after the PLL circuit 200 or CDR circuit 300 is started, dynamic calibration may be started simultaneously with the start of the PLL circuit 200 or CDR circuit 300.

[0083] [Note] This specification discloses the following configuration: (Composition 1) A calibration circuit connected to a phase-locked circuit, which includes a voltage-controlled oscillator that receives a control voltage and generates an oscillation signal with a frequency corresponding to the control voltage; a phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and the oscillation signal or the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal; a charge pump that generates a phase difference signal corresponding to the phase difference; and a loop filter that smooths the voltage level of the phase difference signal to generate the control voltage, and which performs calibration of the voltage-controlled oscillator, the calibration circuit comprising: a first comparator that receives a first voltage and compares the first voltage with the control voltage; a second comparator that receives a second voltage with a lower voltage value than the first voltage and compares the second voltage with the control voltage; and a control circuit that changes the gain setting of the voltage-controlled oscillator based on the comparison result of the first comparator and the comparison result of the second comparator. (Configuration 2) The control circuit is a calibration circuit according to configuration 1, wherein the control voltage is higher than the first voltage in the comparison by the first comparator, and the gain setting of the voltage-controlled oscillator is increased. (Composition 3) The control circuit is a calibration circuit according to configurations 1 and 2, wherein the control voltage is lower than the second voltage in the comparison by the second comparator, and the gain setting of the voltage-controlled oscillator is lowered. (Composition 4) A calibration circuit according to any one of configurations 1 to 3, comprising a resistive voltage divider circuit consisting of a plurality of resistive elements connected in series between a predetermined voltage supply line and a ground potential supply line, and a voltage generation circuit that divides the predetermined voltage and the ground potential using the resistive voltage divider circuit to generate the first voltage and the second voltage. (Composition 5) The voltage generation circuit is a calibration circuit according to configuration 4, which includes an N-channel MOS transistor connected in series with the resistive voltage divider circuit and having its drain and gate diode-connected, between the resistive voltage divider circuit and the ground potential supply line. (Composition 6) The calibration circuit according to configuration 5, wherein the voltage generation circuit includes a constant current source connected in series with the resistive voltage divider circuit between the predetermined voltage supply line and one end of the resistive voltage divider circuit. (Composition 7) The calibration circuit according to configuration 5, comprising: a current mirror circuit formed by current mirroring a first P-channel MOS transistor whose source is connected to the power supply voltage supply line, a second P-channel MOS transistor connected in series with the resistive voltage divider circuit between the power supply voltage supply line and the resistive voltage divider circuit, a reference resistor element with one end connected to the drain of the first P-channel MOS transistor and the other end grounded, and a differential amplifier that receives a reference voltage input and supplies a differentially amplified signal obtained by differentially amplified the reference voltage and the potential at one end of the reference resistor element to the gate of the first P-channel MOS transistor. (Composition 8) The phase-locking circuit is a calibration circuit according to any one of configurations 1 to 7, which is a PLL circuit. (Composition 9) The phase-synchronization circuit is a calibration circuit according to any one of configurations 1 to 7, which is a CDR circuit. [Explanation of symbols]

[0084] 100 Calibration Circuit 200 PLL circuits 11 PFD 12 Charge pump 13 Loop Filters 14 VCO 15 divider 21 Calibration Voltage Generation Circuit 22 Control circuits 300 CDR circuit 31 PD

Claims

1. A calibration circuit connected to a phase-synchronous circuit, which includes a voltage-controlled oscillator that receives a control voltage and generates an oscillation signal with a frequency corresponding to the control voltage; a phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and the oscillation signal, or the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal; a charge pump that generates a phase difference signal corresponding to the phase difference; and a loop filter that smooths the voltage level of the phase difference signal to generate the control voltage, and which performs calibration of the voltage-controlled oscillator, A first comparator that receives a first voltage and compares the first voltage with the control voltage, A second comparator receives a second voltage with a lower voltage value than the first voltage and compares the second voltage with the control voltage, A control circuit that changes the gain setting of the voltage-controlled oscillator based on the comparison results from the first comparator and the comparison results from the second comparator, A calibration circuit having

2. The calibration circuit according to claim 1, wherein the control circuit increases the gain setting of the voltage-controlled oscillator when the control voltage is higher than the first voltage in the comparison by the first comparator.

3. The calibration circuit according to claim 1, wherein the control circuit lowers the gain setting of the voltage-controlled oscillator when the control voltage is lower than the second voltage in the comparison by the second comparator.

4. The calibration circuit according to claim 1, comprising a resistive voltage divider circuit consisting of a plurality of resistive elements connected in series between a predetermined voltage supply line and a ground potential supply line, and a voltage generation circuit that divides the predetermined voltage and the ground potential using the resistive voltage divider circuit to generate the first voltage and the second voltage.

5. The calibration circuit according to claim 4, wherein the voltage generation circuit includes an N-channel MOS transistor connected in series with the resistive voltage divider circuit and having its drain and gate diode-connected, between the resistive voltage divider circuit and the ground potential supply line.

6. The calibration circuit according to claim 5, wherein the voltage generation circuit includes a constant current source connected in series with the resistive voltage divider circuit between the predetermined voltage supply line and one end of the resistive voltage divider circuit.

7. The voltage generation circuit is A current mirror circuit is configured by current mirroring a first P-channel MOS transistor whose source is connected to a supply line of a predetermined voltage, and a second P-channel MOS transistor connected in series with the resistive voltage divider circuit between the supply line of the predetermined voltage and the resistive voltage divider circuit. A reference resistor element having one end connected to the drain of the first P-channel MOS transistor and the other end grounded, A differential amplifier that receives a reference voltage input and supplies a differentially amplified signal, obtained by differentially amplified between the reference voltage and the potential at one end of the reference resistor element, to the gate of the first P-channel type MOS transistor, The calibration circuit according to claim 5, including the following:

8. The calibration circuit according to claim 1, wherein the phase-locked circuit is a PLL circuit.

9. The calibration circuit according to claim 1, wherein the phase-locking circuit is a CDR circuit.

Images