Digital phase-locked circuit

Abstract

This invention provides a digital phase-lock circuit that facilitates the correction of group delay caused by an LPF and enables the generation of phase-lock signals without being affected by distortion components, even when dealing with signals over a wide frequency range. [Solution] A digital phase-locking circuit comprising: a frequency range detection unit that includes an IIR type LPF and measures the frequency of an input AC voltage or current; a rectangular wave reference signal generation unit that includes a plurality of FIR type LPFs and a zero-crossing detector and generates a rectangular wave reference signal from the input AC voltage or current; a switch that selects and switches one of the plurality of FIR type LPFs according to the frequency of the input AC voltage or current measured by the frequency range detection unit; and a phase-locking signal generation unit that receives a rectangular wave reference signal formed from the signal from the FIR type LPF selected by the switch and generates a phase-locking signal based on the rectangular wave reference signal.

Description

[Technical Field]

[0001] The present invention relates to a digital phase-synchronization circuit, and more particularly to a fully digital phase-synchronization circuit used for phase synchronization of the input AC voltage or AC current of a bidirectional AC power converter. [Background technology]

[0002] In recent years, by utilizing FPGAs (Field Program Gate Allays) and other technologies, and using hardware description languages ​​(HDLs), it has become possible to realize electronic circuits that perform desired functions as small electronic chips without designing custom LSIs such as ASICs.

[0003] Traditionally, ADPLL (All Digital Phase Locked Loop), which digitizes all the components of a phase-locked circuit, has been implemented using HDL.

[0004] However, conventional ADPLLs were primarily used for phase synchronization of digital signals, such as clock signal synchronization, and were not used as phase synchronization circuits implemented in bidirectional AC power converters.

[0005] Bidirectional AC power converters used as simulated power supplies or loads are equipped with a phase-locking circuit to synchronize the output voltage or current with the input AC voltage or current from the equipment under test. The AC power from the equipment under test input to the bidirectional AC power converter contains distortion components (higher harmonics) and DC components due to disturbances. Therefore, it is necessary to remove these components from the input AC voltage or current using a high-pass filter (HPF) or low-pass filter (LPF).

[0006] Figure 1 shows the basic configuration for incorporating an ADPLL as a phase-locked circuit implemented in a bidirectional AC power converter.

[0007] The phase synchronization circuit 100 incorporating an ADPLL as a phase synchronization circuit implemented in a bidirectional AC power conversion device needs to have a configuration including an analog / digital converter (ADC) 102 that converts an input AC voltage or current 101, which is an analog signal, into a digital signal, an input section 103, an ADPLL 104, and an output section 108. In this configuration, the input section 103 includes a high-pass filter (HPF) 106 and a low-pass filter (LPF) 107, and is for removing distortion components (higher-order harmonics) and DC components caused by disturbances included in the input AC voltage or current 101.

[0008] The output section 105 includes a waveform bank RAM 108 and an AC gain 109, and is for outputting the digital-form phase synchronization signal from the ADPLL as an AC voltage or current.

[0009] Also, in order to implement the phase synchronization circuit 100 by HDL, it is necessary to digitize the input section and the output section excluding the ADC 102.

Summary of the Invention

Problems to be Solved by the Invention

[0010] In the phase synchronization circuit 100 of FIG. 1, when the LPF 106 is realized by a digital circuit, a phase delay occurs due to the LPF. Therefore, when digitizing the phase synchronization circuit, it is necessary to perform delay correction of the output signal according to the phase delay of the LPF.

[0011] The frequency range of the AC voltage or current input to the bidirectional AC power converter is a wide range from 40 Hz to 5 kHz. Therefore, when an infinite impulse response type (hereinafter also referred to as "IIR") LPF is adopted as the LPF, the phase delay changes according to the frequency, and thus it is difficult to correct the phase delay caused by the LPF when targeting an AC voltage or current in a wide frequency range.

[0012] The phase characteristics of a finite impulse response (FIR) low-pass filter (LPF) are linear with respect to frequency, which is expected to simplify phase delay correction. However, when targeting a wide frequency range from 40 Hz to 5 kHz, group delay correction has been difficult.

[0013] Furthermore, since the frequency of higher-order harmonics, which are distortion components caused by disturbances, changes based on the frequency of the input AC voltage or current, when dealing with inputs with a wide frequency range, such as in bidirectional AC power converters, there was a problem that FIR-type LPFs, which have inferior cutoff frequency characteristics compared to IIR-type LPFs, could not adequately remove the harmonic components.

[0014] In light of these problems, the present disclosure aims to provide a digital phase-lock circuit that facilitates the correction of group delay caused by an LPF and can generate a phase-lock signal without being affected by distortion components, even when targeting signals over a wide frequency range. [Means for solving the problem]

[0015] To solve these problems, this disclosure provides a digital phase-locking circuit comprising: a frequency range detection unit that includes an infinite impulse response low-pass filter and measures the frequency of an input AC voltage or current; a rectangular wave reference signal generation unit that includes a plurality of finite impulse response low-pass filters and a zero-cross detector and generates a rectangular wave reference signal from an input AC voltage or current; a switch that selects and switches one of a plurality of finite impulse response low-pass filters according to the frequency of the input AC voltage or current measured by the frequency range detection unit; and a phase-locking signal generation unit that receives a rectangular wave reference signal formed from the signals from the finite impulse response low-pass filters selected by the switch and generates a phase-locking signal based on the rectangular wave reference signal.

[0016] The phase-synchronization signal generation section of the digital phase-synchronization circuit of this disclosure may be equipped with an LPF group delay corrector. The LPF group delay corrector may include a plurality of ring buffers selected according to the selection of the low-pass filter by the switch.

[0017] In yet another embodiment of the present disclosure, the phase-locked signal generator may be configured to fix the signal output by the phase-locked signal generator for a certain period of time from the moment the low-pass filter selection is switched by the switch.

[0018] The digital phase-locked circuit of this disclosure may be implemented by hardware whose circuit configuration can be modified by a hardware description language. [Effects of the Invention]

[0019] The digital phase-locked circuit disclosed herein implements the LPF filter in the square wave reference signal generation unit as a finite impulse response LPF with linear phase delay characteristics, and switches between them according to the input frequency range. Furthermore, the frequency range detection unit employs an infinite impulse response LPF, which has excellent frequency characteristics, as it is not affected by phase delay.

[0020] This makes it easier to correct the group delay caused by the LPF included in the square wave signal input to the subsequent phase-locked signal generation unit, and also provides a digital phase-locked circuit that can generate a phase-locked signal without being affected by distortion components, even when targeting signals over a wide frequency range. [Brief explanation of the drawing]

[0021] [Figure 1] This diagram shows the basic configuration for incorporating an ADPLL as a phase-locked circuit implemented in a bidirectional AC power converter. [Figure 2] This is a diagram showing a schematic configuration of a phase-locked circuit according to a first embodiment of the digital phase-locked circuit of the present disclosure. [Figure 3]This diagram shows the frequency range over which the switch switches between the third and fourth low-pass filters. [Figure 4] This is a schematic diagram showing an example of a phase accumulator DDS. [Figure 5] This is a diagram illustrating the operation of a phase accumulator DDS. [Figure 6] This is a schematic diagram showing an example of an LPF group delay corrector. [Figure 7] This is a block diagram showing a schematic configuration of a phase-locked circuit according to a second embodiment of the digital phase-locked circuit of the present disclosure. [Modes for carrying out the invention]

[0022] Embodiments of this disclosure will be described in detail below with reference to the drawings. The following description is illustrative, and embodiments with modified configurations are possible without departing from the gist of this disclosure. Identical or similar reference numerals indicate identical or similar elements, and repeated descriptions may be omitted. Numerical values ​​in the following description are illustrative, and other numerical values ​​may be used in carrying out this disclosure without departing from the gist of this disclosure.

[0023] (First embodiment) One embodiment of the digital phase-locked circuit described herein, as illustrated in Figure 2, comprises: a frequency range detection unit 207 that includes an infinite impulse response low-pass filter and measures the frequency of an input AC voltage or current; a rectangular wave reference signal generation unit 208 that includes a plurality of finite impulse response low-pass filters and a zero-cross detector and generates a rectangular wave reference signal from an input AC voltage or current; a switch 211 that selects and switches one of a plurality of finite impulse response low-pass filters according to the frequency measured by the frequency range detection unit; and a phase-locked signal generation unit 204 that receives a rectangular wave reference signal formed from signals from the rectangular wave reference signal generation unit, which is generated by the signals from the finite impulse response low-pass filters 218 and 219 selected by the switch 211, and generates a phase-locked signal based on the rectangular wave reference signal.

[0024] Figure 2 shows a schematic configuration of a phase-lock circuit 200 according to a first embodiment of the digital phase-lock circuit of the present disclosure. In Figure 2, the phase-lock circuit 200 is shown as an example of a case where it is connected to an input AC voltage or current 201.

[0025] The phase-locking circuit 200 of this embodiment is designed for AC voltages or currents over a wide frequency range. In this embodiment, the example will be given for inputs covering a wide frequency range from 40 Hz to 5 kHz, but the frequency range may be other than that.

[0026] The phase-locking circuit 200 of this embodiment includes an input section 203 to which an input AC voltage or current converted into a digital signal by an A / D converter (ADC) 202 is input, a phase-locking signal generation section 204, and an output section 205. All sections other than the ADC 202 are composed of digital circuits.

[0027] The ADC202 of this disclosure is an analog-to-digital converter that digitizes an AC voltage or current signal input from an external source.

[0028] The input section 203 consists of a high-pass filter (HPF) 206, a frequency range detection unit 207, and a square wave reference signal generation unit 208. The HPF 206 is a high-pass filter that removes the DC component contained in the input AC voltage or current. In this embodiment, the phase delay of the HPF in the target frequency range of the input AC voltage or current is a negligibly small value, so an infinite impulse response (IIR) type digital filter can be used, but a finite impulse response (FIR) type digital filter may also be used. The input AC voltage or current from which the DC component has been removed by the HPF is output to the frequency range detection unit 207 and the square wave reference signal generation unit 208, which are connected to the subsequent stages.

[0029] Since the digital phase-locked circuit of this disclosure is composed of digital circuits except for the ADC, it may be implemented using hardware that can change its logic configuration using a hardware description language (HDL) such as an FPGA (Field Program Gate Allay).

[0030] (Frequency range detection unit) The frequency range detection unit 207 includes a first frequency detector 209 for the low frequency range, a second frequency detector 210 for the high frequency range, and a switch 211.

[0031] The first frequency detector 209 includes a first low-pass filter (LPF) 212, a first zero-crossing detector 213, and a first frequency counter 214. The second frequency detector 210 includes a second low-pass filter (LPF) 215, a second zero-crossing detector 216, and a second frequency counter 217.

[0032] The first and second LPFs are used to remove distortion components (harmonic signal components) from the input AC voltage or current whose frequency range is detected. Here, the cutoff frequency of the first LPF is set to 300 Hz, and the cutoff frequency of the second LPF is set to 3 kHz.

[0033] The phase-locked circuit has a wide frequency operating range, and the frequency of higher harmonics varies depending on the frequency. For example, the 50th harmonic at 50 Hz is 2.5 kHz, and the 50th harmonic at 1 kHz is 50 kHz. Therefore, multiple frequency detectors equipped with low-pass filters (LPFs) corresponding to the frequency range to be measured are provided.

[0034] Furthermore, each LPF is constructed as an IIR type. By using an IIR type LPF, the cutoff characteristics at frequencies above the cutoff frequency are improved, thus increasing the signal-to-noise ratio. Since the frequency range detection unit is not affected by phase delay, it is advantageous to use an IIR type LPF.

[0035] In the first and second frequency detectors, the first and second zero-crossing detectors respectively detect the zero-crossing of the output signals from the first and second LPFs, and the first and second frequency counters count the period of the zero-crossing signal and output it to the subsequent switch 211.

[0036] In this embodiment, the frequency range detection unit 207 is equipped with two frequency measuring instruments, one for the low frequency range and one for the high frequency range, in order to appropriately cut out harmonic components in the low frequency range and high frequency range depending on the target frequency range. However, it may be equipped with three or more instruments depending on the target frequency range.

[0037] The switch 211 is configured to output a selection signal sel to the selector 221 of the square wave reference signal generation unit 208, for selecting and switching the third and fourth low-pass filters 218 and 219 of the square wave reference signal generation unit 208 according to the frequency range of the input AC voltage or current based on signals from the first and second frequency counters. As will be described later, this selection signal sel outputs a selector selection signal according to the frequency of the input AC voltage or current 201 measured by the frequency range detection unit 207.

[0038] The switch 211 generates a NOT_SEL_STS signal, which is active high when the frequency of the input AC voltage or current is outside the target frequency range, and a NOT_SWITCH_STS signal, which is active low for a certain period of time after the low-pass filter is switched. These signals are output to the phase-synchronous signal generation unit 204. As will be described later, the phase-synchronous signal generation unit 204 is configured so that this NOT_SWITCH_STS signal is input to the CE terminals of the first flip-flop circuit 229 and the second flip-flop circuit 230.

[0039] Figure 3 shows the frequency range over which the switch 211 switches between the third low-pass filter 218 and the fourth low-pass filter 219.

[0040] In FIG. 3, a low frequency range f1 selected by the third low-pass filter 218 and a high frequency range f2 selected by the fourth low-pass filter 219 are shown. As shown in the figure, the low frequency range f1 is f min ≦f1≦f mid1 , and the high frequency range f2 is f mid2 ≦f2≦f max is set. Thus, f1 and f2 are provided with a hysteresis region that overlaps in the frequency range of f mid1 -f mid2 . This prevents frequent switching at the frequency boundary due to the jitter of the phase-locked loop circuit.

[0041] In addition, when the frequency range of the input AC voltage or current is smaller than f min or larger than f max , the switch outputs a signal sel for selecting the f zero generator to the selector.

[0042] In addition, when three or more frequency detectors are provided according to the target frequency range, it may be configured to select a rectangular wave generator according to three or more frequency ranges. In that case, the hysteresis region may be set as shown in FIG. 3 in two adjacent frequency ranges.

[0043] (Rectangular wave reference signal generation unit) Returning to FIG. 2, the rectangular wave reference signal generation unit 208 includes a third low-pass filter 218 for the low frequency range, a fourth low-pass filter 219 for the high frequency range, f zero generator 220, selector 221, and third zero-crossing detector 222.

[0044] The phase-locked loop circuit of the present disclosure is assumed to be used for phase synchronization of the input AC voltage or current of the bidirectional AC power conversion device. The input AC voltage or current input to the bidirectional AC power conversion device contains distortion components (harmonic components). Therefore, it is desirable to remove the harmonic components from the reference signal input to the phase-locked loop circuit for accurate phase detection.

[0045] To remove harmonic components, a low-pass filter (LPF) that removes frequency components higher than the frequency range of the input AC voltage or current should be provided. However, since the frequency range of the input AC voltage or current targeted by bidirectional AC power converters spans a wide frequency band from 40 Hz to 5 kHz, the cutoff frequency of the FIR-type LPF needs to be set differently for the low-frequency range and the high-frequency range.

[0046] Therefore, in this embodiment, a square wave reference signal generation unit 208 is used that allows selection between a third LPF 218 and a fourth LPF 219 in order to remove distortion components (harmonic signal components) from the input AC voltage or current. Here, the cutoff frequency of the third LPF 218 is set to 300 Hz, and the cutoff frequency of the fourth LPF 219 is set to 3 kHz.

[0047] The multiple LPFs 218 and 219 in the rectangular wave generation unit of this embodiment are characterized by being of the FIR type in order to easily compensate for the phase delay caused by the LPFs. By using FIR type LPFs, the phase delay becomes linear with respect to frequency. That is, the time delay caused by the third and fourth LPFs becomes a constant group delay regardless of frequency. For example, when using an FIR filter with a tap coefficient of 1, the phase delay is half the number of taps. As a specific example, when the number of taps of the FIR is 256 and the control period Δts = 4 μs, the group delay is 256 / (2 × 4 × 10 -6 ) can be calculated as = 0.512ms.

[0048] The outputs from the third and fourth LPFs are selected by a selector and input to the subsequent third cellocross detector 222 to generate a square wave, which is then output from the square wave reference signal generation unit 208.

[0049] Selector 221 controls the output from the third LPF218, the output from the fourth LPF219, and f zeroThe generator 220 is configured to select the output according to the selection signal sel from the switch 211 and output it to the subsequent phase-synchronized signal generation unit 204.

[0050] Therefore, the signal from the third or fourth LPF, selected according to the frequency of the input AC voltage or current, is converted into a square wave by the square wave reference signal generation unit 208 and input to the subsequent phase-locked signal generation unit 204 as a reference signal ref.

[0051] In this embodiment, the low-pass filter provided by the rectangular wave reference signal generation unit 208 was described as having two filters corresponding to two frequency ranges set in the frequency range detection unit 207. However, if three or more frequency detectors are provided depending on the target frequency range, then three or more low-pass filters selected according to the three or more frequency ranges may be provided.

[0052] (Phase synchronization signal generation section) Next, the phase-synchronized signal generation unit 204 will be described with reference to Figure 2. The phase-synchronized signal generation unit 204 includes a third frequency counter 224, a phase detector 225, a phase lead / lag counter 226, a loop filter 227, a normalization DDS 228, a first flip-flop circuit 229, a second flip-flop circuit 230, a phase accumulator DDS 231, a frequency limit circuit 232, a phase lock identifier 233, and an LPF group delay corrector 234. It is configured to output clock synchronization signal data dds[y-1:yz] to an output unit 205 which includes a waveform bank RAM 235 and an AC gain 236 that generate an analog output AC voltage or current.

[0053] The phase-locked signal generation unit 204 is a PLL (phase-locked loop) that receives the reference signal ref output from the square wave reference signal generation unit 208, generates a phase-locked signal based on the reference signal ref, and outputs it. It is entirely implemented using digital circuits.

[0054] (Third frequency counter) The third frequency counter 224 is configured to count the period of the reference signal ref input to the phase-synchronized signal generation unit 204 and input the count value to the subsequent normalization DDS 228. In a typical PLL, only the phase difference signal is used, but in the phase-synchronized signal generation unit of this embodiment, the phase change amount Δθ1, which is the center frequency of the synchronization signal pclk output from the phase-synchronized signal generation unit, and the phase change amount Δθ2, which controls the phase lead or lag from the center frequency of pclk are used in combination, so that the input frequency is stable and synchronization is always guaranteed as long as it is within the target frequency range described above.

[0055] The third frequency counter 224 counts one period of the square wave signal of the reference signal ref using the system's control period Δts. The third frequency counter 224 is configured to reset after each period of the reference signal ref. Therefore, the third frequency counter outputs a frequency count value ccnt for each period of the reference signal ref, which is then input to the subsequent normalization DDS 228.

[0056] Furthermore, the third frequency counter outputs a CCNT_STS signal, which indicates whether or not the third frequency counter is in an overflow state, to the phase-locking detector 233, which will be described later. Here, when the third frequency counter is in an overflow state, the CCNT_STS signal becomes active high.

[0057] (Phase detector) The phase detector 225 detects whether the signal, which is the feedback of the phase-synchronization signal output from the phase-synchronization signal generation unit, is phase-leading or lagging relative to the reference signal ref. The phase detector 225 is configured to compare the phases of the reference signal ref and the signal, and outputs a LEAD signal if the phase of the signal is leading the reference signal ref, a LAG signal if it is lagging, and a MATCH signal if they are in agreement. These signals are generated in synchronization with the reference signal ref at each period ti of the input frequency and are processed internally at control period intervals Δts.

[0058] (Phase Advance / Delay Counter) Next, the phase advance / delay counter 226 will be described. The phase advance / delay counter 226 is configured to count the phase difference between the reference signal ref and the signal at the control period Δts and output it as the phase difference count value pcnt. The phase difference count value pcnt is output every period ti of the reference signal ref. The phase difference count value pcnt counted by the phase advance / delay counter 226 has a negative polarity in the case of phase advance, a positive polarity in the case of phase delay, and is 0 when the phases match.

[0059] Also, the phase advance / delay counter 226 is configured to output a PCNT_STS signal, which is information indicating whether the counted phase advance / delay is within a predetermined range, to a phase lock discriminator 233 described later. In this embodiment, it is determined whether the counted phase advance / delay is within a predetermined range by -5 < pcnt < 5, and when the phase count value pcnt is within this range, the OCNT_STS signal is set to active high. However, the range of the phase count value pcnt may be other than this.

[0060] (Loop Filter) The phase difference count value pcnt is output to the loop filter 227. The loop filter 227 calculates a moving average of the phase difference count value pcnt over several periods of the reference signal ref and outputs the phase difference average count value pcnt ave configured to do so. By using the moving average of the phase difference count value pcnt to perform subsequent processing, the moving synchronization operation is stabilized even when the phase difference fluctuates greatly temporarily. Although not limited, here, it is configured to calculate a moving average over 16 periods and output it to the subsequent stage.

[0061] Also, the loop filter 227 is configured to output a pcnt avg _STS signal, which is information indicating whether the output phase difference average count value pcnt avg is within a predetermined range, to the phase lock discriminator 233 described later. In this embodiment, the output phase difference average count value pcntavg Determine whether it is within a predetermined range with -5 < pcnt < 5, and the phase difference average count value pcnt avg When pcnt is within this range avg sets the _STS signal to active high, but the range of the phase difference average count value pcnt avg may be otherwise.

[0062] (Normalized DDS) The normalized DDS228 performs a process of converting from the frequency count value ccnt and the phase difference average count value pcnt ave to the phase change amount Δθ that can be used by the subsequent phase accumulator DDS231.

[0063] Specifically, from the frequency count value ccnt and pcnt ave the phase change amount Δθ that is the frequency of the reference signal ref to be synchronized, that is, the center frequency of pclk output from the synchronization control unit 1と and the phase change amount Δθ2 that controls the phase advance / delay from the center frequency of pclk are output.

[0064] Assuming that the phase change amount Δθ1, the frequency count value ccnt, the control period Δts, and the period of the reference signal ref are ti, then ccnt = ti / Δts, so Δθ1 = 2 y ·Δts / ti = 2 y / ccnt is obtained. Here, y is the number of bits of the normalized DDS228.

[0065] Also, the phase change amount Δθ2 is obtained as follows.

[0066] pcnt ave Since pcnt is the average value of the phase difference, the phase difference ratio between the reference signal ref and the output signal signal of the phase control unit is pcnt ave / ccnt. Let the value obtained by converting this phase difference ratio to the input value of the phase accumulator DDS be Δθe, then Δθe = (pcnt ave / ccnt)·Δθ1.

[0067] Since Δθe is the phase difference itself, using it directly would result in an excessively large control variable, causing oscillation. Therefore, during the ADPLL transition, Δθ2 = (1 / 2 5 )·Δθe, while ADPLL is stable, Δθ² = (1 / 2 7 It is set to operate with )·Δθe. In this way, the normalized DDS228 uses a phase difference ratio to normalize the phase change amount of the ADPLL so that it is the same ratio regardless of frequency.

[0068] (Flip-flop circuit) Δθ1 and Δθ2 output from the normalized DDS228 are latched in a first flip-flop circuit 229 and a second flip-flop circuit 230, which operate with a control period Δts, and output to the DDS phase accumulator 231. The two flip-flop circuits are connected so that the NOT_SWITCH_STS signal from the switch 211 is input to the CE terminal. The switch 211 is configured to output an active low signal as the NOT_SWITCH_STS signal for a certain period of time after the low-pass filter is switched.

[0069] Therefore, the first flip-flop circuit 229 and the second flip-flop circuit 230 do not update Δθ1 and Δθ2, which are held for a certain period of time, when the low-pass filter is switched by the switch 211. As a result, the frequency and phase of the output from the phase-locked signal generation unit are fixed for a certain period of time. In this way, the phase-locked signal generated by the phase-locked signal generation unit 204 is not affected by the switching of the LPF due to the difference in group delays between the third LPF 218 and the fourth LPF 219 provided by the square wave reference signal generation unit 208.

[0070] This fixed time only needs to be greater than or equal to the group delay time of the switched LPF. In this embodiment, however, it is set to two cycles of the reference signal ref so that it is updated in conjunction with the zero-crossing at the third zero-crossing detector. This also prevents the ring buffer of the LPF group delay corrector, which will be described later, from being affected by past data remaining during switching.

[0071] (Phase Accumulator DDS) The phase accumulator DDS231 can change the output frequency with a fixed control period Δts. In this embodiment, the phase accumulator DDS is used as the oscillator for the phase-synchronized signal generation unit 204. The phase accumulator DDS231 operates by adding the phase change amount (Δθ1 + Δθ2), such that dds[y-1:0] = dds[y-1:0] + (Δθ1 + Δθ2). The following explanation assumes that the number of bits y of the DDS is 32, but the number of bits of the DDS may be other.

[0072] The DDS shown as an example in Figure 4(a) operates as follows: dds[31:0] = dds[31:0] + (Δθ1 + Δθ2)[31:0]. As shown in Figure 4(a), the DDS holds the output dds[31:0] in a D-FF (register). Here, dds[31:0] represents values ​​from 0d to 4294967295d by concatenating 32 bits in descending order, as shown in Figure 4(b). The last 'd' in the number indicates a decimal number. CE is input to the D-FF410 in Figure 4(a) at control period intervals Δts. Each time CE is input, (Δθ1 + Δθ2) is added. To simplify the explanation, the operation of the DDS will be described below when the phase change amount (Δθ1 + Δθ2) is constant Δθ.

[0073] If the value of Δθ is small, it takes time for dds[31:0] to reach full count. The period t of the output frequency depends on the value of Δθ. o The phase change amount Δθ and the output period t are determined. o The relationship is Δθ=(2 y (Δts) / t oIt is represented as follows.

[0074] When Δθ is added to dds[31:0] which is at full count, dds[31:0] becomes 0d. The full count of dds can be expressed in binary. dds[31:0]=4294967295d=1111_1111_1111_1111_1111_1111_1111b. The 'b' at the end of the numbers indicates binary. The underscores between the numbers are there to make the number of digits easier to see. For example, if we add 1b, we get 1_0000_0000_0000_0000_0000_0000_0000_0000b, but since the 33rd bit does not exist, this carry of 1 is lost and dds[31:0] becomes 0d. If we add 5d to dds[31:0]=4294967295d, we get dds[31:0]=4d. Thus, in this phase accumulator DDS, even when Δθ is added, dds[31:0] does not become 0d, so it is always added at Δθ intervals, and continuity is maintained because the intervals are equal.

[0075] Figure 5(a) shows the period t when Δθ is changed. o This shows an image. In this example, t o When the value of Δθ at =10ms is doubled, t o This shows how it becomes =20ms. Figure 5(b) is a diagram illustrating how to create a periodic waveform (phase clock). As shown in the figure, dds[31:0] is added with Δθ, so the periodic waveform (phase clock), pclk, is obtained by inverting the most significant bit, dds

[31] .

[0076] dds[31:0] is, 0000_0000_0000_0000_0000_0000_0000_0000b~ 0111_1111_1111_1111_1111_1111_1111_1111b and 1000_0000_0000_0000_0000_0000_0000_0000b~ 1111_1111_1111_1111_1111_1111_1111_1111b It can be divided into the ranges shown here. In these two ranges, the only difference is whether dds

[31] is 0 or 1, and dds[30:0] is exactly the same value. Therefore t o During this time, the intervals in which dds

[31] =0 and the intervals in which dds

[31] =1 are the same length of time. The inverted dds

[31] is called the phase clock or pclk (Phase Clock).

[0077] As explained above, the phase accumulator DDS231 uses the data from dds

[31] to output a period t corresponding to the input phase change amount Δθ. o It can be output as a PCL file.

[0078] Furthermore, the dds[31:0] data from the phase accumulator DDS231 is used as the read address for WaveBankRAM235, where the waveform data described later is stored.

[0079] (Action considering θ2) As shown in Figure 4(a), the phase accumulator DDS231 receives two inputs: a phase change amount Δθ1, which is the center frequency of the pclk output from the synchronization control unit, and a phase change amount Δθ2, which controls the phase lead / lag from the center frequency of the pclk. As mentioned above, Δθ1 is determined by the frequency count value ccnt from the third frequency counter 224, and is therefore reflected instantaneously at each period ti of the reference signal ref. Δθ2 controls the phase lead / lag from the center frequency, that is, it is the phase change amount of the pclk output from the phase control unit. As mentioned above, this Δθ2 is determined by a moving average using a loop filter, so the phase gradually synchronizes.

[0080] When Δθ² > 0, the input Δθ becomes larger, resulting in a higher frequency of pclk, which in turn allows for a phase advance. Conversely, when Δθ² < 0, the input Δθ becomes smaller, resulting in a lower frequency of pclk, which in turn allows for a phase delay.

[0081] (Frequency limit circuit) The frequency limit circuit 232 is configured to determine whether the frequency of pclk output from the phase accumulator DDC231 is within the specified range and to output an OUT_OF_RANGE_STS signal to the phase lock detector indicating whether the frequency of pclk is outside the specified range. Specifically, the frequency f of pclk pclk However, f min1 <f pclk <f max1 It is configured to determine whether or not this is the case. Here, f min1 =f min -f min ·Margin,f max1 =f max +f max • This is the margin. In this embodiment, the margin is set to 6.25%. min and f max This is determined as appropriate based on the specifications, but as described above, in this embodiment, f min is 40Hz, f max It is 5kHz.

[0082] (Phase-locking detector) The phase lock detector 233 is used to notify an external system of the operating status of the phase synchronization signal generation unit 204. The phase lock detector 233 receives the NOT_SEL_STS signal and NOT_SWITCH_STS signal from the switch 211, the CCNT_STS signal from the third frequency counter 224, the PCNT_STS signal from the phase lead / lag counter 226, and the pcnt signal from the loop filter 227. avg The _STS signal and the OUT_OF_RANGE_STS signal from the frequency limit circuit 232 are configured to be input, and the operating state of the phase-locked signal generation unit is determined using these signals as follows.

[0083] The phase lock detector 233 determines that the system is unlocked when three conditions are met: the input frequency is outside the specified range (NOT_SEL_STS signal is active high), a certain amount of time has elapsed since the square wave generator was switched (NOT_SWITCH_STS signal is active high), and the third frequency counter is overflowing (CCNT_STS signal is active high).

[0084] Also, pcnt avg within ±5 (pcnt avg A locked state is determined when all three conditions are met: the STS signal is active high, PCNT is within ±5 (PCNT_STS signal is active high), and the input frequency is within the specified range (NOT_SEL_STS signal is active low).

[0085] And, pcnt avg is outside the ±5 range (pcnt avg A state transition is determined when all three conditions are met: the _STS signal is active low, pcnt is within ±5 (PCNT_STS signal is active low), and the input frequency is within the specified range (NOT_SEL_STS signal is active low).

[0086] (LPF group delay corrector) The reference signal ref input to the phase-synchronized signal generation unit 204 includes a group delay due to the third LPF 218 or the fourth LPF 219 provided by the square wave reference signal generation unit 208. For this reason, the phase-synchronized signal generation unit 204 includes an LPF group delay corrector 234 in the feedback loop of pclk that delays the pclk output from the phase control unit by the amount of its group delay.

[0087] In the digital phase-locked circuit of this disclosure, the LPF of the rectangular wave reference signal generation unit 208 that forms the reference signal ref input to the phase-locked signal generation unit 204 is configured as an FIR type. Therefore, the delay caused by the LPF is a group delay with linear characteristics with respect to frequency. For this reason, the LPF group delay corrector can be easily corrected by using a ring buffer or the like as illustrated in Figure 6.

[0088] Figure 6 shows an example of an LPF group delay corrector using a ring buffer. The LPF group delay corrector 600 in Figure 6 includes a first ring buffer 610 and a second ring buffer 620 that operate with a control period Δts for group delay correction of the third LPF and the fourth LPF.

[0089] Let's explain using the example of correcting the group delay of 0.512 ms when the control period Δts is 4 μs, the tap coefficient is 1, and the order of the FIR filter is 256, as described above.

[0090] To compensate for this group delay, the value 128 addresses prior to the ring buffer is used as the signal for phase difference detection. In this case, the amount of delay to be compensated is 128 × 4 μs = 0.512 ms. Specifically, when pclk data is written to address 1, data at address 129 is read. After the next Δts has elapsed, pclk is written to address 2 and data at address 130 is read. In this way, the address difference between writing and reading is fixed at 128, and the data 128 addresses prior is output.

[0091] In the example shown in Figure 6, there is a first ring buffer 610 corresponding to the group delay amount of the third LPF, a second ring buffer 620 corresponding to the group delay amount of the fourth LPF, and a selector 630 that switches the outputs from the two ring buffers based on the signal SEL from the switch 211 and outputs it as a signal. When implementing a delay circuit using HDL, using memory to cause delays has advantages such as requiring less logic resources than using multiple stages of registers to cause delays.

[0092] (Output section) The output unit 205, specifically the phase-synchronization signal generation unit 204 of the mobile synchronization circuit in this embodiment, uses dds[y-1:0] from the phase accumulator DD231S as the read address to read waveform data stored in the waveform bank RAM235, and forms an analog-type synchronization signal with adjusted amplitude by multiplying that value by ACGAIN236.

[0093] In Figure 2, when the number of bits in the waveform bank RAM address is z (y > z), dds[y-1:yz] is used as the bit read address. For example, if the number of bits y in DDS is 32 and the number of bits z in the waveform bank RAM is 12, the upper 12 bits, dds[31:20], are used as the read address.

[0094] (Second embodiment) Next, a second embodiment of the digital phase-locked circuit of this disclosure will be described with reference to Figure 7. The phase-locked circuit 700 of this embodiment differs in that the square wave reference signal generation unit 702 includes a plurality of square wave generators 703 and 704, and the switch 211 is configured to select and switch one of the plurality of square wave generators according to the frequency measured by the frequency range detection unit.

[0095] In other words, the phase-synchronization circuit of this embodiment is a digital phase-synchronization circuit comprising: a frequency range detection unit 207 that includes an infinite impulse response type low-pass filter and measures the frequency of an input AC voltage or current; a rectangular wave reference signal generation unit 702 that includes a finite impulse response type low-pass filter and a zero-cross detector and has a plurality of rectangular wave generators that output a rectangular wave from an input AC voltage or current; a switch 211 that selects and switches one of the plurality of rectangular wave generators according to the frequency measured by the frequency range detection unit; and a phase-synchronization signal generation unit 204 that receives the rectangular wave reference signals from the rectangular wave generation circuits 703 and 704 selected by the switch 211 and generates a phase-synchronization signal based on the rectangular wave reference signal.

[0096] Figure 7 shows a schematic configuration of the phase-lock circuit 700 of this embodiment of the digital phase-lock circuit of the present disclosure. In Figure 7, the phase-lock circuit 700 is also shown as an example when it is connected to an input AC voltage or current 201. The phase-lock circuit 700 of this embodiment, like the first embodiment in Figure 2, is designed for AC voltages or currents over a wide frequency range. In this embodiment, the explanation will be given using an example where a wide frequency range from 40 Hz to 5 kHz is input, but the frequency range may be other ranges as well.

[0097] The phase-locking circuit 700 of this embodiment includes an input section 701 to which an input AC voltage or current converted into a digital signal by an A / D converter (ADC) 202 is input, a phase-locking signal generation section 204, and an output section 205. All parts other than the ADC 202 are composed of digital circuits. Components in Figure 7 that have the same reference numerals as in Figure 2 are the same as in Figure 2 and will not be described in detail here.

[0098] The input section 701 consists of a high-pass filter (HPF) 206, a frequency range detection unit 207, and a square wave reference signal generation unit 702.

[0099] Since the digital phase-locked circuit of this embodiment is also composed of digital circuits except for the ADC, it may be implemented using hardware that allows the logic configuration to be changed using a hardware description language (HDL) such as an FPGA (Field Program Gate Allay).

[0100] (Square wave reference signal generator) The rectangular wave reference signal generation unit 702 of this embodiment includes a first rectangular wave generator 703 for the low frequency range and a second rectangular wave generator 704 for the high frequency range, and f zero The system includes a generator 705 and a selector 706. The first square wave generator 703 includes a third low-pass filter (LPF) 707 and a third zero-crossing detector 708. The second square wave generator 704 includes a fourth low-pass filter (LPF) 709 and a fourth zero-crossing detector 710.

[0101] In this embodiment as well, two square wave generators are used, each equipped with a third LPF707 and a fourth LPF709, to remove distortion components (harmonic signal components) from the input AC voltage or current. Here, the cutoff frequency of the third LPF is set to 300 Hz, and the cutoff frequency of the fourth LPF is set to 3 kHz.

[0102] In this embodiment as well, the LPFs provided in each of the rectangular wave generation circuits 703 and 704 are configured as FIR type filters to facilitate the compensation of phase delay caused by the LPFs.

[0103] In the rectangular wave reference signal generation unit 702, the outputs from the third and fourth LPFs are input to the subsequent third and fourth cellocross detectors, respectively, to generate rectangular waves, which are then output from the first rectangular wave generator 703 and the second rectangular wave generator 704.

[0104] Selector 706 selects the output from the first square wave generator 703, the output from the second square wave generator 704, and f zero The generator 705 is configured to select the output according to the selection signal sel from the switch 211 and output it to the subsequent phase-synchronized signal generation unit 204.

[0105] Therefore, the square wave reference signal generation unit 702 inputs a square wave from a square wave generator selected according to the frequency of the input AC voltage or current as a reference signal ref to the subsequent phase-synchronized signal generation unit 204.

[0106] In this embodiment, the rectangular wave reference signal generation unit 702 was described as having two rectangular wave generators corresponding to two frequency ranges set in the frequency range detection unit 207. However, if three or more frequency detectors are provided depending on the target frequency range, then three or more rectangular wave generators selected according to the three or more frequency ranges may be provided.

[0107] The phase-synchronized signal generation unit 204 and the output unit 205 are the same as in the first embodiment, so their description is omitted here. [Explanation of symbols]

[0108] 200, 700... Phase locked circuit 201·············Input AC voltage or current 202·············A / D converter (ADC) 203, 701········· Input section 204... Phase synchronization signal generation section 205············Output section 206·············High-pass filter (HPF) 207·············Frequency range detection unit 208, 702... Square wave reference signal generator 209·············First frequency detector 210············Second frequency detector 211·············Switch 212············First Low-Pass Filter (LPF) 213·············First zero-cross detector 214·············First frequency counter 215············Second low-pass filter (LPF) 216·············Second zero-cross detector 217············Second frequency counter 218, 707... Third low-pass filter (LPF) 219, 709...The fourth low-pass filter (LPF) 220, 705·········f zero generator 221, 706·········Selector 222············Third zero-cross detector 224············Third frequency counter 225·············Optical detector 226············· Phase Lead / Lagging Counter 227·············Loop filter 228...Normalized DDS 229············First Flip-Flop Circuit 230············Second flip-flop circuit 231·············Phase Accumulator DDS 232·············Frequency limit circuit 233·············Phase Lock Detector 234·············LPF group delay corrector 235·············Wave Bank RAM 236·············AC Gain 600·············LPF group delay corrector 610·············First ring buffer 620·············Second ring buffer 630············Selector 703············First Square Wave Generator 704············Second square wave generator 708·············Third zero-cross detector 710·············Fourth zero-cross detector

Claims

1. A frequency range detection unit that includes an infinite impulse response low-pass filter and measures the frequency of the input AC voltage or current, A rectangular wave reference signal generation unit that includes multiple finite impulse response low-pass filters and zero-crossing detectors and generates a rectangular wave reference signal from the input AC voltage or current, A switch that selects and switches one of the plurality of finite impulse response type low-pass filters according to the frequency of the input AC voltage or current measured by the frequency range detection unit, A phase-synchronization signal generation unit receives a rectangular wave reference signal formed from the signal from the finite impulse response type low-pass filter selected by the switch, and generates a phase-synchronization signal based on the rectangular wave reference signal. A digital phase-locked circuit equipped with a digital phase-locked circuit.

2. The digital phase-synchronous circuit according to claim 1, characterized in that the phase-synchronous signal generation unit is equipped with an LPF group delay corrector.

3. The digital phase-locked circuit according to claim 2, characterized in that the LPF group delay corrector includes a plurality of ring buffers selected according to the selection of the finite impulse response type low-pass filter by the switch.

4. The digital phase-locked circuit according to claim 1, wherein the switch is configured to fix the signal output by the phase-locked signal generation unit for a certain period of time from the time the selection of the finite impulse response type low-pass filter is switched.

5. The digital phase-locked circuit according to claim 1, characterized in that the frequency range detection unit includes a frequency detector that detects a plurality of different frequency ranges, and each frequency range detected by each frequency detector is set to have a region that partially overlaps with an adjacent frequency range, and this partially overlapping region is set as the hysteresis region for selecting the plurality of finite impulse response type low-pass filters.

6. A digital phase-locked circuit according to any one of claims 1 to 5, implemented by hardware capable of changing the circuit configuration using a hardware description language.

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