Semiconductor equipment

Abstract

To provide a semiconductor device with a novel configuration. [Solution] The system comprises a first substrate on which a first peripheral circuit having a function for driving a first memory cell is provided, a second substrate, and a first memory cell layer having a first element layer having a first memory cell. The first memory cell has a first transistor and a first capacitor. The first transistor has a semiconductor layer having a metal oxide in the channel formation region. The first memory cell layer is stacked on the first substrate in a direction perpendicular or approximately perpendicular to the surface of the first substrate. The second substrate has a circuit for writing or reading data in the first memory cell. The first peripheral circuit and the first memory cell are electrically connected via a first through-electrode provided on the second substrate and the first element layer.

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor properties, and includes circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, or electronic components with chips housed in packages are examples of semiconductor devices. In addition, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices and may contain semiconductor devices. [Background technology]

[0003] Metal oxides are attracting attention as semiconductors applicable to transistors. Transistors having a metal oxide semiconductor in the channel formation region (hereinafter sometimes referred to as "oxide semiconductor transistors" or "OS transistors") have been reported to have extremely low off-currents (e.g., Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been fabricated (e.g., Non-Patent Documents 3 and 4).

[0004] The manufacturing process for OS transistors can be incorporated into conventional CMOS processes for Si transistors. For example, Patent Document 1 discloses a configuration in which multiple layers of memory cell arrays having OS transistors are stacked on a substrate on which Si transistors are provided. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2012 / 0063208 [Non-patent literature]

[0006] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-Patent Document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). [Overview of the project] [Problems that the invention aims to solve]

[0007] One aspect of the present invention aims to provide a semiconductor device with a novel configuration or the like. Or one aspect of the present invention aims to provide a semiconductor device with a novel configuration or the like that can reduce manufacturing costs in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention aims to provide a semiconductor device with a novel configuration or the like that is excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention aims to provide a semiconductor device with a novel configuration or the like that can miniaturize the device in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention aims to provide a semiconductor device with a novel configuration or the like that has small fluctuations in the electrical characteristics of transistors and excellent reliability in a semiconductor device that functions as a memory device using an extremely small off-current.

[0008] The description of multiple problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all the illustrated problems. Also, problems other than those listed will become apparent from the description of this specification, and such problems can also be the problems of one aspect of the present invention.

Means for Solving the Problems

[0009] One aspect of the present invention includes a first substrate provided with a first peripheral circuit having a function of driving a first memory cell, a second substrate, and a first memory cell layer having a first element layer having the first memory cell. The first memory cell has a first transistor and a first capacitor. The first transistor has a semiconductor layer having a metal oxide in a channel formation region. The first memory cell layer is laminated and provided on the first substrate in a direction perpendicular or substantially perpendicular to the surface of the first substrate. The first peripheral circuit and the first memory cell are electrically connected via a first through electrode provided in the second substrate and the first element layer. It is a semiconductor device.

[0010] One aspect of the present invention is a semiconductor device having a first substrate provided with a first peripheral circuit having a function of driving a first memory cell, a second substrate, and a first memory cell layer having a first element layer having the first memory cell. The first memory cell has a first transistor and a first capacitor. The first transistor has a semiconductor layer having a metal oxide in a channel formation region. The first memory cell layer is provided laminated on the first substrate in a direction perpendicular or substantially perpendicular to the surface of the first substrate. The second substrate has an amplifier circuit for writing or reading data in the first memory cell. The first peripheral circuit and the first memory cell are electrically connected via a first through electrode provided in the second substrate and the first element layer.

[0011] In one aspect of the present invention, a semiconductor device having a plurality of first element layers provided laminated in a direction perpendicular or substantially perpendicular to the surface of the first substrate is preferable.

[0012] In one aspect of the present invention, a semiconductor device having a first substrate provided with a second peripheral circuit having a function of driving a second memory cell and a third substrate provided with a second memory cell layer having a second element layer having the second memory cell is preferable. The first memory cell layer is provided between the first substrate and the second memory cell layer. The second memory cell has a second transistor and a second capacitor. The second transistor has a semiconductor layer having silicon in a channel formation region. The second peripheral circuit and the second memory cell are electrically connected via a second through electrode provided in the second substrate, the third substrate, the first element layer, and the second element layer.

[0013] In one aspect of the present invention, a semiconductor device in which the first substrate has a CPU and the second memory cell has a function of holding data held by the CPU is preferable.

[0014] In one embodiment of the present invention, a semiconductor device is preferred which comprises a first substrate on which a second peripheral circuit having a function for driving a second memory cell is provided, a third substrate, and a second memory cell layer having a second element layer having a second memory cell, wherein the first memory cell layer is provided between the first substrate and the second memory cell layer, the second memory cell has a third to fifth transistor and a third capacitor, the third to fifth transistors have a semiconductor layer having a metal oxide in the channel formation region, and the second peripheral circuit and the second memory cell are electrically connected via a second through-electrode provided on the second substrate, the third substrate, the first element layer and the second element layer.

[0015] In one embodiment of the present invention, the metal oxide is a semiconductor device comprising In, Ga, and Zn. A semiconductor device is preferred.

[0016] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings. [Effects of the Invention]

[0017] One embodiment of the present invention can provide a semiconductor device with a novel configuration. Alternatively, one aspect of the present invention can provide a semiconductor device with a novel configuration that can reduce manufacturing costs in a semiconductor device that functions as a memory device utilizing an extremely small off-current. Alternatively, one aspect of the present invention can provide a semiconductor device with a novel configuration that excels in low power consumption in a semiconductor device that functions as a memory device utilizing an extremely small off-current. Alternatively, one aspect of the present invention can provide a semiconductor device with a novel configuration that can reduce the size of the device in a semiconductor device that functions as a memory device utilizing an extremely small off-current. Alternatively, one aspect of the present invention can provide a semiconductor device with a novel configuration that excels in reliability due to small fluctuations in the electrical characteristics of the transistor in a semiconductor device that functions as a memory device utilizing an extremely small off-current.

[0018] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have to possess all of the exemplified effects. In addition, any problems, effects, and novel features of one embodiment of the present invention other than those described above will become clear from the description and drawings of this specification. [Brief explanation of the drawing]

[0019] [Figure 1] Figures 1A through 1C show examples of semiconductor device configurations. [Figure 2] Figures 2A and 2B show examples of semiconductor device configurations. [Figure 3] Figures 3A to 3C show examples of semiconductor device configurations. [Figure 4] Figures 4A and 4B show examples of semiconductor device configurations. [Figure 5] Figures 5A to 5D show examples of semiconductor device configurations. [Figure 6] Figures 6A and 6B show examples of semiconductor device configurations. [Figure 7] Figures 7A to 7C show examples of semiconductor device configurations. [Figure 8] Figures 8A and 8B show examples of semiconductor device configurations. [Figure 9] Figures 9A and 9B show examples of semiconductor device configurations. [Figure 10] Figures 10A to 10C show examples of semiconductor device configurations. [Figure 11] Figure 11 shows an example of a semiconductor device configuration. [Figure 12] Figure 12 shows an example of the configuration of a semiconductor device. [Figure 13] Figures 13A and 13B show examples of semiconductor device configurations. [Figure 14] Figure 14 shows an example of the configuration of a semiconductor device. [Figure 15] Figure 15 shows an example of the configuration of a semiconductor device. [Figure 16] Figures 16A and 16B show examples of semiconductor device configurations. [Figure 17] Figures 17A and 17B show examples of semiconductor device configurations. [Figure 18] Figure 18 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 19] Figure 19 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 20] Figure 20 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 21] Figure 21 is a conceptual diagram showing an example of a semiconductor device configuration. [Figure 22] Figures 22A and 22B are schematic diagrams illustrating an example of an electronic component. [Figure 23] Figure 23 shows an example of an electronic device. [Modes for carrying out the invention]

[0020] Embodiments of the present invention are described below. However, it will be readily apparent to those skilled in the art that an embodiment of the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, an embodiment of the present invention is not to be interpreted as being limited to the contents of the embodiments shown below.

[0021] In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. For example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In drawings, identical elements, elements with similar functions, elements of the same material, or elements formed simultaneously may be denoted by the same reference numeral, and repeated explanations may be omitted.

[0023] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0024] Furthermore, when the same designation is used for multiple elements, especially when it is necessary to distinguish them, identification designations such as "_1", "_2", "[n]", and "[m,n]" may be added to the designation. For example, the second wiring GL is written as wiring GL[2].

[0025] (Embodiment 1) An example of the configuration of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 1C. A semiconductor device is a device that utilizes semiconductor properties and includes a circuit containing semiconductor elements (transistors, diodes, photodiodes, etc.) or a device having such a circuit. The semiconductor device described in this embodiment has the function of a memory device that utilizes a transistor with an extremely small off-current.

[0026] Figure 1A is a schematic cross-sectional view of the semiconductor device described in this embodiment.

[0027] The semiconductor device 10A shown in Figure 1A has peripheral circuits 20 provided on a substrate 25 and memory cell layers 31_1 to 31_N provided with a plurality of memory cells 40_1 to 40_N (where N is an integer) that constitute a memory cell array. The memory cell layers 31_1 to 31_N are sometimes collectively referred to as the memory cell layer 30.

[0028] Although the substrate 25 on which the peripheral circuit 20 is provided is described as a silicon substrate, this embodiment is not limited to this. A silicon substrate refers to a substrate that uses silicon as a semiconductor material, such as a single-crystal silicon substrate. Not limited to silicon, materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., may also be used as the substrate.

[0029] The peripheral circuit 20 includes circuits for outputting signals to drive the memory cells 40_1 to 40_N, such as row drivers and column drivers. The peripheral circuit 20 may also be referred to as a control circuit, drive circuit, or circuit.

[0030] A row driver is a circuit that outputs a signal to drive a memory cell to a word line. The word line has the function of transmitting the word signal to the memory cell. A row driver is sometimes called a word line-side drive circuit. A row driver includes a decoder circuit for selecting the word line according to a specified address, and a buffer circuit, etc. A column driver is a circuit that outputs a signal to drive a memory cell to a bit line, outputs data to be written to the memory cell, and amplifies the data read from the memory cell to the bit line. The bit line has the function of transmitting data to the memory cell. A column driver is sometimes called a bit line-side drive circuit. A column driver includes a sense amplifier, a precharge circuit, a decoder circuit for selecting the bit line according to a specified address, etc.

[0031] The peripheral circuit 20 is preferably used to drive the memory cells 40_1 to 40_N at high speed. Therefore, the peripheral circuit 20 is preferably equipped with high-speed transistors. The transistors in the peripheral circuit 20 are preferably transistors (Si transistors) with excellent field-effect mobility and a channel formation region made of silicon.

[0032] Each of the memory cell layers 31_1 to 31_N has an element layer 51 and a substrate 52. The element layer 51 is a layer containing elements such as transistors and capacitors. Each of the memory cell layers 31_1 to 31_N has memory cells 40_1 to 40_N in the element layer 51. Although two memory cells 40_1 to 40_N are shown in each illustration for the element layer 51, in reality, a configuration with three or more memory cells can be provided.

[0033] The memory cell layers 31_1 to 31_N are stacked perpendicularly or approximately perpendicularly to the surface of the substrate 25. In other words, the element layer 51 and the substrate 52 are stacked perpendicularly or approximately perpendicularly to the surface of the substrate 25. This configuration allows for an increase in the number of memory cells 40_1 to 40_N per unit area. Therefore, the memory density can be increased. In the schematic cross-sectional diagram shown in Figure 1A, the direction perpendicularly or approximately perpendicularly to the surface of the substrate 25 is defined as the z-axis direction in order to explain the arrangement of each component. For ease of understanding, the z-axis direction may be referred to as the direction perpendicular to the surface of the substrate 25 in this specification. "Approximately perpendicular" refers to a state in which the components are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0034] The through-electrodes 54 provided in the memory cell layers 31_1 to 31_N, and the metal bumps 53 provided between the through-electrodes 54, function as wiring for electrically connecting the peripheral circuit 20 and the memory cells 40_1 to 40_N. Since the through-electrodes 54 and metal bumps 53, which function as wiring, can be provided in a direction perpendicular or approximately perpendicular to the surface of the substrate 25, the distance between the peripheral circuit 20 and the memory cells 40_1 to 40_N can be shortened. The through-electrodes 54 and metal bumps 53 can function as bit lines for writing or reading data from the memory cells 40_1 to 40_N, or as word lines for selecting the memory cells 40_1 to 40_N.

[0035] Figure 1B schematically illustrates the data signal Data between the peripheral circuit 20 and the memory cells 40_1 to 40_N. In the semiconductor device 10A of Figure 1A, the input and output of the data signal Data between the peripheral circuit 20 and the memory cells 40_1 to 40_N can be performed via through electrodes 54 provided in the element layer 51 and the substrate 52, and metal bumps 53 provided between the through electrodes 54. As described above, the through electrodes 54 and metal bumps 53, which function as wiring, can shorten the distance between the peripheral circuit 20 and the memory cells 40_1 to 40_N. Therefore, the peripheral circuit 20 can input and output the data signal Data not only with the lower memory cell layer 31_1 but also with the upper memory cell layer 31_N.

[0036] The through-electrodes 54, which penetrate the substrate 52 of the memory cell layers 31_1 to 31_N and the element layer 51, can be formed using through-electrode technology such as TSV (Through Silicon Via). Furthermore, the through-electrodes 54, which penetrate each of the memory cell layers 31_1 to 31_N, can be connected via metal bumps 53 (also called microbumps) provided between each of the memory cell layers 31_1 to 31_N. Alternatively, the through-electrodes 54 of each of the memory cell layers 31_1 to 31_N may be connected using Cu-Cu junctions instead of metal bumps 53. Cu-Cu junctions are a technology that achieves electrical conductivity by connecting Cu (copper) pads. Alternatively, the through-electrodes 54 may be directly connected without using Cu (copper) pads.

[0037] Figure 1C illustrates the circuit configuration of memory cells applicable to memory cells 40_1 to 40_N. The memory circuit 40p shown in Figure 1C has a transistor 41 and a capacitor 42. One of the sources or drains of transistor 41 is connected to wiring BL. The gate of transistor 41 is connected to wiring WL. The other of the sources or drains of transistor 41 is connected to capacitor 42.

[0038] Transistor 41 is preferably an OS transistor. OS transistors have extremely low off-currents. Therefore, the charge corresponding to the data written to memory cells 40_1 to 40_N can be held in capacitor 42 for a long time. In other words, data that has been written to memory cells 40_1 to 40_N can be held for a long time. As a result, the frequency of data refresh can be reduced, and the power consumption of a semiconductor device according to one embodiment of the present invention can be reduced.

[0039] The memory circuit 40p, which has transistor 41, can be called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) using an OS transistor as memory. Because it can be constructed with one transistor and one capacitor, it enables high memory density. In addition, by using an OS transistor, the data retention period can be extended.

[0040] Although transistor 41 is shown as a top-gate or bottom-gate transistor without a back gate electrode, the structure of transistor 41 is not limited to this. It is preferable that transistor 41 has a back gate electrode. By controlling the potential applied to the back gate electrode, the threshold voltage of transistor 41 can be controlled. This allows, for example, increasing the on-current and decreasing the off-current of transistor 41.

[0041] Since memory cells 40_1 to 40_N using OS transistors can be freely arranged on element layers containing OS transistors, integration can be easily achieved. Therefore, the number of memory cells that can be placed per unit area can be increased, thereby increasing memory density.

[0042] Furthermore, OS transistors possess superior electrical characteristics compared to Si transistors in high-temperature environments. Specifically, even at high temperatures of 125°C to 150°C, the ratio of on-current to off-current is large, enabling good switching operation. OS transistors also operate well within the temperature range of -40°C to 190°C. In other words, OS transistors have excellent heat resistance. This is superior to the heat resistance of Phase Change Memory (PCM) (-40°C to 150°C), Resistance Random Access Memory (ReRAM) (-40°C to 125°C), and Magnetoresistive Random Access Memory (MRAM) (-40°C to 105°C).

[0043] Figure 1A describes a configuration in which the memory cell layer 30 is bonded to the substrate 25 using metal bumps 53 and through electrodes 54, but other configurations are also possible.

[0044] Figures 2A and 2B illustrate a configuration in which through-electrodes 54 connect the electrodes of the peripheral circuit 21 on the substrate 25 to the electrodes of the element layer 51 on the memory cell layer 30.

[0045] Figure 2A is a schematic cross-sectional view of a memory cell layer 31 applicable to memory cell layers 31_1 to 31_N of Figure 1A. Figure 2A shows an element layer 51 provided in contact with the substrate 52. Figure 2A also shows a junction layer 57 on the element layer 51.

[0046] The element layer 51 is an OS transistor M of the memory cell 40. OS , and electrode M Cu It has. Electrode M Cu This is the electrode that is connected when forming the through electrode 54. Electrode M Cu When using copper (Cu), it is effective to cover the electrode surface with gold (Au) to suppress oxidation of the surface when forming the through electrode 54. Note that electrode MCu It is also possible to adopt a configuration having a conductor other than copper.

[0047] The bonding layer 57 flattens the bonding surface with the substrate 25, and silicon oxide (SiO X ) etc. is suitable, in which the hydroxyl groups between the bonding layer 57 and the surface of the substrate 25 can form a bond. Silicon oxide (SiO X ) is preferable because it can improve the flatness of the surface as compared with silicon nitride (SiN) etc. Note that when the layer formed on the surface of the substrate 25 and the bonding layer 57 are each formed of a layer containing silicon oxide (SiO X ) and the flatness of the silicon oxide is enhanced, the hydroxyl groups (OH groups) on the surface of the silicon oxide on the surface of the substrate 25 and the hydroxyl groups (OH groups) on the surface of the silicon oxide of the bonding layer 57 are bonded by van der Waals forces, and Si-O-Si bonds and H2O molecules may be generated by subsequent heat treatment.

[0048] FIG. 2B is a cross-sectional schematic view in the case where the memory cell layer 31 of FIG. 2A is bonded to the substrate 25 face down (face-down bonding). The substrate 25 has the Si transistor M Si and the electrode M Cu which the peripheral circuit 21 has. The through electrodes 54 provided in the element layer 51 and the substrate 52 are provided so as to connect the electrode M Cu which the memory cell 40 has and the electrode M Cu which the peripheral circuit 21 has.

[0049] The bonding of the substrate 25 and the memory cell layer 31 can be performed in a range with a maximum of 350°C to 450°C without exposing it to a high temperature such as 1000°C or higher by enhancing the flatness of the bonding layer 57 etc. That is, the bonding of the substrate 25 and the memory cell layer 31 can be performed without exposing it to a high temperature. Therefore, along with the element layer 51 being exposed to a high temperature, the OS transistor M OSThis makes it possible to suppress fluctuations in the electrical characteristics. In addition, since the Si transistor is not exposed to high temperatures during bonding of the substrate 25 and the memory cell layer 31, it becomes possible to use copper wiring.

[0050] The bonding of the substrate 25 and the memory cell layer 31 described above is effective not only when bonding memory cell layers 31 having OS transistors, but also when bonding memory cell layers having Si transistors. Since the bonding temperature can be maintained within a range of 350°C to 450°C, it is also possible to configure the system to alternately bond memory cell layers having Si transistors and memory cell layers having OS transistors.

[0051] One embodiment of the present invention uses OS transistors, which have extremely low off-currents, as transistors provided in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and manufactured repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs. Another embodiment of the present invention allows for improved memory density by arranging the transistors constituting the memory cell vertically rather than in a planar direction, thereby enabling miniaturization of the device. Furthermore, because OS transistors exhibit less fluctuation in electrical characteristics compared to Si transistors even in high-temperature environments, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, resulting in a semiconductor device that functions as a highly reliable memory device.

[0052] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0053] (Embodiment 2) In this embodiment, a configuration example of a semiconductor device, which is one aspect of the present invention, will be described, but with a configuration different from that of Embodiment 1. Details of explanations that overlap with those of Embodiment 1 will be omitted, as they will be referenced from the previous explanation.

[0054] Figure 3A is a schematic cross-sectional view of the semiconductor device described in this embodiment. The semiconductor device 10B shown in Figure 3A has another memory cell layer 60 on top of the memory cell layer 30 described in Embodiment 1. The other memory cell layer 60 has, as an example, memory cell layers 61_1 and 61_N (memory cell layers 61_1 and 61_2 are shown) on which memory cells 70_1 and 70_N (memory cells 70_1 and 70_2 are shown). Also in Figure 3A, the substrate 25 has peripheral circuits 21 in addition to peripheral circuits 20.

[0055] The peripheral circuit 21 includes circuits for outputting signals to drive the memory cells 70_1 to 70_N, such as a row driver and a column driver. It is preferable that the peripheral circuit 21 drives the memory cells 70_1 to 70_N at high speed. Therefore, it is preferable that the peripheral circuit 21 has high-speed transistors. The transistors in the peripheral circuit 21 are preferably transistors (Si transistors) with excellent field-effect mobility and a silicon channel formation region. The peripheral circuit 21 may also be referred to as a control circuit, drive circuit, or simply a circuit.

[0056] Each of the memory cell layers 61_1 to 61_N has an element layer 62 and a substrate 63. The memory cell layers 61_1 to 61_N are stacked perpendicular to or approximately perpendicular to the surface of the substrate 25. This configuration allows for an increase in the number of memory cells 70_1 to 70_N per unit area, thereby increasing memory density. The schematic cross-sectional diagram shown in Figure 3A defines the z-axis direction, which is perpendicular to or approximately perpendicular to the surface of the substrate 25, in order to explain the arrangement of each component.

[0057] A portion of the through-electrodes 54 provided in the memory cell layers 31_1 to 31_N, a portion of the through-electrodes 54A provided in the memory cell layers 61_1 to 61_N, and a portion of the metal bumps 53 provided between the through-electrodes 54A and 54 function as wiring for electrically connecting the peripheral circuit 21 and the memory cells 70_1 to 70_N. Since the through-electrodes 54, 54A, and metal bumps 53, which function as wiring, can be provided in a direction perpendicular or approximately perpendicular to the surface of the substrate 25, the distance between the peripheral circuit 21 and the memory cells 70_1 to 70_N can be shortened. The through-electrodes 54, 54A, and metal bumps 53 can function as bit lines for writing or reading data from the memory cells 70_1 to 70_N, or as word lines for selecting the memory cells 70_1 to 70_N.

[0058] Figure 3B illustrates the circuit configuration of memory cells applicable to memory cells 70_1 to 70_N. The memory circuit 70p shown in Figure 3B has transistors 71 to 73 and a capacitor 74. One of the sources or drains of transistor 71 is connected to wiring BL. The gate of transistor 71 is connected to wiring WL. The other of the sources or drains of transistor 71 is connected to the gate of transistor 72 and capacitor 74. One of the sources or drains of transistor 72 is connected to wiring BL. The other of the sources or drains of transistor 72 is connected to one of the sources or drains of transistor 73. The gate of transistor 73 is connected to wiring RL, which provides a read signal.

[0059] In Figure 3B, a shared wiring BL is shown for both data writing and reading; however, different wirings may be used for the wiring BL. For example, transistors 71 and 72 may be connected to different wiring BLs (reading wiring RBL and writing wiring WBL). Also, although Figure 3B illustrates a memory circuit with three transistors, a memory circuit with two transistors can be used by omitting transistor 73.

[0060] Transistor 71 is preferably an OS transistor. OS transistors have extremely low off-currents. Therefore, the charge corresponding to the data written to memory cells 70_1 to 70_N can be held for a long time in the gate of transistor 72 and capacitor 74. In other words, data written to memory cells 70_1 to 70_N can be held for a long time. That is, the memory circuit 70p has non-volatile properties. A memory cell composed of a memory circuit 70p having an OS transistor is referred to in this specification as NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory). Since NOSRAM rewrites data by charging and discharging a capacitor, in principle there is no limit to the number of rewrites, and data can be written and read with low energy. In addition, because the circuit configuration of the memory cell is simple, it is easy to increase the capacity. Therefore, NOSRAM is a memory with a large capacity, low power consumption, and high rewrite endurance.

[0061] NOSRAM can increase the data capacity per memory cell compared to DOSRAM by using multi-level memory with three or more values. Furthermore, NOSRAM is suitable for long-term data retention because written data can be read non-destructively. On the other hand, DOSRAM requires destructive reading of written data, making it suitable for use in memory layers with high write and read frequencies. Therefore, it is preferable to position the memory cell layer 30, which contains DOSRAM memory cells, closer to the substrate 25 than the memory cell layer 60, which contains NOSRAM memory cells. In other words, it is preferable to provide the memory cell layer 30 between the substrate 25 and the memory cell layer 60.

[0062] The data held in the memory cells can be configured to be transferred to the NOSRAM as appropriate depending on the usage status. For example, as shown in Figure 3C, the data signals Data held in memory cells 40_1 to 40_N can be transferred to memory cells 70_1 and 70_2 via peripheral circuits 20 and 21.

[0063] One embodiment of the present invention uses OS transistors, which have extremely low off-currents, as transistors provided in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and manufactured repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs. Another embodiment of the present invention allows for improved memory density by arranging the transistors constituting the memory cell vertically rather than in a planar direction, thereby enabling miniaturization of the device. Furthermore, because OS transistors exhibit less fluctuation in electrical characteristics compared to Si transistors even in high-temperature environments, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, resulting in a semiconductor device that functions as a highly reliable memory device.

[0064] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0065] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device, which is one aspect of the present invention, will be described, with a configuration different from that of Embodiments 1 and 2. Details of explanations that overlap with Embodiments 1 and 2 will be omitted, as they will be referenced from those explanations.

[0066] Figure 4A is a schematic cross-sectional view of a memory cell layer 31A applicable to a semiconductor device according to one embodiment of the present invention. The memory cell layer 31A shown in Figure 4A has a configuration in which multiple memory cells 40_1 in the element layer 51 are stacked in the z-axis direction, similar to the memory cell layer 31_1 described in Embodiment 1 or 2. Although Figure 4A shows the memory cell layer 31_1, the same applies to memory cell layers 31_2 to 31_N. The wiring connecting the memory cells 40_1 in the element layer 51 is sometimes called a wiring LBL (local bit line). Unlike the through-electrode 54 described in the above embodiment, the wiring LBL is a wiring composed of a conductor provided between the layers of the element layer 51.

[0067] Figure 4B is a schematic cross-sectional view of the semiconductor device described in this embodiment. The semiconductor device 10C shown in Figure 4B has a configuration in which the configuration of the memory cell layer 31A described in Figure 4A is applied to the memory cell layers 31_1 to 31_N of each layer. By adopting this configuration, the number of memory cells per unit area can be increased, and the number of metal bumps 53 and through electrodes 54 can be reduced, thereby reducing manufacturing costs and increasing memory density.

[0068] One embodiment of the present invention uses OS transistors, which have extremely low off-currents, as transistors provided in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and manufactured repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs. Another embodiment of the present invention allows for improved memory density by arranging the transistors constituting the memory cell vertically rather than in a planar direction, thereby enabling miniaturization of the device. Furthermore, because OS transistors exhibit less fluctuation in electrical characteristics compared to Si transistors even in high-temperature environments, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, resulting in a semiconductor device that functions as a highly reliable memory device.

[0069] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0070] (Embodiment 4) In this embodiment, a configuration example of a semiconductor device, which is one aspect of the present invention, will be described, but with a configuration different from that of Embodiments 1 to 3. Details of explanations that overlap with Embodiments 1 to 3 will be omitted, as they will be referenced from those previous explanations.

[0071] Figure 5A is a schematic cross-sectional view of a memory cell layer 31B applicable to a semiconductor device according to one embodiment of the present invention. The memory cell layer 31B shown in Figure 5A has a configuration in which peripheral circuits 20_1 (peripheral circuits 20_1 to 20_N) capable of performing some of the functions of peripheral circuits 20 are provided on the substrate 52, as described in Embodiments 1 to 3 of the memory cell layer 31_1 (memory cell layers 31_1 to 31_N). Although Figure 5A illustrates an example of application to memory cell layer 31_1, the same applies to memory cell layers 31_2 to 31_N. The wiring connecting the peripheral circuits 20_1 provided on the substrate 52 and the memory cells 40_1 of the element layer 51 is sometimes called a wiring LBL (local bit line). The wiring LBL is a wiring composed of a conductor provided between the layers of the substrate 52 and the element layer 51, similar to the wiring LBL described in Embodiment 3 above. Peripheral circuits 20_1 (peripheral circuits 20_1 to 20_N) can be circuits such as sense amplifiers that have the function of amplifying signals in order to perform some of the functions of peripheral circuit 20, such as writing or reading data.

[0072] Figure 5B is a schematic cross-sectional view of the semiconductor device described in this embodiment. The semiconductor device 10D shown in Figure 5B has a configuration in which the configuration of the memory cell layer 31B described in Figure 5A is applied to the memory cell layers 31_1 to 31_N of each layer.

[0073] If the number of memory cell layers 31_1 to 31_N is, for example, 100 or more, the distance between the uppermost memory cell layer and the peripheral circuit 20 may be short. In this case, by having a data amplification function in the peripheral circuits 20_1 to 20_N, it becomes possible to input and output data between the uppermost memory cell layer and the peripheral circuit 20. For example, as shown in Figure 5C, by configuring peripheral circuits 20_1 to 20_N to amplify the data signal Data held in the memory cells 40_1 to 40_N, it becomes possible to input and output data between the memory cells 40_1 to 40_N and the peripheral circuit 20 without a large difference in data writing speed and reading speed.

[0074] In the configuration of the memory cell layer 31B described in Figure 5A, multiple memory cells 40_1 in the element layer 51 may be stacked in the z-axis direction. In the memory cell layer 31C shown in Figure 5D, peripheral circuits 20_1 are provided on the substrate 52, and multiple memory cells 40_1 are stacked in the z-axis direction on the element layer 51.

[0075] Figure 5(B) describes a configuration in which the memory cell layer 31B is bonded to the substrate 25 using metal bumps 53 and through electrodes 54, but other configurations are also possible.

[0076] Figures 6A and 6B illustrate a configuration in which through-electrodes 54 connect the electrodes of the peripheral circuit 21 on the substrate 25 to the electrodes of the substrate 52 on the memory cell layer 31B.

[0077] Figure 6A is a schematic cross-sectional view of a memory cell layer 31B applicable to memory cell layers 31_1 to 31_N of Figure 5A. Figure 6A shows an element layer 51 provided in contact with the substrate 52. Figure 6A also shows a junction layer 57 on the element layer 51.

[0078] The element layer 51 is an OS transistor M of the memory cell 40. OS It has.

[0079] Peripheral circuits 20 applicable to peripheral circuits 20_1 to 20_N include Si transistor M Si and electrode M Cu It has. Electrode M Cu This is the electrode that is connected when forming the through electrode 54. Electrode M Cu When using copper (Cu), it is effective to cover the electrode surface with gold (Au) to suppress oxidation of the surface when forming the through electrode 54. Note that electrode M Cu It is also possible to have a configuration that includes a conductor other than copper.

[0080] The bonding layer 57 flattens the bonding surface with the substrate 25, and the hydroxyl groups of the bonding layer 57 and the substrate 25 surface can form bonds, and is made of silicon dioxide (SiO₂). X ) are preferred.

[0081] Figure 6B is a schematic cross-sectional view of the case where the memory cell layer 31B of Figure 6A is bonded to the substrate 25 face-down (face-down bonding). The substrate 25 contains the Si transistor M of the peripheral circuit 21. Si , and electrode M Cu The through-electrode 54 provided in the element layer 51 and substrate 52 is the electrode M of the peripheral circuit 20. Cu And the electrode M of the peripheral circuit 21 Cu It is provided to connect and .

[0082] The bonding of the substrate 25 and the memory cell layer 31B can be performed within a range of 350°C to 450°C without exposing it to high temperatures of 1000°C or higher, by improving the flatness of the junction layer 57, etc. In other words, the bonding of the substrate 25 and the memory cell layer 31B can be performed without exposing it to high temperatures. Therefore, the OS transistor M, which is affected by exposure of the element layer 51 to high temperatures, can be avoided. OS This makes it possible to suppress fluctuations in the electrical characteristics. In addition, since the Si transistor is not exposed to high temperatures during bonding of the substrate 25 and the memory cell layer 31B, it becomes possible to use copper wiring.

[0083] The bonding of the substrate 25 and the memory cell layer 31B described above is effective not only when bonding memory cell layers 31B having OS transistors and Si transistors, but also when bonding memory cell layers having only Si transistors, such as memory cell layers with DRAM. Since the bonding temperature can be maintained within a range of 350°C to 450°C, it is also possible to configure the bonding of memory cell layers having Si transistors and memory cell layers having OS transistors and Si transistors alternately.

[0084] One embodiment of the present invention uses OS transistors, which have extremely low off-currents, as transistors provided in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and manufactured repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs. Another embodiment of the present invention allows for improved memory density by arranging the transistors constituting the memory cell vertically rather than in a planar direction, thereby enabling miniaturization of the device. Furthermore, because OS transistors exhibit less fluctuation in electrical characteristics compared to Si transistors even in high-temperature environments, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, resulting in a semiconductor device that functions as a highly reliable memory device.

[0085] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0086] (Embodiment 5) In this embodiment, a configuration example of a semiconductor device, which is one aspect of the present invention, will be described, but with a configuration different from that of Embodiments 1 to 4. Details of explanations that overlap with Embodiments 1 to 4 will be omitted, as they will be referenced from those previous explanations.

[0087] Figure 7A is a schematic cross-sectional view of the semiconductor device described in this embodiment. The memory cell layer 80 shown in Figure 7A shows a configuration in which a DRAM (Dynamic Random Access Memory) having Si transistors is provided on a substrate 84. In Figure 7A, the substrate 84 has peripheral circuits 81, transistors 82, and capacitors 83. The peripheral circuits 81 may also be referred to as control circuits, drive circuits, or circuits. The transistors 82 and capacitors 83 correspond to elements that constitute the memory cells of the DRAM.

[0088] Figure 7B is a schematic cross-sectional view of the semiconductor device described in this embodiment. The semiconductor device 10E shown in Figure 7B has a memory cell layer 80 described in Figure 7A on top of the memory cell layer 30 described in Embodiment 1. Although a single layer of the memory cell layer 80 is shown, it may be a multilayer. Also in Figure 7B, the substrate 25 has peripheral circuits 22 in addition to peripheral circuits 20.

[0089] The peripheral circuit 22 includes a circuit for outputting signals to drive the memory cells of the DRAM, which are composed of transistors 82 and capacitors 83 in the memory cell layer 80, such as a row driver and a column driver. It is preferable that the peripheral circuit 22 has high-speed transistors. The transistors in the peripheral circuit 22 are preferably transistors (Si transistors) with excellent field-effect mobility and a silicon channel formation region. The peripheral circuit 22 may also be referred to as a control circuit, drive circuit, or simply a circuit.

[0090] The through-electrodes 54 provided in the memory cell layers 31_1 to 31_N, a portion of the through-electrode 54B provided in the memory cell layer 80, and a portion of the metal bump 53 provided between the through-electrode 54B and the through-electrode 54 function as wiring for electrically connecting the peripheral circuit 22 to the memory cells of the DRAM, which are composed of transistors 82 and capacitors 83. Since the through-electrodes 54, 54B, and metal bumps 53, which function as wiring, can be provided in a direction perpendicular or approximately perpendicular to the surface of the substrate 25, the distance between the peripheral circuit 22 and the memory cells of the DRAM, which are composed of transistors 82 and capacitors 83, can be shortened. The through-electrodes 54, 54B, and metal bumps 53 can function as bit lines for writing or reading data to the memory cells of the DRAM, which are composed of transistors 82 and capacitors 83, or as word lines for selecting the memory cells of the DRAM, which are composed of transistors 82 and capacitors 83.

[0091] In Figure 7B, a configuration is shown in which a memory cell layer 80 having DRAM memory cells is bonded to a memory cell layer 30 having DOSRAM memory cells bonded to a substrate 25, but other configurations are also possible. In Figure 7C, a configuration is also shown in which a memory cell layer 30 having DOSRAM memory cells is bonded to a memory cell layer 80 having DRAM memory cells, which is bonded to a substrate 25 in multiple layers. Furthermore, the memory cell layer provided on the memory cell layer 80 may be a memory cell layer having NOSRAM memory cells instead of a memory cell layer having DOSRAM memory cells, or a memory cell layer in which a memory cell layer having NOSRAM memory cells and a memory cell layer having DOSRAM memory cells are stacked may be provided on the memory cell layer 30.

[0092] DRAM with Si transistors offers superior data transfer speeds compared to DOSRAM with OS transistors. On the other hand, DOSRAM with OS transistors can reduce the frequency of data refreshes compared to DRAM with Si transistors, thus effectively reducing power consumption. To achieve both high data transfer speed and low power consumption, the semiconductor device 10E with DRAM shown in this embodiment is effective in switching the state of the memory cell that holds the data according to the data access status between multiple states.

[0093] For example, Figure 8A illustrates Mode D1, where data is stored in DRAM, and Modes DOS1 and DOS2, where data is stored in DOSRAM. Modes DOS1 and DOS2 differ in their data refresh frequency. Compared to Mode DOS1, Mode DOS2 further reduces power consumption by lowering the data refresh frequency. By switching between the modes shown in Figure 8A according to the data access status, it is possible to achieve both high data transfer speed and low power consumption.

[0094] Figure 8B also illustrates mode NOS1, which stores data using NOSRAM, in addition to modes D1, DOS1, and DOS2, which store data using DOSRAM, as shown in Figure 8A. The memory cell layer containing NOSRAM can be placed on top of the memory cell layer 30. Unlike DOSRAM, NOSRAM allows for non-destructive reading, so it is effective to switch to mode NOS1, which stores data using NOSRAM, when data access is infrequent. By switching between the modes shown in Figure 8B according to the data access status, it is possible to achieve both high data transfer speed and low power consumption.

[0095] Figure 9A illustrates the Si transistors in the DRAM memory cell described in Figure 8A. Figure 9A shows schematic cross-sectional views of transistor 82 and capacitor 83. In the transistor 82 shown in Figure 9A, the gate electrode GE embedded in the silicon substrate, the source electrode SE provided on the source side of transistor 82, and the drain electrode DE provided on the drain side of transistor 82 are shown. The capacitor 83 provided on the upper layer of transistor 82 is shown as a so-called three-dimensional capacitor provided by forming a deep hole.

[0096] Figure 9B also illustrates the OS transistor of the DOSRAM memory cell described in Figure 1C of Embodiment 1. Figure 9B shows schematic cross-sectional views of transistor 41 and capacitor 42. In the transistor 41 shown in Figure 9B, the gate electrode GE is provided in the region overlapping with the semiconductor layer SEM on the substrate, the source electrode SE is provided on the source side of transistor 41, and the drain electrode DE is provided on the drain side of transistor 41. The capacitor 42 provided on the upper layer of transistor 41 is a so-called three-dimensional capacitor provided by forming a deep hole.

[0097] In the OS transistor of DOSRAM, capacitor 42 is a three-dimensional capacitor, but other configurations are also possible. Because the OS transistor has an extremely low off-current, the capacitance of the capacitor can be estimated to be small. Therefore, as shown in Figure 10A, it is also possible to use a two-dimensional capacitor.

[0098] The Si transistors in DRAM have a higher off-current compared to OS transistors. Therefore, in order to reduce the off-current in Si transistors, the channel length (L in Figure 9A) is important. CH The height of the capacitor (H in Figure 9A) needs to be increased. Therefore, the transistor 82 needs to be mounted extending in the z-axis direction, making it difficult to make the substrate thin. In addition, the capacitance of the capacitor 83 needs to be increased in order to retain the charge. Therefore, the height of the capacitor 83 (H in Figure 9A) needs to be increased. CAP83) needs to be increased. Therefore, in a memory cell layer having a DRAM with Si transistors, the film thickness T in the z-axis direction is required in the portion where transistor 82 and capacitor 83 are provided. D The size increases (memory cell layer 80 in Figure 10B).

[0099] On the other hand, as explained in Embodiment 1, the OS transistor in DOSRAM has an extremely low off-current. Therefore, in order to reduce the off-current, the channel length (L in Figure 9B) is increased by extending it in the z-axis direction, etc. CH There is no need to lengthen the ). Therefore, the substrate 52 in the z-axis direction can be made thinner for the transistor 41. In addition, in order to increase the capacitance of the capacitor 42, the height of the capacitor 42 (H in Figure 9B) is reduced. CAP42 There is no need to increase the thickness. Therefore, in a memory cell layer having a DOSRAM with an OS transistor, the thickness T in the z-axis direction is present in the element layer where the transistor 41 and capacitor 42 are provided. DOS This allows for a reduction in thickness (memory cell layer in Figure 10C). Therefore, in a memory cell layer with DOSRAM, the thickness of each layer can be reduced compared to a memory cell layer with DRAM, in a configuration where memory cell layers are stacked and bonded together.

[0100] One embodiment of the present invention uses OS transistors, which have extremely low off-currents, as transistors provided in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and manufactured repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs. Another embodiment of the present invention allows for improved memory density by arranging the transistors constituting the memory cell vertically rather than in a planar direction, thereby enabling miniaturization of the device. Furthermore, because OS transistors exhibit less fluctuation in electrical characteristics compared to Si transistors even in high-temperature environments, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, resulting in a semiconductor device that functions as a highly reliable memory device.

[0101] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0102] (Embodiment 6) In this embodiment, a configuration example of a semiconductor device, which is one aspect of the present invention, will be described, but with a configuration different from that of Embodiments 1 to 5. Details of explanations that overlap with Embodiments 1 to 5 will be omitted, as they will be referenced from those previous explanations.

[0103] Figure 11 is a schematic cross-sectional view of the semiconductor device described in this embodiment. The semiconductor device 10E_PU shown in Figure 11 has a configuration in which the peripheral circuit 22 is replaced with a CPU 110 in the substrate 25 described in Embodiment 5.

[0104] The data held by the CPU 110 can be stored in the memory cells of the DRAM, which consist of memory cells 40_1 to 40_N, transistor 82, and capacitor 83. Alternatively, the data held by the CPU 110 can be stored in memory cells having OS transistors with a different circuit configuration than the memory cells 40_1 to 40_N.

[0105] The CPU110 generates significant heat due to the high-speed signal input and output operations and the resulting current flow. When DRAM is bonded to this CPU, this heat can make data retention difficult.

[0106] As shown in Figure 11, in this embodiment, a memory cell layer 80 having DRAM can be provided via a memory cell layer 30 having memory cells 40_1 to 40_N having OS transistors. OS transistors can perform good switching operation even in high-temperature environments because the ratio of on-current to off-current is large. In addition, the memory cell layer 80 having DRAM can be provided spaced apart from the CPU 110 via the memory cell layer 30 having memory cells 40_1 to 40_N having OS transistors. Therefore, a semiconductor device can be made that combines the characteristics of a memory device that utilizes an extremely small off-current and a memory device that can operate at high speed, and has excellent reliability with small fluctuations in the electrical characteristics of the transistors.

[0107] Next, an example configuration of the CPU 110 will be described. In this embodiment, a CPU 110 having CPU cores capable of power gating will be described.

[0108] Figure 12 shows an example configuration of the CPU 110. The CPU 110 includes a CPU core 200, an L1 (level 1) cache memory device 202, an L2 cache memory device 203, a bus interface unit 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 includes a flip-flop 220.

[0109] The bus interface unit 205 interconnects the CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203.

[0110] In response to externally input interrupt signals and signals such as SLEEP1 issued by the CPU 110, the PMU 193 generates the clock signal GCLK1 and various PG (power gating) control signals. The clock signal GCLK1 and PG control signals are input to the CPU 110. The PG control signals control the power switches 210-212 and the flip-flop 220.

[0111] Power switches 210 and 211 control the supply of voltages VDDD and VDD1 to the virtual power line V_VDD (hereinafter referred to as the V_VDD line), respectively. Power switch 212 controls the supply of voltage VDDH to the level shifter (LS) 214. Voltage VSSS is input to the CPU 110 and PMU 193 without going through the power switches. Voltage VDDD is input to the PMU 193 without going through the power switches.

[0112] Voltages VDDD and VDD1 are drive voltages for CMOS circuits. Voltage VDD1 is lower than voltage VDDD and is the drive voltage in sleep mode. Voltage VDDH is the drive voltage for OS transistors and is higher than voltage VDDD.

[0113] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power-gated power domain. Each power-gated power domain is provided with one or more power switches. These power switches are controlled by a PG control signal.

[0114] Flip-flop 220 is used as a register. Flip-flop 220 has a backup circuit. The following is a description of flip-flop 220.

[0115] Figure 13A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 includes a scan flip-flop 221 and a backup circuit 222. The scan flip-flop 221 is provided on the substrate 25 in Figure 11, and the backup circuit 222 can be provided on the same layer as the memory cell layer 30.

[0116] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0117] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SC is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for the reset signal.

[0118] The signal SCE is a scan enable signal and is generated by the PMU193. The PMU193 generates signals BK and RC. The level shifter 214 level-shifts signals BK and RC to generate signals BKH and RCH. Signal BK is a backup signal, and signal RC is a recovery signal.

[0119] The circuit configuration of scan flip-flop 221 is not limited to Figure 13A. Flip-flops available in standard circuit libraries can be used.

[0120] The backup circuit 222 includes nodes SD_IN, SN11, transistors M11 to M13, and a capacitive element C11.

[0121] Node SD_IN is the input node for scan test data and is connected to node Q1 of scan flip-flop 221. Node SN11 is the holding node of backup circuit 222. Capacitor element C11 is a holding capacitance for holding the voltage of node SN11.

[0122] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 controls the conduction state between node SD_IN and node SD. The on / off states of transistors M11 and M13 are controlled by signal BKH, and the on / off state of transistor M12 is controlled by signal RCH.

[0123] Transistors M11 to M13 are OS transistors, similar to the transistors in the memory cell layer 31 described above. The diagram shows transistors M11 to M13 with back gates. The back gates of transistors M11 to M13 are connected to the power line that supplies voltage VBG1.

[0124] It is preferable that at least transistors M11 and M12 are OS transistors. Due to the characteristics of OS transistors, which have an extremely low off-current, the voltage drop at node SN11 can be suppressed, and since data retention consumes almost no power, the backup circuit 222 has non-volatile properties. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is, in principle, not limited in the number of rewrites, and data can be written and read with low energy.

[0125] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Figure 13B, the backup circuit 222 can be stacked on top of the scan flip-flop 221, which is composed of a silicon CMOS circuit.

[0126] The backup circuit 222 has significantly fewer elements than the scan flip-flop 221, so there is no need to change the circuit configuration or layout of the scan flip-flop 221 in order to stack the backup circuit 222. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be placed within the area where the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be reduced to zero even when the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 on the flip-flop 220, power gating of the CPU core 200 becomes possible. Because less energy is required for power gating, it is possible to power gate the CPU core 200 with high efficiency.

[0127] By providing the backup circuit 222, a parasitic capacitance from transistor M11 is added to node Q1. However, this is small compared to the parasitic capacitance from the logic circuit connected to node Q1, so it does not affect the operation of scan flip-flop 221. In other words, even with the backup circuit 222, the performance of flip-flop 220 is not substantially reduced.

[0128] For example, the CPU core 200 can be configured in low-power states such as clock gating, power gating, and hibernation. The PMU 193 selects the low-power mode for the CPU core 200 based on interrupt signals, the SLEEP1 signal, etc. For example, when transitioning from the normal operating state to the clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0129] For example, when transitioning from normal operation to hibernation, the PMU193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU193 turns off power switch 210 and turns on power switch 211 to input voltage VDD1 to the CPU core 200. Voltage VDD1 is a voltage that does not cause data loss in scan flip-flop 221. When performing frequency scaling, the PMU193 reduces the frequency of the clock signal GCLK1.

[0130] When the CPU core 200 transitions from normal operation to power gating, the data on scan flip-flop 221 is backed up to backup circuit 222. When the CPU core 200 returns from power gating to normal operation, the data on backup circuit 222 is recovered to scan flip-flop 221.

[0131] Figure 14 shows an example of the power gating sequence for CPU core 200. In Figure 14, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for power switches 210 to 212 and are generated by PMU 193. When signal PSE0 is "H" or "L", power switch 210 is on or off. The same applies to signals PSE1 and PSE2.

[0132] Before time t1, the system is in a normal operation state. Power switch 210 is on, and voltage VDDD is input to the CPU core 200. Scan flip-flop 221 operates normally. At this time, level shifter 214 does not need to be operated, so power switch 212 is off, and signals SCE, BK, and RC are "L". Since node SC is "L", scan flip-flop 221 stores the data of node D1. In the example in Figure 14, at time t1, node SN11 of backup circuit 222 is "L".

[0133] The operation during backup is described below. At operation time t1, PMU193 stops the clock signal GCLK1 and sets the signal PSE2, BK, to "H". The level shifter 214 becomes active and outputs the "H" signal BKH to the backup circuit 222.

[0134] Transistor M11 of backup circuit 222 is turned on, and the data from node Q1 of scan flip-flop 221 is written to node SN11 of backup circuit 222. If node Q1 of scan flip-flop 221 is "L", node SN11 remains "L", and if node Q1 is "H", node SN11 becomes "H".

[0135] PMU193 sets signal PSE2, BK, to "L" at time t2, and signal PSE0 to "L" at time t3. At time t3, CPU core 200 transitions to the power gating state. Alternatively, signal PSE0 may be lowered at the same time as signal BK.

[0136] This section explains the operation during power-gating. When signal PSE0 becomes "L," the voltage on the V_VDD line drops, causing data loss at node Q1. Node SN11 continues to retain the data from node Q1 at time t3.

[0137] The operation during recovery is described below. At time t4, PMU193 transitions from the power gating state to the recovery state by setting signal PSE0 to "H". Charging of the V_VDD line begins, and when the voltage of the V_VDD line reaches VDDD (time t5), PMU193 sets signals PSE2, RC, and SCE to "H".

[0138] Transistor M12 turns on, and the charge of capacitive element C11 is distributed to nodes SN11 and SD. If node SN11 is "H", the voltage at node SD rises. Since node SC is "H", the data from node SC is written to the input latch circuit of scan flip-flop 221. When the clock signal GCLK1 is input to node CK at time t6, the data from the input latch circuit is written to node Q1. In other words, the data from node SN11 has been written to node Q1.

[0139] At time t7, PMU193 sets signals PSE2, SCE, and RC to "L", and the recovery operation ends.

[0140] The backup circuit 222 using OS transistors is highly suitable for normally-off computing because it has low dynamic and static power consumption. The CPU 110, including the CPU core 200 with the OS transistor backup circuit 222, can be referred to as NoffCPU (registered trademark). NoffCPU has non-volatile memory and can shut off power supply when operation is not required. Even with the addition of a flip-flop 220, it is possible to minimize performance degradation and dynamic power consumption increases of the CPU core 200.

[0141] The CPU core 200 may have multiple power domains capable of power gating. Each power domain is provided with one or more power switches for controlling voltage input. The CPU core 200 may also have one or more power domains that are not power gated. For example, a power gating control circuit for controlling the flip-flop 220 and power switches 210-212 may be provided in a power domain that is not power gated.

[0142] Note that the application of flip-flop 220 is not limited to CPU 110. In CPU 110, flip-flop 220 can be applied to registers located in power domains that are power-gated.

[0143] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0144] (Embodiment 7) In this embodiment, a configuration example of a semiconductor device, which is one aspect of the present invention, will be described, but with a configuration different from that of Embodiments 1 to 5. Details of explanations that overlap with Embodiments 1 to 5 will be omitted, as they will be referenced from those previous explanations.

[0145] Figure 15 is a schematic cross-sectional view of the semiconductor device described in this embodiment. The semiconductor device 10F shown in Figure 15 has a configuration in which through electrodes 54 are provided with multiple memory cell layers 31_1 to 31_N of each layer described in Figure 1A stacked on top of each other. In other words, in the semiconductor device 10F shown in Figure 15, the memory cells 40_1 and 40_2 of the memory cell layer 31_1 and the memory cell layer 31_2 can be connected by through electrodes 54 without using metal bumps 53. By adopting this configuration, the number of memory cells per unit area can be increased, and the number of metal bumps 53 and through electrodes 54 can be reduced, thereby reducing manufacturing costs and increasing memory density.

[0146] One embodiment of the present invention uses OS transistors, which have extremely low off-currents, as transistors provided in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, resulting in a semiconductor device with low power consumption. OS transistors can be stacked and manufactured repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs. Another embodiment of the present invention allows for improved memory density by arranging the transistors constituting the memory cell vertically rather than in a planar direction, thereby enabling miniaturization of the device. Furthermore, because OS transistors exhibit less fluctuation in electrical characteristics compared to Si transistors even in high-temperature environments, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, resulting in a semiconductor device that functions as a highly reliable memory device.

[0147] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0148] (Embodiment 8) In this embodiment, modified examples of circuits applicable to the semiconductor devices described in Embodiments 1 to 6 above will be described with reference to Figures 16A and 16B.

[0149] Figure 16A illustrates an example configuration of a semiconductor device having memory cell layers stacked on a substrate, which includes an amplification circuit capable of amplifying the data signals held in the memory cells.

[0150] The block diagram shown in Figure 16A is a block diagram of a memory cell layer 31 applicable to memory cell layers 31_1 to 31_N described in Embodiment 1. The memory cell layer 31 has an amplification circuit 49 between the peripheral circuit 20 provided on the substrate 52 and the plurality of memory cells 40 provided on the element layer 51.

[0151] The schematic diagram shown in Figure 16A defines the z-axis direction to explain the arrangement of each component. For ease of understanding, the z-axis direction may be referred to as the direction perpendicular to the surface of the substrate 52 in the specification. In Figure 16A, in the element layer 51 provided on the substrate 52, the amplification circuit 49 and the multiple memory cells 40 are provided by stacking transistors in the z-axis direction.

[0152] The amplification circuit 49 is provided between the wiring LBL for connecting multiple memory cells 40 and the wiring GBL for connecting the peripheral circuit 20 and the circuit above it. The amplification circuit 49 has the function of amplifying the potential of the wiring LBL connected to the memory cell 40 and transmitting it to the wiring GBL connected to the peripheral circuit 20, and the function of transmitting the potential of the peripheral circuit 20 to the wiring LBL connected to the memory cell 40. The wiring GBL may be called a global bit line. The wiring LBL may be called a local bit line. The wiring LBL and wiring GBL have the function of bit lines for writing or reading data from the memory cell. In the drawings, the wiring LBL and wiring GBL may be shown with thick lines or thick dotted lines to improve visibility.

[0153] Figure 16B shows an example of the circuit configuration of the amplifier circuit 49. The amplifier circuit 49 has transistors 91 to 94. Transistors 91 to 94 can each be made up of OS transistors and are shown as n-channel type transistors.

[0154] Transistor 91 is a transistor that controls the potential of wiring GBL to a potential corresponding to the potential of wiring LBL during the period when data is read from memory cell 40. Transistor 92 is a transistor that functions as a switch to which a selection signal MUX is input to the gate, and in accordance with the selection signal MUX, the on or off state between the source and drain is controlled. Transistor 93 is a transistor that functions as a switch to which a write control signal WE is input to the gate, and in accordance with the write control signal WE, the on or off state between the source and drain is controlled. Transistor 94 is a transistor that functions as a switch to which a read control signal RE is input to the gate, and in accordance with the read control signal RE, the on or off state between the source and drain is controlled. The source side of transistor 94 is supplied with a fixed potential, which is ground potential GND.

[0155] One embodiment of the present invention can be manufactured by repeatedly providing transistors on a substrate in the vertical direction using the same manufacturing process. In one embodiment of the present invention, memory density can be improved by arranging the OS transistors constituting the memory cell in the vertical direction instead of the planar direction, and the device can be miniaturized. By configuring the memory cell layer 31 to have an amplification circuit 49, the wiring LBL is connected to the gate of the transistor 91, so that a data signal can be read out to the wiring GBL using the small potential difference of the wiring LBL.

[0156] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0157] (Embodiment 9) This embodiment shows an example of an integrated circuit (referred to as an IC chip) having semiconductor devices 10A to 10F. The semiconductor device 10 can be made into a single IC chip by mounting multiple dies on a packaging substrate. Figures 17A and 17B show an example of its configuration.

[0158] Figure 17A shows a schematic cross-sectional view of the IC chip 100A, which has a substrate 25 on a package substrate 101. As an example, it has a memory cell layer in which four memory cell layers 31_1 and 31_4 are stacked on the substrate 25. Solder balls 102 are provided on the package substrate 101 for connecting the IC chip 100A to a printed circuit board or the like. The memory cell layers 31_1 to 31_4 can be stacked by repeating the configuration of creating OS transistors in the element layer 51 that is in contact with the substrate 52. Furthermore, peripheral circuits provided on the silicon substrate and each circuit such as memory cells in the memory cell layers 31_1 to 31_4 can be connected by through-electrodes 54 such as TSVs (Through Silicon Vias) that are provided through the substrate 52 and element layer 51 of each layer. In addition, each layer can be electrically connected via through-electrodes 54 provided through each layer and metal bumps 53 (also called microbumps) provided between each layer.

[0159] As another example, the schematic cross-sectional view of the IC chip 100B shown in Figure 17B has a substrate 25 on a package substrate 101, and for example, a memory cell layer in which four memory cell layers 31_1 and 31_4 are stacked on the substrate 25. Peripheral circuits (not shown) provided on the substrate 25 and each circuit of the memory cells (not shown) having memory cell layers 31_1 and 31_4 are bonded together using electrodes 55 and 56 provided on the substrate 52 and element layer 51 of each layer. Cu-Cu junction can be used as a technique to electrically join different layers using electrodes 55 and 56. Cu-Cu junction is a technique that achieves electrical conductivity by connecting Cu (copper) pads together.

[0160] (Embodiment 10) The following describes an example of a schematic cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0161] Figure 18 shows an example of a semiconductor device in which memory units 470 (memory units 470_1 to 470_m: m is an integer of 2 or more; Figure 18 shows the case where m=2) are stacked on an element layer 411 having circuits provided on a semiconductor substrate 311. The element layer 411 having circuits provided on the semiconductor substrate 311 corresponds to the substrate 25 having peripheral circuits 21 etc. as described in Embodiments 1 to 6 above. The memory unit 470 corresponds to the memory cell layer 31 having memory cells 40 as described in Embodiments 1 to 6 above.

[0162] Figure 18 shows an element layer 411 and multiple memory units 470 stacked on the element layer 411. The example shows that each of the multiple memory units 470 has a transistor layer 413 (transistor layer 413_1 to transistor layer 413_m) corresponding to each memory unit 470, and multiple memory device layers 415 (memory device layer 415_1 to memory device layer 415_n: n is an integer of 2 or more) on each transistor layer 413. While the example shows each memory unit 470 having a transistor layer 413 on the substrate 450 and a memory device layer 415 on the transistor layer 413, this embodiment is not limited to this. Alternatively, multiple memory device layers 415 may be provided on the substrate 450, and transistor layers 413 may be provided on the multiple memory device layers 415, or memory device layers 415 may be provided above and below the transistor layer 413 on the substrate 450. The transistor layer 413 corresponds to the layer having transistors in the amplification circuit 49, etc., described in Embodiment 8 above. The memory device layer 415 corresponds to the layer having transistors in the memory cell 40, etc., described in Embodiments 1 to 6 above.

[0163] The semiconductor substrate 311 and the substrate 450 can be made from materials selected from Si, Ge, SiGe, GaAs, GaAlAs, GaN, and InP, respectively.

[0164] The element layer 411 has transistors 300 provided on the semiconductor substrate 311 and can function as a circuit (sometimes called a peripheral circuit) of a semiconductor device. Examples of circuits include column drivers, row drivers, column decoders, row decoders, sense amplifiers, precharge circuits, amplification circuits, word line driver circuits, output circuits, and control logic circuits.

[0165] The transistor layer 413 has a transistor 200T and can function as a circuit to control each memory unit 470. The memory device layer 415 has a memory device 420. The memory device 420 shown in this embodiment has a transistor and a capacitor.

[0166] The value of m is not particularly restricted, but is between 2 and 100, preferably between 2 and 50, and more preferably between 2 and 10. Similarly, the value of n is not particularly restricted, but is between 2 and 100, preferably between 2 and 50, and more preferably between 2 and 10. The product of m and n is between 4 and 256, preferably between 4 and 128, and more preferably between 4 and 64.

[0167] Figure 18 also shows a cross-sectional view in the channel length direction of transistor 200T included in the memory unit and the transistors of the memory device 420.

[0168] As shown in Figure 18, a transistor 300 is provided on a semiconductor substrate 311, and a transistor layer 413 and a memory device layer 415 of a memory unit 470 are provided on the transistor 300. Within one memory unit 470, the transistor 200T of the transistor layer 413 and the memory device 420 of the memory device layer 415 are electrically connected by a plurality of conductors 424, and the transistor 300 and the transistor 200T of the transistor layer 413 in each memory unit 470 are electrically connected by conductors 426, conductor 427, and conductor 430. Furthermore, it is preferable that conductor 426 is electrically connected to the transistor 200T via conductor 428 which is electrically connected to one of the source, drain, or gate of the transistor 200T. It is preferable that conductors 424 are provided on each layer of the memory device layer 415. The conductor 427 is located on the top layer of each memory unit 470 and is electrically connected to the conductors 426 and 430.

[0169] The materials included in conductors 426, 427, and 430 can be selected from Cu, W, Ti, Ta, and Al, respectively.

[0170] Although Figure 18 shows an example where the substrate 450 of the memory unit 470 is located on the side of the transistor 300, this embodiment is not limited to this. As shown in Figure 19, the memory unit 470 may be configured such that the memory device layer 415 is located on the side of the transistor 300.

[0171] In Figure 18, the conductor 426 is provided so as to penetrate the memory device layer 415, and the conductor 430 is provided so as to penetrate the memory device layer 415, the transistor layer 413, and the substrate 450.

[0172] On the other hand, in Figure 19, the conductor 426 is provided so as to penetrate the substrate 450 and the transistor layer 413, and the conductor 430 is provided so as to penetrate the substrate 450, the transistor layer 413, and the memory device layer 415.

[0173] To suppress leakage between the conductor 426 and the conductor 430, it is preferable that insulators be provided on each of their sides.

[0174] Furthermore, as will be described in detail later, it is preferable to provide an insulator on the sides of conductor 424 and conductor 426 to suppress the permeation of impurities such as water or hydrogen, or oxygen. For example, silicon nitride, aluminum oxide, or silicon nitride oxide may be used as such an insulator.

[0175] The memory device 420 has a transistor and a capacitor on its side, and the transistor can have a structure similar to the transistor 200T in the transistor layer 413.

[0176] In this case, it is preferable that the transistor 200T uses a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor in the semiconductor containing the region where the channel is formed (hereinafter also referred to as the channel formation region).

[0177] As an oxide semiconductor, metal oxides such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, oxide semiconductors containing indium oxide, In-Ga oxide, or In-Zn oxide, i.e., In, Ga, and Zn, may be used. Note that by using an oxide semiconductor with a high proportion of indium, the on-current or field-effect mobility of the transistor can be increased.

[0178] The transistor 200T, which uses an oxide semiconductor in the channel formation region, exhibits extremely low leakage current in the non-conductive state, thus enabling the provision of a low-power semiconductor device. Furthermore, since oxide semiconductors can be deposited using methods such as sputtering, they can be used in transistors 200T that constitute highly integrated semiconductor devices.

[0179] On the other hand, transistors using oxide semiconductors are prone to exhibiting normally-on characteristics (where a channel exists and current flows through the transistor even without applying voltage to the gate electrode) due to variations in their electrical properties caused by impurities and oxygen vacancies in the oxide semiconductor.

[0180] Therefore, it is preferable to use oxide semiconductors with reduced impurity concentration and defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0181] Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor as much as possible. Examples of impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0182] In particular, hydrogen as an impurity contained in oxide semiconductors causes oxygen vacancies (V) in oxide semiconductors. O It can also form an oxygen vacancy. In addition, a defect in which hydrogen is placed in the oxygen vacancy (hereinafter referred to as V) may form. O It is sometimes called H. ) can generate carrier electrons. Furthermore, some hydrogen can react with oxygen bonded to a metal atom to generate carrier electrons.

[0183] Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics. Furthermore, since hydrogen in oxide semiconductors is easily affected by stresses such as heat and electric fields, a high hydrogen content in the oxide semiconductor may degrade the reliability of the transistor.

[0184] Therefore, it is preferable to use a high-purity, intrinsic oxide semiconductor with reduced impurities such as hydrogen and oxygen vacancies for the 200T transistor.

[0185] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0186] (Embodiment 11) In this embodiment, we will describe in detail the peripheral circuit 20 having a circuit for driving a memory cell array including a memory cell 40 in the semiconductor device 10 described in Embodiments 1 to 6.

[0187] Figure 20 is a block diagram showing an example configuration of a semiconductor device that functions as a memory device. The semiconductor device 10s has peripheral circuits 20 and a memory cell array 40MA. The peripheral circuits 20 have a row decoder 571, a word line driver circuit 572, a column driver 575, an output circuit 573, and a control logic circuit 574.

[0188] The column driver 575 includes a column decoder 581, a pre-charge circuit 582, an amplification circuit 583, and a writing circuit 584. The pre-charge circuit 582 has the function of pre-charging wiring BL, etc. The amplification circuit 583 has the function of amplifying the data signal read from wiring BL. The amplified data signal is output to the outside of the semiconductor device 10s as a digital data signal RDATA via the output circuit 573.

[0189] The semiconductor device 10s is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 20, and a high power supply voltage (VIL) for the memory cell array 40MA from an external source.

[0190] The semiconductor device 10s also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder 571 and the column decoder 581, and WDATA is input to the writing circuit 584.

[0191] The control logic circuit 574 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 571 and column decoder 581. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 574 are not limited to these; other control signals may be input as needed. For example, a control signal for determining bad bits may be input to identify data signals read from a specific memory cell address as bad bits.

[0192] Furthermore, the aforementioned circuits and signals can be selected or omitted as needed.

[0193] Generally, various types of memory are used in semiconductor devices such as computers, depending on the application. Figure 21 shows the different types of memory in a hierarchical structure. Higher-level memory devices require faster access speeds, while lower-level memory devices require larger storage capacity and higher recording density. In Figure 21, from the top layer upwards, the memory is shown as registers integrated into the processing unit such as the CPU, followed by SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0194] Memory integrated as registers into arithmetic processing units such as CPUs is frequently accessed by the arithmetic processing unit because it is used for temporary storage of calculation results. Therefore, faster operating speed is required than storage capacity. Registers also have the function of holding configuration information for the arithmetic processing unit.

[0195] SRAM is used, for example, as a cache. A cache has the function of duplicating and storing some of the information held in main memory. By duplicating frequently used data in the cache, the speed of accessing that data can be increased.

[0196] DRAM is used, for example, in main memory. Main memory has the function of holding programs, data, etc., read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm². 2 That is the case.

[0197] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored long-term, or various programs used by processing units. Therefore, storage requires a large storage capacity and high recording density rather than just operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm². 2 That is the case.

[0198] A semiconductor device functioning as a storage device according to one aspect of the present invention has a high operating speed and is capable of long-term data retention. The semiconductor device according to one aspect of the present invention can be suitably used as a semiconductor device located in a boundary region 901 that includes both the layer where the cache is located and the layer where the main memory is located. Furthermore, the semiconductor device according to one aspect of the present invention can be suitably used as a semiconductor device located in a boundary region 902 that includes both the layer where the main memory is located and the layer where the storage is located.

[0199] (Embodiment 12) This embodiment shows an example of an electronic component and electronic device incorporating the semiconductor device shown in the above embodiment.

[0200] <Electronic Components> First, we will explain an example of an electronic component incorporating a semiconductor device 10, etc., using Figures 22A and 22B.

[0201] Figure 22(A) shows a perspective view of an electronic component 700 and a substrate (mounted substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 22(A) has a semiconductor device 10 in which a memory cell layer 30 is stacked on a silicon substrate 25 within a mold 711. The semiconductor device 10 can be the semiconductor devices 10A to 10F described in Embodiment 1. In Figure 22A, some parts are not shown in order to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 10 by a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and each is electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0202] Figure 22B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 10 are provided on the interposer 731.

[0203] Electronic component 730 shows an example where the semiconductor device 10 is used as high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

[0204] The package substrate 732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 731 can be a silicon interposer, a resin interposer, etc.

[0205] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0206] It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0207] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0208] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0209] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 10 and the semiconductor device 735.

[0210] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 22B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0211] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0212] <Electronic equipment> Next, an example of an electronic device equipped with the above-mentioned electronic components will be explained using Figure 23.

[0213] The robot 7100 is equipped with an illuminance sensor, microphone, camera, speaker, display, various sensors (infrared sensor, ultrasonic sensor, accelerometer, piezoelectric sensor, light sensor, gyroscope, etc.), and a movement mechanism. Electronic component 730 has a processor and other components and has the function of controlling these peripheral devices. For example, electronic component 700 has the function of storing data acquired by the sensors.

[0214] The microphone has the function of detecting acoustic signals such as the user's voice and ambient sounds. The speaker has the function of emitting audio signals such as voice and warning sounds. Robot 7100 can analyze the audio signals input via the microphone and emit the necessary audio signals from the speaker. Robot 7100 can communicate with the user using the microphone and speaker.

[0215] The camera has the function of capturing images of the area around the robot 7100. The robot 7100 also has the function of moving using a mobility mechanism. The robot 7100 can capture images of its surroundings using the camera and analyze the images to detect obstacles and other issues during its movement.

[0216] The aircraft 7120 has propellers, cameras, and batteries, and is capable of autonomous flight. Electronic component 730 has the function of controlling these peripheral devices.

[0217] For example, image data captured by the camera is stored in electronic component 700. Electronic component 730 can analyze the image data and detect the presence or absence of obstacles during movement. Furthermore, electronic component 730 can estimate the remaining battery level from changes in the battery's storage capacity.

[0218] The cleaning robot 7140 has a display on its top surface, multiple cameras on its sides, brushes, control buttons, and various sensors. Although not shown in the illustration, the cleaning robot 7140 is equipped with wheels, a suction port, etc. The cleaning robot 7140 is self-propelled, can detect dirt, and can suck up the dirt through a suction port located on its underside.

[0219] For example, the electronic component 730 can analyze images captured by the camera to determine the presence or absence of obstacles such as walls, furniture, or steps. Furthermore, if the image analysis detects objects that could become entangled in the brush, such as wiring, it can stop the brush from rotating.

[0220] The automobile 7160 includes an engine, tires, brakes, steering system, camera, etc. For example, electronic component 730 controls the automobile 7160 to optimize its driving state based on data such as navigation information, speed, engine status, gear selection status, and brake usage frequency. For example, image data captured by the camera is stored in electronic component 700.

[0221] Electronic component 700 and / or electronic component 730 can be incorporated into a TV device 7200 (television receiver), a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, etc.

[0222] For example, the electronic component 730 built into the TV device 7200 can function as an image engine. For instance, the electronic component 730 performs image processing such as noise reduction and resolution upconversion.

[0223] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 has a microphone, camera, speaker, various sensors, and a display unit. These peripheral devices are controlled by electronic component 730.

[0224] PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. A keyboard 7232 and a monitor unit 7233 can be connected to the PC7230 wirelessly or via a wired connection. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a home game console. A controller 7262 can be connected to the game console 7260 wirelessly or via a wired connection. Electronic components 700 and / or 730 can also be incorporated into the controller 7262.

[0225] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0226] <Notes regarding the description in this specification, etc.> The above embodiments and a description of each component in those embodiments are provided below.

[0227] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0228] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0229] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0230] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0231] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0232] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0233] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0234] Furthermore, the terms "electrode" and "wiring" in this specification do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wiring" are formed as a single unit.

[0235] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0236] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0237] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0238] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0239] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0240] In this specification, "A and B are connected" includes not only those that are directly connected, but also those that are electrically connected. Here, "electrically connected" means that when there is an object between A and B that has some kind of electrical effect, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0241] 10A: Semiconductor device, 20: Peripheral circuit, 25: Substrate, 30: Memory cell layer, 31_1: Memory cell layer, 31_2: Memory cell layer, 31_N: Memory cell layer, 40_1: Memory cell, 40_2: Memory cell, 40_N: Memory cell, 40p: Memory circuit, 40: Memory cell, 41: Transistor, 42: Capacitor

Claims

[Claim 1] A first substrate is provided with a first peripheral circuit having a function to drive the first memory cell, The device comprises a second substrate, a first element layer having the first memory cell, and a first memory cell layer having the first memory cell. The first memory cell has a first transistor and a first capacitor, The first transistor has a semiconductor layer having a metal oxide in the channel formation region, The first memory cell layer is provided stacked on the first substrate in a direction perpendicular or approximately perpendicular to the surface of the first substrate. A semiconductor device in which the first peripheral circuit and the first memory cell are electrically connected via a first through-electrode provided on the second substrate and the first element layer.

Images