Multilayer ceramic capacitor
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MURATA MFG CO LTD
- Filing Date
- 2024-12-04
- Publication Date
- 2026-06-16
AI Technical Summary
【0008】 本発明によれば、第1主面偏析層、第2主面偏析層、第1側面偏析層および第2側面偏析層が設けられているので、全体として信頼性を高めた積層セラミックコンデンサを実現することができる。
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Figure 2026097583000001_ABST
Abstract
Claims
1. Equipped with a laminate, The laminate includes a plurality of stacked dielectric layers and a plurality of internal electrode layers. The laminate has a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction. An external electrode is arranged so as to cover at least a portion of the first end face and at least a portion of the second end face, and is electrically connected to at least one of the plurality of internal electrode layers. The first external dielectric layer is arranged to cover the first main surface side of the first main surface internal electrode layer, which is the closest of the plurality of internal electrode layers to the first main surface. The second external dielectric layer is arranged so as to cover the second main surface side of the second main surface internal electrode layer, which is the closest of the plurality of internal electrode layers to the second main surface. A first main surface segregation layer is disposed between the first main surface internal electrode layer and the first external dielectric layer. A second main surface segregation layer is disposed between the second main surface internal electrode layer and the second external dielectric layer. A first side segregation layer and a second side segregation layer are arranged at both ends in the width direction of the plurality of internal electrode layers. A multilayer ceramic capacitor in which each of the first main surface segregation layer, the second main surface segregation layer, the first side surface segregation layer, and the second side surface segregation layer contains a specific group of elements, which includes one or more elements selected from the group consisting of rare earth elements, Si, and elements of the Si group.
2. The multilayer ceramic capacitor according to claim 1, wherein the displacement of the edges of the plurality of internal electrode layers in the width direction is within 5 μm.
3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the specified group of elements includes a first element which is Si or an element of the Si group, and a second element which is a rare earth element, and the molar ratio of the first element to Ti is greater than the molar ratio of the second element to Ti.
4. The multilayer ceramic capacitor according to claim 3, wherein the molar ratio of the first element to Ti is 1.0 or more and 2.5 or less.
5. The multilayer ceramic capacitor according to claim 3, wherein the molar ratio of the second element to Ti is 0.3 or more and 1.1 or less.
6. The multilayer ceramic capacitor according to claim 1, wherein the specified element group consists only of Si.
7. The multilayer ceramic capacitor according to claim 1, wherein the specified group of elements includes one or more elements selected from the group consisting of Dy, Ho, Tb, and Y.
8. The multilayer ceramic capacitor according to claim 1, wherein the thickness of each of the plurality of dielectric layers is 0.4 μm or more and 0.45 μm or less.