Multilayer ceramic electronic components and circuit boards

Abstract

To provide a multilayer ceramic electronic component with which reliability can be heightened, a circuit board on which the multilayer ceramic electronic component is mounted, and a method for manufacturing the multilayer ceramic electronic component.SOLUTION: The multilayer ceramic electronic component comprises a ceramic element assembly, and first and second external electrodes that face each other in an X-axis direction. The ceramic element assembly has a plurality of internal electrodes, first and second end faces, and four connecting faces that connect between the first and second end faces, and is formed in a rectangular parallelepiped shape. The connecting faces have an uneven region located between the first and second external electrodes. The uneven region is formed along an extension direction that crosses the X axis, and includes a plurality of recesses arrayed along an array direction that is orthogonal to a depth direction and the extension direction, and protrusions disposed between the plurality of recesses. A depth of the recesses in the depth direction is 0.1 μm or more and less than 2.5 μm. An array pitch of the recesses along the array direction is 1 μm or more and 80 μm or less.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component, a circuit board on which the same is mounted, Regarding circuit boards.

Background Art

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors include, for example, a ceramic body and first and second external electrodes disposed at ends of the ceramic body. When a leakage current occurs in the ceramic body, the insulation resistance between these external electrodes decreases, and the multilayer ceramic electronic component is likely to fail.

[0003] For example, in a high-temperature and high-humidity environment, dew condensation may occur on the surface of the multilayer ceramic electronic component, and thereby a leakage current may occur on the surface of the ceramic body. Therefore, Patent Document 1 discloses a technique of providing a water repellent on the surface of the multilayer ceramic electronic component.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the technique described in Patent Document 1, it is necessary to mask the external electrodes when applying the water repellent, and the process can be complicated especially for small-sized multilayer ceramic electronic components. For this reason, there is a need for a technique that can improve the reliability of multilayer ceramic electronic components in a simpler manner and suitable for small-sized multilayer ceramic electronic components.

[0006] In view of the above circumstances, an object of the present invention is to provide a multilayer ceramic electronic component capable of enhancing reliability, a circuit board on which the same is mounted, and a method for manufacturing a multilayer ceramic electronic component. [Means for solving the problem]

[0007] To achieve the above objective, a multilayer ceramic electronic component according to one embodiment of the present invention comprises a ceramic body and first and second external electrodes. The ceramic body is configured in a rectangular parallelepiped shape and has a plurality of internal electrodes stacked in the first axial direction via a ceramic layer, first and second end faces perpendicular to a second axis orthogonal to the first axial direction from which the plurality of internal electrodes are drawn out, and four connecting surfaces connecting the first and second end faces and extending along the second axial direction. The first and second external electrodes are positioned on the first and second end faces, respectively, and face each other in the second axial direction. At least one of the connection surfaces has an uneven region located between the first and second external electrodes. The aforementioned uneven region is A plurality of recesses are formed along the extending direction intersecting the second axis, recessed in the depth direction perpendicular to the second axis and the extending direction, and arranged along the arrangement direction perpendicular to the depth direction and the extending direction, Includes a convex portion disposed between the plurality of recesses. The depth of the recess in the depth direction is 0.1 μm or more and less than 2.5 μm. The arrangement pitch of the recesses along the arrangement direction is 1 μm or more and 80 μm or less.

[0008] In this configuration, multiple recesses and protrusions are formed along the extending direction intersecting the second axis, thereby increasing the length between the first and second external electrodes along the connection surface. This suppresses leakage current due to migration and prevents a decrease in the insulation resistance of the multilayer ceramic electronic component. Furthermore, by setting the depth of the recesses to 0.1 μm or more and less than 2.5 μm, and the arrangement pitch of the recesses to 1 μm or more and 80 μm or less, defects such as cracks and chips in the uneven regions can be suppressed. Therefore, the reliability of the multilayer ceramic electronic component can be improved.

[0009] The arrangement pitch of the recesses relative to the depth of the recesses may be 0.41 times or more and 700 times or less. This ensures that the surface is sufficiently contoured by recesses and protrusions, and more reliably suppresses defects such as cracks and chips in the uneven areas.

[0010] Furthermore, from a similar viewpoint, the ratio of the arrangement pitch of the recesses to the depth of the recesses may be 2.5 times or more and 80 times or less.

[0011] The dimension in the first axial direction may be 110 μm or less. This allows for the creation of thin multilayer ceramic electronic components.

[0012] For example, at least one of the connecting surfaces having the uneven region may extend along the second axial direction and a third axial direction perpendicular to the first and second axes.

[0013] For example, at least one of the connecting surfaces having the uneven region is It has a pair of electrode-forming regions covered by the first and second external electrodes, and an intermediate region between the pair of electrode-forming regions, The uneven region may be formed only in the intermediate region. By preventing the formation of uneven areas in the electrode formation region, the external electrodes can be flattened, thereby suppressing defects during mounting.

[0014] The first and second external electrodes are, respectively, The device may have a conductive thin film and a plating film formed on the conductive thin film. Using a conductive thin film as a base for the plating film makes it easier to construct thin external electrodes.

[0015] Specifically, the thickness of the conductive thin film may be 1.0 μm or less. Furthermore, the conductive thin film may be composed of a sputtered film.

[0016] For example, the extending direction of the concave portion may be a direction perpendicular to the second axis. Alternatively, the extending direction of the concave portion may be a direction that intersects the second axis at an acute angle.

[0017] For example, the arithmetic mean height Sa of the concave portion and the convex portion may each be 1.0 μm or less. For example, the maximum height Sz of the concave portion and the convex portion may each be 5.0 μm or less. By these means, the concave portion and the convex portion can be smoothed, and cracks and chipping of the ceramic element can be more reliably suppressed.

[0018] For example, the absolute value of the difference in the arithmetic mean height Sa between the concave portion and the convex portion may be 0.06 μm or less. For example, the absolute value of the difference in the maximum height Sz between the concave portion and the convex portion may be 4.0 μm or less.

[0019] A circuit board according to another aspect of the present invention includes a multilayer ceramic electronic component and a mounting board on which the multilayer ceramic electronic component is mounted. The multilayer ceramic electronic component has a ceramic element, a first external electrode, and a second external electrode. The ceramic element has a plurality of internal electrodes laminated in a first axial direction via ceramic layers, a first end face and a second end face from which the plurality of internal electrodes are drawn out and perpendicular to a second axis orthogonal to the first axial direction, and four connection faces connecting between the first end face and the second end face and extending along the second axial direction, and is configured in a rectangular parallelepiped shape. The first and second external electrodes are respectively disposed on the first and second end faces, face each other in the second axial direction, and are connected to the mounting board. At least one of the connection faces facing the mounting board has a concavo-convex region located between the first and second external electrodes. The concavo-convex region is A plurality of recesses are formed along the extending direction intersecting the second axis, recessed in the depth direction perpendicular to the second axis and the extending direction, and arranged along the arrangement direction perpendicular to the depth direction and the extending direction, Includes a convex portion disposed between the plurality of recesses. The depth of the recess in the depth direction is 0.1 μm or more and less than 2.5 μm. The arrangement pitch of the recesses along the arrangement direction is 1 μm or more and 80 μm or less.

[0020] A method for manufacturing a multilayer ceramic electronic component according to yet another embodiment of the present invention includes the step of forming a rectangular parallelepiped unfired ceramic body having a plurality of internal electrodes stacked in a first axial direction via a ceramic layer, first and second end faces perpendicular to a second axis orthogonal to the first axial direction, and four connecting surfaces connecting the first and second end faces and extending along the second axial direction. The aforementioned ceramic body is fired. A conductive thin film is formed on at least one of the four connecting surfaces of the fired ceramic body, and on the first and second end faces. By irradiating the conductive thin film on the connection surface with a short-pulse laser along a scanning direction intersecting the second axis, the conductive thin film is removed, and a recess is formed on the connection surface along the scanning direction. [Effects of the Invention]

[0021] As described above, the present invention provides a multilayer ceramic electronic component capable of improving reliability, a circuit board on which it is mounted, and a method for manufacturing the multilayer ceramic electronic component. [Brief explanation of the drawing]

[0022] [Figure 1] This figure shows a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 2] This is a cross-sectional view of a multilayer ceramic capacitor along the line A-A' in Figure 1. [Figure 3] This is a cross-sectional view of a multilayer ceramic capacitor along the line B-B' in Figure 1. [Figure 4] The above is a top view (plan view) of the multilayer ceramic capacitor. [Figure 5] This is a cross-sectional view of a portion of Figure 2, enlarged. [Figure 6] This is a cross-sectional view of a circuit board on which a multilayer ceramic capacitor according to this embodiment is mounted. [Figure 7] This flowchart shows the manufacturing method for the multilayer ceramic capacitor described above. [Figure 8] This is a perspective view illustrating the manufacturing process of the above-mentioned multilayer ceramic capacitor, and is a diagram illustrating step S01. [Figure 9] This is a cross-sectional view illustrating the manufacturing process of the multilayer ceramic capacitor shown above, and is a diagram illustrating step S04. [Figure 10] This is a perspective view illustrating the manufacturing process of the multilayer ceramic capacitor shown above, and is a diagram illustrating step S05. [Figure 11] Figure A is a schematic plan view illustrating step S05 of the manufacturing process of the multilayer ceramic capacitor described above, and schematically shows the spots on the scanning line of the short-pulse laser. Figure B is a graph illustrating the energy distribution of the laser light irradiated to each spot of the short-pulse laser, as well as the spot diameter and processing diameter. [Figure 12] Figure A is a schematic plan view illustrating step S05 of the manufacturing process of the multilayer ceramic capacitor described above, showing the processing area formed by adjacent spots in a direction perpendicular to the scanning direction (X-axis direction). Figure B is a graph showing an example of the energy distribution of laser light in two adjacent spots in a direction perpendicular to the scanning direction (X-axis direction). Figure C is a schematic diagram showing the cross-sections of recesses and protrusions formed by spots having the energy distribution of B. [Figure 13] Graphs A and B, respectively, illustrate the energy distribution of laser beams with the same spot diameter but different power outputs. [Figure 14]This graph shows the surface roughness values ​​of convex and concave areas when the output power of a short-pulse laser is 9W, 7W, and 5W, with A representing the arithmetic mean height Sa and B representing the maximum height Sz. [Figure 15] Figure 14A is a graph showing the absolute value of the difference in arithmetic mean heights Sa between the convex part P2 and the concave part P1, calculated from the results. Figure 14B is a graph showing the absolute value of the difference in maximum heights Sz between the convex part P2 and the concave part P1, calculated from the results. [Figure 16] This figure shows a multilayer ceramic capacitor according to a modified example of the first embodiment described above, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 17] This figure shows a multilayer ceramic capacitor according to a second embodiment of the present invention, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 18] This is a cross-sectional view illustrating the manufacturing process of the multilayer ceramic capacitor shown above, and is a diagram illustrating step S04. [Figure 19] This figure shows a multilayer ceramic capacitor according to a modified example of the second embodiment described above, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 20] This figure shows a multilayer ceramic capacitor according to a third embodiment of the present invention, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 21] This flowchart shows the manufacturing method for the multilayer ceramic capacitor described above. [Figure 22] This figure shows a multilayer ceramic capacitor according to a modified example of the third embodiment described above, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 23] This figure shows a multilayer ceramic capacitor according to another modified example of the third embodiment described above, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 24] This figure shows a multilayer ceramic capacitor according to another modified example of the third embodiment described above, and is a cross-sectional view of the position corresponding to Figure 2. [Figure 25] This is a top view (plan view) of a multilayer ceramic capacitor according to the fourth embodiment of the present invention. [Modes for carrying out the invention]

[0023] Embodiments of the present invention will be described below with reference to the drawings. The drawings show mutually orthogonal X, Y, and Z axes as appropriate. The X, Y, and Z axes define a fixed coordinate system fixed to the multilayer ceramic capacitor.

[0024] <First Embodiment> [Overall configuration of a multilayer ceramic capacitor] Figures 1 to 3 show a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. Figure 1 is a perspective view of the multilayer ceramic capacitor 10. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 10 along the line A-A' in Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 10 along the line B-B' in Figure 1.

[0025] The multilayer ceramic capacitor 10 comprises a ceramic body 11, a first external electrode 14a, and a second external electrode 14b.

[0026] The ceramic body 11 is constructed as a rectangular parallelepiped having a first end face 11a and a second end face 11b extending along the Y-axis and Z-axis, a first side surface 11c and a second side surface 11d extending along the X-axis and Z-axis, and a first main surface 11e and a second main surface 11f extending along the X-axis and Y-axis. The term "rectangular parallelepiped" means that it is substantially rectangular in shape, and for example, the surface of the ceramic body may have gentle irregularities, and the edges connecting each face of the ceramic body 11 may be rounded.

[0027] The first and second end faces 11a and 11b are configured as flat surfaces perpendicular to the X-axis. In this embodiment, a flat surface does not have to be strictly planar as long as it is perceived as flat when viewed as a whole. For example, it includes surfaces with minute irregularities or gently curved shapes within a predetermined range.

[0028] In this embodiment, the first side surface 11c, the second side surface 11d, the first main surface 11e, and the second main surface 11f are each configured as connecting surfaces S that connect the first and second end surfaces 11a and 11b and extend along the X-axis direction. As will be described later, at least one of the four connecting surfaces S has an uneven region P.

[0029] The multilayer ceramic capacitor 10 of this embodiment is configured as a low-profile type with a thin thickness in the Z-axis direction. Specifically, the dimensions of the multilayer ceramic capacitor 10 in the Z-axis direction are, for example, 100 μm or less. The dimensions of the multilayer ceramic capacitor 10 in the X-axis direction are, for example, 0.1 mm or more and 2.0 mm or less. The dimensions of the multilayer ceramic capacitor 10 in the Y-axis direction are, for example, 0.1 mm or more and 2.0 mm or less. The multilayer ceramic capacitor 10 may have its longitudinal side in either the X-axis direction or the Y-axis direction, and in the examples shown in Figures 1 to 3, it has its longitudinal side in the X-axis direction. Note that the "dimensions" of the multilayer ceramic capacitor 10 in a certain direction refer to the maximum dimension in that direction.

[0030] The first external electrode 14a is positioned on the first end face 11a. The second external electrode 14b is positioned on the second end face 11b. The external electrodes 14a and 14b face each other in the X-axis direction. As will be described later, the external electrodes 14a and 14b may extend from the end faces 11a and 11b to other faces.

[0031] The ceramic body 11 has a first internal electrode 12 and a second internal electrode 13 stacked in the Z-axis direction via a ceramic layer. In the example shown in Figures 2 and 3, the internal electrodes 12 and 13 are both sheet-like structures extending along the XY plane and are arranged alternately along the Z-axis direction.

[0032] The internal electrodes 12 and 13 mainly contain a conductive component. Typical conductive components include nickel (Ni), but other examples include copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof.

[0033] For example, the thickness of each internal electrode 12, 13 in the Z-axis direction can be, for example, 0.2 μm or more and 1.0 μm or less. This allows the internal electrodes 12, 13 to be made thin. Note that the number of layers of the internal electrodes 12, 13 is not limited to the example shown.

[0034] The first internal electrode 12 is drawn out to the first end face 11a and spaced apart from the second end face 11b. As a result, the first internal electrode 12 is connected to the first external electrode 14a at the first end face 11a and insulated from the second external electrode 14b. The second internal electrode 13 is drawn out to the second end face 11b and spaced apart from the first end face 11a. As a result, the second internal electrode 13 is connected to the second external electrode 14b at the second end face 11b and insulated from the first external electrode 14a.

[0035] With this configuration, when a voltage is applied between the external electrodes 14a and 14b of the multilayer ceramic capacitor 10, a voltage is applied to multiple ceramic layers between the internal electrodes 12 and 13. As a result, the multilayer ceramic capacitor 10 stores a charge corresponding to the voltage between the external electrodes 14a and 14b.

[0036] The ceramic body 11 is composed of ceramics not only in the ceramic layer between the internal electrodes 12 and 13, but also around the internal electrodes 12 and 13. The dielectric ceramic used in the ceramic body 11 has, for example, a perovskite structure represented by the general formula ABO3. Examples of dielectric ceramics having a perovskite structure include materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0037] Specifically, dielectric ceramics may be composed of other materials besides barium titanate, such as strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Ti,Zr,Ti)O3), barium calcium zirconate titanate ((Ba,Ca)(Ti,Zr)O3), barium zirconate (BaZrO3), and titanium dioxide (TiO2).

[0038] The thickness of each ceramic layer in the Z-axis direction can be, for example, 0.2 μm to 1.0 μm. This allows for a thinner ceramic body 11 and increases the capacitance of the multilayer ceramic capacitor 10.

[0039] [External electrode configuration] As shown in Figures 1 and 2, the first external electrode 14a extends from the first end face 11a to the first main surface 11e and both side surfaces 11c and 11d. Similarly, the second external electrode 14b extends from the second end face 11b to the first main surface 11e and both side surfaces 11c and 11d. The external electrodes 14a and 14b do not need to extend to the lower Z-axis ends (ends on the second main surface 11f side) of the end faces 11a and 11b and the side surfaces 11c and 11d; they only need to cover the ends of all internal electrodes 12 and 13 that are exposed on the end faces 11a and 11b.

[0040] In this embodiment, each external electrode 14a, 14b has multiple layers. Specifically, each external electrode 14a, 14b has a conductive thin film 141 and a plating film 142 formed on the conductive thin film 141.

[0041] In this embodiment, the conductive thin film 141 is configured as a sputtered film formed by a sputtering method. Alternatively, the conductive thin film 141 may be a conductive thin film formed by an electroless plating method, vapor deposition method, printing method, or dip method, etc. The conductive thin film 141 includes, for example, Ti, Ni, Ag, Au, Pt, Pd, Cu, tantalum (Ta), tungsten (W), or alloys thereof. The conductive thin film 141 may be a single layer or may consist of multiple layers.

[0042] The thickness of the conductive thin film 141 may be, for example, 1.0 μm or less. This allows the external electrodes 14a and 14b to be made thinner, and the multilayer ceramic capacitor 10 to be made thinner.

[0043] The plating film 142 forms the outer layer of the external electrodes 14a and 14b and covers the conductive thin film 141. The plating film 142 is a film formed on the conductive thin film 141 as a substrate by a wet plating method such as electroplating, and has one or more layers. Each layer of the plating film 142 mainly consists of at least one of the following: Ni, Cu, tin (Sn), Pd, and Ag.

[0044] These external electrodes 14a and 14b must be reliably insulated to prevent short circuits caused by electrical conductivity. On the other hand, in light of the recent miniaturization of multilayer ceramic capacitors 10, the distance between the external electrodes 14a and 14b has also decreased, increasing the risk of electrical conductivity between the external electrodes 14a and 14b. Furthermore, with the diversification of applications for multilayer ceramic capacitors 10, they are increasingly being used in high-humidity environments. This also contributes to the increased risk of insulation failure in multilayer ceramic capacitors 10.

[0045] For example, in a high-humidity environment, condensation may form on the surface of the ceramic element 11, causing the metal in the external electrodes 14a and 14b to ionize and dissolve. This can lead to so-called migration, where metal ions move across the surface of the ceramic element 11. As metal ions dissolved from one external electrode approach the other external electrode, the risk of leakage current generation on the surface of the ceramic element 11 increases. Therefore, it is believed that a longer distance traveled by metal ions between the external electrodes 14a and 14b reduces the risk of insulation failure in the multilayer ceramic capacitor 10.

[0046] Furthermore, for example, during the formation of the plating film 142, so-called plating elongation may occur, where the plating film 142 extends from the conductive thin film 141 to the surface of the ceramic substrate 11. If plating elongation occurs, the solder formed on the external electrodes 14a and 14b is more likely to come into contact with each other during mounting to the mounting substrate, increasing the likelihood of a short circuit.

[0047] To suppress insulation failures in such multilayer ceramic capacitors 10, the inventors conceived of forming irregularities (undulations) on the surface of the ceramic element 11 and increasing the length along the surface of the ceramic element 11 between the external electrodes 14a and 14b. Furthermore, the inventors found that depending on the shape of the irregularities, defects such as cracks in the ceramic element 11 are more likely to occur, and therefore found an optimal shape of irregularities to improve the reliability of the multilayer ceramic capacitor 10. The configuration of the irregularity region P in this embodiment will be described below.

[0048] [Composition of uneven areas] Figure 4 is a plan view of the multilayer ceramic capacitor 10 as seen from above in the Z-axis direction (on the first main surface 11e side). In this embodiment, the first main surface 11e has an uneven region P located between the external electrodes 14a and 14b. In this embodiment, in addition to the first main surface 11e, the first side surface 11c and the second side surface 11d may also have an uneven region P. The uneven region P on the first main surface 11e will be described in detail below, and the uneven regions P on the first side surface 11c and the second side surface 11d will be described later.

[0049] In this embodiment, the first main surface 11e, which is configured as the connection surface S, has a pair of electrode formation regions S1 covered by external electrodes 14a and 14b, and an intermediate region S2 between the pair of electrode formation regions S1, and the uneven region P is formed only in the intermediate region S2. In other words, the uneven region P is not formed in the electrode formation region S1. As a result, the external electrodes 14a and 14b can be flattened, and the orientation of the multilayer ceramic capacitor 10 during mounting can be stabilized.

[0050] The uneven region P includes a plurality of recesses P1 and a plurality of protrusions P2 positioned between the recesses P1. In Figure 4, the protrusions P2 are represented by a diagonal pattern.

[0051] In this embodiment, each recess P1 is formed along the Y-axis direction and recesses in the Z-axis direction. Multiple recesses P1 are regularly arranged along the X-axis direction. That is, in this embodiment, the extension direction of the recess P1 is parallel to the Y-axis direction, the depth direction is parallel to the Z-axis direction, and the arrangement direction is parallel to the X-axis direction. The recess P1 includes a bottom P10, which is the deepest part, in a cross-section (e.g., XZ cross-section) parallel to the depth direction and the arrangement direction (see Figure 5). The extension direction of the recess P1 is the extension direction of the bottom P10.

[0052] The convex portion P2 is formed along the Y-axis direction between the concave portions P1. The convex portion P2 includes the most protruding apex P20 in a cross-section (e.g., XZ section) (see Figure 5). The direction of extension of the convex portion P2 is the direction of extension of the apex P20, and in this embodiment, it is parallel to the Y-axis direction.

[0053] For example, if the X-axis dimension of the multilayer ceramic capacitor 10 is 1.0 mm, the number of recesses P1 included in the uneven region P is preferably 2 or more and 60 or less. The number of protrusions P2 included in the uneven region P is preferably 1 or more and 59 or less. The ratio of the X-axis dimension of the uneven region P to the X-axis dimension of the multilayer ceramic capacitor 10 is preferably 5% or more and 60% or less. Furthermore, it is preferable that the uneven region P is formed over the entire Y-axis direction of the first main surface 11e. The number of recesses P1 and protrusions P2 can be appropriately adjusted according to the X-axis length between the external electrodes 14a and 14b.

[0054] In this embodiment, the uneven region P can be formed by laser irradiation. More specifically, the uneven region P is formed, for example, as a scanning trace when a short-pulse laser is irradiated onto a conductive thin film formed over the entire first main surface 11e, causing the conductive thin film to sublimate and be removed. In this case, the shapes of the recesses P1 and protrusions P2 can be adjusted by the irradiation and scanning conditions of the short-pulse laser. Details of the method for forming the uneven region P will be described later.

[0055] In this embodiment, the uneven region P is configured such that recesses P1 extending in the Y-axis direction and protrusions P2 are alternately arranged in the X-axis direction, and the region is undulated at regular intervals along the X-axis direction. As a result, in order to cross the surface of the uneven region P in the X-axis direction, one must pass through the undulations caused by the recesses P1 and protrusions P2. In other words, the uneven region P can increase the length of the contour of the first main surface 11e in the XZ cross-section between the external electrodes 14a and 14b.

[0056] Therefore, the uneven region P reduces the risk of conductivity between the external electrodes 14a and 14b. For example, when migration occurs, the risk of metal ions dissolved from one external electrode approaching the other external electrode can be reduced, thereby suppressing the generation of leakage current. In addition, the undulations of the recessed portion P1 and the convex portion P2 can suppress plating elongation along the X-axis direction.

[0057] On the other hand, if the depth of the recess P1 is too great, the convex portion P2 will protrude sharply, making the ceramic body 11 more susceptible to cracks and chips. Also, if the arrangement pitch of the recesses P1 is too narrow or too wide, it increases the risk of cracks and chips, and causes problems such as insufficient relief of the recesses P1 and convex portion P2. Therefore, in this embodiment, the shape of the recess P1 is set as follows to suppress problems associated with unevenness while suppressing conductivity between the external electrodes 14a and 14b.

[0058] Figure 5 is a cross-sectional view that is an enlarged portion of Figure 2. Note that in the cross-sectional views of Figure 5 and Figure 2, the depth of the uneven region P is exaggerated compared to its actual depth. As shown in Figure 5, the uneven region P is formed by repeating gentle curves.

[0059] In this embodiment, the depth d1 of the recess P1 is 0.1 μm or more and less than 2.5 μm. This makes the depth of the recess P1 gradual and suppresses cracks in the protrusion P2. Preferably, the depth d1 is 0.2 μm or more and 2.3 μm or less, and more preferably 0.5 μm or more and 2.0 μm or less. This provides the effect of increasing the surface area of ​​the first main surface 11e due to the recess P1, and more reliably suppresses cracks and chips in the protrusion P2.

[0060] The depth d1 of the recess P1 in the Z-axis direction (depth direction) is defined as the dimension from the top P20 of the convex portion P2 to the bottom P10 of the recess P1 in the cross-section (e.g., XZ section) of the uneven region P. If the depths of the recesses P1 included in the uneven region P are different, the average value of the depths of the multiple recesses P1 is taken as the depth d1. Furthermore, if the heights of the tops P20 on both sides of the recess P1 are different, the dimension from the higher top P20 to the bottom P10 of the recess P1 is measured.

[0061] The dimension along the X-axis direction (arrangement direction) between the bottoms P10 of adjacent recesses P1 is defined as the arrangement pitch d2 of the recesses P1. For example, the arrangement pitch d2 of the recesses P1 can be the average value of the dimensions between the bottoms P10 at multiple locations in the cross-section (e.g., XZ section) of the uneven region P. The average values ​​of depth d1 and arrangement pitch d2 can be calculated by measuring, for example, 10 randomly selected locations.

[0062] The arrangement pitch d2 of the recesses P1 is 1 μm or more and 80 μm or less, preferably 2 μm or more and 70 μm or less, and more preferably 5 μm or more and 40 μm or less. By setting the arrangement pitch d2 within the above range, undulations along the X-axis can be effectively formed, and cracks and chips in the ceramic body 11 can be suppressed. Furthermore, by setting the arrangement pitch d2 to 80 μm or less, the residue of the conductive thin film can be suppressed when the conductive thin film is removed by irradiation with a short-pulse laser.

[0063] The ratio of the array pitch d2 of the recesses P1 to the depth d1 of the recesses P1 is preferably 0.41 times or more and 700 times or less, more preferably 2.5 times or more and 80 times or less. This makes it possible to make the array pitch d2 of the recesses P1 sufficiently large relative to the depth d1 of the recesses P1, and to form stable undulations on the first main surface 11e.

[0064] In this embodiment, the recesses P1 and protrusions P2 are configured as undulations formed at regular intervals within the connecting surface S, unlike surface roughness. Therefore, surface roughness, such as surface roughness, can be measured for each of the recesses P1 and protrusions P2.

[0065] The surface roughness of the recess P1 and the protrusion P2 is preferably small. For example, the arithmetic mean height Sa of the recess P1 and the protrusion P2 is preferably 1.1 μm or less, and more preferably 0.5 μm or less. Also, the maximum height Sz of the recess P1 and the protrusion P2 is preferably 5.1 μm or less, and more preferably 3.0 μm or less.

[0066] As a result, the surfaces of the protrusions P2 and recesses P1 are sufficiently smoothed, which helps to suppress damage such as cracks. Furthermore, when the multilayer ceramic capacitor 10 is mounted on a substrate and then sealed with resin, the resin can easily penetrate between the uneven areas P and the substrate or other electronic components, thereby improving the insulation properties of the resin seal.

[0067] Furthermore, the absolute value of the difference in the arithmetic mean heights Sa of the convex portion P2 and the concave portion P1 is preferably 0.06 μm or less, and more preferably 0.04 μm or less. Also, the absolute value of the difference in the maximum heights Sz of the convex portion P2 and the concave portion P1 is preferably 4.0 μm or less, and more preferably 2.0 μm or less. This makes it possible to further improve the surface smoothness of the convex portion P2 and the concave portion P1, thereby further enhancing the effect of suppressing damage such as cracks and improving the sealing performance by the resin.

[0068] The surface roughness Sa and Sz of the convex portion P2 and concave portion P1 are defined as the surface roughness measured along their respective extension directions. Specifically, the measurement area for the surface roughness Sa and Sz of each convex portion P2 and concave portion P1 is the area including the top P20 or bottom P10, with a length of, for example, 30 to 200 μm along the extension direction and a width of 0.5 to 10 μm along the perpendicular alignment direction. For multiple concave portions P1 and convex portions P2, the average value of the surface roughness Sa and Sz measured for each is calculated.

[0069] The surface roughness Sa and Sz of the convex portion P2 and concave portion P1 can be controlled, for example, by the output of a short-pulse laser when forming the uneven region P by irradiation with a short-pulse laser. This will be described later.

[0070] Furthermore, the uneven regions P on connection surfaces S other than the first main surface 11e only need to have the same shape as the uneven regions P on the first main surface 11e. Having two or more of the connection surfaces S have uneven regions P can further improve the reliability of the multilayer ceramic capacitor 10.

[0071] Specifically, the recesses P1 on each connecting surface S are formed along an extension direction intersecting the X-axis, recessed in a depth direction perpendicular to the X-axis and the extension direction, and arranged along an alignment direction perpendicular to the depth direction and the extension direction. The protrusions P2 are positioned between the multiple recesses P1. The depth of the recesses P1 in the depth direction is 0.1 μm or more and less than 2.5 μm, and the pitch of the recesses P1 along the alignment direction is 1 μm or more and 80 μm or less. For example, on the first side surface 11c and the second side surface 11d, the extension direction of the recesses P1 is in a direction intersecting the X-axis, and may be parallel to the Z-axis direction, for example. The depth direction of the recesses P1 is parallel to the Y-axis direction, for example.

[0072] [Circuit board] The multilayer ceramic capacitor 10 with the above configuration is mounted, for example, on a circuit board 100. Figure 6 is a cross-sectional view of the circuit board 100 according to this embodiment.

[0073] The circuit board 100 includes a multilayer ceramic capacitor 10 and a mounting board 110 on which the multilayer ceramic capacitor 10 is mounted. The mounting board 110 has lands (connection electrodes) 111 that are connected to the multilayer ceramic capacitor 10. The external electrodes 14a and 14b of the multilayer ceramic capacitor 10 are connected to the lands 111, for example, by solder H.

[0074] In the manufacturing process of the circuit board 100, first, solder H is placed on each land 111 of the mounting board 110. The multilayer ceramic capacitor 10 is placed on the mounting board 110 with the first main surface 11e of the ceramic body 11 facing the mounting board 110 and the positions of the external electrodes 14a and 14b aligned with the positions of the lands 111.

[0075] When the mounting substrate 110 on which the multilayer ceramic capacitor 10 is placed is heated in a reflow oven or the like, the solder H on the land 111 melts. As a result, the molten solder H wets and spreads along the land 111 of the mounting substrate 110 and the surface of the external electrodes 14a and 14b of the multilayer ceramic capacitor 10. As the solder H cools and solidifies, the multilayer ceramic capacitor 10 is connected to the mounting substrate 110.

[0076] In its molten state, the solder H basically wets and spreads across the surfaces of the external electrodes 14a and 14b. However, if the external electrodes 14a and 14b are thin, the solder may also spread to the surface of the ceramic body 11, such as the first main surface 11e. If the solder H on both external electrodes 14a and 14b comes into contact, the external electrodes 14a and 14b will become conductive, and a short circuit may occur.

[0077] In contrast, in this embodiment, the first main surface 11e has an uneven region P, and recesses P1 and protrusions P2 are formed along the Y-axis direction which intersects (is perpendicular to) the X-axis. Therefore, the solder H is less likely to spread along the X-axis direction, and the risk of contact between the solder H of the external electrodes 14a and 14b can be reduced.

[0078] Furthermore, as described above, since plating elongation along the X-axis direction of the external electrodes 14a and 14b is less likely to occur, the risk of electrical conductivity of the external electrodes 14a and 14b can be reduced.

[0079] Furthermore, the circuit board 100 may be sealed by a resin film applied to the mounting substrate 110. In this case, the presence of an uneven region P on the first main surface 11e guides the resin in the direction of the Y axis, which is the direction of extension of the recess P1, making it easier for the resin to enter the gap between the first main surface 11e and the mounting substrate 110. This enhances the insulating effect of the resin film.

[0080] Furthermore, by ensuring that the surface roughness Sa,Sz of the recess P1 and the protrusion P2, and the absolute value of the difference between the surface roughness Sa,Sz of the recess P1 and the protrusion P2 are within the above-mentioned range, the surface smoothness of the recess P1 and the protrusion P2 is enhanced. This makes it easier for the sealing resin to penetrate between the uneven region P and the mounting substrate 110.

[0081] [Manufacturing method for multilayer ceramic capacitors] Figure 7 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 10. Figures 8 to 15 are diagrams illustrating the manufacturing process of the multilayer ceramic capacitor 10. The manufacturing method of the multilayer ceramic capacitor 10 will be explained below with reference to these figures.

[0082] (Step S01: Lamination of ceramic sheets) In this step, referring to Figure 8, a laminated sheet 104 is fabricated by stacking ceramic sheets 101, 102, and 103.

[0083] The ceramic sheets 101, 102, and 103 are composed of unfired ceramic green sheets, with dielectric ceramics as the main component. These ceramic sheets 101, 102, and 103 are formed into sheets using methods such as the doctor blade method, die coater method, and gravure coater method.

[0084] As shown in Figure 8, internal electrode patterns 112 and 113 are formed on the ceramic sheets 101 and 102. The internal electrode patterns 112 and 113 are formed by applying a conductive paste to the ceramic sheets 101 and 102. The first internal electrode pattern 112 corresponds to the first internal electrode 12 and is formed on the first ceramic sheet 101. The second internal electrode pattern 113 corresponds to the second internal electrode 13 and is formed on the second ceramic sheet 102. No internal electrode pattern is formed on the ceramic sheet 103.

[0085] The ceramic sheets 101, 102, and 103 shown in Figure 8 have cut lines Lx and Ly for separating the ceramic body 11 into individual pieces. Each internal electrode pattern 112 and 113 is configured in a rectangular shape, for example, extending across a single cut line Ly. The second internal electrode pattern 113 is formed offset from the first internal electrode pattern 112 by one chip in the X-axis or Y-axis direction.

[0086] Then, as shown in Figure 8, ceramic sheets 101 and 102, each having internal electrode patterns 112 and 113 formed on it, are stacked alternately, and ceramic sheets 103, which do not have internal electrode patterns, are stacked above and below them. These ceramic sheets 101, 102, and 103 are integrated by being pressed together. Note that the number of ceramic sheets 101, 102, and 103 is not limited to the example shown in Figure 8.

[0087] (Step S02: Cutting) In this step, an unfired ceramic body 11 is produced by cutting the laminated sheet 104 along the cut lines Lx and Ly. Methods such as push cutting and blade dicing can be used for cutting.

[0088] (Step S03: Firing) In this step, the unfired ceramic body 11 is sintered. This produces the ceramic body 11 shown in Figures 1-3. The firing temperature can be determined based on the sintering temperature of the ceramic body 11. For example, when using barium titanate (BaTiO3) based material, the firing temperature can be set to approximately 1000-1350°C. Furthermore, firing can be carried out, for example, under a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0089] (Step S04: Formation of conductive thin film) In this step, referring to Figure 9, a conductive thin film E is formed on the end faces 11a, 11b and on at least one of the four connecting faces S. In this embodiment, the conductive thin film E is formed on five faces, for example, the first main face 11e, the first and second end faces 11a, 11b, and the first and second side faces 11c, 11d, but not on the second main face 11f. In the next step, a portion of this conductive thin film E is removed to form the conductive thin film 141 of the external electrodes 14a, 14b.

[0090] In this embodiment, the conductive thin film E is formed by sputtering. Sputtering may be performed, for example, on the first main surface 11e as the target for film formation. This allows the film formation material to wrap around not only the first main surface 11e, but also the end faces 11a, 11b, and the side faces 11c, 11d. As a result, if the ceramic substrate 11 is thin in the Z-axis direction, sputtering on the first main surface 11e as the target for film formation can form a conductive thin film E that sufficiently covers the internal electrodes 12, 13 exposed on the end faces 11a, 11b.

[0091] Alternatively, sputtering may be performed on each surface to be coated by changing the orientation of the ceramic substrate 11.

[0092] By forming a conductive thin film E by sputtering, it is possible to form a conductive thin film E with a thickness of, for example, 1.0 μm or less. This allows for a thinner multilayer ceramic capacitor 10 and makes it easier to remove the conductive thin film E by irradiation with a short-pulse laser in the next step.

[0093] In this embodiment, a conductive thin film E is formed over the entire first main surface 11e. Therefore, a mask is not required during sputtering. Consequently, the steps of forming and removing the mask can be omitted, increasing manufacturing efficiency. This is also advantageous for small multilayer ceramic capacitors 10, where high precision is required for mask formation.

[0094] (Step S05: Irradiation with a short-pulse laser) In this step, a short-pulse laser with a short pulse width is irradiated onto the conductive thin film E on the connection surface S. As a result, the conductive thin film E in the area irradiated by the short-pulse laser sublimes and is removed, forming the conductive thin films 141 of the external electrodes 14a and 14b. Consequently, an uneven region P is formed on the connection surface S.

[0095] Specifically, the short-pulse laser used in this step can be selected from pulse lasers with a pulse width in the picosecond range or less. Examples of such short-pulse lasers include picosecond lasers with a pulse width in the picosecond range and femtosecond lasers with a pulse width in the femtosecond range. Specifically, the pulse width of the short-pulse laser is preferably 100 picoseconds or less. By using such a short-pulse laser, the energy intensity at each spot of the laser light is increased. As a result, the conductive thin film E can be reliably sublimated without the conductive thin film E melting or the ceramic substrate 11 burning.

[0096] In this embodiment, a conductive thin film E formed in the center of the connection surface S in the X-axis direction is removed. The ratio of the length of the area where the conductive thin film E is removed in the X-axis direction to the length of the conductive thin film E on the connection surface S in the X-axis direction is preferably, for example, 5% or more and 60% or less. Furthermore, it is preferable that the conductive thin film E is removed over the entire length of the connection surface S in the direction perpendicular to the X-axis.

[0097] In this step, it is preferable that the short-pulse laser irradiation is performed on each of the connection surfaces S on which the conductive thin film E is formed. This ensures that the conductive thin film E is reliably divided in the X-axis central part of the ceramic body 11, and the conductive thin films 141 of the external electrodes 14a and 14b are formed.

[0098] Figure 10 shows a state in which a short-pulse laser (laser) L is irradiated onto a conductive thin film E on the first main surface 11e of a ceramic substrate 11. An example of irradiating the first main surface 11e with the laser L will be explained using Figure 10.

[0099] In the example shown in Figure 10, multiple ceramic substrates 11 are arranged in the Y-axis direction and irradiated with a laser L. This allows the conductive thin film E of multiple ceramic substrates 11 to be continuously irradiated with the laser L, thereby increasing manufacturing efficiency. However, the method is not limited to this, and a single ceramic substrate 11 may also be irradiated with the laser L.

[0100] Laser L is emitted by a laser oscillator and scanned by a scanning mechanism. In Figure 10, Le indicates a lens used to focus the laser beam and adjust the spot diameter.

[0101] The laser L scans the conductive thin film E with the Y-axis direction, which is the direction in which the recess P1 extends, as the scanning direction. After scanning along one scanning line, the laser L shifts in the X-axis direction and scans along the next scanning line. In this way, as the laser L repeatedly scans along multiple scanning lines, the conductive thin film E is removed in predetermined widths, and multiple scan marks are formed on the first main surface 11e.

[0102] In this embodiment, recesses P1 are formed on the first main surface 11e by the scanning marks of the laser L. As a result, on the first main surface 11e after laser irradiation, a plurality of recesses P1 formed along the Y-axis direction (scanning direction) are arranged along the X-axis direction. In addition, protrusions P2 are formed between adjacent recesses P1. As a result, an uneven region P is formed on the first main surface 11e.

[0103] The number of recesses P1 is adjusted by the number of scanning lines. The shape of the recesses P1 can be adjusted by the size and output of the laser L spot, as described below. The specific conditions of the laser L, such as output, scanning speed, wavelength of the laser light, and pulse frequency, can be appropriately determined according to the materials constituting the conductive thin film E and the ceramic substrate 11, as well as the thickness of the conductive thin film E. For example, the wavelength of the laser light can be selected from wavelengths in the ultraviolet region (200 nm or more) to the visible light region (1000 nm or less), and a green laser can be used as such a laser L.

[0104] Figure 11A is a schematic plan view showing the spot Sp1 on the scanning line Ln of the laser L. Figure 11B is a graph illustrating the energy distribution of the laser light irradiated onto each spot Sp1, the spot diameter, and the processing diameter, with the vertical axis representing energy intensity and the horizontal axis representing the position centered on the spot center Sp0. In the following explanation, we will describe an example where the spot Sp1 of the laser L is approximately circular, but the explanation is not limited to this.

[0105] As shown in Figure 11A, the short-pulse laser L is irradiated such that multiple spots Sp1 overlap in the scanning direction along the scanning line Ln. As shown in Figure 11B, the energy distribution of the laser light irradiated to each spot Sp1 has, for example, a Gaussian distribution, and the energy intensity increases as it approaches the spot center Sp0.

[0106] To sublimate the conductive thin film E, energy greater than or equal to a predetermined threshold Th shown in Figure 11B is required. Therefore, the processing diameter d4 of the processing region Sp2 from which the conductive thin film E is removed becomes smaller than the spot diameter d3. In other words, as shown in Figure 11A, the size of the processing region Sp2 from which the conductive thin film E is actually removed is smaller than the size of the spot Sp1.

[0107] In the processing region Sp2, a portion of the ceramic substrate 11 is removed along with the conductive thin film E. As shown in Figure 11B, the energy of the laser light irradiated onto the processing region Sp2 increases towards the spot center Sp0, so the processing region Sp2 takes on a concave shape with the spot center Sp0 as the center. In other words, the processing region Sp2 forms a concave portion P1, and the spot center Sp0 forms a bottom portion P10.

[0108] As shown in Figure 11A, the machining area Sp2 is formed continuously in the scanning direction, thereby forming a recess P1 along the scanning direction. Therefore, the groove width of the recess P1 depends on the size of the machining area Sp2, i.e., the machining diameter d4. The machining diameter d4 is preferably 10 μm to 100 μm, taking into consideration the balance between machining accuracy and machining efficiency.

[0109] On the other hand, at the periphery of the processing area Sp2, the depth of the recess P1 gradually decreases, and residual conductive thin film E is more likely to occur. For this reason, as shown in Figure 12A, processing areas Sp2 on adjacent scanning lines Ln are overlapped by a predetermined ratio (lapping ratio R) with respect to the processing diameter d4. The lapping ratio R (%) is the ratio of the overlapping length in the X-axis direction of the two processing areas Sp2 when the processing diameter d4 is set to 100%. In this embodiment, the lapping ratio R is preferably 10% to 95%, and more preferably 30% to 90%, in order to prevent residual conductive thin film E. Note that in Figure 12A, for convenience, multiple processing areas Sp2 on the scanning line Ln are shown as a continuous strip-shaped region.

[0110] Figure 12B is a graph showing an example of the energy distribution of laser light in two adjacent spots Sp1 in a direction perpendicular to the scanning direction (X-axis direction), where the vertical axis represents energy intensity and the horizontal axis represents position in the X-axis direction. Figure 12C is a diagram showing an example of the cross-sectional shape of a recess P1 and a protrusion P2 formed corresponding to a spot Sp1 having the energy distribution shown in Figure 12B.

[0111] As shown in Figures 12B and 12C, the bottom P10 of a recess P1 is formed at the spot center Sp0 on each scanning line Ln, and the top P20 of a convex P2 is formed at the point between two spot centers Sp0 where the sum of the irradiated energy intensities is lowest. The distance between adjacent scanning lines Ln (scanning pitch) is equal to the array pitch d2, which is the distance between the bottoms P10 of adjacent recesses P1.

[0112] Therefore, the array pitch d2 is expressed by the following formula using the overlap rate R (%) and the machining diameter d4. d2 = (100 - R) × d4

[0113] Thus, the arrangement pitch d2 of the recesses P1 in this embodiment can be controlled by the overlap rate R (%) and the machining diameter d4.

[0114] Next, we will explain how to control the depth of the recess P1. Figures 13A and 13B are graphs illustrating the energy distribution of laser beams with the same spot diameter d3 but different outputs, where the vertical axis represents energy intensity and the horizontal axis represents the position centered on the spot center Sp0.

[0115] In the examples shown in Figures 13A and 13B, the thick line shows the energy distribution of the spot for the laser with the highest output Pw1, the solid line for the laser with the second highest output Pw2, and the dashed line for the laser with the lowest output Pw3. As described above, the bottom P10 of the recess P1 is formed at the spot center Sp0 where the energy intensity of each spot Sp1 is maximum, and the depth of the recess P1 has a positive correlation with the maximum energy intensity of each spot Sp1. Therefore, the depth of the recess P1 can be increased by increasing the output of the laser L. In the examples shown in Figures 13A and 13B, the recess P1 can be formed deeper in the order of lasers Pw3, Pw2, and Pw1.

[0116] In the example shown in Figure 13A, there is a positive correlation between the laser output and the processing diameter d4, but as shown in Figure 13B, there may also be a negative correlation between the laser output and the processing diameter d4.

[0117] Furthermore, the output of the laser L can also be used to control the surface roughness of the convex portion P2 and the concave portion P1. An example of this can be shown below.

[0118] Figures 14A and 14B are graphs showing the surface roughness values ​​of the convex portion P2 and concave portion P1 when the output power of the short-pulse laser is 9W, 7W, and 5W. Figure 14A shows the arithmetic mean height Sa, and Figure 14B shows the maximum height Sz. In these figures, the horizontal axis represents the output power of the short-pulse laser. Figure 15A is a graph showing the absolute value of the difference in arithmetic mean height Sa between the convex portion P2 and concave portion P1, calculated from the results of Figure 14A. Figure 15B is a graph showing the absolute value of the difference in maximum height Sz between the convex portion P2 and concave portion P1, calculated from the results of Figure 14B. In these graphs, the horizontal axis represents the output power of the short-pulse laser, and the vertical axis represents the absolute value (μm) of the difference in arithmetic mean height Sa or maximum height Sz. Note that "Untreated" in Figures 14 and 15 refers to the measured values ​​for the first main surface 11e before the formation of the conductive thin film E.

[0119] In these tests, seven recesses P1 were formed. A YAG laser with a wavelength of 532 nm was used as the short-pulse laser, with the laser scanning direction set to the Y-axis, the laser pulse length to 10-20 picoseconds, the laser scanning speed to 1000 m / s, and the laser pulse frequency to 400 kHz. In these tests, all conditions except the laser output were kept substantially the same.

[0120] The surface roughness of the convex portion P2 and concave portion P1 was calculated as the average value of the surface roughness of five measurement areas. The measurement areas were defined as regions with a length of 200 μm along the extension direction and a width of 10 μm along the perpendicular alignment direction. The arithmetic mean height Sa and maximum height Sz were measured using a laser microscope (Keyence Corporation, VK-X3000).

[0121] As shown in Figures 14A, B and 15A, B, it was found that the difference in surface roughness between the recess P1 and the protrusion P2 increases as the output of the laser L increases. From these results, it is preferable to set the output of the short-pulse laser to, for example, 7W or less in order to keep the absolute value of the difference in the arithmetic mean height Sa of the protrusion P2 and the recess P1 to 0.05 μm or less, and the absolute value of the difference in the maximum height Sz of the protrusion P2 and the recess P1 to 2.0 μm or less.

[0122] (Step S06: Plating layer formation) Finally, a multilayer ceramic capacitor 10, as shown in Figures 1-3, is fabricated by forming a single or multiple plating film 142 on the processed conductive thin film 141. The plating film 142 can be formed, for example, by electroplating.

[0123] [Examples and Comparative Examples] Examples and comparative examples of the above embodiments will now be described. Samples of multilayer ceramic capacitors for Examples 1 to 6 and Comparative Examples 1 and 2 were prepared by changing the output (power), spot diameter d3, and overlap ratio R of the short-pulse laser. In Examples 1 to 6, samples were prepared under conditions where the depth of the recesses on the first main surface was 0.1 μm or more and less than 2.5 μm, and the arrangement pitch of the recesses was 1 μm or more and 80 μm or less. In Comparative Example 1, a sample was prepared under conditions where the depth of the recesses was 2.5 μm. In Comparative Example 2, a sample was prepared under conditions where the arrangement pitch of the recesses was 90 μm. The conditions of the short-pulse laser for Examples 1 to 6 and Comparative Examples 1 and 2, and the shape of the recesses after manufacturing are shown in Table 1.

[0124] In both the above examples and comparative examples, the X, Y, and Z axis dimensions of the multilayer ceramic capacitor sample were set to 1.0 mm × 0.5 mm × 0.11 mm. Furthermore, in both the above examples and comparative examples, a YAG laser with a wavelength of 532 nm was used as the short-pulse laser, with the laser scanning direction set to the Y-axis, the laser pulse duration to 10-20 p-seconds, the laser scanning speed to 1000 m / second, and the pulse frequency to 400 kHz. A galvanometer scanner and an f-theta (θ) lens were used for scanning the short-pulse laser. In addition, the configuration of the multilayer ceramic capacitor sample was substantially the same in both the above examples and comparative examples, except for the shape of the uneven regions.

[0125] [Table 1]

[0126] The uneven areas of the samples from Examples 1-6 and Comparative Examples 1 and 2 were visually inspected. Samples without structural defects such as cracks or residual conductive thin films were classified as OK, while those with structural defects were classified as NG. The results are shown in Table 1.

[0127] As shown in Table 1, no structural defects were observed in the uneven regions of the samples from Examples 1 to 6, resulting in an OK rating. On the other hand, in Comparative Example 1, where the depth of the recesses was 2.5 μm, cracks occurred in the uneven regions, resulting in an NG rating. Furthermore, in Comparative Example 2, where the arrangement pitch of the recesses was 90 μm, a conductive thin film remained in the uneven regions, resulting in an NG rating.

[0128] These results indicate that in the samples of Comparative Examples 1 and 2, leakage currents are easily generated on the surface and internally due to the effects of cracks and residual conductive thin films. On the other hand, in Examples 1 to 6, in addition to the formation of irregularities, there are no structural defects on the surface, which improves reliability.

[0129] [Differentiation] Figure 16 shows a modified example of this embodiment of a multilayer ceramic capacitor 10A, and is a cross-sectional view of the position corresponding to Figure 2. As shown in the figure, the entire first main surface 11e (connecting surface S) may be composed of an uneven region P. In this case, for example, as shown in Figure 9, after forming a conductive thin film E on the first and second end surfaces 11a, 11b and the first main surface 11e, a short-pulse laser L can be irradiated onto the entire first main surface 11e to form an uneven region P on the entire first main surface 11e.

[0130] Furthermore, the external electrodes 14a and 14b do not extend from the end faces 11a and 11b to the first main surface 11e, but may be formed only on the end faces 11a and 11b.

[0131] <Second Embodiment> Figure 17 shows a multilayer ceramic capacitor 10B according to a second embodiment of the present invention, and is a cross-sectional view of the position corresponding to Figure 2. In the following, components corresponding to the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0132] As shown in Figure 17, in the multilayer ceramic capacitor 10B according to this embodiment, in addition to the first main surface 11e, the second main surface 11f also has an uneven region P. Although not shown in the figure, the side surfaces 11c and 11d may also have an uneven region P, similar to the first embodiment.

[0133] As an example of a manufacturing method for the multilayer ceramic capacitor 10B, as shown in Figure 18, in step S04, a conductive thin film E is formed on the end faces 11a, 11b and the main faces 11e, 11f. Then, in step S05, a short-pulse laser is irradiated onto the main faces 11e, 11f to remove the conductive thin film E and to form an uneven region P.

[0134] In this embodiment, in step S04, the conductive thin film E may be formed on all six surfaces of the ceramic body 11, and in step S05, the main surfaces 11e, 11f and the side surfaces 11c, 11d may be irradiated with a short-pulse laser.

[0135] In this configuration, both main surfaces 11e and 11f have uneven regions P, which effectively suppresses conductivity between the external electrodes 14a and 14b on these surfaces. For example, when a multilayer ceramic capacitor 10B is mounted on a mounting substrate 110, condensation tends to remain on the upper main surface opposite to the mounting substrate 110. In contrast, in the multilayer ceramic capacitor 10, regardless of whether the first main surface 11e or the second main surface 11f is on the upper side, both main surfaces 11e and 11f have uneven regions P, which effectively suppresses the movement of condensation on the upper main surface in the X-axis direction. Therefore, according to the above configuration, the progress of migration between external electrodes can be more reliably slowed down, and the reliability of the multilayer ceramic capacitor 10 can be improved.

[0136] In the example shown in Figure 17, the main surfaces 11e and 11f each have a pair of electrode-forming regions S1 and an intermediate region S2, and the uneven region P is formed only in the intermediate region S2. Alternatively, as with the multilayer ceramic capacitor 10C shown in Figure 19, a region P may be formed on the entire surface of at least one of the main surfaces 11e, 11f, similar to the example shown in Figure 16.

[0137] <Third Embodiment> Figure 20 shows a multilayer ceramic capacitor 10D according to a third embodiment of the present invention, and is a cross-sectional view of the position corresponding to Figure 2.

[0138] As shown in Figure 20, in the multilayer ceramic capacitor 10D according to this embodiment, the external electrodes 14a and 14b have two types of undercoat films. Specifically, the external electrodes 14a and 14b have a conductive thin film 141 and a plating film 142 formed by a conductive thin film E, in addition to a conductive sintered film 143. The conductive sintered film 143 is formed on the end faces 11a and 11b and is configured, for example, as a film formed by baking a conductive paste.

[0139] Figure 21 is a flowchart of the manufacturing method according to this embodiment. As shown in the figure, the manufacturing method of the multilayer ceramic capacitor 10D according to this embodiment includes, in addition to steps S01 to S06 similar to those of the first embodiment, a conductive sintered film formation step in step S07 before the conductive thin film formation step in step S04.

[0140] In step S07, the conductive paste for forming the conductive sintered film 143 is applied, for example, to cover the end faces 11a and 11b, respectively, and to extend to parts of the main faces 11e and 11f and the side faces 11c and 11d. The method of applying the conductive paste is not particularly limited, and a dipping method, printing method, etc., can be appropriately selected. The conductive sintered film 143 is formed to be thicker than the conductive thin film 141 and is not easily sublimated by irradiation with a short-pulse laser, so it is not formed in the laser irradiation area.

[0141] In step S04, the conductive thin film E is formed on the end faces 11a, 11b and the connecting surface S including the first main surface 11e, and is also formed on the conductive sintered film 143. In step S05, similar to the first embodiment, the conductive thin film E is irradiated with a short-pulse laser L, thereby removing the conductive thin film E and forming an uneven region P on the connecting surface S including the first main surface 11e.

[0142] The manufacturing method in this embodiment is not limited to the example shown in Figure 21. For example, a conductive paste for the conductive sintered film 143 may be applied before step S03, and the ceramic body 11 and the conductive sintered film 143 may be fired simultaneously in step S03.

[0143] In this embodiment, the formation of a conductive sintered film 143 on the end faces 11a and 11b ensures that the external electrodes 14a and 14b are more reliably connected to the internal electrodes 12 and 13. Furthermore, this configuration also effectively suppresses conductivity between the external electrodes 14a and 14b while suppressing problems associated with the unevenness of the region P.

[0144] Figures 22 to 24 show multilayer ceramic capacitors 10E, 10F, and 10G according to modified examples of this embodiment, and are cross-sectional views at the position corresponding to Figure 2. As shown in Figure 22, in the multilayer ceramic capacitor 10E, a region P may be formed on the entire surface of the first main surface 11e, similar to the modified example of the first embodiment (Figure 16). Alternatively, as shown in Figure 23, in the multilayer ceramic capacitor 10F, in addition to the first main surface 11e, the second main surface 11f may also have an uneven region P, similar to the second embodiment (Figure 17). Alternatively, as shown in Figure 24, in the multilayer ceramic capacitor 10G, a rough region P may be formed on the entire surface of at least one of the main surfaces 11e and 11f, similar to the modified example of the second embodiment (Figure 19).

[0145] <Fourth Embodiment> In the above embodiment, an example was shown in which the recess P1 is formed along the Y-axis direction, but the invention is not limited to this, and the recess P1 may be formed along a direction intersecting the X-axis direction.

[0146] Figure 25 is a top view (plan view) of a multilayer ceramic capacitor 10H according to the fourth embodiment of the present invention, and shows the first main surface 11e. As shown in the figure, in the multilayer ceramic capacitor 10H, the recess P1 of the uneven region P is formed along the extending direction that intersects the X axis at an acute angle. This also makes it possible to increase the length of the contour of the first main surface 11e in the XZ cross-section between the external electrodes 14a and 14b, thereby suppressing conductivity between the external electrodes 14a and 14b.

[0147] Furthermore, in this configuration, the inner edge portion 144 facing the uneven region P of the external electrodes 14a and 14b is in contact with the recess P1 and the protrusion P2. Generally, the portion of the ceramic body 11 that is in contact with the inner edge portion 144 is prone to stress due to substrate distortion after mounting, and cracks tend to propagate along the inner edge portion 144. In contrast, in the above configuration, since the recess P1 and the protrusion P2 are in contact with the inner edge portion 144, cracks are less likely to propagate along the inner edge portion 144. Therefore, crack propagation in the ceramic body 11 and the resulting decrease in insulation resistance can be more effectively suppressed.

[0148] <Other Embodiments> Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. For example, embodiments of the present invention can be embodiments that combine the embodiments described above.

[0149] In the embodiments described above, an example was given in which a short-pulse laser is repeatedly scanned along a parallel direction. However, after repeated scanning along a parallel direction, the surface after scanning may be repeatedly scanned again along a direction intersecting that direction. This allows for the formation of recesses along the direction of the later scan, and more reliably prevents the retention of conductive thin films within the uneven regions.

[0150] In the above-described embodiment, an example was given in which the uneven region is formed by scanning with a short-pulse laser, but the method of forming the uneven region is not limited to this.

[0151] The present invention is applicable not only to multilayer ceramic capacitors but also to all multilayer ceramic electronic components having a ceramic body and first and second external electrodes. Examples of multilayer ceramic electronic components to which the present invention can be applied, other than multilayer ceramic capacitors, include chip varistors, chip thermistors, and multilayer inductors.

[0152] The multilayer ceramic electronic component according to the present invention is not limited to a configuration in which the dimension in the X-axis direction is larger than the dimension in the Y-axis direction; it may also be a configuration in which the dimension in the Y-axis direction is larger than the dimension in the X-axis direction. Furthermore, it may also be a configuration in which the dimension in the X-axis direction and the dimension in the Y-axis direction are the same.

[0153] The multilayer ceramic electronic component according to the present invention is not limited to a two-terminal type with two external electrodes, but may also be a multi-terminal type with three or more external electrodes. In this case, the direction in which external electrodes of different polarities face each other is defined as the second axis direction, and the surface of the ceramic body placed between these external electrodes is defined as the connection surface. If there are multiple directions in which external electrodes of different polarities face each other, one of these directions is defined as the second axis direction. The connection surface is then formed to include a plurality of recesses formed along the extending direction intersecting the second axis, recessed in the depth direction perpendicular to the second axis and the extending direction, and arranged along the arrangement direction perpendicular to the depth direction and the extending direction, as well as protrusions placed between the plurality of recesses, thereby forming a recessed region having the depth and arrangement pitch described above. This also effectively suppresses conductivity between external electrodes of different polarities and improves reliability. [Explanation of symbols]

[0154] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H Multilayer ceramic capacitors 11 Ceramic Body 11a,11b end face 11c,11d side 11e,11f Main surface 12,13 Internal electrode 14a,14b External electrode 141 Undercoat (Second Undercoat) 142 Plating film P Uneven area P1 recess P2 protrusion S connection surface S1 electrode formation area S2 intermediate area

Claims

1. A rectangular parallelepiped ceramic body having a plurality of internal electrodes stacked in the first axial direction via a ceramic layer, first and second end faces perpendicular to a second axis orthogonal to the first axial direction from which the plurality of internal electrodes are drawn, and four connecting surfaces connecting the first and second end faces and extending along the second axial direction, The first and second external electrodes are arranged on the first and second end faces respectively and face each other in the second axial direction, It is equipped with, At least one of the connection surfaces has a pair of electrode-forming regions covered by the first and second external electrodes, and an uneven region located between the first and second external electrodes. The aforementioned uneven region is A plurality of recesses are formed along the extending direction intersecting the second axis, recessed in the depth direction perpendicular to the second axis and the extending direction relative to the electrode formation region, and arranged along the arrangement direction perpendicular to the depth direction and the extending direction, Includes a convex portion disposed between the plurality of recesses, The depth of the recess in the depth direction is 0.1 μm or more and less than 2.5 μm. The arrangement pitch of the recesses along the arrangement direction is 1 μm or more and 80 μm or less. Multilayer ceramic electronic components.

2. A multilayer ceramic electronic component according to claim 1, The arrangement pitch of the recesses relative to the depth of the recesses is between 0.41 and 700 times. Multilayer ceramic electronic components.

3. A multilayer ceramic electronic component according to claim 1, The ratio of the arrangement pitch of the recesses to the depth of the recesses is 2.5 times or more and 80 times or less. Multilayer ceramic electronic components.

4. A multilayer ceramic electronic component according to claim 1, The dimension in the first axial direction is 110 μm or less. Multilayer ceramic electronic components.

5. A multilayer ceramic electronic component according to claim 1, At least one of the connecting surfaces having the uneven region is Extending along the second axial direction and the third axial direction perpendicular to the first and second axes Multilayer ceramic electronic components.

6. A multilayer ceramic electronic component according to claim 1, At least one of the connecting surfaces having the uneven region is It has a pair of electrode-forming regions covered by the first and second external electrodes, and an intermediate region between the pair of electrode-forming regions, The aforementioned uneven region is formed only in the intermediate region. Multilayer ceramic electronic components.

7. A multilayer ceramic electronic component according to claim 1, The first and second external electrodes are, respectively, A conductive thin film and a plating film formed on the conductive thin film, Multilayer ceramic electronic components.

8. A multilayer ceramic electronic component according to claim 7, The thickness of the conductive thin film is 1.0 μm or less. Multilayer ceramic electronic components.

9. A multilayer ceramic electronic component according to claim 7 or 8, The conductive thin film is composed of a sputtered film. Multilayer ceramic electronic components.

10. A multilayer ceramic electronic component according to claim 1, The direction of extension of the recess is perpendicular to the second axis. Multilayer ceramic electronic components.

11. A multilayer ceramic electronic component according to claim 1, The direction in which the recess extends intersects the second axis at an acute angle. Multilayer ceramic electronic components.

12. A multilayer ceramic electronic component according to claim 1, The arithmetic mean height Sa of the recess and the protrusion is 1.0 μm or less, respectively. Multilayer ceramic electronic components.

13. A multilayer ceramic electronic component according to claim 1, The maximum height Sz of the recess and the protrusion are 5.0 μm or less, respectively. Multilayer ceramic electronic components.

14. A multilayer ceramic electronic component according to claim 1, The absolute value of the difference in the arithmetic mean height Sa of the recess and the protrusion is 0.06 μm or less. Multilayer ceramic electronic components.

15. A multilayer ceramic electronic component according to claim 1, The absolute value of the difference between the maximum heights Sz of the recess and the protrusion is 4.0 μm or less. Multilayer ceramic electronic components.

16. Multilayer ceramic electronic components and A mounting substrate on which the aforementioned multilayer ceramic electronic components are mounted, It is equipped with, The aforementioned multilayer ceramic electronic component is A rectangular parallelepiped ceramic body having a plurality of internal electrodes stacked in the first axial direction via a ceramic layer, first and second end faces perpendicular to a second axis orthogonal to the first axial direction from which the plurality of internal electrodes are drawn, and four connecting surfaces connecting the first and second end faces and extending along the second axial direction, The first and second external electrodes are arranged on the first and second end faces, respectively, facing each other in the second axial direction, and connected to the mounting substrate, It has, Of the connection surfaces, at least one surface facing the mounting substrate has a pair of electrode-forming regions covered by the first and second external electrodes, and an uneven region located between the first and second external electrodes. The aforementioned uneven region is A plurality of recesses are formed along the extending direction intersecting the second axis, recessed in the depth direction perpendicular to the second axis and the extending direction relative to the electrode formation region, and arranged along the arrangement direction perpendicular to the depth direction and the extending direction, Includes a convex portion disposed between the plurality of recesses, The depth of the recess in the depth direction is 0.1 μm or more and less than 2.5 μm. The arrangement pitch of the recesses along the arrangement direction is 1 μm or more and 80 μm or less. Circuit board.

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