Pulse voltage source for plasma processing applications

Abstract

The present invention provides a waveform generator and method for a plasma processing system that plasma-processes a substrate in a processing chamber that provides a pulse voltage source for completing a desired plasma-assisted process on the substrate. [Solution] The waveform generator includes a first voltage stage 444. The first voltage stage includes a first voltage source (capacitive element 406), a first switch (combination of transistor 414, gate drive circuit 422, and trigger), an earth reference (node ​​N11), a transformer 470 having a first transformation ratio and including a primary winding 472 connected to the first voltage source and the earth reference, and a secondary winding 474 whose first end is connected to the earth reference and whose second end is connected to a load 426 through a common node, and a first diode D3 connected in parallel with the primary winding of the first transformer. The waveform generator also generally includes one or more additional voltage stages (second voltage stage 442, third voltage stage 440) connected to the load through a common node.

Description

[Technical Field]

[0001] Embodiments of this disclosure generally relate to systems used in semiconductor device manufacturing. More specifically, embodiments of this disclosure relate to plasma processing systems used for processing substrates. [Background technology]

[0002] Reliably fabricating high aspect ratio features is one of the key technical challenges in next-generation semiconductor devices. One method for forming high aspect ratio features is to use a plasma-assisted etching process to collide the material formed on the substrate surface with the material through openings formed within a patterned mask layer on the substrate surface.

[0003] As technology nodes advance towards 2nm, atomic-level precision is required in plasma processing to fabricate smaller features with larger aspect ratios. In etching processes where plasma ions play a major role, controlling the energy of ions has always been a challenge for the semiconductor equipment industry. In a typical plasma-assisted etching process, the substrate is placed on an electrostatic chuck (ESC) positioned in a processing chamber, plasma is formed on the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath (i.e., a region where electrons are drastically reduced) formed between the plasma and the substrate surface. Conventional radio frequency (RF) substrate biasing methods used sinusoidal RF waveforms to excite the plasma and form the plasma sheath, but they could not form the desired feature sizes for these small devices. Recently, it has been found that utilizing a pulsed plasma source that supplies high-voltage direct current (DC) pulses to one or more electrodes in the processing chamber may be useful for desirablely controlling the plasma sheath formed on the substrate surface.

[0004] Traditionally, pulsed power supplies have supplied a pulsed DC bias to the cathode (i.e., a metal plate that can be coupled to the plasma using capacitive coupling through a dielectric layer). When designing such pulsed power supplies, some of the key design considerations are switching frequency and power dissipation capability. MOSFETs are primarily used in pulsed power supplies to facilitate high-speed switching. However, despite significant advancements in the fields of SiC and GaN MOSFETs, the maximum operating switching frequencies of these MOSFETs are limited to tens to hundreds of kHz. As the semiconductor industry shrinks device dimensions to less than 10 nm, pulsed DC bias sources with switching frequencies in the upper half of the hundreds of kHz range could become a highly influential tool for further controlling critical high-aspect-ratio features such as etching selectivity and uniformity.

[0005] Therefore, in this field, there is a need for a pulsed voltage source and a biasing method that can complete a desirable plasma-assisted process on a substrate. [Overview of the project]

[0006] Embodiments provided herein generally include apparatus (e.g., plasma treatment systems) and methods for plasma treatment of substrates in a processing chamber.

[0007] Several embodiments relate to a waveform generator. This waveform generator generally includes a first voltage stage. This first voltage stage includes a first voltage source, a first switch, the first terminal of the first voltage source being connected to the first terminal of the first switch, a ground reference, the second terminal of the first switch being connected to the ground reference, a transformer having a first transformation ratio, the first transformer including a primary winding connected to the second terminal of the first voltage source and the ground reference, and a secondary winding having a first end and a second end, the first end of which is connected to the ground reference, and a first diode connected in parallel with the primary winding of the first transformer. This waveform generator also generally includes a second voltage stage. The second voltage stage comprises a second voltage source, a second switch, the first terminal of the second voltage source being connected to the first terminal of the second switch, a second ground reference, the second terminal of the second switch being connected to the second ground reference, and a second transformer having a second transform ratio, the second transformer including a primary winding connected to the second terminal of the second voltage source and the second ground reference, and a secondary winding having a first end and a second end, the first end being connected to the second end of the secondary winding of the first transformer and the second end being connected to a load through a common node, and a second diode connected in parallel with the primary winding of the second transformer.

[0008] Several embodiments relate to methods for waveform generation. These methods generally involve generating a first voltage pulse at a common node by closing a first switch having a first terminal and a second terminal, wherein the first terminal of the first switch is connected to a first terminal of a first voltage source, the second terminal of the first voltage source is connected to a first terminal of the primary winding of a first transformer having a first transformation ratio, the second terminal of the first switch is connected to a second terminal of the primary winding of the first transformer and to ground, and the common node is connected to a first terminal of the secondary winding of the first transformer. A method for waveform generation also generally involves generating a second voltage pulse at a common node by closing a second switch having a first terminal and a second terminal, wherein the first terminal of the second switch is connected to the first terminal of a second voltage source, the second terminal of the second voltage source is connected to the first terminal of the primary winding of a second transformer having a second transformation ratio, the second terminal of the first switch is connected to the second terminal of the primary winding of the second transformer and to ground, and a second bias voltage is generated by the second voltage source between the first and second terminals of the second voltage source, and the first terminal of the secondary winding of the second transformer is connected to the second terminal of the secondary winding of the first transformer, with the common node located between the first terminal of the secondary winding of the first transformer and the load.

[0009] Some embodiments relate to a non-transient computer-readable medium for generating waveforms containing instructions executable by one or more processors. The instructions generally include generating a first voltage pulse at a common node by closing a first switch having a first terminal and a second terminal, wherein the first terminal of the first switch is connected to a first terminal of a first voltage source, the second terminal of the first voltage source is connected to a first terminal of the primary winding of a first transformer having a first transformation ratio, the second terminal of the first switch is connected to a second terminal of the primary winding of the first transformer and to ground, and the common node is connected to a first terminal of the secondary winding of the first transformer. The instruction also generally involves generating a second voltage pulse at a common node by closing a second switch having a first terminal and a second terminal, wherein the first terminal of the second switch is connected to the first terminal of a second voltage source, the second terminal of the second voltage source is connected to the first terminal of the primary winding of a second transformer having a second transformation ratio, the second terminal of the first switch is connected to the second terminal of the primary winding of the second transformer and to ground, and a second bias voltage is generated by the second voltage source between the first and second terminals of the second voltage source, and the first terminal of the secondary winding of the second transformer is connected to the second terminal of the secondary winding of the first transformer, with the common node located between the first terminal of the secondary winding of the first transformer and the load.

[0010] To gain a more detailed understanding of the features of this disclosure described above, a more detailed description of this disclosure, which is briefly summarized above, can be obtained by referring to the embodiments. Some embodiments are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered to limit the scope of this disclosure, as other equally valid embodiments are also permissible. [Brief explanation of the drawing]

[0011] [Figure 1]This is a schematic cross-sectional view of one or more embodiments of a processing system configured to carry out the methods described herein. [Figure 2] This shows the stray capacitance and substrate support capacitance related to the processing chamber. [Figure 3] A to C show examples of voltage waveforms that may be provided during plasma processing. [Figure 4] A schematic diagram of a pulser according to a specific embodiment of this disclosure is shown. [Figure 5A] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 5B] This is a graph showing the output provided by the pulser during the operating mode shown in Figure 5A, according to a particular embodiment of the present disclosure. [Figure 6] A simplified schematic diagram of the pulser's operating modes according to a specific embodiment of this disclosure is shown. [Figure 7A] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 7B] This is a graph showing the output provided by the pulser during the operating mode shown in Figure 7A, according to a particular embodiment of the present disclosure. [Figure 8A] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 8B] This is a graph showing the output provided by the pulser during the operating mode shown in Figure 8A, according to a particular embodiment of the present disclosure. [Figure 9A] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 9B] This is a graph showing the output provided by the pulser during the operating mode shown in Figure 9A, according to a particular embodiment of the present disclosure. [Figure 10A] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 10B]This is a graph showing the output provided by the pulser during the operating mode shown in Figure 10A, according to a particular embodiment of the present disclosure. [Figure 11A] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 11B] This is a graph showing the output provided by the pulser during the operating mode shown in Figure 11A, according to a particular embodiment of the present disclosure. [Figure 11C] This is a graph showing the switch state of a pulser in various operating modes according to a specific embodiment of the present disclosure. [Figure 11D] Figure 11C is a graph showing the output provided by the pulser during the operating mode shown in a particular embodiment of the present disclosure. [Figure 12] A charging circuit used to charge a capacitive element is shown according to a particular aspect of this disclosure. [Figure 13] This is a process flow diagram illustrating a waveform generation method according to a specific embodiment of the present disclosure. [Modes for carrying out the invention]

[0012] For ease of understanding, the same reference numerals have been used to indicate identical elements common to multiple figures, where possible. It is assumed that components and features of one embodiment can be usefully incorporated into other embodiments without further description.

[0013] Certain aspects of this disclosure generally relate to techniques for generating voltage waveforms for plasma processing systems. Conventionally, pulsed power supplies provide pulsed DC bias to a cathode (metal plate) coupled to the plasma through a dielectric layer. Some of the key design considerations when designing such pulsed power supplies are switching frequency and power dissipation capability. MOSFETs are primarily used in pulsed power supplies to facilitate high-speed switching. However, despite significant advances in the fields of SiC and GaN MOSFETs, the maximum operating switching frequencies of these MOSFETs are limited to tens to hundreds of kHz. In the semiconductor industry, as device dimensions shrink to less than 10 nm, pulsed DC bias sources with switching frequencies in the upper half of the hundreds of kHz range may be a highly influential tool for further control over important high aspect ratio features such as etching selectivity and uniformity.

[0014] In embodiments of this disclosure, a pulse power supply (e.g., a waveform generator) may include multiple stacked modules, enabling greater flexibility in different characteristics of the generated waveforms. In some embodiments, the waveform generator can be tuned to generate configurable output voltage waveforms for various applications and their respective requirements, which may include various characteristics such as current, voltage, switching frequency (e.g., pulse frequency), pulse width, peak amplitude, pulse shape, and other requirements. In this way, the waveform generator may be able to better control important high-aspect characteristics, including etching selectivity and uniformity. In some embodiments, the waveform generator may mask limitations of certain components, such as the maximum operating switching frequency or maximum voltage of transistors commonly available in semiconductor switches commonly used in waveform generation, in order to better control important high-aspect features, including improved etching selectivity, uniformity, and overall (throughout) in the processing system 10. Thus, the waveform generator may be able to generate voltage waveforms having a desired energy distribution function (IEDF) on the substrate surface.

[0015] Examples of plasma treatment systems Figure 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. However, it should be noted that the embodiments described herein can be used with processing systems configured to be usable in other plasma-assisted processes such as plasma-enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD)), plasma processing processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD)).

[0016] As shown in the figure, the processing system 10 is configured to form a capacitively coupled plasma (CCP), and the processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) located in the processing space 129, opposite a lower electrode (e.g., a substrate support assembly 136) located in the processing space 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., an RF generator 118) is electrically coupled to one of the upper or lower electrodes and supplies an RF signal. This RF signal is configured to ignite and maintain a plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to the upper and lower electrodes, respectively, and located within the processing region between them. Typically, one of the opposing upper or lower electrodes is connected to ground or a second RF power source. One or more components of the substrate support assembly 136, such as the support base 107, are electrically connected to the plasma generator assembly 163, which includes the RF generator 118, and the chamber lid 123 is electrically connected to ground. As shown in the figure, the processing system 10 includes the processing chamber 100, the substrate support assembly 136, and the system controller 126.

[0017] The processing chamber 100 typically includes a chamber body 113, which includes a chamber lid 123, one or more side walls 122, and a chamber base 124, collectively defining a processing space 129. The one or more side walls 122 and the chamber base 124 generally include a material sized to form structural supports for the elements of the processing chamber 100, and configured to withstand the pressure and additional energy applied while plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. In one embodiment, the one or more side walls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0018] A gas inlet 128, positioned to penetrate the chamber lid 123, is used to supply one or more processing gases to the processing space 129 from a processing gas source 119, which is in fluid communication with the gas inlet 128. The substrate 103 enters and exits the processing space 129 through one or more openings (not shown) in the sidewalls 122. The openings in one or more sidewalls 122 are sealed by slit valves (not shown) during plasma processing of the substrate 103.

[0019] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence (including the substrate biasing method described herein) used to process the substrate 103. The CPU 133 is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated subprocessors. The memory 134, generally non-volatile memory, may include random-access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuitry 135 is conventionally connected to the CPU 133 and includes caches, clock circuits, input / output subsystems, power supplies, and combinations thereof. Software instructions (programs) and data may be coded and stored in memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are executable by the components in the processing chamber 10.

[0020] Typically, a program readable by the CPU 133 in the system controller 126 includes code. When executed by the CPU 133, this code performs tasks relating to the plasma processing scheme described herein. The program may also include instructions. These instructions are used to control various hardware and electrical components within the processing chamber 10 to perform various process tasks and various process sequences used to carry out the methods described herein. In one embodiment, the program includes instructions used to perform one or more of the steps described later in relation to Figure 13.

[0021] The processing system may include a plasma generator assembly 163, a first pulsed voltage (PV) source assembly 196 for establishing a first PV waveform on the bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform on the edge control electrode 115. The first or second PV waveform may be generated using a waveform generator, which is described in detail herein with reference to Figures 4-11. In some embodiments, the plasma generator assembly 163 supplies an RF signal to the support base 107 (e.g., a power electrode or cathode). This RF power signal may be used to generate (maintain and / or ignite) plasma 101 in a processing area located between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency of 1 MHz or more, or about 2 MHz or more (e.g., about 13.56 MHz or more).

[0022] As described above, in some embodiments, the plasma generator assembly 163, which includes an RF generator 118 and an RF generator assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal frequency, based on a control signal supplied from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107, which is located in close proximity to the substrate support 105 and within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain the plasma 101 of the processing gas located in the processing space 129.

[0023] In some embodiments, the support base 107 is an RF electrode electrically coupled to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, which are located together within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical elements. These one or more electrical elements are configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator P1 in the PV waveform generator 150, and thus obstructs the flow of current to the RF matching circuit 162 and the RF generator 118.

[0024] In some embodiments, an RF generator assembly 160 and an RF generator 118 are used to ignite and maintain the plasma 101 using an electromagnetic field generated by a processing gas placed in the processing space 129 and RF power (RF signal) supplied to the support base 107 by the RF generator 118. The processing space 129 is fluidly connected to one or more dedicated vacuum pumps through a vacuum outlet 120, which maintains the processing space 129 in a near-atmospheric state and exhausts the processing gas and / or other gases from there. In some embodiments, a substrate support assembly 136 placed in the processing space 129 is positioned on a support shaft 138. The support shaft 138 is grounded and extends through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to supply RF power to a bias electrode 104 located within the substrate support 105 and facing the support base 107.

[0025] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107, as briefly described above. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a grounding plate 112, as will be further described later. The support base 107 is electrically insulated from the chamber base 124 by the insulating plate 111, and the grounding plate 112 is placed between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and positioned on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature between the substrate support 105 and the substrate 103 placed on the substrate support 105 during substrate processing.

[0026] Typically, the substrate support 105 is formed from a dielectric material (e.g., a bulk sintered ceramic material such as a corrosion-resistant metal oxide material or a metal nitride material), which is, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 within a processing area on the bias electrode 104 are determined and / or monitored by measuring the RF waveform established at the bias electrode 104.

[0027] In one configuration, the bias electrode 104 is a chucking pole used to fix (chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 to the plasma 101 using one or more of the pulsed voltage bias schemes described herein. Typically, the bias electrode 104 is formed from one or more conductive components (e.g., one or more metal meshes, foils, plates, or a combination thereof).

[0028] In some embodiments, the bias electrode 104 is electrically connected to a clamp network 116. The clamp network 116 supplies a chucking voltage (e.g., a static DC voltage) between approximately -5000V and approximately 5000V to the bias electrode 104 using an electrical conductor such as a coaxial transmission line 106 (e.g., a coaxial cable). Further as described below, the clamp network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor (also referred to herein as blocking capacitor C5). The blocking capacitor C5 is located between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0029] The substrate support assembly 136 may further include an edge control electrode 115 positioned below the edge ring 114, surrounding the bias electrode 104, and / or positioned at a certain distance from the center of the bias electrode 104. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, as shown in Figure 1, the edge control electrode 115 is positioned within a region of the substrate support 105. In some embodiments, as shown in Figure 1, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned at a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 to the bias electrode 104. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned on or within a region of the quartz tube 110 surrounding at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is located within or connected to an edge ring 114. The edge ring 114 is located on and adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AlN).

[0030] The edge control electrode 115 can be biased using a PV waveform generator 150 different from the PV waveform generator 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased using a PV waveform generator 150 that is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of a second PV source assembly 197 is configured to bias the edge control electrode 115.

[0031] The power supply line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 to an optional filter assembly 151 and bias electrode 104. In the following discussion, we will mainly describe the power supply line 157 of the first PV source assembly 196 used to connect the PV waveform generator 150 to the bias electrode 104, but the power supply line 158 of the second PV source assembly 197, which connects the PV waveform generator 150 to the edge control electrode 115, will contain the same or similar components. One or more electrical conductors in the various parts of the power supply line 157 include: (a) a single coaxial cable or combination of coaxial cables (e.g., a flexible coaxial cable connected in series with a rigid coaxial cable), (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements of (a) to (e). The optional filter assembly 151 includes one or more electrical elements. These one or more electrical elements are configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power supply line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118, thereby suppressing the flow of current to the PV waveform generator 150.

[0032] The second PV source assembly 197 includes a clamp network 116, so that the bias applied to the edge control electrode 115 can be configured similarly to the bias applied to the bias electrode 104 by the clamp network 116 connected within the first PV source assembly 196. By applying similarly configured PV waveforms and clamp voltages to the bias electrode 104 and the edge control electrode 115, the plasma uniformity across the substrate surface during processing can be improved, thereby improving the results of the plasma processing process.

[0033] In some embodiments, the processing chamber 100 further includes a quartz tube 110 or collar. The quartz tube 110 or collar at least partially surrounds a portion of the substrate support assembly 136, thereby preventing the substrate support 105 and / or support base 107 from coming into contact with corrosive processing gases or plasma, cleaning gases or plasma, or their byproducts. Typically, the quartz tube 110, insulating plate 111, and grounding plate 112 are surrounded by a cathode liner 108. In some embodiments, a plasma screen 109 is positioned between the cathode liner 108 and a side wall 122 to prevent plasma from forming in the space below the plasma screen 109 between the cathode liner 108 and one or more side walls 122.

[0034] Exemplary representative circuit of the processing chamber Figure 2 shows the stray capacitance and escape capacitance related to the processing chamber. Stray capacitance 204(C stray ) represents the capacitance between the electrode of the processing chamber and ground, and the substrate support capacitance 202 is, in this specification, the electrostatic chuck capacitance (C esc Also known as ), it represents the capacitance between the bias electrode 104 and the substrate support surface 105A. As shown in the figure, C esc The output node (U out (displayed as) is generated between the composite load (e.g., plasma load) simply represented by the resistive element 206. (e.g., node U)load To make the shape of the voltage pulse (in ) square, as will be described in more detail herein, a slope is implemented with respect to the voltage across C esc and the voltage across C stray (for example, the voltage at U out ). A slope is implemented with respect to the voltage across C stray (for example, the compensation current (I comp )) such that it can be equal to the load current (I esc ) across C load multiplied by the ratio of the capacitance of C stray to the capacitance of C esc . The output current (I out ) can be equal to the sum of I load and I comp . This can be expressed by the following equation. TIFF2026097785000002.tif10170

[0035] Exemplary voltage waveform for the processing chamber FIG. 3A shows an example of a voltage waveform that can be supplied to an electrode disposed within a processing chamber, such as the bias electrode 104 shown in FIG. 1. The waveform generally includes two main stages: an ion current stage and a sheath collapse stage. At the beginning of the ion current stage, a high voltage sheath is formed above the substrate due to a decrease in the wafer voltage, and positive ions are accelerated towards the substrate 103. The positive ions tend to deposit positive charges on the substrate surface and gradually increase the substrate voltage positively. When a square wave is supplied, a positive slope occurs in the substrate voltage due to the ion current towards the substrate (for example, at U load shown in FIG. 2). As shown in FIG. 3C, a negative slope is implemented with respect to the voltage at U load (at the load) such that the shape of the voltage pulse is square, as shown in FIG. 3A. As shown in FIG. 3B, it is used to form a voltage across the electrostatic chuck capacitance element C out . FIG. 3C shows an example of a desired voltage waveform that can be established on a substrate disposed on a substrate support assembly 136 disposed within the processing chamber 100. During the ion current stage, between the bias electrode 104 and the electrostatic chuck capacitor C esc esc ​Implementing a slope is generally called current compensation, and during this stage U load It is used to form a constant voltage as seen. The voltage difference between the start and end of the ion current phase determines the width of the ion energy distribution function (IEDF). The larger the voltage difference, the wider the ion energy distribution, and therefore the wider the IEDF. To achieve single-energy ions and a narrow IEDF width, a current compensation operation is performed to flatten the substrate voltage waveform during the ion current phase. In some embodiments, the voltage waveform has a frequency (1 / T) between approximately 50 kHz and 1000 kHz. p ) can be supplied. In some embodiments, the voltage waveform established at the electrode has an on-time, which is the ion current period (e.g., the length of the ion current stage) and the waveform period T P It is defined as the ratio of (for example, the length of the sheath collapse stage + the length of the ion current stage) and is greater than 50% or greater than 70%, for example between 80% and 95%. In some embodiments, the waveform period is period T P A voltage waveform having a duration of approximately 2.5 microseconds (μs) is continuously repeated within a waveform burst having a burst period between approximately 100 μs and approximately 10 milliseconds (ms). The burst of the PV waveform can have a burst duty cycle between approximately 5% and 100% (e.g., between approximately 50% and approximately 95%), where the duty cycle is the ratio of the burst period to the sum of the burst period and the non-burst period separating the burst periods (i.e., the period during which no PV waveform is generated). As shown, the sheath collapse stage can be approximately 200 ns. SH It may have a duration of [this].

[0036] Example of a waveform generator Figure 4 shows a pulser 400 (also referred to herein as a waveform generator) according to a particular embodiment of the present disclosure. In some embodiments, the pulser 400 may be contained within a power supply (e.g., PV waveform generator 150). As shown, the pulser 400 may include several stacked inductive adder modules (e.g., 440, 442, 444), pulse capacitive elements 402, 404, 406 (indicated as C1, C2, C3, C4), and transistors 410, 412, 414 (indicated as Q1, Q2, Q3). Transistors 410, 412, and 414 may be power transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) with parallel diodes (e.g., body diodes D1, D2, and D3). Each transistor 410, 412, and 414 may function as a switch, which is sometimes referred to herein as a switch. In some embodiments, transistors 410, 412, and 414 may be mounted on a printed circuit board. Capacitive elements 402, 404, and 406 may function as voltage storage elements that can be charged using a charging circuit such as the one shown in Figure 12. In some embodiments, transistors 410, 412, and 414 may each be coupled to gate drive circuits 418, 420, and 422. Each gate drive circuit 418, 420, and 422 has a trigger that can receive a signal from the system controller 126 to be activated or deactivated, thereby setting the gate state in each transistor 410, 412, and 414. The capacitive elements shown in Figures 4, 6, and 12 act substantially as voltage sources. The exemplary pulser 400 illustrates the capacitive elements for ease of understanding, but any suitable voltage source may be used.

[0037] Resistor 424 (indicated as R1) represents an internal series resistor of the pulser connected to the load 426. The composite load 426, which may be formed by the plasma formed in the plasma processing chamber, may be represented by a capacitive element 428 (indicated as C4) and a resistive element 430 (indicated as R2). As shown in the figure, the capacitive element 406 and transistor 414 form a first voltage stage 444 (e.g., a module), and the capacitive element 404 and transistor 412 form a second voltage stage 442 (e.g., a module). Pulsar 400 also includes a third voltage stage 440 (e.g., a module) having a capacitive element 402 and transistor 410. The output of pulser 400 is connected to a common node 480 which is connected (e.g., capacitively coupled) to the composite load 426. Pulsar 400 is implemented with three voltage stages, but embodiments of the present disclosure may be implemented with one, two, or three or more voltage stages. In some embodiments of the pulser 400, one or more voltage stages may be duplicated once or multiple times, such as in a configuration including a first voltage stage 444, two or more second voltage stages 442, and a third voltage stage 440.

[0038] In some embodiments, the common node 480 and load 426 are configured to be capacitively coupled to the support base 107 by supplying RF power supplied to the support base 107 by the RF generator 118. In some embodiments, the common node 480 may be configured to be capacitively coupled to the cathode RF feed provided through node 190 (Figure 1). During plasma processing, the plasma 101 will act as a combined load 426.

[0039] In some embodiments, as shown in Figure 4, the pulser 400 may include a first voltage stage 444. The first voltage stage 444 has a first switch (e.g., a combination of a transistor 414, a gate drive circuit 422, and a trigger) having a first terminal connected to a first terminal of a first voltage source (e.g., a capacitive element 406) at node N9. The second terminal of the first switch is connected to an earth reference at node N11. The first voltage stage 444 may further include a first transformer 470. This first transformer 470 comprises a core 476, a primary winding 472 connected to a second terminal of the first voltage source 406 at node N10, and a secondary winding 474 having a first end connected to a first earth reference via node N12. The primary winding of the first transformer is also connected to an earth reference at node N11. The first voltage stage 444 may further include a first diode D3 in parallel with the primary winding 472 of the first transformer 470. The first end of diode D3 may be connected to the second terminal and primary winding of the first voltage source 406 at node N10. The second end of diode D3 may be connected to the first terminal and primary winding of the first switch 414 via node N12. The first transformer may have a first transformation ratio. The ratio of the transformer is the number of primary turns (W) of the primary winding 472. p ) and the number of secondary turns of the secondary winding 474 (W s It is the relative ratio of ). The transformation ratio (i.e., W p :W s ) is a step-up transformer (i.e., W s >W p ) or step-down transformer (i.e., W s <W p It generates one of the following:

[0040] In some embodiments, as shown in Figure 4, the pulser 400 may include a second voltage stage 442. The second voltage stage 442 has a second switch (e.g., a combination of a transistor 412, a gate drive circuit 420, and a trigger) having a first terminal connected to a first terminal of a second voltage source (e.g., a capacitive element 404) at node N5. The second terminal of the second switch is connected to a second earth reference at node N7. The second voltage stage 442 may further include a second transformer 460. This second transformer 460 comprises a core 466, a primary winding 462 connected to a second terminal of the second voltage source 404 at node N6, and a first end of the secondary winding 464 connected to a second end of the secondary winding 474 of the first transformer 470. The primary winding of the second transformer 460 is also connected to an earth reference at node N7. The second voltage stage 442 may further include a second diode D2 in parallel with the primary winding 462 of the second transformer 460. The first end of diode D2 may be connected to the second terminal and primary winding of the second voltage source 404 at node N6. The second end of diode D2 may be connected to the first terminal and primary winding of the second switch 412 via node N8. The second transformer 460 may have a second transformation ratio as described above. In some embodiments of the pulser 400, such as configurations in which only two voltage stages (i.e., voltage stages 442 and 444) exist, the second end of the secondary winding 464 of the second transformer 460 may be configured to be connected via a common node 480 to an electrode located in the processing chamber 100, such as a bias electrode 104.

[0041] In some embodiments, as shown in Figure 4, the pulser 400 may include a third voltage stage 440. The third voltage stage 440 has a third switch (e.g., a combination of a transistor 410, a gate drive circuit 418, and a trigger) having a first terminal connected to a first terminal of a third voltage source (e.g., a capacitive element 402) at node N1. The second terminal of the third switch is connected to a third earth reference at node N3. The third voltage stage 440 may further include a third transformer 450. This third transformer comprises a core 456, a primary winding 452 connected to a second terminal of the third voltage source 402 at node N2, and a secondary winding 454 having a first end connected to a second end of the secondary winding 464 of the second transformer 460. The primary winding of the third transformer is also connected to an earth reference at node N3. The third voltage stage 440 may further include a third diode D1 in parallel with the primary winding 452 of the third transformer 450. The first end of diode D1 may be connected to the second terminal and primary winding of the third voltage source 402 at node N2. The second end of diode D1 may be connected to the first terminal and primary winding of the third switch 410 via node N4. The third transformer may have a third transformation ratio as described above. In some embodiments of the pulser 400, as shown in Figure 4, the second end of the secondary winding 454 of the third transformer 450 may be configured to be connected through a common node 480 to an electrode located in the processing chamber 100, such as a bias electrode 104.

[0042] In some embodiments, cores (e.g., 456, 466, 476) used within transformers 450, 460, 470 of modules 440, 442, 444 of the pulser 400 are used to modulate the possible output waveforms of the pulser 400. The characteristics of the cores (e.g., 456, 466, 476) define the maximum allowable switching frequency and pulse width of the output waveforms that can be created by the pulser 400. Some of the characteristics of the cores (e.g., 456, 466, 476) that may affect the output waveforms created by the pulser 400 include magnetic saturation flux density, flux swing, residual flux density, cross-sectional area, volume, and weight. In some embodiments, each of the cores (e.g., 456, 466, 476) has a saturation magnetic flux density between 1.4 Tesla (T) and 1.8 T, a magnetic flux swing between 2.4 T and 3.6 T, a residual magnetic flux density between 0.2 T and 0.8 T, and a magnetic field of 6 square centimeters (cm²). 2 ) and 9cm 2 The cross-sectional area between 2 kg and 4 kg, the weight between 2 kg and 4 kg, and 700 cubic centimeters (cm²). 3 ) and 1500cm 3 It has at least one of the volumes between [the specified volume] and [the specified volume].

[0043] In some embodiments, different cores (e.g., 456, 466, 476) may be used for different modules 440, 442, and 444 of the pulser 400 to customize the characteristics of the output waveform. In some embodiments, each module 440, 442, and 444 has its own ground reference. In some embodiments, the first, second, and third transform ratios of each transformer 450, 460, and 470 are the same. In other embodiments, one or more transformers in the pulser 400 have different transform ratios than other transformers in other stages of the pulser 400. Furthermore, having each module as a ground reference can also reduce dielectric breakdown between gate drive circuits at higher voltages (such as arc discharge), which is a problem in certain conventional pulser designs. In some embodiments, the output of each module 440, 442, and 444 is connected to the same ground reference as the gate drive circuit input, so that the pulser 400 may be less susceptible to electromagnetic interference during operation.

[0044] In some embodiments, the transformation ratio of the first transformer (i.e., the first transformation ratio) may be the same as the transformation ratio of the second transformer (i.e., the second transformation ratio). In other embodiments, the transformation ratio of the first transformer may be different from the transformation ratio of the second transformer. For example, the first transformation ratio may be smaller than or larger than the second transformation ratio. In some embodiments, the transformation ratio of the third transformer (i.e., the third transformation ratio) may be the same as the transformation ratios of the first and second transformers. In other embodiments, the transformation ratio of the third transformer may be different from the transformation ratios of the first and second transformers. The combination of transformation ratios between the transformers of each voltage stage 440, 442, 444 (e.g., module) may be arbitrary. The transformer ratios can be changed to customize the output voltage waveform of Pulser 400 with different voltages and pulse widths. Each module 440, 442, and 444 can supply pulses. Each pulse seen at the common node 480 depends on the voltage and transformer ratio stored in the capacitors 402, 404, and 406 of each module. By triggering with varying transformer ratios of multiple modules of Pulser 400, the shape and pulse width of the output signals generated in the secondary windings of the modules can be changed to match the desired IEDF. In some embodiments, each transformer (e.g., 450, 460, 470) of the voltage stages 440, 442, and 444 (e.g., modules) is connected in series.

[0045] As shown, each capacitive element 402, 404, and 406 can be charged to a specific voltage depending on the characteristics of the waveform being implemented. The transistors, gate drive circuits, and triggers of each module 440, 442, and 444 can act as switches controlled by the system controller 126. For example, each capacitive element 402, 404, and 406 is charged to 800 volts when the gate drive circuit and the triggers in each module 440, 442, and 444 (e.g., transistors 410, 412, and 414) act as closed switches. In some embodiments, the capacitive elements 402, 404, and 406 can be charged to higher or lower voltages to implement different voltage levels for waveforms suitable for different embodiments. In some embodiments, each voltage stage 440, 442, and 444 may have a module design that is easily replaceable in case of failure. The operation of the pulser 400 for generating the waveform shown in Figure 3A will be described in more detail with reference to Figures 6 to 11.

[0046] Example of a generated voltage waveform In some embodiments, transistors 410, 412, and 414 can be triggered by gate signals at different time instances to increase the switching frequency and address the limited switching frequency of commercially available transistors in supplying voltage pulses for various processing applications, such as plasma etching. In this way, output voltages can be obtained at different timestamps, thereby increasing the effective switching frequency at the output (e.g., common node 480) and effectively circumventing the switching frequency limitations of typical commercially available transistors. In some embodiments, some parameters of the gate signals applied to transistors 410, 412, and 414 can be modified. For example, the start time and / or width of the trigger gate signal can be modified to generate output voltages with different waveform characteristics, as illustrated and described herein. In some embodiments, multiple different DC power modules enabling output voltages with different amplitudes at electrodes in the processing chamber 100 may be coupled to modules 440, 442, and 444, capacitively coupled to a composite load 426 at a common node 480 coupled to a bias electrode 104, for example. In some embodiments, varying the duty cycle ratio between modules 440, 442, and 444 can result in output voltages with different peak amplitudes within the pulse. Furthermore, gate signals applied to modules 440, 442, and 444 can be triggered in a manner that causes overlap in the generated voltage waveforms. This can help enable a more favorable IED (Input-Effective Field Definition) of the output waveform.

[0047] Figure 5A is a graph showing the state of the switches (e.g., transistors 410, 412, 414) and the generated voltage of the pulser 400 during an operating mode according to a particular embodiment of the present disclosure. The magnitudes of the voltages associated with the various operating modes and circuit elements shown in Figures 5 to 11D are intended to provide examples of voltages that can be established during pulse waveform generation and are not intended to limit the scope of the disclosure provided herein. Graph 500A shows the state of transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) when a gate signal (e.g., a trigger) is applied simultaneously to the respective gate drive circuits 418, 420, and 422 (e.g., gate drive 418 triggers transistor 410, gate drive 420 triggers transistor 412, and gate drive 422 triggers transistor 414). The applied gate signal is a Transistor-Transistor Logic (TTL) signal and may be between 1.5V and 5V. In some embodiments, the system controller 126 may control the application of gate signals to gate drive circuits 418, 420, and 422 to activate transistors 410, 412, and 414 of modules 440, 442, and 444. In graph 500A of Figure 5A, a gate signal (e.g., V1) is applied simultaneously to each module 440, 442, and 444 (e.g., between times T1 and T2), and each module generates pulse triggers TR1, TR2, and TR3. Module 440 generates pulse TR1, module 442 generates pulse TR2, and module 444 generates pulse TR3. Graph 500B, shown in Figure 5B, shows the voltage (e.g., V2) observed at the common node 480 between times T1 and T2 as a result of the generated pulses P1, P2, and P3. The pulses may be repeated between intervals T3 and T4, as shown in the figure. By simultaneously triggering multiple modules of Pulsar 400, an increase in the output voltage of the common node 480 (e.g., the voltage at load 426) can be tolerated.For example, if each module of the pulser generates a 1200V pulse on the secondary winding of each transformer 450, 460, and 470, the voltages of the simultaneous pulses P1, P2, and P3 will be added together, resulting in a voltage of 3600V at the electrode connected to the common node 480.

[0048] Figure 6 shows a further simplified schematic diagram of the pulser 400 shown in Figure 4, illustrating an example of an operating mode of the pulser 400 according to a particular embodiment of this disclosure. The operating modes and circuit elements shown in Figure 6 illustrate an example of how different voltages may be established at different times during pulse waveform generation and are therefore not intended to limit the scope of the disclosure provided herein. Other embodiments may include other combinations of modules 440, 442, and 444 that are triggered simultaneously or at different times in their respective gate drive circuits 418, 420, and 422 to generate desired voltages at a common node 480 at different times during processing. In the example shown in Figure 6, transistors 410, 412, and 414 are represented by switches and function as switches. In this example, only the gate drive 418 of module 440 is triggered by a gate signal command provided by the system controller 126, resulting in the closing of the switch representing transistor 410. In this example, the gate drive circuit 420 of the second module 442 and the gate drive circuit 422 of the third module 444 are not triggered by gate signal commands provided by the system controller 126, and therefore the switches representing transistors 412 and 414 remain open.

[0049] Figure 7A is a graph showing the state of transistor 410 (e.g., Q1) of pulser 400 during the operating mode shown in the schematic configuration shown in Figure 6, according to a particular embodiment of the present disclosure. In Figures 5A, 5B, and 7A to 9B, V1 represents the gate signal, which may be a TTL signal (e.g., between 1.5V and 5V). V2 represents the output voltage, which may be adjusted as described herein. As described above, when a switching signal (e.g., the gate signal) is applied, the switch (e.g., transistor 410) closes, enabling pulse generation. Graph 700A in Figure 7A shows the state of transistor 410 when the gate signal is applied to the transistor by the gate drive circuit 418 (e.g., between times T1 and T2). In Graph 700A, a gate signal (e.g., V1) is applied to the gate drive circuit 418 of module 440 as a trigger pulse TR1, and therefore only the triggered module 440 generates pulse P1, which is shown in Figure 700B. Graph 700B, shown in Figure 7B, shows the voltage (e.g., V2) seen at the common node 480 between times T1 and T2 as a result of the voltage pulse P1 generated by module 440. In contrast to the above example where multiple modules of pulser 400 are triggered simultaneously, triggering only a single module generates a smaller output voltage because the other modules do not generate pulse voltages simultaneously. When multiple modules are generating pulse voltages simultaneously, the generated pulses are added together by the series connection of the secondary windings of each module, which extend from ground connected at node N11 to the common node 480. Therefore, in some embodiments, a pulser using multiple modules simultaneously may be able to generate higher pulses than a pulser using only a single module. As shown in Figure 7B, the pulses may be repeated between intervals T3 and T4. For example, if each module of the pulser is configured to generate a 1200V pulse in the secondary winding connected to each module, then in this example, only 1200V will be seen at the common node 480 because only one module (e.g., module 440) is instructed to generate the pulse.

[0050] Figure 8A is a graph showing the state of switches (e.g., transistors 410, 412, 414) as a function of time, used to generate voltage pulses from pulser 400 during another example of operating modes, according to a particular embodiment of the present disclosure. Graph 800A shows the state of each of transistors 410, 412, 414 (e.g., Q1, Q2, Q3) when gate signals are applied to each of the respective gate drive circuits 418, 420, 422 at different times. In some embodiments, the system controller 126 may control the application of gate signals to each of the gate drive circuits 418, 420, 422 to activate each of the transistors 410, 412, 414 of module 440, 442, 444 at desired times within the pulsed sequence. In Graph 800A, the gate signal (e.g., V1) is first applied to module 440 to generate pulse trigger TR1 between times T1 and T2, then to module 442 to generate pulse trigger TR2 between times T3 and T4, and finally to module 444 between times T5 and T6 to generate trigger TR3. Graph 800B, shown in Figure 8B, shows the voltage (e.g., V2) seen at the common node 480 as a result of the voltage pulses P1, P2, and P3 generated during each time interval. When multiple modules of pulser 400 are triggered consecutively, an increase in the frequency of the output voltage may be permitted. The pulses are as shown, with intervals T7-T8, T9-T 10 , T 11 ~T 12This can be repeated during the interval. In some embodiments, by sequentially supplying pulses from each module in the pulser, the pulse frequency (F1) provided by the pulser 400 can achieve an output pulse frequency that masks the limitations of the switching hardware frequency (F2) found in each module. This is because the hardware of each module only needs to supply a pulse at its place in the pulse sequence (e.g., every three pulses in the sequence in Figure 8B), thus preventing each module from exceeding its ability to reliably supply pulses at frequencies (F1) that exceed the functional limits of the hardware (e.g., voltage limits, switching frequency limits, and other limits of transistors 410, 412, 414). Between pulses, as a result of the long wire and the associated stray inductance, some ringing (e.g., 802) may occur in the voltage waveform. The amount of ringing can be adjusted and / or minimized by the design of the pulser 400 and processing system 10 used.

[0051] Figure 9A is a graph showing the state of the switches (e.g., transistors 410, 412, 414) of pulser 400 between different examples of operating modes according to a particular embodiment of the present disclosure. Graph 900A shows the state of each of transistors 410, 412, 414 (e.g., Q1, Q2, Q3) when gate signals are applied to each of the respective gate drive circuits 418, 420, 422 at different times. In some embodiments, the system controller 126 may control the application of gate signals to the gate drive circuits 418, 420, 422 in order to activate the transistors 410, 412, 414 of modules 440, 442, 444. As shown in Figure 9A, the system controller 126 may transmit gate signals with different pulse widths to the gate drive circuits 418, 420, 422. In Graph 900A, first a gate signal (e.g., V1) is applied to module 440, generating a trigger pulse TR1 between times T1 and T2. Another gate signal (e.g., V1) is applied to module 442, generating a trigger pulse TR2 between times T3 and T4. A third gate signal (e.g., V1) is applied to module 444 between times T5 and T6, generating a trigger pulse TR3. As shown in Figure 9B, graph 800B shows the voltage (e.g., V2) seen at the common node 480 as a result of the voltage pulses P1, P2, P3 generated between intervals defined by the signals provided by the system controller 126. As a result of varying pulse widths of the applied gate signals, the widths of each pulse P1, P2, P3 supplied to the common node 480 are different. In this way, the output waveform can include generated pulses, each having a different pulse width, provided at desired times in the pulse sequence. By triggering multiple modules of pulser 400 using different gate signals with different pulse widths, it is possible to allow changes in the shape and pulse width of the output signal to match a desired IEDF. The pulses are as shown, between intervals T7-T8, T9-T 10 , T 11 ~T 12 This can be repeated during the interval.

[0052] Figure 10A is a graph showing the state of the switches (e.g., transistors 410, 412, 414) of pulser 400 between different examples of operating modes according to a particular embodiment of the present disclosure. In Figures 10A and 10B, V1 represents the gate signal, which may be a TTL signal (e.g., between 1.5V and 5V). V2, V3, and V4 represent the output voltages (e.g., 1000V, 2000V, and 3000V). Graph 1000A shows the state of each of the transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) when different gate signals are applied to each of the respective gate drive circuits 418, 420, and 422 at different times. In some embodiments, a system controller 126 may control the application of gate signals provided to the gate drive circuits 418, 420, and 422 to activate the transistors 410, 412, and 414 of modules 440, 442, and 444. The system controller 126 can transmit gate signals of different pulse widths to the gate drive circuits 418, 420, and 422. In Graph 1000A, first a gate signal (e.g., V1) is applied to module 440, generating a trigger pulse TR1 between times T1 and T2. Another gate signal (e.g., V1) is applied to module 442, generating a trigger pulse TR2 between times T3 and T4. A third gate signal is applied to module 444 between times T5 and T6, generating a trigger pulse TR3. Graph 1000B, shown in Figure 10B, shows the voltages generated at the common node 480 as a result of the pulses P1, P2, and P3 generated by each module 440, 442, and 444 during their respective time intervals. During the time interval between times T1 and T2, pulse P1 is generated by the voltage (V) stored in the capacitive element 402 (e.g., a voltage source). s1 This includes a voltage V3, which is supplied to the primary winding 452, and this voltage V3 causes the voltage V3 of the transformer 450 to be generated in the secondary winding 454 at a first transformation ratio. During the time interval between times T3 and T4, the pulse P2 is the voltage (V) stored in the capacitive element 404 (e.g., the voltage source). s2This includes a voltage V4 supplied to the primary winding 462, which causes the voltage V4 to be generated in the secondary winding 464 by the second transformation ratio of the transformer 460. During the time interval between times T5 and T6, the pulse P3 is generated by supplying a voltage (V) stored in the capacitive element 406 (e.g., a voltage source). s3 The voltage V2 is generated by supplying a voltage V2 to the primary winding 472, which in turn generates a voltage V2 in the secondary winding 474 due to the first transformation ratio of the first transformer 470. As a result of the change in the applied pulse width and the differences in the transformation ratio and / or input voltage applied by the use of transformers 450, 460, and 470, the width and magnitude of each pulse P1, P2, and P3 are different. In this way, output waveforms with different voltages and different pulse widths can be generated, which may enable a more favorable IEDF of the output waveform. In one example, the module may include transformers, each having the same transformation ratio, while the voltage input sources are configured to provide different peak input voltages, so that different peak voltage levels can be generated in the output voltage waveform pulses P1, P2, and P3. In another example, the module may include transformers, each having different transformation ratios, while the voltage input sources are configured to provide the same peak input voltage, so that different peak voltage levels can be generated in the output voltage waveform pulses P1, P2, and P3. By triggering multiple modules of Pulser 400 using gate signals with different pulse widths and input voltages, the shape and pulse width of the output signal can be modified to match the desired IEDF. The pulses are spaced as shown, with intervals T7-T8, T9-T 10 , T 11 ~T 12 This can be repeated between these points.

[0053] Figure 11A is a graph showing the state of the switches (e.g., transistors 410, 412, 414) of pulser 400 between different examples of operating modes according to a particular embodiment of the present disclosure. In Figures 11A-11D, V1 and V5 represent gate signals, respectively, which may be TTL signals (e.g., between 1.5V and 5V). V2, V3, V4, V6, and V7 represent output voltages (e.g., 1000V, 2000V, 3000V). Graph 1100A shows the state of each of the transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) when gate signals are applied to each of them, with the gate drive circuits 418, 420, and 422 overlapping. In some embodiments, the system controller 126 supplies gate signals to gate drive circuits 418, 420, and 422 to activate transistors 410, 412, and 414 of modules 440, 442, and 444, generating the pulse sequence shown in Figure 11B. The system controller 126 may transmit gate signals containing time-overlapping pulses to the gate drive circuits 418, 420, and 422. In Graph 1100A, first a gate signal (e.g., V1) is applied to module 440, generating a trigger pulse TR1 between times T1 and T2. Another gate signal is applied to module 442, generating a trigger pulse TR2 between times T1 and T3. A third gate signal is applied to module 444 between times T1 and T4, generating a trigger TR3. Here, the time interval between times T1 and T2 includes the duplicate gate signal (e.g., V1) provided to the gate drive circuits 418, 420, and 422, the continuing duplicate gate signal (e.g., V1) provided to the gate drive circuits 420, and 422 during the time interval between times T2 and T3, and the continuing gate signal (e.g., V1) provided to the gate drive circuit 422 during the time interval between T3 and T4. Graph 1100B shown in Figure 11B shows the voltage pulses generated as a result of the voltage pulses P1, P2, and P3 generated during each of those time intervals shown in Figure 11A. During the time interval between times T1 and T2, a first portion of a pulse is generated, including pulses P1, P2, and P3 generated by modules 440, 442, and 444 to form a portion of a pulse having voltage V2.During the time interval between times T2 and T3, a second portion of the pulse is generated, including pulses P2 and P3 generated by modules 442 and 444 to form a portion of the pulse having voltage V3. During the time interval between times T3 and T4, a third portion of the pulse is generated, including pulse P3 generated by module 444 to form a portion of the pulse having voltage V4. The portions of the pulse may be repeated during time intervals T5-T6, T6-T7, and T7-T8, as shown in Figure 11B. In some embodiments, the pulses P1, P2, and P3 supplied to the gate drive circuits 418, 420, and 422 are generated by the system controller such that at least portions of two or more pulses overlap in time. As described herein, the transformer ratios of the transformers in modules 440, 442, and 444 can be changed to customize the output voltage waveform of the pulser 400 with different voltages and different pulse widths. By triggering multiple Pulsar 400 modules with various transformation ratios, the shape and pulse width of the output signals can be made to overlap, potentially generating waveforms that enable a desired IEDF distribution during plasma processing.

[0054] Figure 11C is a graph showing the state of the switches (e.g., transistors 410, 412, 414) of pulser 400 between different examples of operating modes according to a particular embodiment of the present disclosure. The system controller 126 changes the gate signals supplied to gate drive circuits 418, 420, 422, which are used to activate transistors 410, 412, 414 of modules 440, 442, 444, thereby achieving voltage waveforms that step up or step down voltages to generate waveforms that enable a desired IEDF distribution. The timing of the gate signals applied to gate drive circuits 418, 420, 422 can be manipulated to control the overlap of the voltage pulses P1, P2, P3 supplied by each module 440, 442, 444, and generate different types of waveforms to form a more favorable IEDF during plasma processing. Graph 1100D (Figure 11D) shows the time T as a result of the applied trigger pulses TR4, TR5, TR6. 10 Step down, time T11 An example of a step-up voltage waveform is shown. Graph 1100D shows the state of each transistor 410, 412, 414 (e.g., Q1, Q2, Q3) when different gate signals are applied to their respective gate drive circuits 418, 420, 422 in a superimposed manner. In some embodiments, the system controller 126 may control the application of gate signals to the gate drive circuits 418, 420, 422 in order to activate the transistors 410, 412, 414 of modules 440, 442, 444. The gate drive circuits 418, 420, 422 may apply gate signals in a superimposed manner. In Graph 1100C, the gate signal (e.g., V5) is first applied at time T9 and T 10 A trigger pulse TR4 is applied to module 440 between and , and then time T 10 and T 11 A trigger pulse TR5 is applied to module 442 between and at time T to generate a trigger pulse TR6. 11 and T 12 It is applied to module 444 between time T9 and T 10 The interval between is time T. 10 and T 11 The interval and overlap between them, time T 10 and T 11 The interval between is time T. 11 and T 12 The intervals between them overlap. Graph 1100D shows the voltages observed at common node 480 as a result of pulses P1, P2, and P3 generated during each interval, at times T9 and T 10 During the interval between time T, pulse P1 generates voltage V6. 10 and T 11 During the interval between time T, pulse P2 generates voltage V7. 11 and T 12 During the interval between and , pulse P3 generates voltage V6. The pulses are as shown in the diagram, with interval T 13 ~T 14 , T 14 ~T 15 , T 15 ~T 16This can be repeated between the two. In this example, both pulses P4 and P6 contain a voltage (e.g., V6) higher than the voltage (e.g., V7) contained in pulse P5, as illustrated. By triggering multiple modules of the pulser 400, each capable of generating different voltages, it may be possible to generate a variety of waveforms that can enable a desired IEDF distribution.

[0055] Figure 12 shows a charging circuit 1200 used to charge a capacitive element 1212 according to a particular aspect of this disclosure. Capacitive element 1212 may correspond to any one of capacitive elements 402, 404, or 406. In other words, a charging circuit (e.g., similar to charging circuit 1200) may be implemented for each of the capacitive elements 402, 404, or 406 to charge them to their respective voltages, as described herein. The charging circuit 1200 may include an inverter 1202 for converting a DC voltage to an alternating current (AC) voltage. The AC voltage may be supplied to the primary winding 1206 of a transformer 1204. The transformer may generate an AC voltage in a secondary winding 1208 having a higher voltage than the AC voltage in the primary winding 1206. For example, to charge the inverter 1202, the AC voltage in the secondary winding 1208 may have a peak voltage of 1200 volts. The AC voltage of the secondary winding 1208 can be supplied to the rectifier 1210 to generate a DC signal used to charge the capacitive element 1212.

[0056] Examples of voltage waveform generation Figure 13 is a process flow diagram showing a waveform generation method 1300 according to a particular embodiment of the present disclosure. Method 1300 may be performed by a waveform generation system including a waveform generator such as a pulser 400 and / or a control circuit such as a system controller 126. The following discussion of method 1300 will be explained in conjunction with a schematic diagram of the pulser 400 shown in Figure 4. As described above, in some embodiments, the common node 480 shown in Figure 4 is configured to be connected to an electrode in the plasma processing system 10.

[0057] In step 1302, the waveform generator (e.g., pulser 400) supplies a first pulse from the first voltage stage 444 at a first time interval. Supplying the first pulse from the first voltage stage involves generating a first voltage pulse at the common node 480 by closing a first switch (e.g., transistor 414) connected to the first voltage source 406 and the first transformer 470. The first voltage source 406 supplies a first voltage V to the primary winding 472 of the first transformer 470. P1 The first transformer has a first transformation ratio, and therefore the second voltage V T2 This is formed within the secondary winding 474 of the first transformer. Here, the second voltage V T2 The first voltage V P1 It is equal to multiplying by the transformation ratio. The common node 480 connected to the first terminal of the secondary winding 474 is then supplied with the second voltage V T2 A first pulse, which includes the specified element, will appear.

[0058] In step 1304, the waveform generator (e.g., pulser 400) supplies a second pulse from the second voltage stage 442 at a second time. Supplying the second pulse from the second voltage stage 442 involves generating a second voltage pulse at the common node 480 by closing a second switch (e.g., transistor 412) coupled to the second voltage source 404 and the second transformer 460. The second voltage source 404 supplies a third voltage V to the primary winding 462 of the second transformer 460. P3 The second transformer has a second transformation ratio, and therefore the fourth voltage V T4 This is formed within the secondary winding 464 of the second transformer. Here, the fourth voltage V T4 This is the third voltage V P3 This is equal to multiplying by the second transformation ratio. The common node 480 connected to the first terminal of the secondary winding 464 is then supplied with the fourth voltage V T4A formed second pulse including it will appear. When the second module 442 supplies the second pulse, the second pulse may be combined with the generated first pulse provided in step 1302 as desired, such as one or more of the pulse-like configurations described above in relation to FIGS. 5A to 11D.

[0059] In step 1306, the waveform generator (e.g., pulsar 400) supplies a third pulse from the third voltage stage 440 at a third time. Supplying the third pulse from the third voltage stage 440 will include generating a third voltage pulse at the common node 480 by closing a third switch (e.g., transistor 410) connected to the third voltage source 402 and the third transformer 450. The third voltage source 402 is configured to supply a fifth voltage V P5 to the primary winding 452 of the third transformer 450. The third transformer has a third turns ratio, and thus, a sixth voltage V T6 is formed within the secondary winding 464 of the second transformer. Here, the sixth voltage V T6 is equal to the fifth voltage V P5 multiplied by the third turns ratio. At the common node 480 connected to the first terminal of the secondary winding 454, a formed third pulse including the supplied sixth voltage V T6 will appear. When the third module 442 supplies the third pulse, the third pulse may be combined with the generated first and / or second pulses provided in steps 1302 and 1304 as desired, such as one or more of the pulse-like configurations described above in relation to FIGS. 5A to 11D.

[0060] In some embodiments of method 1300, steps 1302, 1304, 1306 may each be separated by a time interval. In other embodiments of method 1300, the supply of pulses provided between steps 1302, 1304, 1306 may at least partially overlap, as described above. As described herein, the method 1300 referred to in FIGS. 5A-5B and FIGS. 7A-11D may include varying the turns ratio during plasma processing to trigger multiple modules of the pulsar 400 to customize the output voltage waveform of the pulsar 400 at different voltages and different pulse widths so as to be able to generate waveforms that enable a desired IEDF distribution during plasma processing.

[0061] In some embodiments, the third turns ratio may be the same as the first turns ratio or the second turns ratio. In other embodiments, the third turns ratio may be different from the first turns ratio and the second turns ratio. As described above, in some embodiments, the first turns ratio, the second turns ratio, and the third turns ratio are all the same or all different from each other. In one example, the turns ratio may be in the range between 1:1 and 1:4 (for example, in the range between 1:1.5 and 1:4). In an alternative example, the turns ratio may be in the range between 4:1 and 1:1 (for example, in the range between 2:1 and 1.5:1).

[0062] In some embodiments, the first voltage V P1 , the third voltage V P3 , and the fifth voltage V P5 supplied by the first voltage source 406, the second voltage source 404, and the third voltage source 402 are all set to the same voltage level (for example, +100 to +800 volts). In some embodiments, one or more of the first voltage V P1 , the third voltage V P3 , and the fifth voltage V P5 are set to different voltage levels. In one example, the first voltage V P1 , the third voltage V P3 , the fifth voltage V P5 are set to voltage levels in the range of +100 to +800 volts. In another example, the first voltage V P1 , the third voltage VP3 , and the fifth voltage V P5 The voltage level is set to 100 to 10,000 volts (e.g., 100 to 1,000 volts). In some embodiments, the polarity of the output voltage seen at the common node 480 may be negative, and may be changed to positive.

[0063] The processing chamber 100 includes a system controller 126, which includes a CPU 133, a memory 134, and a support circuit 135, as described above. In some embodiments, the memory 134 may be a computer-readable medium memory configured to store instructions (e.g., computer-executable code) that, when executed by the CPU 133, cause the processing chamber 100 to perform the operations shown in Figure 13 and described above, or other operations to perform various techniques considered herein to provide voltage waveforms.

[0064] In some embodiments, the CPU 133 has a circuit configured to implement code stored in a computer-readable medium (e.g., memory 134). For example, this circuit includes a circuit for supplying a first pulse from a first voltage stage (e.g., 444) in a first time and a second pulse from a second voltage stage (e.g., 442) in a second time. In some embodiments, the circuit includes a circuit for supplying a third pulse from a third voltage stage (e.g., 440) in a third time.

[0065] Additional considerations The term "connection" as used here refers to a direct or indirect connection between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C are still considered connected to each other, even if they are not in direct physical contact with each other. For example, an object may be considered connected to an object even if it is not in direct physical contact with the second object.

[0066] The above description applies to embodiments of the present disclosure, but other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. The first voltage stage, First voltage source, A first switch, wherein the first terminal of the first voltage source is connected to the first terminal of the first switch. A grounding reference, wherein the second terminal of the first switch is connected to the grounding reference, and A transformer having a first transformation ratio, wherein the first transformer is The primary winding connected to the second terminal of the first voltage source and the ground reference, and A secondary winding having a first end and a second end, wherein the first end is connected to the ground reference. transformers A first voltage stage having, The second voltage stage, Second voltage source, A second switch, wherein the first terminal of the second voltage source is connected to the first terminal of the second switch. A second grounding reference wherein the second terminal of the second switch is connected to the second grounding reference, and A second transformer having a second transformation ratio, wherein the second transformer is A primary winding connected to the second terminal of the second voltage source and the second ground reference, and A secondary winding having a first end and a second end, wherein the first end is connected to the second end of the secondary winding of the first transformer, and the second end is configured to be connected to a load through a common node. The second transformer, which includes A second voltage stage having A waveform generator equipped with the following features.

2. The first voltage stage further comprises a first diode connected in parallel with the primary winding of the first transformer. The waveform generator according to claim 1, wherein the second voltage stage further comprises a second diode connected in parallel with the primary winding of the second transformer.

3. The waveform generator according to claim 2, wherein the first diode is connected to a first node and a second node, the first node is located between the second terminal of the voltage source and the first terminal of the primary winding, and the second node is located between the first terminal of the first switch and the second terminal of the primary winding.

4. The waveform generator according to claim 2, wherein the first diode includes the body diode of the first switch, or the second diode includes the body diode of the second switch.

5. The waveform generator according to claim 1, wherein the first transformation ratio is different from the second transformation ratio.

6. The waveform generator according to claim 5, wherein the first transformation ratio is smaller than the second transformation ratio.

7. The waveform generator according to claim 5, wherein the first transformation ratio is greater than the second transformation ratio.

8. The first switch, A transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), Gate drive circuit and A waveform generator according to claim 1, including the following:

9. The waveform generator according to claim 1, wherein the first voltage source includes a capacitive element.

10. The waveform generator according to claim 1, wherein the common node is configured to be capacitively coupled to the plasma formed within the processing area of ​​the plasma processing system.

11. The waveform generator according to claim 10, wherein the common node is connected to a bias electrode located in a substrate support located within the plasma processing system.

12. The third voltage stage, A third voltage source and A third switch, wherein the first terminal of the third voltage source is connected to the first terminal of the third switch, A third grounding reference, wherein the second terminal of the third switch is connected to the third grounding reference, A third transformer having a third transformation ratio, wherein the third transformer is A primary winding connected to the second terminal of the third voltage source and the third ground reference, and A secondary winding having a first end and a second end, wherein the first end is connected to the second end of the secondary winding of the second transformer, and the second end of the third transformer is connected to the load through the common node. A third transformer, including, A third diode connected in parallel with the primary winding of the second transformer and The waveform generator according to claim 1, further comprising a third voltage stage having the following:

13. A method for generating a voltage waveform, The first voltage pulse is generated at a common node at a first time by closing a first switch having a first terminal and a second terminal, The first terminal of the first switch is connected to the first terminal of the first voltage source. The second terminal of the first voltage source is connected to the first terminal of the primary winding of a first transformer having a first transformation ratio. The second terminal of the first switch is connected to the second terminal of the primary winding of the first transformer and to ground. The common node generates a first voltage pulse which is connected to the first terminal of the secondary winding of the first transformer. The method involves generating a second voltage pulse at the common node at a second time by closing a second switch having a first terminal and a second terminal, The first terminal of the second switch is connected to the first terminal of the second voltage source. The second terminal of the second voltage source is connected to the first terminal of the primary winding of a second transformer having a second transformation ratio. The second terminal of the first switch is connected to the second terminal of the primary winding of the second transformer and to ground. A second bias voltage is generated by the second voltage source between the first terminal and the second terminal of the second voltage source. The first terminal of the secondary winding of the second transformer generates a second voltage pulse, which is connected to the second terminal of the secondary winding of the first transformer. Includes, A method wherein the common node is located between the first terminal of the secondary winding of the first transformer and the load.

14. The method according to claim 13, wherein the first voltage pulse and the second voltage pulse overlap in time.

15. The method according to claim 13, wherein the common node is connected to a bias electrode located in a substrate support located within a plasma processing system.

16. The method according to claim 13, wherein the first voltage transformation ratio is different from the second voltage transformation ratio.

17. The method according to claim 13, wherein the first time overlaps with the second time.

18. A third voltage pulse is generated at the common node at a third time by closing a third switch having a first terminal and a second terminal. It further includes, The first terminal of the third switch is connected to the first terminal of the third voltage source. The second terminal of the third voltage source is connected to the first terminal of the primary winding of the third transformer having a third transformation ratio. The second terminal of the third switch is connected to the second terminal of the primary winding of the third transformer and to ground. A third bias voltage is generated by the third voltage source between the first terminal and the second terminal of the third voltage source. The method according to claim 13, wherein the first terminal of the secondary winding of the second transformer is connected to the second terminal of the secondary winding of the first transformer.

19. The method according to claim 18, wherein the third transformation ratio is different from the first transformation ratio and the second transformation ratio.

20. A non-temporary computer-readable medium for generating waveforms, The first voltage pulse is generated at a common node at a first time by closing a first switch having a first terminal and a second terminal, The first terminal of the first switch is connected to the first terminal of the first voltage source. The second terminal of the first voltage source is connected to the first terminal of the primary winding of a first transformer having a first transformation ratio. The second terminal of the first switch is connected to the second terminal of the primary winding of the first transformer and to ground. The common node generates a first voltage pulse which is connected to the first terminal of the secondary winding of the first transformer. The method involves generating a second voltage pulse at the common node at a second time by closing a second switch having a first terminal and a second terminal, The first terminal of the second switch is connected to the first terminal of the second voltage source. The second terminal of the second voltage source is connected to the first terminal of the primary winding of a second transformer having a second transformation ratio. The second terminal of the first switch is connected to the second terminal of the primary winding of the second transformer and to ground. A second bias voltage is generated by the second voltage source between the first terminal and the second terminal of the second voltage source. The first terminal of the secondary winding of the second transformer generates a second voltage pulse, which is connected to the second terminal of the secondary winding of the first transformer. The instructions include instructions that can be executed by one or more processors to perform the following: The common node is a non-temporary computer-readable medium located between the first terminal of the secondary winding of the first transformer and the load.

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