Indication device

Abstract

To provide a display device with high resolution. To provide a display device with low power consumption. [Solution] The display device includes a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. The first transistor has its gate electrically connected to the first wiring, one of its source and drain connected to the second wiring, and the other of its source and drain connected to the gate of each of the plurality of second transistors. The plurality of second transistors are connected in series or in parallel. The first transistor has a first semiconductor layer through which current flows in a first or second direction, and each of the plurality of second transistors has a second semiconductor layer through which current flows in a first or second direction.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device. Another aspect of the present invention relates to an electronic device equipped with a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties. [Background technology]

[0003] In recent years, there has been a trend towards higher resolution display panels. Devices requiring high-resolution display panels, such as those for virtual reality (VR) or augmented reality (AR), have seen a surge in development in recent years.

[0004] Furthermore, typical examples of display devices applicable to display panels include light-emitting devices equipped with light-emitting elements such as organic EL (Electro Luminescence) elements and light-emitting diodes (LEDs), liquid crystal display devices, or electronic paper that displays information using electrophoretic methods.

[0005] The basic structure of an organic EL element consists of a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be obtained from the light-emitting organic compound. Because a display device using such an organic EL element does not require a backlight, which is necessary for liquid crystal displays and the like, it is possible to realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2002-324673 [Overview of the project] [Problems that the invention aims to solve]

[0007] In the aforementioned wearable devices for VR or AR, the short distance between the eyes and the display panel necessitates the placement of focus-adjusting lenses between them. Because these lenses magnify a portion of the screen, a low resolution display panel can lead to a diminished sense of reality and immersion.

[0008] Furthermore, in the case of battery-powered devices, reducing the power consumption of the display panel is required to extend the continuous usage time. In particular, high brightness is required for AR devices in order to display images superimposed on ambient light.

[0009] One aspect of the present invention aims to provide a display device with high resolution. One aspect of the present invention aims to provide a display device with low power consumption. One aspect of the present invention aims to provide a display device with high brightness. One aspect of the present invention aims to provide a display device with a high aperture ratio. One aspect of the present invention aims to provide a highly reliable display device.

[0010] One aspect of the present invention aims to provide a novel display device, display module, or electronic device. Alternatively, it aims to provide a method for manufacturing the above-mentioned display device with high yield. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a display device having a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. The gate of the first transistor is electrically connected to the first wiring, one of its source and drain is electrically connected to the second wiring, and the other of its source and drain is electrically connected to the gate of each of the plurality of second transistors. The plurality of second transistors are connected in series. The first transistor has a first semiconductor layer through which current flows in a first or second direction. Each of the plurality of second transistors has a second semiconductor layer through which current flows in a first or second direction.

[0013] Another aspect of the present invention is a display device having a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. The gate of the first transistor is electrically connected to the first wiring, one of its source and drain is electrically connected to the second wiring, and the other of its source and drain is electrically connected to the gate of each of the plurality of second transistors. Each of the plurality of second transistors has one of its source and drain electrically connected, and the other of its source and drain electrically connected. The first transistor has a first semiconductor layer through which current flows in a first direction or a second direction. Each of the plurality of second transistors has a second semiconductor layer through which current flows in a first direction or a second direction.

[0014] Also, in any of the above, it is preferable to have a light-emitting element having an anode and a cathode. Further, in one of the plurality of second transistors, it is preferable that one of the source and the drain is electrically connected to the anode or the cathode.

[0015] Also, in any of the above, it is preferable that the plurality of second transistors have substantially equal channel lengths and substantially equal channel widths respectively.

[0016] Also, in any of the above, it is preferable that the first transistor and the plurality of second transistors have substantially equal channel lengths and substantially equal channel widths.

[0017] Also, in any of the above, among the plurality of second transistors, it is preferable that two adjacent second transistors each have a channel formation region in one island-shaped second semiconductor layer.

[0018] Also, in any of the above, the plurality of second transistors each have a second semiconductor layer, and it is preferable that the plurality of second semiconductor layers are arranged at equal intervals in the first direction or the second direction.

[0019] Also, in any of the above, the second semiconductor layer preferably contains a metal oxide containing one or both of indium and zinc. Further, the first semiconductor layer preferably contains the same metal oxide as the second semiconductor layer.

[0020] Also, in any of the above, it is preferable to have a third transistor. The third transistor has a third semiconductor layer. The third semiconductor layer preferably contains the same semiconductor material as the first semiconductor layer and has a portion with a substantially identical upper surface shape to the first semiconductor layer. Further, in the third transistor, it is preferable that at least one of the gate, the source, and the drain is electrically floating.

Advantages of the Invention

[0021] According to one aspect of the present invention, a display device with high resolution can be provided. Alternatively, a display device with low power consumption can be provided. Alternatively, a display device with high brightness can be provided. Alternatively, a display device with a high aperture ratio can be provided. Alternatively, a highly reliable display device can be provided.

[0022] Furthermore, according to one aspect of the present invention, a novel display device, display module, or electronic device can be provided. Alternatively, a method for manufacturing the above-mentioned display device with high yield can be provided. Or, at least one of the problems of the prior art can be mitigated.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0024] [Figure 1] Figures 1A to 1C show examples of pixel circuit configurations. [Figure 2] Figures 2A to 2E show examples of pixel circuit configurations. [Figure 3] Figures 3A to 3D show examples of pixel circuit configurations. [Figure 4] Figure 4 is a timing chart showing an example of a driving method for the display device. [Figure 5] Figure 5 shows an example of a transistor configuration. [Figure 6] Figures 6A to 6E show examples of transistor configurations. [Figure 7] Figures 7A to 7E show examples of transistor configurations. [Figure 8] Figures 8A and 8B show examples of transistor configurations. [Figure 9] Figure 9 shows an example of a display device configuration. [Figure 10] Figures 10A to 10E show examples of display device configurations. [Figure 11] Figure 11 shows an example of a display device configuration. [Figure 12] Figures 12A to 12E show examples of display device configurations. [Figure 13] Figure 13 shows an example of a display device configuration. [Figure 14] Figure 14 shows an example of a display device configuration. [Figure 15] Figure 15 shows an example of a display device configuration. [Figure 16] Figure 16 shows an example of a display device configuration. [Figure 17] Figures 17A to 17F show examples of the configuration of a light-emitting device. [Figure 18] Figures 18A and 18B show examples of electronic device configurations. [Figure 19] Figures 19A and 19B show examples of the configuration of electronic equipment. [Figure 20] Figures 20A and 20B show the electrical characteristics of the transistor according to the embodiment. [Figure 21] Figure 21 is a photograph of the display state of the display panel according to the embodiment. [Figure 22] Figures 22A and 22B show the measurement results of the viewing angle dependence of the display panel according to the embodiment. [Figure 23] Figure 23 is a block diagram of the drive circuit for the display panel according to the embodiment. [Figure 24] Figure 24 shows the measurement results of the brightness of the display panel according to the embodiment during duty cycle driving. [Modes for carrying out the invention]

[0025] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0026] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatch patterns are the same, and reference numerals may not be assigned.

[0027] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0028] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0029] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0030] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, that direction may be described as "down," and the opposite direction as "up."

[0031] In this specification, the term "EL layer" refers to a layer (also called a light-emitting layer) provided between a pair of electrodes of a light-emitting element and containing at least a light-emitting substance, or a laminate including a light-emitting layer.

[0032] In this specification, a display panel, which is one form of a display device, has the function of displaying (outputting) images or the like on its display surface. Therefore, a display panel is one form of an output device.

[0033] Furthermore, in this specification, a display panel on which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is attached, or on which an IC is mounted on the board using a COG (Chip On Glass) method, may be referred to as a display panel module, display module, or simply a display panel.

[0034] (Embodiment 1) This embodiment describes an example of the configuration of a display device according to one aspect of the present invention.

[0035] One aspect of the present invention is a display device having a plurality of pixels arranged in a matrix. The display device has a plurality of gate lines (first wiring) to which gate signals (also called scan signals, scanning signals, etc.) are supplied, and a plurality of source lines (second wiring) to which source signals (also called video signals, data signals, etc.) are supplied. The gate lines are provided to extend in a first direction, and the source lines are provided to extend in a second direction intersecting the first direction.

[0036] A pixel is provided corresponding to the intersection of one source line and one gate line. A pixel has one or more display elements and two or more transistors. A pixel has pixel electrodes that function as electrodes for the display elements.

[0037] Each pixel has a first transistor and a second transistor. In this case, it is preferable that the second transistor is composed of multiple transistors (also called subtransistors) that share a common gate. For example, the second transistor is composed of multiple subtransistors connected in series. Alternatively, the second transistor is composed of multiple subtransistors connected in parallel. Alternatively, the second transistor is composed of a group of multiple subtransistors connected in parallel connected in series (hereinafter also referred to as series-parallel connection).

[0038] Here, a subtransistor refers to one of a group of transistors that share a common gate and are connected in series or parallel. When multiple subtransistors are connected in parallel, the gate, source, and drain are common to each subtransistor. When multiple subtransistors are connected in series, the gates are common to each subtransistor, and two adjacent subtransistors are connected such that the source of one and the drain of the other are common to the other. In the following, subtransistors may also be simply referred to as transistors.

[0039] Furthermore, it is preferable that each of the multiple subtransistors constituting the second transistor has approximately equal channel length and channel width. That is, it is preferable that the second transistor is constructed by connecting multiple subtransistors with the same design size in series, parallel, or series-parallel. This reduces the inter-pixel variation in the electrical characteristics of the second transistor compared to when the second transistor is constructed as a single transistor.

[0040] Furthermore, it is preferable that all of the subtransistors constituting the second transistor have the same channel length direction. For example, it is preferable to arrange each subtransistor so that the channel length direction of all transistors is parallel to the first direction or the second direction. In this case, it is also preferable that the channel width direction of all subtransistors is equal.

[0041] Furthermore, it is preferable that the channel formation regions of the multiple subtransistors are arranged at equal intervals. The channel formation region referred to here is a part of the semiconductor layer of the transistor that, in a plan view, overlaps with the gate.

[0042] Furthermore, it is preferable that the channel length and channel width of the first transistor and one of the subtransistors are approximately equal to each other. Moreover, it is preferable that they are equal in both the channel length direction and the channel width direction. In particular, it is preferable that all of the multiple transistors constituting the pixel are composed of subtransistors designed to be the same size.

[0043] Furthermore, it is preferable that the channel length direction of the first transistor is parallel to the first or second direction. In this case, it is preferable that the channel length direction of the subtransistor is parallel to the channel length direction of the first transistor. This is preferable because aligning the direction of current flow for multiple transistors constituting a pixel simplifies the design.

[0044] Below, we will explain more specific examples with reference to the diagrams.

[0045] [Example Configuration] Figures 1A, 1B, and 1C show an example of a pixel circuit of a display device according to one embodiment of the present invention.

[0046] The pixel circuits shown in Figures 1A, 1B, and 1C include transistors M1 and M2, capacitor C1, and light-emitting element EL. The pixel circuits are electrically connected by wirings GL, SL, AL, and CL.

[0047] A gate signal is supplied to wiring GL. A source signal is supplied to wiring SL. Constant potentials are supplied to wirings AL and CL, respectively. The anode side of the light-emitting element EL can be made to a high potential, and the cathode side to a lower potential than the anode side.

[0048] Transistor M1 can also be called a selection transistor and functions as a switch to control the selection and deselection of pixels. Transistor M1 has its gate electrically connected to wiring GL, one of its source and drain electrically connected to wiring SL, and the other electrically connected to one electrode of capacitor C1 and transistor M2.

[0049] Capacitor C1 functions as a retaining capacitor. The other electrode of capacitor C1 is electrically connected to one electrode of the light-emitting element EL. Note that capacitor C1 may be omitted if it is not needed.

[0050] Transistor M2 can also be called a driving transistor and has the function of controlling the current flowing to the light-emitting element EL.

[0051] Transistor M2 is composed of multiple transistors (subtransistors).

[0052] In Figure 1A, transistor M2 is a series of p transistors (where p is an integer greater than or equal to 2) connected in series. iIt has (where i is an integer from 1 to p). Transistor m i The gates are electrically connected (also said to be common).

[0053] Among transistors m1 to m p For transistor m1, one of the source and drain is electrically connected to wiring AL, and the other is electrically connected to one of the source and drain of transistor m2. Transistor m p One of the source and drain is electrically connected to the other of the source and drain of transistor m p-1 The other is electrically connected to one electrode of light-emitting element EL and the other electrode of capacitor C1. For transistors m1 and m p Except for transistor m i (Transistors m2 to m p-1 ) One of the source and drain is electrically connected to the other of the source and drain of transistor m i-1 The other is electrically connected to one of the source and drain of transistor m i+1

[0054] FIG. 1B shows a configuration having q (where q is an integer of 2 or more) transistors m j (where j is an integer from 1 to q) to which transistor M2 is connected in parallel. Transistor m j The gates, sources, and drains are common, respectively.

[0055] For transistors m1 to m q The gates are electrically connected to the other of the source and drain of transistor M1, respectively. Also, for transistors m1 to m q One of the source and drain is electrically connected to wiring AL, and the other is electrically connected to one electrode of light-emitting element EL, respectively.

[0056] FIG. 1C shows that transistor M2 is composed of p×q transistors m ij ​This is an example of a configuration consisting of q units, each having p transistors connected in series, connected in parallel.

[0057] In the configuration shown in Figures 1A, 1B, and 1C, transistor m constitutes transistor M2. i , transistor m j or transistor m ij It is preferable to use transistors (hereinafter referred to as transistor m when these are not distinguished) that have the same transistor structure and approximately the same channel length and channel width.

[0058] For example, let the channel length of transistor m be L and the channel width be W. In this case, transistor M2 in Figure 1A can be treated as a single transistor with a channel length of p × L and a channel width of W. Similarly, transistor M2 in Figure 1B can be treated as a single transistor with a channel length of L and a channel width of q × W. Furthermore, transistor M2 in Figure 1C can be treated as a single transistor with a channel length of p × L and a channel width of q × W.

[0059] Next, we will explain an example of a pixel circuit different from the one described above. In the following, we will illustrate and explain the case where the transistor M2 is a configuration in which multiple transistors are connected in series as exemplified in Figure 1A, but the transistor M2 exemplified in Figures 1B and 1C can also be used.

[0060] The pixel circuit shown in Figure 2A has the same configuration as in Figure 1A, with the addition of transistor M3. Furthermore, wiring V0 is electrically connected to the pixel circuit in Figure 2A.

[0061] Transistor M3 has its gate electrically connected to wiring GL, and one of its source and drain is electrically connected to the anode of the light-emitting element EL, while the other is electrically connected to wiring V0.

[0062] Wiring V0 provides a constant potential when writing data to the pixel circuit. This helps to suppress variations in the gate-source voltage of transistor M2.

[0063] The pixel circuit shown in Figure 2B is a combination of transistors m of transistors M1 and M2 in the pixel circuit of Figure 1A. i This is an example of applying a transistor with a pair of gates.

[0064] In transistor M1, the pair of gates are electrically connected. This increases the current that the transistor can supply. Also, in transistor M2, transistors m1 to m n Each back gate is a transistor m n It is electrically connected to the other side of the source and drain of the transistor m. For example, if a higher potential is applied to wiring AL than to wiring CL, the transistor m n The source of the transistor is electrically connected to the back gate of each transistor. This configuration allows for stabilization of the electrical characteristics of transistor M2 and improvement of its reliability.

[0065] Figure 2C shows an example where a transistor with a pair of gates is applied to each transistor in the pixel circuit of Figure 2A.

[0066] Figures 2D and 2E show different examples of transistor M2. As shown in Figure 2D, transistors m1 through m n Each of the back gates may be electrically connected to its own source. Also, as shown in Figure 2E, transistors m1 to m n Each of the back gates and gates may be electrically connected.

[0067] Figure 3A shows the configuration shown in Figure 2A with the addition of transistor M4. In Figure 3A, three wires that function as gate wires (wires GL1, GL2, and GL3) are electrically connected.

[0068] Transistor M4 has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor M2, while the other is electrically connected to wiring V0. Also, the gate of transistor M1 is electrically connected to wiring GL1, and the gate of transistor M3 is electrically connected to wiring GL2.

[0069] By making transistors M3 and M4 conductive during the same period, the source and gate of transistor M2 become at the same potential, making transistor M2 non-conductive. This allows the current flowing to the light-emitting element EL to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0070] The pixel circuit shown in Figure 3B is an example where capacitor C2 is added to the circuit in Figure 3A. Capacitor C2 functions as a holding capacitor.

[0071] The pixel circuits shown in Figures 3C and 3D are examples of applying a pair of gate transistors to Figure 3A or Figure 3B, respectively. Transistors M1, M3, and M4 are transistors with a pair of gates electrically connected, while transistor M2 is a transistor with one gate electrically connected to the source.

[0072] [Example of driving method] The following describes an example of a driving method for a display device to which the pixel circuit illustrated in Figure 3A is applied. The same driving method can also be applied to Figures 3B, 3C, and 3D.

[0073] Figure 4 shows a timing chart for the driving method of the display device. Here, the potential changes of the gate lines of row k, wiring GL1[k], wiring GL2[k], and wiring GL3[k], and the gate lines of row k+1, wiring GL1[k+1], wiring GL2[k+1], and wiring GL3[k+1] are shown. Figure 4 also shows the timing of the signal applied to wiring SL, which functions as a source line.

[0074] This example shows a driving method that divides one horizontal period into an on-time period and an off-time period. Also, the horizontal period in row k and the horizontal period in row k+1 are shifted by the gate line selection period.

[0075] During the k-th row's illumination period, a high-level potential is first applied to wires GL1[k] and GL2[k], and a source signal is applied to wire SL. This causes transistors M1 and M3 to conduct, and the potential corresponding to the source signal is written from wire SL to the gate of transistor M2. Subsequently, a low-level potential is applied to wires GL1[k] and GL2[k], causing transistors M1 and M3 to become non-conductive, and the gate potential of transistor M2 is maintained.

[0076] Next, the process transitions to the illumination period of row k+1, and data is written using the same procedure as described above.

[0077] Next, we will explain the off-period. During the off-period of the k-th row, a high-level potential is applied to wirings GL2[k] and GL3[k]. This causes transistors M3 and M4 to conduct, and as the same potential is supplied to the source and gate of transistor M2, almost no current flows through transistor M2. As a result, the light-emitting element EL turns off. All subpixels located in the k-th row turn off. The subpixels in the k-th row remain off until the next on-period.

[0078] Next, the process transitions to the blackout period for row k+1, and as described above, all subpixels in row k+1 become black.

[0079] Thus, a driving method that includes periods of the light being off during a horizontal display period, rather than remaining lit the entire time, can also be called duty cycle driving. By using duty cycle driving, the afterimage phenomenon when displaying videos can be reduced, thus enabling the creation of display devices with high video display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0080] In duty cycle operation, the ratio of the lighting period to the horizontal period can be called the duty cycle. For example, a duty cycle of 50% means that the lighting period and the off period are of equal length. The duty cycle can be freely set and can be adjusted as appropriate within a range of, for example, higher than 0% and less than or equal to 100%.

[0081] The above is an explanation of the example of the drive method.

[0082] [Example of transistor configuration] Next, an example of a transistor configuration that can be applied to the pixels of a display device according to one aspect of the present invention will be described.

[0083] Figure 5 shows a schematic top view and a schematic cross-sectional view of transistor 10. Transistor 10 has a semiconductor layer 31, a conductive layer 21, a conductive layer 22, an insulating layer 51, an insulating layer 52, etc.

[0084] The semiconductor layer 31 has a region 31i that functions as a channel-forming region and a pair of regions 31n that function as low-resistance regions, flanking the region 31i. One of the pair of regions 31n functions as a source and the other as a drain. The insulating layer 51 is provided covering the semiconductor layer 31, and a portion of it functions as a gate insulating layer. The conductive layer 22 is provided on the insulating layer 51, and a portion of it functions as a gate electrode. The conductive layer 22 has a portion that overlaps with region 31i of the semiconductor layer 31. The insulating layer 52 functions as an interlayer insulating layer and is provided covering the insulating layer 51 and the conductive layer 22. The pair of conductive layers 21 are each provided on the insulating layer 52. At the contact portion 41, the conductive layer 21 is electrically connected to region 31i through openings provided in the insulating layer 52 and the insulating layer 51. A portion of the conductive layer 21 functions as either a source electrode or a drain electrode.

[0085] The semiconductor layer 31 preferably has a metal oxide (oxide semiconductor) with a larger band gap than silicon. This makes it possible to realize a transistor with low off-current. In particular, the semiconductor layer 31 preferably has a metal oxide containing one or both of indium and zinc.

[0086] Alternatively, the semiconductor layer 31 may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystal silicon).

[0087] In Figure 5, transistor 10 is shown as a so-called top-gate type transistor, where the gate electrode is located above the semiconductor layer 31. However, the structure of the transistor is not limited to this, and various configurations can be used. For example, bottom-gate type transistors or dual-gate type transistors can be applied to the display device.

[0088] The following describes transistors and pixel circuits, etc., fabricated by combining the transistor 10 shown in Figure 5 as the basic configuration. Unless otherwise specified, components formed on the same plane using the same process will be denoted by the same reference numerals. For example, a conductive layer that partially functions as a gate electrode and a conductive layer formed in the same process as the said conductive layer and functioning as wiring will be denoted by the same reference numerals.

[0089] Figure 6A shows the circuit diagrams of transistors 10a and 10b as described below. Transistors 10a and 10b are composed of four transistors 10 connected in series and sharing a common gate. Each transistor 10 has a channel formation region in an island-shaped semiconductor layer 31.

[0090] Figure 6B shows an example of a schematic top view of transistor 10a. Figure 6C shows a schematic cross-sectional view along the cutting line A1-A2 in Figure 6A. Transistor 10a has four conductive layers 22, which function as gate electrodes, arranged at equal intervals on an island-shaped semiconductor layer 31, separated by an insulating layer 51.

[0091] The four conductive layers 22 are electrically connected via conductive layer 21. The conductive layers 22 and conductive layer 21 are electrically connected at the contact portion 42. This constitutes four transistors connected in series. Although this example shows four conductive layers 22 connected by conductive layer 21, a single conductive layer 22 with a comb-shaped top surface may also be used.

[0092] A pair of conductive layers 21 are provided at both ends of the semiconductor layer 31 in the longitudinal direction, electrically connected to region 31n. A conductive layer 21 may also be provided in the region between two adjacent conductive layers 22.

[0093] Figure 6D shows a schematic top view of transistor 10b. Figure 6E shows a schematic cross-sectional view along the cutting line A3-A4 in Figure 6D. Transistor 10b has a configuration in which two semiconductor layers 31, spaced apart and symmetrically arranged (in this case, vertically symmetrically), are connected by a conductive layer 21. In addition, two conductive layers 22, spaced apart and symmetrically arranged (in this case, horizontally symmetrically), are positioned so as to intersect with the two semiconductor layers 31. This configuration allows for a reduction in the occupied area.

[0094] Figure 7A shows the circuit diagram of transistor 10c. Transistor 10c is composed of four transistors 10 connected in parallel, each sharing a gate, source, and drain.

[0095] Figure 7B shows an example of a schematic top view of transistor 10c. Figure 7C shows a schematic cross-sectional view along the cutting line A5-A6 in Figure 7B. Transistor 10c has one conductive layer 22 intersecting four island-shaped semiconductor layers 31 that are arranged at equal intervals. The conductive layer 21 is connected at both ends of each of the four island-shaped semiconductor layers 31.

[0096] Figure 7D shows the circuit diagram of transistor 10d. Transistor 10d has four transistors with a common gate. In addition, two of the four transistors are connected in series.

[0097] Figure 7E shows an example of a schematic top view of transistor 10d. Transistor 10d has the same configuration as in Figure 6D, except that the shape of the conductive layer 21 is different. The two semiconductor layers 31 are provided with a pair of conductive layers 21 connected to both ends. Each pair of conductive layers 21 electrically connects two semiconductor layers.

[0098] Although examples of transistors 10a to 10d show a configuration with four transistors 10, the system is not limited to this configuration, and can have two, three, or five or more transistors 10.

[0099] [Layout method example] The following describes an example layout when combining transistors with approximately equal channel length and channel width.

[0100] Figure 8A shows the basic configuration. In Figure 8A, multiple semiconductor layers 31, whose longitudinal direction is parallel to the X direction, are arranged at equal intervals in the Y direction. Furthermore, multiple conductive layers 22, whose longitudinal direction is parallel to the Y direction, are arranged at equal intervals in the X direction. The intersection of the conductive layers 22 and the semiconductor layers 31 becomes the channel formation region (region 31i) of the transistor.

[0101] Here, let Py be the spacing of the semiconductor layer 31 in the Y direction. Also, let Px be the spacing of the conductive layer 22 in the X direction.

[0102] Furthermore, as shown in Figure 8A, it is preferable that the semiconductor layer 31 is processed such that the width in the Y direction of the region located between the two conductive layers 22 is larger than the width of the region overlapping with the conductive layers 22. This increases the area of ​​the contact portion 41 between the semiconductor layer 31 and the conductive layers 21, thereby reducing the resistance between them (also called contact resistance or contact resistance).

[0103] Using the layout shown in Figure 8A as a basic configuration, by dividing the semiconductor layer 31 extending in the X direction, dividing the conductive layer 22 extending in the Y direction, and connecting the semiconductor layers 31 to each other, the conductive layers 22 to each other, or the semiconductor layer 31 and the conductive layer 22 with the conductive layer 21, transistors 10 with approximately equal channel length and channel width can be combined to construct transistors of various sizes or various circuits.

[0104] Figure 8B shows an example of an application of the layout in Figure 8A. Figure 8B shows transistors 10e, 10f, 10g, and 10h, among others.

[0105] Transistor 10e is a single transistor. Transistors 10f and 10g are each configured with two transistors connected in series. Transistor 10h is configured with four transistors connected in two parallel and two series, similar to transistor 10e shown in Figure 7E.

[0106] Figure 8B shows multiple conductive layers 21. As shown in Figure 8B, it is preferable to arrange the conductive layers 21 at as equal intervals as possible. This reduces variations in the processed shape of the conductive layers 21. Figure 8B shows an example where the spacing between the conductive layers 21 is the same as the spacing between the conductive layers 22, Px.

[0107] Furthermore, dummy layers may be placed in areas where transistors are not located. For example, electrically floating semiconductor layers 31, conductive layers 22, or conductive layers 21 may be placed in the empty spaces. A dummy layer is a layer provided in empty spaces for purposes such as stabilizing the manufacturing process and reducing processing variations, and is basically not considered as a component of the circuit. Therefore, dummy layers are either electrically floating or have a constant voltage applied to them. It is also preferable to provide dummy layers in layers other than semiconductor layers.

[0108] Furthermore, as shown in Figure 8B, multiple dummy transistors 11 may be arranged. A dummy transistor is a transistor that has a stacked structure that functions as a transistor, and in which one or more of its gate, drain, or source are electrically floating.

[0109] In this way, by placing dummy transistors 11 in areas where transistors are not provided, variations in the processed shapes of the semiconductor layer 31 and the conductive layer 22 can be reduced, and variations in the electrical characteristics of the transistors can be reduced.

[0110] [Example of pixel configuration] The following describes specific examples of pixel configurations.

[0111] [Configuration Example 1] Figure 9 shows a schematic top view of a pixel 20 in the display device. The pixel 20 has sub-pixels 20R, 20G, and 20B. The display device has multiple pixels 20, which are arranged periodically in the X and Y directions.

[0112] Sub-pixel 20R has an element-emitting element 12R that emits red light. Sub-pixel 20G has an element-emitting element 12G that emits green light. Sub-pixel 20B has an element-emitting element 12B that emits blue light.

[0113] The light-emitting elements 12R, 12G, and 12B may each contain different light-emitting materials, or they may each be configured as a combination of a white-emitting light-emitting element and a color filter, or they may each be configured as a combination of a blue or purple light-emitting element and a color conversion material (such as a quantum dot).

[0114] Figures 10A to 10E show schematic top views of a single sub-pixel 20X extracted from the pixel 20 shown in Figure 9. Sub-pixel 20X can be applied to sub-pixels 20R, 20G, and 20B. Note that the light-emitting element is omitted in this diagram.

[0115] In Figure 10B, the pixel electrode 24 shown in Figure 10A is indicated only by its outline with a dashed line, and an example of the upper surface shape of the conductive layer 23 is shown.

[0116] The wiring formed by the conductive layer 23 functions as a power supply line to the light-emitting element 12R, etc., and is supplied with a constant potential. When the pixel electrode 24 functions as an anode, a high power supply potential is supplied to the wiring, and when it functions as a cathode, a low power supply potential is supplied.

[0117] As shown in Figure 10B, it is preferable that the conductive layer 23, which functions as wiring, has portions that extend not only in the Y direction but also in the X direction. This allows the conductive layer 23 to have a grid-like top surface shape, which suppresses the effects of voltage drop compared to the case where the top surface shape is striped.

[0118] In Figure 10C, the conductive layer 23 in Figure 10B is shown only as a dashed outline. Similarly, in Figure 10D, the conductive layer 21 in Figure 10C is shown only as a dashed outline. Furthermore, in Figure 10E, the conductive layer 22 in Figure 10D is shown only as a dashed outline.

[0119] Figures 10C and 10D show transistors 30a and 30b. Figure 10D also shows the semiconductor layer 31a of transistor 30a and the semiconductor layer 31b of transistor 30b. Transistor 30a functions as a selection transistor, controlling the selection and deselection of subpixels. Transistor 30b functions as a drive transistor, controlling the current flowing through the light-emitting element.

[0120] In transistor 30a, a conductive layer 22, which functions as a gate line, constitutes part of the gate. One of the source and drain is electrically connected to a conductive layer 21, which functions as a source line, and the other is electrically connected to the gate of transistor 30b. In transistor 30b, one of the source and drain is electrically connected to a conductive layer 23, and the other is electrically connected to a pixel electrode 24.

[0121] Here, transistor 30b is composed of four transistors connected in series and sharing a common gate. Transistor 30b can be treated as a single transistor with a channel length four times that of transistor 30a and a channel width equal to that of transistor 30a. Transistor 30b has four channel-forming regions in a single island-shaped semiconductor layer 31b.

[0122] Here, we show an example in which the upper surface shapes of the semiconductor layer 31a and the semiconductor layer 31b each have a pair of thick portions where contact portions are arranged and a thin portion that is formed as a channel.

[0123] Furthermore, in the sub-pixel 20X, the semiconductor layer 31a of transistor 30a and the semiconductor layer 31b of transistor 30b are arranged such that current flows in the Y direction, that is, parallel to the extension direction of the conductive layer 21 which functions as a source line. In other words, transistors 30a and 30b are arranged such that the channel length direction is parallel to the Y direction and the channel width direction is parallel to the X direction. Aligning the direction of current flow for multiple transistors constituting a pixel in this way is preferable because it simplifies the design.

[0124] Here, it is preferable that multiple dummy layers 32 are provided, as shown in Figure 10D and other figures. The dummy layers 32 can be formed by processing the same film as semiconductor layers 31a and 31b, and can have the same composition as them. In Figures 10A to 10E, different hatching patterns are applied to the semiconductor layers 31a and 31b and the dummy layers 32 to distinguish them.

[0125] The top surface shape of the dummy layer 32 is preferably the same as the top surface shape of the semiconductor layer 31a and semiconductor layer 31b, or a shape that periodically combines them. In the sub-pixel 20X, one of the dummy layers 32 has a top surface shape having two or more thick portions and a thin portion connecting the two thick portions in the Y direction. Each dummy layer 32 is arranged so that its longitudinal direction is parallel to the Y direction. Also, one dummy layer 32 is arranged across multiple pixels arranged in the Y direction.

[0126] In this way, by placing the dummy layer 32 in the region where semiconductor layers 31a and 31b are not provided, variations in the processed shape of semiconductor layers 31a and 31b can be reduced, and variations in the electrical characteristics of transistors 30a and 30b can be reduced.

[0127] It is preferable to arrange the dummy layer 32 so as much as possible in the areas where semiconductor layers 31a and 31b are not provided. In the sub-pixel 20X, an example is shown in which the dummy layer 32 is placed while avoiding the area where the conductive layer 21 is provided, but the dummy layer 32 may also be placed overlapping the conductive layer 21.

[0128] In this example, two transistors are shown in a single sub-pixel, but the configuration is not limited to this, and configurations with three or more transistors are also possible. In this case, it is preferable that the semiconductor layer has the same pattern for all transistors provided in the sub-pixel, and that the direction of the current flowing through the semiconductor layer is aligned.

[0129] [Configuration Example 2] The following describes configuration examples that differ in some aspects from those described above, with reference to the drawings. Note that explanations of parts that overlap with those described above may be omitted. Furthermore, in the drawings shown below, configurations with the same function will be given the same hatching pattern and reference numerals, and explanations may be omitted.

[0130] Figure 11 shows a schematic top view of the display device illustrated below. In the display device shown in Figure 11, the wiring such as source lines and power lines extending in the Y direction is made of conductive layer 23, and the wiring such as gate lines extending in the X direction is made of conductive layer 21.

[0131] Figures 12A to 12E show schematic top views of the sub-pixel 20X. The display device illustrated below differs from the display device illustrated in Configuration Example 1 above in that the orientation of the semiconductor layer is different and that it has four transistors. The sub-pixel 20X shown in Figures 11 and 12A to 12E corresponds to the pixel circuit illustrated in Figure 3A, for example.

[0132] As shown in Figures 12C and 12D, the sub-pixel 20X has transistors 30a, 30b, 30c, and 30d. Transistors 30a, 30c, and 30d are each composed of a single transistor. Transistor 30b has a configuration in which six transistors are connected in series. Transistor 30b has two channel formation regions in each of the three semiconductor layers 31b arranged at equal intervals in the Y direction.

[0133] Furthermore, the dummy layer 32 is arranged so that its longitudinal direction is parallel to the X direction. The dummy layer 32 is arranged across multiple pixels that are aligned in the X direction.

[0134] Furthermore, in Figure 12D and other figures, a dummy layer 29, which is formed in the same process as the conductive layer 22 and is electrically floating, is shown with a different hatching pattern to distinguish it from the conductive layer 22, which functions as a gate electrode or wiring.

[0135] The sub-pixel 20X has a plurality of dummy transistors 11, which are composed of dummy layers 32 and 29.

[0136] The above is an explanation of examples of pixel configurations.

[0137] [Example of cross-sectional configuration] Next, an example of a cross-sectional configuration of a display device according to one aspect of the present invention will be described.

[0138] [Cross-sectional configuration example 1] Figure 13 is a schematic cross-sectional view of the display device 200A. The display device 200A has light-emitting elements 250R, 250G, transistors 210, 220, and capacitive elements 240 between substrates 201 and 202.

[0139] The transistor 210 is a transistor in which a channel formation region is formed on a substrate 201. The substrate 201 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 210 includes a portion of the substrate 201, a conductive layer 211, a low-resistance region 212, an insulating layer 213, an insulating layer 214, etc. The conductive layer 211 functions as a gate electrode. The insulating layer 213 is located between the substrate 201 and the conductive layer 211 and functions as a gate insulating layer. The low-resistance region 212 is a region of the substrate 201 doped with impurities and functions as either a source or a drain. The insulating layer 214 is provided covering the side surface of the conductive layer 211.

[0140] Furthermore, an element isolation layer 215 is provided between two adjacent transistors 210 so as to be embedded in the substrate 201.

[0141] A wiring layer 203 is provided between transistors 210 and 220. The wiring layer 203 has a structure in which layers with one or more wirings are stacked. Each layer has a conductive layer 271, and an interlayer insulating layer 273 is provided between two layers. Furthermore, a plug 272 provided in the interlayer insulating layer 273 electrically connects the conductive layers 271 of different layers.

[0142] A transistor 220 is provided on the wiring layer 203. The transistor 220 is a transistor in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed.

[0143] The transistor 220 includes a semiconductor layer 221, an insulating layer 223, a conductive layer 224, a pair of conductive layers 225, an insulating layer 226, a conductive layer 227, and the like.

[0144] An insulating layer 231 is provided on the wiring layer 203. The insulating layer 231 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the wiring layer 203 side to the transistor 220, and prevents oxygen from detaching from the semiconductor layer 221 to the wiring layer 203 side. As the insulating layer 231, for example, a film that is less permeable to hydrogen or oxygen than a silicon oxide film, such as an aluminum oxide film, hafnium oxide film, or silicon nitride film, can be used.

[0145] A conductive layer 227 is provided on an insulating layer 231, and an insulating layer 226 is provided covering the conductive layer 227. The conductive layer 227 functions as the first gate electrode of the transistor 220, and a portion of the insulating layer 226 functions as the first gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, for at least the portion of the insulating layer 226 that is in contact with the semiconductor layer 221.

[0146] The semiconductor layer 221 is provided on the insulating layer 226. Preferably, the semiconductor layer 221 has a metal oxide (also called an oxide semiconductor) film having semiconductor properties.

[0147] When the semiconductor layer 221 is an In-M-Zn oxide, possible atomic ratios of metal elements in the sputtering target used to deposit the In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc.

[0148] Furthermore, using a target containing a polycrystalline oxide as the sputtering target is preferable because it facilitates the formation of a crystalline semiconductor layer 221. The atomic ratio of the deposited semiconductor layer 221 includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 221 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the deposited semiconductor layer 221 may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0149] Furthermore, when the atomic ratio is stated as In:Ga:Zn=4:2:3 or nearby, it includes the case where, when In is set to 4, Ga is between 1 and 3, and Zn is between 2 and 4. Also, when the atomic ratio is stated as In:Ga:Zn=5:1:6 or nearby, it includes the case where, when In is set to 5, Ga is greater than 0.1 and 2 or less, and Zn is between 5 and 7. Also, when the atomic ratio is stated as In:Ga:Zn=1:1:1 or nearby, it includes the case where, when In is set to 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0150] Furthermore, the semiconductor layer 221 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wider energy gap than silicon in this way, the off-current of the transistor can be reduced.

[0151] Furthermore, the semiconductor layer 221 is preferably a non-single-crystal structure. Non-single-crystal structures include, for example, the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Among non-single-crystal structures, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density.

[0152] The following section describes CAAC (c-axis aligned crystal). CAAC represents one example of a crystal structure.

[0153] CAAC structure is a type of crystalline structure found in thin films and other materials that have multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). In this structure, each nanocrystal has its c-axis oriented in a specific direction, while its a-axis and b-axis are not oriented, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films with a CAAC structure tend to have the c-axis of each nanocrystal oriented in the direction of the film's thickness, the direction normal to the surface it is formed on, or the direction normal to the surface of the film.

[0154] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. Furthermore, because clear grain boundaries cannot be observed in CAAC-OS, it is less susceptible to the reduction in electron mobility caused by grain boundaries. Also, since the crystallinity of oxide semiconductors can decrease due to impurities and defects, CAAC-OS can be considered an oxide semiconductor with fewer impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Consequently, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable.

[0155] In crystallography, it is common to define a unit cell with a specific axis designated as the c axis, among the three axes (crystal axes) a, b, and c that constitute the unit cell. In particular, in crystals with a layered structure, it is common to define the two axes parallel to the plane direction of the layer as the a and b axes, and the axis intersecting the layer as the c axis. A typical example of such a layered crystal is graphite, which is classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the cleavage planes, and the c axis is perpendicular to the cleavage planes. For example, the crystal of InGaZnO4, which has a layered YbFe2O4 type crystal structure, can be classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0156] In oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films), the crystalline regions may not be clearly visible in TEM observation images. The crystalline regions in microcrystalline oxide semiconductor films are often between 1 nm and 100 nm in size, or between 1 nm and 10 nm. In particular, oxide semiconductor films containing nanocrystals (nc) that are microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm, are called nc-OS (nanocrystalline oxide semiconductor) films. Furthermore, in nc-OS films, the grain boundaries may not be clearly visible in TEM observation images, for example.

[0157] nc-OS films exhibit periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). Furthermore, nc-OS films show no regularity in crystal orientation between different crystalline regions. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. For example, when structural analysis of an nc-OS film is performed using an XRD instrument with an X-ray diameter larger than that of the crystalline region, out-of-plane analysis does not detect peaks indicating crystal planes. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the crystalline region (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal region (for example, 1 nm to 30 nm), a region of high brightness is observed in a circular (ring-shaped) pattern, and multiple spots may be observed within this ring-shaped region.

[0158] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-OS films lack regularity in crystal orientation between different crystalline regions. Therefore, nc-OS films have a higher defect level density compared to CAAC-OS films. Consequently, nc-OS films may have a higher carrier density and higher electron mobility compared to CAAC-OS films. Therefore, transistors using nc-OS films may exhibit high field-effect mobility.

[0159] nc-OS films can be formed by reducing the oxygen flow rate ratio during deposition compared to CAAC-OS films. Furthermore, nc-OS films can also be formed by lowering the substrate temperature during deposition compared to CAAC-OS films. For example, nc-OS films can be deposited at relatively low substrate temperatures (e.g., below 130°C) or even without heating the substrate, making them suitable for use with large glass or resin substrates and increasing productivity.

[0160] An example of a metal oxide crystal structure is described below. Metal oxides formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) at a substrate temperature between 100°C and 130°C tend to adopt either an nc (nano crystal) structure or a CAAC structure, or a mixed structure of both. On the other hand, metal oxides formed at room temperature (RT) tend to adopt an nc crystal structure. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0161] A pair of conductive layers 225 are provided in contact with the semiconductor layer 221 and function as source and drain electrodes.

[0162] Furthermore, an insulating layer 232 is provided covering the top and side surfaces of the pair of conductive layers 225, as well as the side surfaces of the semiconductor layer 221, and an insulating layer 261 is provided on top of the insulating layer 232. The insulating layer 232 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 221 from the interlayer insulating layer, and prevents oxygen from detaching from the semiconductor layer 221. An insulating film similar to that used for the insulating layer 231 can be used for the insulating layer 232.

[0163] The insulating layer 232 and the insulating layer 261 are provided with openings that reach the semiconductor layer 221. Inside these openings, an insulating layer 223 is embedded in contact with the insulating layer 261, the insulating layer 232, the sides of the conductive layer 225, and the upper surface of the semiconductor layer 221, and a conductive layer 224 is embedded on the insulating layer 223. The conductive layer 224 functions as a second gate electrode, and the insulating layer 223 functions as a second gate insulating layer.

[0164] The upper surfaces of the conductive layer 224, the insulating layer 223, and the insulating layer 261 are flattened so that their heights are approximately the same, and the insulating layer 233 is provided covering them. An opening is provided in the laminated structure between the insulating layer 233 and the insulating layer 231, and a portion of the insulating layer 233 is in contact with the insulating layer 231 at this opening. The insulating layer 261 functions as an interlayer insulating layer. The insulating layer 233 also functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from above. As the insulating layer 233, an insulating film similar to that of the insulating layer 231 can be used.

[0165] A capacitive element 240 is provided on the insulating layer 233.

[0166] The capacitive element 240 has a conductive layer 241, a conductive layer 242, and an insulating layer 243 located between them. The conductive layer 241 functions as one electrode of the capacitive element 240, the conductive layer 242 functions as the other electrode of the capacitive element 240, and the insulating layer 243 functions as the dielectric of the capacitive element 240.

[0167] An insulating layer 234 is provided covering the capacitive element 240. The insulating layer 234 can be made of the same insulating film as the insulating layer 231. An insulating layer 262 is provided on the insulating layer 231 via an interlayer insulating layer and wiring, and light-emitting elements 250R and 250G are provided on the insulating layer 262.

[0168] The light-emitting element 250R includes a conductive layer 251, a conductive layer 252R, an EL layer 253W, and a conductive layer 254, etc.

[0169] The conductive layer 251 is reflective to visible light, and the conductive layer 252R is transparent to visible light. The conductive layer 254 is both reflective and transparent to visible light. The conductive layer 252R functions as an optical adjustment layer to adjust the optical distance between the conductive layer 251 and the conductive layer 254. The optical adjustment layer can have different thicknesses between light-emitting elements with different emission colors. The conductive layer 252R on the light-emitting element 250R and the conductive layer 252G on the light-emitting element 250G have different thicknesses.

[0170] An insulating layer 256 is provided to cover the ends of the conductive layer 252R and the ends of the conductive layer 252G.

[0171] The EL layer 253W and the conductive layer 254 are provided in common across multiple pixels. The EL layer 253W has an emissive layer that emits white light.

[0172] An insulating layer 235 is provided covering the light-emitting elements 250R and 250G, etc. The insulating layer 235 functions as a barrier film that prevents impurities such as water from diffusing to the light-emitting elements 250R and 250G, etc. The insulating layer 235 can be made of the same film as the insulating layer 231.

[0173] A lens array 257 is provided on the light-emitting element 250R and on the light-emitting element 250G via an adhesive layer 263. Light emitted from the light-emitting element 250R is focused by the lens array 257, colored by the coloring layer 255R, and emitted to the outside. The lens array 257 may be omitted if it is not needed.

[0174] Furthermore, a colored layer 255R, a colored layer 255G, and a colored layer 255B are provided on the lens array 257 via an insulating layer 264. A colored layer 255R is provided on the light-emitting element 250R via the lens array 257. A colored layer 255G is also provided on the light-emitting element 250G. In addition, a portion of the colored layer 255B is shown in Figure 13.

[0175] For example, the colored layer 255R transmits red light, the colored layer 255G transmits green light, and the colored layer 255B transmits blue light. This increases the color purity of the light from each light-emitting element, enabling the creation of a display device with higher display quality.

[0176] The display device 200A has a substrate 202 on the viewing side. Substrate 202 and substrate 201 are bonded together. As substrate 202, a translucent substrate such as a glass substrate, quartz substrate, sapphire substrate, or plastic substrate can be used.

[0177] The colored layers 255R, 255G, and 255B are formed on the substrate 201 side of the substrate 202. An insulating layer 264 is provided covering the colored layers 255R, etc., and a lens array 257 is provided on the substrate 201 side of the insulating layer 264. The substrate 202, on which the colored layers 255R, 255G, 255B, and lens array 257 are provided, is bonded to the substrate 201 by an adhesive layer 263. By forming the colored layers 255R, 255G, 255B, and lens array 257 on the substrate 202 side in this way, the temperature of the heat treatment in the formation process can be increased.

[0178] In this example, the colored layers 255R, 255G, 255B, and lens array 257 were formed on the substrate 202 side. However, the colored layers and lens array 257 may also be formed on the insulating layer 235. In that case, the alignment accuracy between each light-emitting element and each colored layer can be improved compared to the case where the colored layers are formed on the substrate 202 side before bonding the substrate 201 and substrate 202 together.

[0179] This configuration makes it possible to realize a display device with extremely high resolution and high display quality.

[0180] [Cross-sectional configuration example 2] Figure 14 shows a schematic cross-sectional view of display device 200B, which has some configuration differences from display device 200A.

[0181] Display device 200B shows an example where the EL layer 253W is divided on an insulating layer 256 located between two light-emitting elements. Dividing the EL layer 253W prevents leakage current from occurring between the light-emitting elements via the EL layer 253W. This is preferable because it prevents unintended light emission and improves contrast and color reproduction.

[0182] The EL layer 253W may be divided by a deposition method using a fine metal mask, but it is preferable that it be finely processed by a photolithography method.

[0183] [Cross-sectional configuration example 3] Figure 15 is a schematic cross-sectional view of the display device 200C.

[0184] The light-emitting element 250R has an EL layer 253R that emits red light. The light-emitting element 250G has an EL layer 253G that emits green light.

[0185] Furthermore, this example shows a display device 200C that does not have a colored layer.

[0186] Furthermore, the EL layer 253R and the EL layer 253G are processed so that they do not come into contact with each other between two adjacent light-emitting elements. In other words, the ends of the EL layer 253R and the ends of the EL layer 253G are positioned opposite each other on the insulating layer 256 between two adjacent light-emitting elements. The EL layer 253R and the EL layer 253G may be fabricated separately by a deposition method using a fine metal mask, but it is preferable that they are each finely processed by a photolithography method.

[0187] Furthermore, an insulating layer 258 is provided between the light-emitting element 250R and the light-emitting element 250G, in contact with the side surface of the EL layer 253R, the side surface of the conductive layer 252R, the side surfaces of the pair of conductive layers 251, the upper surface of the insulating layer 262, the side surface of the conductive layer 252G, and the side surface of the EL layer 253G. The insulating layer 258 can be made of a material with low water permeability, and an insulating film similar to that of the insulating layer 231 can be used. In particular, it is preferable to use an inorganic insulating film formed by the ALD method. It is even more preferable to use an aluminum oxide film formed by the ALD method.

[0188] Furthermore, a resin layer 259 is provided on the insulating layer 258 to fill the recesses located between adjacent pixels. The resin layer 259 functions as a planarizing film and has the function of improving the coverage of the film (e.g., conductive layer 254) formed on it.

[0189] Here, we show the case where the thicknesses of conductive layer 252R and conductive layer 252G, which function as optical adjustment layers, are different, but the optical adjustment layers of each light-emitting element may be the same thickness. In this case, it is preferable to use a part of the EL layer as an optical adjustment layer and control the optical path length by its thickness. Furthermore, conductive layer 252R and conductive layer 252G, etc., may not be provided.

[0190] [Cross-sectional configuration example 4] Figure 16 is a schematic cross-sectional view of the display device 200D. The display device 200D differs from the display device 200C mainly in that it does not have a transistor 210.

[0191] An insulating layer 231 is provided on the substrate 201, and a transistor 220 is provided on the insulating layer 231. However, if there is no risk of impurities diffusing from the substrate 201, the insulating layer 231 may be omitted.

[0192] As the substrate 201, it is preferable to use a substrate with a low coefficient of thermal expansion. For example, it is preferable to use a single-crystal semiconductor substrate such as single-crystal silicon or silicon carbide, or a high-melting-point insulating substrate such as sapphire or quartz.

[0193] The above is an explanation of the cross-sectional configuration examples.

[0194] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0195] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0196] (Embodiment 2) In this embodiment, a light-emitting element (also called a light-emitting device) and a light-receiving element (also called a light-receiving device) that can be used in a light-receiving device according to one aspect of the present invention will be described.

[0197] In this specification, devices fabricated using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or an FMM may be referred to as MML (Metal Maskless) structured devices.

[0198] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. A white light-emitting device can be combined with a colored layer (for example, a color filter) to create a full-color display device.

[0199] [Light-emitting devices] Furthermore, light-emitting devices can be broadly classified into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. To obtain white light emission in a single-structure device, one should select light-emitting layers such that the light emitted from each of the two or more layers is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0200] A tandem device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. By using light-emitting layers that emit light of the same color in each light-emitting unit, the brightness per given current can be increased, and a more reliable light-emitting device can be achieved compared to a single structure. To obtain white light emission in a tandem structure, the light from the light-emitting layers of multiple light-emitting units can be combined to produce white light emission. The combination of light-emitting colors that produces white light emission is the same as that for a single structure. In a tandem device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0201] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem structure) with SBS structure light-emitting devices, SBS structure light-emitting devices can consume less power than white light-emitting devices. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting devices. On the other hand, white light-emitting devices are preferable because their manufacturing process is simpler than that of SBS structure light-emitting devices, which can lead to lower manufacturing costs or higher manufacturing yields.

[0202] <Example of light-emitting device configuration> As shown in Figure 17A, the light-emitting device has an EL layer 790 between a pair of electrodes (lower electrode 791, upper electrode 792). The EL layer 790 can be composed of multiple layers, such as layer 720, light-emitting layer 711, and layer 730. Layer 720 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). The light-emitting layer 711 may include, for example, a light-emitting compound. Layer 730 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0203] A configuration having a layer 720, an emissive layer 711, and a layer 730 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 17A is referred to as a single structure.

[0204] Furthermore, Figure 17B shows a modified example of the EL layer 790 of the light-emitting device shown in Figure 17A. Specifically, the light-emitting device shown in Figure 17B includes a layer 730-1 on the lower electrode 791, a layer 730-2 on layer 730-1, a light-emitting layer 711 on layer 730-2, a layer 720-1 on the light-emitting layer 711, a layer 720-2 on layer 720-1, and an upper electrode 792 on layer 720-2. For example, when the lower electrode 791 is the anode and the upper electrode 792 is the cathode, layer 730-1 functions as a hole injection layer, layer 730-2 functions as a hole transport layer, layer 720-1 functions as an electron transport layer, and layer 720-2 functions as an electron injection layer. Alternatively, if the lower electrode 791 is used as the cathode and the upper electrode 792 as the anode, layer 730-1 functions as an electron injection layer, layer 730-2 functions as an electron transport layer, layer 720-1 functions as a hole transport layer, and layer 720-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 711 and increase the efficiency of carrier recombination within the light-emitting layer 711.

[0205] Furthermore, as shown in Figures 17C and 17D, a configuration in which multiple light-emitting layers (light-emitting layers 711, 712, and 713) are provided between layer 720 and layer 730 is also a variation of the single structure.

[0206] Furthermore, as shown in Figures 17E and 17F, a configuration in which multiple light-emitting units (EL layers 790a and EL layers 790b) are connected in series via an intermediate layer (charge generation layer) 740 is referred to as a tandem structure in this specification. In this specification, the configuration shown in Figures 17E and 17F is referred to as a tandem structure, but it is not limited to this, and for example, a tandem structure may also be called a stack structure. By using a tandem structure, a light-emitting device capable of high-brightness light emission can be made.

[0207] In Figure 17C, the light-emitting layers 711, 712, and 713 may be made of the same light-emitting material.

[0208] Furthermore, different light-emitting materials may be used for the light-emitting layers 711, 712, and 713. When the light emitted by the light-emitting layers 711, 712, and 713 are complementary in color, white light emission is obtained. Figure 17D shows an example in which a colored layer 795, which functions as a color filter, is provided. By passing white light through the color filter, light of the desired color can be obtained.

[0209] Furthermore, in Figure 17E, the same light-emitting material may be used for both the light-emitting layer 711 and the light-emitting layer 712. Alternatively, light-emitting materials that emit different types of light may be used for both the light-emitting layer 711 and the light-emitting layer 712. When the light emitted by the light-emitting layer 711 and the light emitted by the light-emitting layer 712 are complementary colors, white light emission is obtained. Figure 17F shows an example in which a colored layer 795 is further provided.

[0210] Furthermore, in Figures 17C, 17D, 17E, and 17F, as shown in Figure 17B, layer 720 and layer 730 may be a laminated structure consisting of two or more layers.

[0211] Furthermore, in Figure 17D, the same light-emitting material may be used for light-emitting layers 711, 712, and 713. Similarly, in Figure 17F, the same light-emitting material may be used for light-emitting layers 711 and 712. In this case, by applying a color conversion layer instead of the colored layer 795, it is possible to obtain light of a desired color different from that of the light-emitting material. For example, by using a blue light-emitting material for each light-emitting layer, blue light can pass through the color conversion layer to obtain light with a longer wavelength than blue (e.g., red, green, etc.). Fluorescent materials, phosphorescent materials, or quantum dots can be used as the color conversion layer.

[0212] The light-emitting color of the light-emitting device can be red, green, blue, cyan, magenta, yellow, or white, depending on the material that makes up the EL layer 790. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the light-emitting device.

[0213] A light-emitting device that emits white light preferably has a configuration that includes two or more types of light-emitting materials in its light-emitting layer. To obtain white light emission, it is sufficient to select light-emitting materials such that the light emitted by each of the two or more materials is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a light-emitting device that emits white light as a whole can be obtained. The same applies to light-emitting devices that have three or more light-emitting layers.

[0214] The light-emitting layer preferably contains two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable to have two or more light-emitting materials, and for each light-emitting material to emit light that contains spectral components of two or more colors from R, G, and B.

[0215] [Light-emitting devices] Here, we will describe a specific example of the configuration of a light-emitting device.

[0216] The light-emitting device has at least a light-emitting layer. The light-emitting device may also have layers other than the light-emitting layer that include a material with high hole injection properties, a material with high hole transport properties, a hole-blocking material, a material with high electron transport properties, an electron-blocking material, a material with high electron injection properties, or a bipolar material (a material with high electron transport and hole transport properties).

[0217] The light-emitting device may use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting device can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0218] For example, a light-emitting device may have a configuration that includes, in addition to the light-emitting layer, one or more layers from among a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0219] The hole injection layer is a layer that injects holes from the anode into the hole transport layer, and is a layer containing a material with high hole injection capabilities. Examples of materials with high hole injection capabilities include aromatic amine compounds and composite materials containing hole transport materials and acceptor materials (electron-accepting materials).

[0220] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. The hole transport layer is a layer containing a hole-transporting material. The hole-transporting material is 1 × 10⁻¹⁶ -6 cm 2 Materials having a hole mobility of / Vs or higher are preferred. However, other materials can also be used as long as they have higher hole transport capabilities than electron transport. Preferred hole transport materials include π-electron-rich heteroaromatic compounds (e.g., carbazole derivatives, thiophene derivatives, furan derivatives, etc.) and aromatic amines (compounds having an aromatic amine skeleton), which are materials with high hole transport capabilities.

[0221] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. The electron transport layer is a layer containing an electron-transporting material. The electron-transporting material is 1 × 10⁻¹⁶ -6 cm 2 Materials having an electron mobility of / Vs or higher are preferred. However, other materials can also be used as long as they have higher electron transport capabilities than holes. Examples of electron-transporting materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds containing nitrogen-containing heteroaromatic compounds.

[0222] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer, and is a layer containing a material with high electron injection capabilities. Alkali metals, alkaline earth metals, or compounds thereof can be used as materials with high electron injection capabilities. Composite materials containing both electron transport materials and donor materials (electron-donating materials) can also be used as materials with high electron injection capabilities.

[0223] Examples of electron injection layers include lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), 8-(quinolinolato)lithium (abbreviated as Liq), 2-(2-pyridyl)phenolate (abbreviated as LiPP), 2-(2-pyridyl)-3-pyridinolatritium (abbreviated as LiPPy), 4-phenyl-2-(2-pyridyl)phenolate (abbreviated as LiPPP), and lithium oxide (LiO2). xAlkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used. Furthermore, the electron injection layer may be a multilayer structure of two or more layers. For example, this multilayer structure may consist of lithium fluoride in the first layer and ytterbium in the second layer.

[0224] Alternatively, an electron-transporting material may be used as the electron injection layer described above. For example, a compound having a lone pair of electrons and an electron-deficient heteroaromatic ring can be used as the electron-transporting material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), or a triazine ring can be used.

[0225] Furthermore, it is preferable that the lowest unoccupied molecular orbital (LUMO) of an organic compound containing a lone pair of electrons is between -3.6 eV and -2.3 eV. In general, the highest occupied molecular orbital (HOMO) level and LUMO level of an organic compound can be estimated by methods such as cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, and inverse photoelectron spectroscopy.

[0226] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviated as BPhen), 2,9-bis(naphthalene-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated as NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviated as HATNA), and 2,4,6-tris[3'-(pyridine-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviated as TmPPPyTz) can be used in organic compounds containing lone pairs of electrons. Compared to BPhen, NBPhen has a higher glass transition temperature (Tg) and superior heat resistance.

[0227] The luminescent layer is a layer containing a luminescent material. The luminescent layer may contain one or more types of luminescent materials. Suitable luminescent materials include those exhibiting colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, and red. Furthermore, materials emitting near-infrared light may also be used as luminescent materials.

[0228] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0229] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0230] Examples of phosphorescent materials include organometallic complexes (especially iridium complexes) having a 4H-triazole skeleton, 1H-triazole skeleton, imidazole skeleton, pyrimidine skeleton, pyrazine skeleton, or pyridine skeleton; organometallic complexes (especially iridium complexes) using phenylpyridine derivatives having electron-withdrawing groups as ligands; platinum complexes; and rare earth metal complexes.

[0231] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of these organic compounds may be hole-transporting materials and / or electron-transporting materials. Alternatively, one or more of these organic compounds may be bipolar materials or TADF materials.

[0232] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting device.

[0233] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0234] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0235] (Embodiment 3) This embodiment describes an example of the configuration of an electronic device to which a display device according to one aspect of the present invention is applied.

[0236] A display device and display module according to one aspect of the present invention can be applied to the display section of an electronic device having a display function. Examples of such electronic devices include electronic devices with relatively large screens such as television sets, notebook personal computers, monitors, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and sound playback devices.

[0237] In particular, the display device and display module according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because they can increase the resolution. Examples of such electronic devices include wearable devices that can be worn on the head, such as wristwatch-type and bracelet-type information terminals (wearable devices), VR devices such as head-mounted displays, and AR devices such as glasses.

[0238] Figure 18A shows a perspective view of a spectacle-type electronic device 800. The electronic device 800 includes a pair of display panels 801, a pair of housings 802, a pair of optical elements 803, a pair of mounting parts 804, and the like.

[0239] The electronic device 800 can project an image displayed on the display panel 801 onto the display area 806 of the optical element 803. Furthermore, because the optical element 803 is translucent, the user can view the image displayed on the display area 806 superimposed on the transmitted image seen through the optical element 803. Therefore, the electronic device 800 is an electronic device capable of AR display.

[0240] Furthermore, one of the housings 802 is equipped with a camera 805 capable of capturing images of the area in front. Although not shown, one of the housings 802 is also equipped with a wireless receiver or a connector to which a cable can be connected, allowing video signals and the like to be supplied to the housing 802. Additionally, by equipping the housing 802 with an accelerometer such as a gyro sensor, the orientation of the user's head can be detected and an image corresponding to that orientation can be displayed in the display area 806. Preferably, the housing 802 is equipped with a battery, which can be charged wirelessly or via a wired connection.

[0241] Next, using Figure 18B, a method for projecting an image onto the display area 806 of the electronic device 800 will be described. Inside the housing 802, a display panel 801, a lens 811, and a reflector 812 are provided. In addition, the portion of the optical element 803 corresponding to the display area 806 has a reflective surface 813 that functions as a half-mirror.

[0242] Light 815 emitted from the display panel 801 passes through the lens 811 and is reflected towards the optical element 803 by the reflector 812. Inside the optical element 803, the light 815 undergoes total internal reflection repeatedly at the end face of the optical element 803 and reaches the reflective surface 813, where an image is projected. As a result, the user can see both the light 815 reflected by the reflective surface 813 and the transmitted light 816 that has passed through the optical element 803 (including the reflective surface 813).

[0243] Figure 18 shows an example where the reflector 812 and the reflective surface 813 each have curved surfaces. This increases the degree of freedom in optical design and allows for a thinner optical component 803 compared to when they are flat. However, the reflector 812 and the reflective surface 813 may also be flat.

[0244] As the reflector 812, a material having a mirror surface can be used, and it is preferable that it has a high reflectivity. Also, as the reflective surface 813, a half-mirror that utilizes the reflection of a metal film may be used, but using a prism that utilizes total internal reflection can increase the transmittance of transmitted light 816.

[0245] Here, it is preferable that the housing 802 has a mechanism for adjusting the distance between the lens 811 and the display panel 801, or the angle between them. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, one or both of the lens 811 or the display panel 801 may be configured to move in the optical axis direction.

[0246] Furthermore, it is preferable that the housing 802 has a mechanism that allows the angle of the reflector 812 to be adjusted. By changing the angle of the reflector 812, the position of the display area 806 on which the image is displayed can be changed. This makes it possible to position the display area 806 in an optimal position according to the user's eye position.

[0247] A display device or display module according to one aspect of the present invention can be applied to the display panel 801. Therefore, an electronic device 800 capable of displaying extremely high resolution can be obtained.

[0248] Figures 19A and 19B show perspective views of the goggle-type electronic device 850. Figure 19A is a perspective view showing the front, top, and left side of the electronic device 850, while Figure 19B is a perspective view showing the rear, bottom, and right side of the electronic device 850.

[0249] The electronic device 850 includes a pair of display panels 851, a housing 852, a pair of mounting parts 854, a cushioning member 855, a pair of lenses 856, and the like. The pair of display panels 851 are each provided inside the housing 852 in a position where they can be seen through the lenses 856.

[0250] The electronic device 850 is an electronic device for VR. When the user wears the electronic device 850, they can view the image displayed on the display panel 851 through the lens 856. Furthermore, by displaying different images on a pair of display panels 851, a three-dimensional display using parallax can also be performed.

[0251] Furthermore, an input terminal 857 and an output terminal 858 are provided on the rear side of the housing 852. A cable can be connected to the input terminal 857 to supply video signals from a video output device or other device, or to supply power for charging a battery located inside the housing 852. The output terminal 858 functions, for example, as an audio output terminal, and earphones, headphones, etc., can be connected to it. However, if the system is configured to output audio data via wireless communication, or if audio is output from an external video output device, the audio output terminal does not need to be provided.

[0252] Furthermore, it is preferable that the housing 852 has a mechanism that allows adjustment of the left and right positions of the lens 856 and the display panel 851 so that they are in the optimal position according to the user's eye position. It is also preferable that the housing 852 has a mechanism that adjusts the focus by changing the distance between the lens 856 and the display panel 851.

[0253] A display device or display module according to one aspect of the present invention can be applied to the display panel 851. Therefore, an electronic device 850 capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0254] The cushioning member 855 is the part that comes into contact with the user's face (forehead, cheeks, etc.). By ensuring that the cushioning member 855 is in close contact with the user's face, light leakage can be prevented, thereby enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 855 so that it comes into close contact with the user's face when the user wears the electronic device 850. For example, materials such as rubber, silicone rubber, urethane, and sponge can be used. Furthermore, if the surface of a sponge or similar material is covered with cloth, leather (genuine leather or synthetic leather), gaps are less likely to form between the user's face and the cushioning member 855, effectively preventing light leakage. In addition, using such materials is preferable because it feels good against the skin and does not make the user feel cold when worn in cold seasons. It is preferable that the components that come into contact with the user's skin, such as the cushioning member 855 or the mounting part 854, be removable, as this makes cleaning or replacement easier.

[0255] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Examples]

[0256] In this embodiment, a display device according to one aspect of the present invention was fabricated. Regarding the pixels of the fabricated display device, the pixel circuit shown in FIG. 3C in Embodiment 1 was applied. For transistors M1 to M4, transistors using an oxide semiconductor for the semiconductor in which a channel is formed were applied. For transistors M1, M3, and M4, transistors with a channel length of 200 nm and a channel width of 60 nm were applied, and for transistor M2, a configuration in which eight of these transistors were connected in series was adopted. Regarding the cross-sectional configuration of the fabricated display device, reference can be made to FIG. 14.

[0257] First, the electrical characteristics of the transistors applied to the display device are shown. The transistor has a Trench-gate-self-aligned (TGSA) structure fabricated using an LSI process node, and is formed such that a channel of an oxide semiconductor (OS) is covered from above and below by a top gate electrode and a back gate electrode. A CAAC-OS film was used for the oxide semiconductor. The measured transistor has a channel length of about 200 nm and a channel width of about 60 nm. Here, similar to those used for transistor M2, measurements were made on a device in which eight of these transistors were connected in series.

[0258] FIG. 20A shows the measured Id-Vg characteristics. FIG. 20A shows the two Id-Vg characteristics when the drain voltage is 0.1 V and 1.2 V combined. Despite being a fine transistor, as shown in FIG. 20A, it exhibits normally-off characteristics, and the off-current was below the detection limit (1×10 -12 A) of the measuring instrument.

[0259] FIG. 20B shows the Id-Vd characteristics. FIG. 20B shows the four Id-Vd characteristics when the gate voltage is 0.9 V, 1.7 V, 2.5 V, and 3.3 V combined. Despite being a fine transistor, as shown in FIG. 20B, it exhibits high saturation.

[0260] The fabricated display device has a structure in which a circuit (SiLSI) composed of Si transistors (SiFETs), a circuit (OSLSI) composed of OS transistors (OSFETs), and an OLED element are stacked. Table 1 shows the specifications of the fabricated display device. Table 1 shows the size of the display area, resolution, pixel size, pixel density, aperture ratio, pixel arrangement, colorization method, emission method, frame frequency, source driver, scan driver (gate driver), and stacking structure from top to bottom.

[0261]

Table 1

[0262] In particular, as the colorization method, the Side-by-side method was applied, in which light-emitting elements are made separately in red (R), green (G), and blue (B) using photolithography without using a metal mask. The pixel circuit was formed using OS transistors, and the driving circuits such as the source driver and scan driver were formed using Si transistors.

[0263] The display photograph of the prototype display device is shown in Fig. 21. An OS transistor with a channel length refined to 200 nm was stacked on the Si transistor, and it was confirmed that a display device with an extremely high definition of 2731 ppi can display good images.

[0264] Subsequently, the viewing angle dependence of the chromaticity of each of R, G, and B in the fabricated display device was measured. The measurement results of the viewing angle dependence are shown in Figs. 22A and 22B. The schematic diagrams of the measurement directions are also shown in Figs. 22A and 22B. Fig. 22A shows the results for the horizontal viewing angle, and Fig. 22B shows the results for the vertical viewing angle. In each figure, the horizontal axis is the angle (Horizontal viewing angle or Vertical viewing angle) when the normal direction of the display surface is 0 degrees, and the vertical axis is the ratio (Δu’v’) of the change in chromaticity when it is 0 at 0 degrees.

[0265] As shown in Figures 22A and 22B, it was confirmed that Δu'v' takes small values ​​of 0.03 or less in both the horizontal and vertical directions within a field of view of plus or minus 60 degrees.

[0266] Next, Figure 23 shows a block diagram of the drive circuit section of the fabricated display device. Here, eight source drivers with 360-channel output terminals are arranged below the display area (2x4). Each of the eight circuits is connected to the controller (CNTR) via bus wiring (BUS). In addition, the drive circuit section includes a scan driver, a 1-input, 2-output DeMUX circuit, input / output (IO), an LVDS circuit, and a debug circuit (Pixel debug).

[0267] The fabricated display device is capable of duty cycle driving as shown in Embodiment 1, Figures 3 and 4. Figure 24 shows the results of measuring the change in brightness when the fabricated display device is driven with a different duty cycle. In Figure 24, the horizontal axis is the duty cycle (Duty[%]) and the vertical axis is the brightness (Luminance[cd / m²]). 2 ]). In the figure, the dashed line represents the ideal value, and the plotted line represents the measured value. As shown in Figure 24, it was confirmed that the luminance changes linearly with respect to the duty cycle and closely matches the ideal value. Furthermore, when the duty cycle is set to 100%, the white display shows 5000 cd / m². 2 It was confirmed that the above brightness level was achieved.

[0268] One embodiment of the present invention allows for the placement of various functional circuits in addition to the drive circuit below the display area, and also enables higher functionality, a narrower bezel, a smaller chip size, and a reduction in the number of external terminals compared to conventional devices. [Explanation of Symbols]

[0269] 10: Transistor, 10a-h: Transistor, 11: Dummy transistor, 12B: Light-emitting element, 12G: Light-emitting element, 12R: Light-emitting element, 20: Pixel, 20B: Sub-pixel, 20G: Sub-pixel, 20R: Sub-pixel, 20X: Sub-pixel, 21: Conductive layer, 22: Conductive layer, 23: Conductive layer, 24: Pixel electrode, 29: Dummy layer, 30a-d: Transistor, 31: Semiconductor layer, 31a: Semiconductor layer, 31b: Semiconductor layer, 31i: Region, 31n: Region, 32: Dummy layer, 41: Contact area, 42: Contact area, 51: Insulating layer, 52: Insulating layer

Claims

1. A display device having pixels with multiple subpixels, At least one of the subpixels has a first transistor, a plurality of second transistors, and a plurality of third transistors. The first transistor has its gate electrically connected to a gate line, one of its source and drain electrically connected to the source line, and the other of its source and drain electrically connected to the gates of each of the plurality of second transistors. The plurality of the second transistors each have p transistors (where p is an integer of 2 or more) connected in series. The first transistor has a first semiconductor layer, The plurality of second transistors each have a second semiconductor layer. The plurality of third transistors each have a third semiconductor layer, The third semiconductor layer contains the same semiconductor material as the first semiconductor layer and has a portion whose upper surface shape is substantially the same as that of the first semiconductor layer. The aforementioned second semiconductor layer is surrounded by the aforementioned third semiconductor layer. A display device in which the plurality of third transistors have at least one of their gate, source, and drain electrically floating.

2. In claim 1, It has an luminescent element, The light-emitting element has an anode and a cathode, A display device in which one of the plurality of the second transistors has either its source or drain electrically connected to the anode or the cathode.

Images