Semiconductor equipment

JP2026097967AActive Publication Date: 2026-06-16SEMICON ENERGY LAB CO LTD

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
SEMICON ENERGY LAB CO LTD
Filing Date
2026-03-06
Publication Date
2026-06-16

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  • Figure 2026097967000001_ABST
    Figure 2026097967000001_ABST
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Abstract

The present invention provides a semiconductor device that mitigates the effects of variations in the threshold voltage of transistors and enables accurate and easy differentiation between multiple states. [Solution] The memory cell array 210 includes a source line SL, a bit line BL, a word line WL, and memory cells 200 connected to the bit line and the word line; a second signal line and word line drive circuit 213 that drives a plurality of second signal lines and a plurality of word lines to select a memory cell specified by an input address signal; a write circuit 211 that outputs a write potential to a first signal line; a read circuit 212 that compares the bit line potential input from the bit line connected to the specified memory cell with a plurality of read potentials; a control circuit 216 that selects one of a plurality of correction voltages based on the comparison result between the bit line potential and the plurality of read potentials; and a potential generation circuit 217 that generates a write potential and a plurality of read potentials and supplies them to the write circuit and the read circuit.
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Claims

1. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, and a third transistor having silicon in its third channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, It comprises a third insulating film having a region positioned above the oxide semiconductor film, In a plan view, the first conductive film does not have a region that overlaps with the second channel-forming region. Semiconductor equipment.

2. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, and a third transistor having silicon in its third channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, It comprises a third insulating film having a region positioned above the oxide semiconductor film, In a plan view, the first conductive film does not have an area that overlaps with the second channel-forming area. The second insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. The third insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. Semiconductor equipment.

3. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, and a third transistor having silicon in its third channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, A third conductive film having a region positioned above the third insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. In a plan view, the first conductive film does not have an area that overlaps with the second channel-forming area. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor where the third conductive film overlaps with the first conductive film. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. Semiconductor equipment.

4. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, and a third transistor having silicon in its third channel formation region. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is a semiconductor device electrically connected to the second signal line, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, A third conductive film having a region positioned above the third insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. In a plan view, the first conductive film does not have an area that overlaps with the second channel-forming area. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor where the third conductive film overlaps with the first conductive film. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. The second insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. The third insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. Semiconductor equipment.

5. In any one of claims 1 to 4, In a plan view, the channel formation region of the first transistor has a region in which current flows in a direction intersecting the channel length direction of the second transistor. Semiconductor equipment.

6. In any one of claims 1 to 5, The charge held at the gate of the first transistor corresponds to three or more potentials, Semiconductor equipment.

7. In any one of claims 1 to 6, The first insulating film comprises nitrogen and silicon, Semiconductor equipment.

8. In any one of claims 1 to 7, A signal is input to the gate of the first transistor via the second transistor. Semiconductor equipment.

9. In any one of claims 1 to 8, The second transistor has an off-current of 1 × 10⁻⁶ -17 It is less than or equal to A / μm. Semiconductor equipment.