Semiconductor equipment

Abstract

This invention provides a novel semiconductor device with a smaller size and lower power consumption. [Solution] In the semiconductor device 100, the accelerator 20 includes a memory circuit 24, a drive circuit 15, and an arithmetic processing unit 21. The memory circuit includes a first data holding unit, a second data holding unit, and a data reading unit. The first data holding unit, the second data holding unit, and the data reading unit each have a first transistor. The first transistor has a first semiconductor layer having a metal oxide in the channel formation region. The first data held in the first data holding unit and the second data held in the second data holding unit are weight data W1~W input to the arithmetic circuit. N The arithmetic processing unit receives weight data and input data A1~A via the drive circuit. N A sum-of-accumulate operation is performed. The arithmetic processing unit and the drive circuit each include a second transistor having a second semiconductor layer with silicon in the channel formation region.

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

Background Art

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like have become widespread. In such electronic devices, since a large amount of data is processed at high speed, technological development regarding performance improvement of semiconductor devices is active. Regarding technologies for achieving higher performance, for example, there is a so-called SoC (System on Chip) in which an accelerator such as a GPU (Graphics Processing Unit) and a CPU are tightly coupled. In semiconductor devices with improved performance by SoC, heat generation and increased power consumption become problems.

[0004]

[0004] In AI (Artificial Intelligence) technology, since the amount of calculations and the number of parameters become enormous, the amount of operations increases. The increase in the amount of operations is a factor that increases heat generation and power consumption, and thus architectures for reducing the amount of operations have been actively proposed. Representative architectures include Binary Neural Network ( BNN) and Ternary Neural Network (TNN), and This is particularly effective for reducing the size of the circuit and lowering power consumption (see, for example, Patent Document 1).

[0005] For example, in TNN, data originally represented with 32-bit or 16-bit precision By compressing the value of "Ta" into three values, "+1", "0", or "-1", the computational complexity and the number of parameters are reduced. This can be significantly reduced. Also, BNN originally uses 32-bit or 16-bit precision. By compressing the represented data into binary values ​​of "+1" or "-1", the computational complexity and parameters are reduced. The number of data points can be significantly reduced. BNN or TNN are effective for reducing circuit size and power consumption. Therefore, applications that require low power consumption in limited hardware resources and They are considered to be a good match. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] International Publication No. 2019 / 078924 [Overview of the project] [Problems that the invention aims to solve]

[0007] TNN calculations use tri-valued data. This tri-valued data is stored in SRAM (Static R). When storing data in AM, the number of transistors in the memory cell increases. There is a risk that it will become difficult to miniaturize the device. Also, as transistors become smaller... As a result, the power consumption associated with the leakage current of the transistor increases, affecting the overall power consumption of the semiconductor device. There is a risk that the contribution will become larger.

[0008] Furthermore, in the sum-of-products operation of a fully connected neural network, data is read from memory during the operation. As the frequency of misfires increases, the challenge lies in how to reduce the charging and discharging energy of the bit lines. This is important for reducing power consumption. In order to reduce the charging and discharging energy of the bit line, When the T-wire is shortened, the area of ​​the memory cell array increases, which significantly increases the area of ​​the peripheral circuitry. There is a risk of an increase. Also, in order to shorten the bit wire, lamination techniques and the like may be used. When using a technology to integrate memory cell arrays in three dimensions, the electrical connection is Because the gap between the connection points is large, parasitic capacitance and other factors increase, which reduces the charge and discharge energy. There is a risk that it will not happen.

[0009] One aspect of the present invention aims to provide a miniaturized semiconductor device. One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one of the objectives is to provide a semiconductor device with a novel configuration.

[0010] Furthermore, one aspect of the present invention does not necessarily have to solve all of the above problems, but at least It would be good if it could solve one of the problems. Also, the description of the above problem is due to the existence of other problems. This does not preclude the following. Other issues are described in the specification, claims, drawings, etc. Therefore, it becomes clear from the description in the specification, claims, drawings, etc. It is possible to identify other issues besides those mentioned above. [Means for solving the problem]

[0011] One aspect of the present invention comprises a CPU and an accelerator, wherein the accelerator is a first The first memory circuit has a Mori circuit, a drive circuit, and a sum-of-accumulate circuit, and the first memory circuit holds the first data. It has a first data storage unit, a second data storage unit, and a data reading unit, and the first data storage unit and the second data storage unit The holding unit and the data reading unit each have a first transistor, and the first transistor is The first semiconductor layer has a metal oxide in the channel formation region and is held in the first data holding section. The first data and the second data held in the second data holding unit are entered into the sum-of-accumulate circuit. The weight data is used, and the sum-of-accumulate circuit receives the weight data and input via the drive circuit. It has the function of performing a sum-of-products operation on input data, and the sum-of-products operation circuit and the drive circuit are respectively It has a second transistor, and the second transistor has silicon in the channel formation region. It has a second semiconductor layer, and the first transistor and the second transistor are arranged in a stacked manner. It is a semiconductor device.

[0012] One aspect of the present invention comprises a CPU and an accelerator, wherein the accelerator is a first The first memory circuit has a Mori circuit, a drive circuit, and a sum-of-accumulate circuit, and the first memory circuit holds the first data. It has a first data storage unit, a second data storage unit, and a data reading unit, and the first data storage unit and the second data storage unit The holding unit and the data reading unit each have a first transistor, and the first transistor is The first semiconductor layer has a metal oxide in the channel formation region and is held in the first data holding section. The first data and the second data held in the second data holding unit are entered into the sum-of-accumulate circuit. The weight data is used, and the sum-of-accumulate circuit receives the weight data and input via the drive circuit. It has the function of performing a sum-of-products operation on input data, and the sum-of-products operation circuit and the drive circuit are respectively It has a second transistor, and the second transistor has silicon in the channel formation region. A second semiconductor layer, a well region having an impurity element that imparts conductivity, and the well region and The device has an oxide layer provided in contact with the second semiconductor layer, and includes a first transistor and a second transistor. A zista is a semiconductor device that is arranged in a stacked configuration.

[0013] One aspect of the present invention comprises a CPU and an accelerator, wherein the accelerator is a first The first memory circuit has a Mori circuit, a drive circuit, and a sum-of-accumulate circuit, and the first memory circuit holds the first data. It has a first data storage unit, a second data storage unit, and a data reading unit, and the first data storage unit and the second data storage unit The holding unit and the data reading unit each have a first transistor, and the first transistor is The first semiconductor layer has a metal oxide in the channel formation region and is held in the first data holding section. The first data and the second data held in the second data holding unit are entered into the sum-of-accumulate circuit. The weight data is used, and the sum-of-accumulate circuit receives the weight data and input via the drive circuit. It has the function of performing a sum-of-products operation on input data, and the sum-of-products operation circuit and the drive circuit are respectively It has a second transistor, and the second transistor has silicon in the channel formation region. The CPU has a second semiconductor layer and includes a flip-flop with a backup circuit. It has a CPU core, and the backup circuit has a third transistor, and the third transistor It has a third semiconductor layer having a metal oxide in the channel formation region, and the first transistor and The semiconductor device is configured such that the third transistor and the second transistor are stacked together. .

[0014] One aspect of the present invention comprises a CPU and an accelerator, wherein the accelerator is a first The first memory circuit has a Mori circuit, a drive circuit, and a sum-of-accumulate circuit, and the first memory circuit holds the first data. It has a first data storage unit, a second data storage unit, and a data reading unit, and the first data storage unit and the second data storage unit The holding unit and the data reading unit each have a first transistor, and the first transistor is The first semiconductor layer has a metal oxide in the channel formation region and is held in the first data holding section. The first data and the second data held in the second data holding unit are entered into the sum-of-accumulate circuit. The weight data is used, and the sum-of-accumulate circuit receives the weight data and input via the drive circuit. It has the function of performing a sum-of-products operation on input data, and the sum-of-products operation circuit and the drive circuit are respectively It has a second transistor, and the second transistor has silicon in the channel formation region. A second semiconductor layer, a well region having an impurity element that imparts conductivity, and the well region and The CPU has an oxide layer provided in contact with the second semiconductor layer, and a backup circuit is provided. The CPU core has a flip-flop, and the backup circuit is a third transistor. The third transistor has a zista, and the third semiconductor has a metal oxide in the channel formation region. It has layers, and the first transistor, the third transistor, and the second transistor are stacked. It is a semiconductor device that is provided as such.

[0015] In one embodiment of the present invention, the backup circuit flips when the CPU is not operating. It has the function of retaining the data held in the flop even when the power supply voltage is cut off. A semiconductor device is preferred.

[0016] In one embodiment of the present invention, the first data holding unit and the second data holding unit are first transient By making the sta a non-conductive state, it has the function of holding the first and second data, semi A conductive device is preferred.

[0017] In one embodiment of the present invention, the first memory circuit provides a first bit for reading the first data. The line, and the second bit line for reading the second data, are electrically connected to the first bit line. The second bit line is provided perpendicular or approximately perpendicular to the substrate surface on which the second transistor is located. A semiconductor device is preferred, which is electrically connected to a multiply-accumulate circuit via a first wiring harness.

[0018] In one embodiment of the present invention, the metal oxide comprises In, Ga, and Zn, and is used in semiconductor devices. It is preferable to place it there.

[0019] Further aspects of the present invention will be described in the following embodiments, and It is also indicated in the drawings. [Effects of the Invention]

[0020] One aspect of the present invention can provide a miniaturized semiconductor device. Alternatively, the present invention One embodiment can provide a semiconductor device with reduced power consumption. Or, a novel configuration We can provide semiconductor devices.

[0021] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention is It is not necessarily required to have all of the effects exemplified. Furthermore, with respect to one embodiment of the present invention, For issues, effects, and novel features other than those mentioned above, please refer to the description and drawings in this specification. It will become clear eventually. [Brief explanation of the drawing]

[0022] [Figure 1] Figures 1A and 1B illustrate an example of the configuration of a semiconductor device. [Figure 2] Figures 2A and 2B illustrate an example of a semiconductor device configuration. [Figure 3] Figures 3A, 3B, and 3C illustrate examples of semiconductor device configurations. [Figure 4] Figure 4 illustrates an example of a semiconductor device configuration. [Figure 5] Figures 5A, 5B, and 5C illustrate examples of semiconductor device configurations. [Figure 6] Figures 6A and 6B illustrate an example of a semiconductor device configuration. [Figure 7] Figures 7A and 7B illustrate an example of the configuration of a semiconductor device. [Figure 8] Figures 8A and 8B illustrate an example of the configuration of a semiconductor device. [Figure 9] Figures 9A and 9B illustrate an example of the configuration of a semiconductor device. [Figure 10] Figures 10A and 10B illustrate an example of the configuration of a semiconductor device. [Figure 11] Figure 11 is a diagram illustrating an example of a semiconductor device configuration. [Figure 12] Figure 12 is a diagram illustrating an example of a CPU configuration. [Figure 13] Figures 13A and 13B illustrate an example of a CPU configuration. [Figure 14] Figure 14 is a diagram illustrating an example of a CPU configuration. [Figure 15] Figure 15 shows an example of the configuration of a semiconductor device. [Figure 16] Figures 16A and 16B show examples of transistor configurations. [Figure 17] Figures 17A to 17C show examples of transistor configurations. [Figure 18] Figures 18A to 18C show examples of transistor configurations. [Figure 19] Figure 19A illustrates the classification of IGZO crystal structures. Figure 19B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 19C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 20] Figure 20 is a diagram illustrating an example of an integrated circuit configuration. [Figure 21]Figures 21A and 21B illustrate an example of an integrated circuit configuration. [Figure 22] Figures 22A and 22B illustrate examples of integrated circuit applications. [Figure 23] Figures 23A and 23B illustrate examples of applications for integrated circuits. [Figure 24] Figures 24A, 24B, and 24C illustrate examples of applications for integrated circuits. [Figure 25] Figure 25 illustrates an example of an integrated circuit application. [Figure 26] Figure 26 is a diagram illustrating an example. [Modes for carrying out the invention]

[0023] Embodiments of the present invention will be described below. However, one embodiment of the present invention is not limited to the following description. The invention is not defined, and its form and details may vary without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that this can be changed. Therefore, one embodiment of the present invention is The description of the embodiments shown below shall not be interpreted as being limited to the following.

[0024] In this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to the constituent elements. This is added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. Also, for example, the embodiments described herein The component referred to as "first" in one is in another embodiment or in the claims. It may also be the component referred to in "Second" in [the relevant section]. Furthermore, for example, in this specification, etc. In one embodiment, the component referred to as "first" is used in other embodiments, or It may be omitted in the claims.

[0025] In the drawing, elements that are identical or have similar functions, elements made of the same material, or Elements formed simultaneously may be assigned the same reference numeral, and the explanation of this repetition is omitted. It may happen.

[0026] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This can happen. This is due to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring). The same applies to (etc.).

[0027] Furthermore, when using the same sign for multiple elements, especially when it is necessary to distinguish between them... The symbols are followed by identification codes such as "_1", "_2", "[n]", and "[m,n]". In some cases, it may be written as follows: For example, the second wiring GL may be written as wiring GL[0].

[0028] (Embodiment 1) The configuration and operation of a semiconductor device according to one aspect of the present invention will be described.

[0029] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, computing devices, and memory devices. A device is one form of a semiconductor device. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection Devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, electronic equipment Some devices, such as those mentioned above, can be said to possess semiconductor devices.

[0030] Figures 1A and 1B are diagrams illustrating a semiconductor device 100 according to one aspect of the present invention. Yes. In the semiconductor device 100 shown in Figures 1A and 1B, as an example, there is a CPU 10, and The accelerator 20 and bus 30 are shown. The CPU 10 has CPU cores 11 and It has a backup circuit 12. The accelerator 20 has a drive circuit 15 and an arithmetic processing unit 21 , has memory sections 22_1 to 22_N (where N is a natural number). The drive circuit 15 has memory section 2 This is a circuit for driving 2. The arithmetic processing unit 21 has arithmetic circuits 23_1 to 23_N. The drive circuit 15 drives the memory units 22_1 to 22_N and the arithmetic processing unit 21. This is a circuit for that purpose. Each of the memory sections 22_1 to 22_N has a memory circuit 24. The memory sections 22_1 to 22_N are sometimes referred to as device memory or shared memory. The Mori circuit 24 has a transistor 25 having a semiconductor layer 29 having a channel formation region. do.

[0031] CPU10 is responsible for running the operating system, controlling data, performing various calculations and programming. It has the function to perform general-purpose processing, such as executing commands. The CPU 10 has CPU cores 11. The CPU core 11 corresponds to one or more CPU cores. The CPU 10 is power supply A backup circuit 12 that can retain data in the CPU core 11 even if the voltage supply is interrupted. It has. The power supply voltage is supplied from the power domain to the power switch, etc. It can be controlled by electrical disconnection. The power supply voltage is called the drive voltage. In some cases, a backup circuit 12 may be made of, for example, an oxide semiconductor. A transistor (OS transistor) having an iconductor in its channel formation region. A memory having the following characteristics is preferred.

[0032] The backup circuit 12, which is composed of OS transistors, is made of Si CMOS. The CPU core 11 can be stacked with the backup circuit 12. Because it is smaller than the area of ​​CPU core 11, it does not increase the circuit area on the CPU core. A backup circuit 12 can be placed there. The backup circuit 12 is located at the CPU core It has the function of holding the data of the registers that 11 has. The backup circuit 12 has the function of data It is also called a data retention circuit.

[0033] Furthermore, the configuration of the CPU core 11 includes a backup circuit 12 having an OS transistor. Further details will be explained in Embodiment 3.

[0034] Accelerator 20 is a program called from the host program (kernel, etc.) It also has the function of executing a kernel program. Accelerator 20 For example, parallel processing of matrix operations in graphics processing, neural networks This allows for parallel processing of multiply-accumulate operations, parallel processing of floating-point operations in scientific and technical calculations, etc. can.

[0035] Memory units 22_1 to 22_N are devices that store data processed by the accelerator 20. It has the capability to perform parallel processing of multiply-accumulate operations in neural networks. Specifically, it can perform parallel processing of weights. DATA W1 to W N It can store the weight data W1 to W N This is used in TNN This data is represented by one of three values: "+1", "0", or "-1". Memory section 22_1 to In the memory circuit 24 of 22_N, three-value data is stored in two data storage units, and binary data is stored in two data storage units. It has the function of storing 3-value data by holding the voltage value. Note that it is not limited to 3 values. It was also possible to use data with four or more values.

[0036] The arithmetic processing unit 21 and the memory units 22_1 to 22_N are connected via bit lines PBL and bit lines NBL. Any one of the memory units 22_1 to 22_N has a memory circuit 24 connected to a pair of bit lines PBL and bit line NBL. Note that a pair of bit lines PBL and bit line NBL may be represented by omitting the bit line BL. A pair of bit lines PBL and bit line NBL are respectively connected to any one of the arithmetic circuits 23_1 to 23_N. A pair of bit lines PBL and bit line NBL are the wirings for giving weight data W1 to W N from the memory unit 22 (any one of the memory units 22_1 to 22_N is referred to as the memory unit 22) to the arithmetic circuit 23 (any one of the arithmetic circuits 23_1 to 23_N is referred to as the arithmetic circuit 23).

[0037] The drive circuit 15 and the arithmetic processing unit 21 are connected via a data input line A IN . Any one of the arithmetic circuits 23_1 to 23_N receives any one of the input data A1 to A IN via the data input line A. The input data A1 to A N are data represented by two values of “+1” N or “-1” used in the TNN. The data input line A is the wiring for giving the input data A1 to A IN to the arithmetic circuit 23. With such a configuration, arithmetic processing based on an architecture such as a Terna ry Neural Network (TNN) can be efficiently performed by the arithmetic processing unit 21. N In the memory circuit 24, the semiconductor layer 29 of the transistor 25 is an oxide semiconductor.​​​​​​​​​​​ Yes, it exists. In other words, transistor 25 is an OS transistor. The memory circuit 24 is an OS A memory having transistors (hereinafter also referred to as OS memory) is preferred. OS memory This has the function of retaining charge according to the voltage value by making the OS transistor non-conductive. do.

[0039] Because the band gap of metal oxides is 2.5 eV or more, OS transistors are extremely small. It has a current. For example, when the voltage between the source and drain is 3.5V and the room temperature (25℃) is below. In this case, the off-current per 1 μm of channel width is 1 × 10⁻⁶. -20 Less than A, 1 x 10 -22 A Less than, or 1 × 10⁻⁶ -24 It can be less than A. That is, the drain current O The on / off current ratio can be set to between 20 and 150 digits. Therefore, the OS memory Therefore, the amount of charge leaking from the holding node via the OS transistor is extremely small. OS memory can function as a non-volatile memory circuit, thus enabling the accelerator's power gate This makes it possible to do so.

[0040] High-density integrated semiconductor devices can generate heat due to the operation of their circuits. Due to the heat generated, the temperature of the transistor rises, which changes the characteristics of that transistor. Changes in field-effect mobility and a decrease in operating frequency can occur. OS transistors Because it has higher thermal resistance than Si transistors, changes in field-effect mobility occur due to temperature changes. It is less prone to stiffness and less likely to experience a decrease in operating frequency. Furthermore, OS transistors are temperature Even if the voltage increases, the drain current increases exponentially with respect to the gate-source voltage. It is easy to maintain performance. Therefore, by using OS transistors, it is possible to maintain performance in high temperature environments. It can operate stably.

[0041] The metal oxides used in OS transistors are Zn oxide, Zn-Sn oxide, and Ga- Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (where M is Ti , one of the following selected from Ga, Y, Zr, La, Ce, Nd, Sn, or Hf Examples include (multiple). In particular, metal oxides using Ga as M are used in OS transistors. In this case, by adjusting the ratio of elements, transistors with superior electrical properties such as field-effect mobility can be produced. This is preferable because it allows for this. In addition, an oxide containing indium and zinc is added. Titanium, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium One of the following materials selected from neodymium, hafnium, tantalum, tungsten, magnesium, etc. , or may include multiple types.

[0042] To improve the reliability and electrical characteristics of OS transistors, metal oxides are applied to the semiconductor layer. These are metal oxides having crystalline parts such as CAAC-OS, CAC-OS, and nc-OS. Preferably, CAAC-OS refers to c-axis-aligned crystal CAC-OS is an abbreviation for line oxide semiconductor. Cloud-Aligned Composite Oxide Semiconductor It is an abbreviation for tor. nc-OS stands for nanocrystalline oxide. It is an abbreviation for semiconductor.

[0043] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, This refers to the part where the direction has changed.

[0044] CAC-OS has the function of conducting electrons (or holes) that act as carriers, and the function of conducting electrons (or holes) that act as carriers It has a function that prevents electrons from flowing. It separates the function that allows electrons to flow from the function that prevents electrons from flowing. This allows both functions to be maximized. In other words, CAC-OS can be used as an OS transition. By using it in the channel formation region of the sta, both high on-current and extremely low off-current can be achieved. This can be achieved.

[0045] Metal oxides have a large band gap, making them difficult to excite electrons, and the effective quality of holes Due to its large size, OS transistors are different from typical Si transistors. Avalanche collapse and the like may be less likely to occur. Therefore, for example, avalanche collapse may be less likely to occur. This can suppress hot carrier degradation, etc. By suppressing hot carrier degradation, high performance can be achieved. OS transistors can be driven with rain voltage.

[0046] OS transistors are storage-type transistors that use electrons as the majority carriers. Compared to inverting transistors with pn junctions (typically Si transistors), the short One of the channel effects is DIBL (Drain-Induced Barrier L). The effect of power (worring) is small. In other words, OS transistors are less powerful than Si transistors. It also has high resistance to short-channel effects.

[0047] OS transistors have high resistance to short-channel effects, therefore OS transistors By using OS transistors, the channel length can be reduced without degrading reliability. The integration density of the circuit can be increased. As the channel length is miniaturized, the drain electric field becomes stronger. However, as shown above, OS transistors exhibit avalanche decay more readily than Si transistors. It is less likely to happen.

[0048] Furthermore, OS transistors have high resistance to short-channel effects, unlike Si transistors. It becomes possible to make the gate insulating film thicker than the star. For example, channel length and channel Even in minute transistors with a width of 50 nm or less, a gate insulating film thickness of about 10 nm is used. It may be possible to implement this. By increasing the thickness of the gate insulating film, parasitic capacitance can be reduced. This allows for improved circuit operation speed. Also, by increasing the thickness of the gate insulating film, the gate Because leakage current through the insulating film is reduced, static current consumption is reduced.

[0049] Therefore, the accelerator 20 has a memory circuit 24 which is the OS memory, and Data can be retained even if the power supply of the source voltage is interrupted. Therefore, the power of accelerator 20 Gating becomes possible, allowing for a significant reduction in power consumption.

[0050] The memory circuit 24, which is composed of OS transistors, can be constructed using Si CMOS. It can be mounted in stack with the calculation circuit 23. Therefore, it does not lead to an increase in circuit area. It can be placed anywhere.

[0051] The memory circuit 24 preferably has a NOSRAM circuit configuration. "(Registered Trademark)" refers to "Nonvolatile Oxide Semiconductor NOSRAM is an abbreviation for "or RAM". NOSRAM uses a 2-transistor (2T) memory cell. , or a 3-transistor type (3T) gain cell, where the access transistor is an OS transistor This refers to memory, specifically a zista. The OS transistor is in the off state, and its source and drain are connected. The current flowing through it, that is, the leakage current, is extremely small. NOSRAM has extremely low leakage current. By using small characteristics to hold a charge corresponding to the data within the memory circuit, non-volatile memory It can be used as a harpoon. In particular, NOSRAM destroys the data it holds. Because it is possible to read data without destructive means that only the data reading operation can be performed on a large scale. It is suitable for parallel processing of multiply-accumulate operations in neural networks, which are repeated over and over.

[0052] The arithmetic processing unit 21 has the function of performing arithmetic processing using digital values. It is less susceptible to noise. Therefore, accelerator 20 is required to produce highly accurate calculation results. It is suitable for performing calculation processing. The calculation processing unit 21 is Si CMOS, that is It is composed of a transistor (Si transistor) having silicon in the channel formation region. This configuration is preferable. This configuration allows the OS transistor to be stacked with the transistor.

[0053] The drive circuit 15 has a function for storing weight data in memory units 22_1 to 22_N. It has. The drive circuit 15 also provides input data to the calculation circuits 23_1 to 23_N. It has the functionality to perform operations such as sum-of-accumulate calculations on a neural network.

[0054] The memory circuit 24 and arithmetic circuits 23_1 to 23_N, which are composed of OS transistors, With respect to the substrate surface on which the drive circuit 15 and calculation circuits 23_1 to 23_N are provided, the surface is roughly perpendicular. Electrically connected via bit lines NBL and PBL which are provided extending in the perpendicular direction. It continues. Note that "approximately vertical" refers to a state where the items are arranged at an angle of 85 degrees or more and 95 degrees or less. In this specification, the X, Y, and Z directions shown in Figure 1B, etc., are... These are directions that are orthogonal or intersect with each other. Also, the X and Y directions are relative to the substrate surface. The planes are parallel or approximately parallel, and the Z-direction is perpendicular or approximately perpendicular to the substrate surface.

[0055] The arithmetic circuits 23_1 to 23_N receive input data A1 to A N and weight data W1 to W N Using this, you can perform operations such as integer arithmetic, single-precision floating-point arithmetic, and double-precision floating-point arithmetic. It has the function of performing offset operations. The arithmetic circuit 23 repeatedly performs the same operations such as multiply-accumulate operations. It has the function of performing.

[0056] The arithmetic circuits 23_1 to 23_N connect the bit line NBL of the memory circuit 24 and the bit The configuration includes one arithmetic circuit 23 for each line PBL, that is, for each column. Column-Parallel Calculation). By adopting this configuration, The memory circuit 24 can process data for one row (up to all bit lines) in parallel. Compared to multiply-accumulate operations using CPU10, the data bus size between the CPU and memory is (32 Because it is not limited by bits, etc., Column-Parallel Calc In lation, the degree of parallelism of calculations can be greatly increased, which is an AI technology. - Training of neural networks (deep learning), scientific and technical computing that performs floating-point operations This can improve the computational efficiency of any massive computational processing. In addition, the memory circuit 24 Because the calculations on the output data can be completed and read, memory access (C It can reduce the power consumption generated by data transfer between the PU and memory, and calculations performed by the CPU. Increases in heat and power consumption can be suppressed. Furthermore, one arithmetic circuit 23 and memory The physical distance between circuits 24 can be reduced, for example, by stacking them to shorten the wiring distance. Therefore, parasitic capacitance occurring in the signal lines can be reduced, making it possible to lower power consumption.

[0057] In the arithmetic circuits 23_1 to 23_N, the semiconductor layer of the transistors constituting the circuit is It is a recon. A transistor that has silicon as its semiconductor layer is called a Si transistor. Si transistors are embedded in a silicon substrate and undergo burried oxide formation. Thus, it has an insulating layer (also called a BOX layer) and single-crystal silicon on the insulating layer. A configuration formed using an SOI substrate is preferred. The silicon substrate is, for example, a p-type single crystal. It is a silicon substrate.

[0058] The silicon substrate in the region where the Si transistor is installed contains impurity elements that impart conductivity. Multiple well regions with added components can be stacked. The well region has a potential. By independently changing this, it can be made to function as a bottom gate electrode. Therefore, the threshold voltage of the Si transistor can be controlled. In particular, negative voltage in the well region By applying an electric potential, the threshold voltage of the Si transistor is increased, and the off-current is reduced. This makes it possible to reduce S. To reduce the drain current when the potential applied to the gate electrode of the i-transistor is 0V. This can be done. Also, impurities in the channel formation region can be controlled for the purpose of controlling the threshold voltage. Since elemental addition is unnecessary, variations in threshold voltage can be reduced, and the power supply voltage can be lowered. This makes it possible to reduce power consumption in the arithmetic circuits 23_1 to 23_N, and perform This can improve computational efficiency.

[0059] Bus 30 electrically connects CPU 10 and accelerator 20. In other words, CPU 1 Data can be transmitted between 0 and accelerator 20 via bus 30.

[0060] Next, we will explain the advantages of the configuration shown in Figures 1A and 1B. In Figure 2A, This is a schematic diagram of 1B viewed from the z direction in a plan view. Note that in Figure 2A, there are six arithmetic circuits. 23_1 to 23_6 are arranged in the y-direction, and six memory sections 2 are arranged so that they overlap in the z-direction. Figures 2_1 to 22_6 are shown. Also, in Figure 2A, data input line A IN 6 via The diagram shows a drive circuit 15 that provides input data A1 to A6 to the calculation circuits 23_1 to 23_6. They are doing it.

[0061] In Figure 2A, the arithmetic circuits 23_1 to 23_6 consist of a pair of bit lines NBL and PB. Data W (W1 to W6) is represented as three values ​​based on the data of L, and data input line A I N The input data A (A1 to A6) and the output signal Y1 to Y, which corresponds to the product (=W × A) of the two. You get 6.

[0062] Furthermore, in Figure 2A, the arithmetic circuits 23_1 to 23_6 are each connected to the memory unit 22_1. It is connected to 22_6 via the bit line NBL and PBL (shown as a single opening in Figure 2A). In other words, it is illustrated as being connected via wiring extending in the z direction. That is, bit line N BL and PBL provide arithmetic circuits 23_1 to 23_6 and memory sections 22_1 to 22_6. And, can be placed at a short distance. Therefore, bit lines NBL, PBL, and others This reduces the parasitic capacitance with that element. Therefore, the charge due to charging and discharging of the bit line This can reduce power consumption and improve computing efficiency.

[0063] In addition, in the configuration of Figure 2A, all transistors in the memory section 22_1 to 22_6 are O Since it is an S transistor, the arithmetic circuit 23_1 to 23_ is composed of Si transistors. 6 can be stacked on top of each other. Therefore, the arithmetic circuit and the memory section can be arranged on top of each other. Therefore, the circuit area that would increase due to the placement of the memory section can be reduced. Therefore, the semiconductor device can be miniaturized. In addition, it extends from the drive circuit 15 and is provided Data input line A IN It can be shortened.

[0064] Furthermore, in Figure 2B, the arithmetic circuits 23_1 to 23_6 and the memory sections 22_1 to 22_6 are A schematic diagram of the arrangement when the elements are arranged alternately in the y-direction is shown in the same manner as in Figure 2A. Figure 2 Example B uses SRAM (Static RAM) for the data retention circuit of the memory circuit. This is the case when the memory circuit is constructed with Si transistors. Therefore, the calculation is as shown in Figure 2A. The processing unit and memory unit are not stacked on top of each other, but are arranged side by side on a flat surface.

[0065] In Figure 2B, the arithmetic circuits 23_1 to 23_6 are each provided adjacent to each other. Bit lines NBL and PBL (1 in Figure 2A) are provided extending from sections 22_1 to 22_6. The connections are made as shown in the diagram (as illustrated in the book's wiring diagram). In other words, they are connected via wiring that extends in the y direction. This is illustrated in the diagram. In other words, the bit lines NBL and PBL are used to perform calculations on circuits 23_1 to 23_ 6 and the memory sections 22_1 to 22_6 can be arranged at a distance longer than the z-direction. Therefore, the parasitic capacitance between the bit line NBL, PBL and other elements increases. Therefore, the charge increases due to the charging and discharging of the bit line. For this reason, one aspect of the present invention is shown in Figure 2A. This configuration can be said to be excellent for miniaturization and low power consumption.

[0066] One aspect of the present invention relates to a semiconductor device comprising an accelerator and a CPU, wherein the device is miniaturized. A semiconductor device can be provided. Alternatively, one aspect of the present invention provides an accelerator and C In a semiconductor device equipped with a PU, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention relates to a semiconductor device in which the number of data transfers in the CPU is reduced. This can be provided. Or, a semiconductor device with a novel configuration can be provided. A semiconductor device according to one aspect of the invention has a non-von Neumann architecture, and as the processing speed increases Compared to the von Neumann architecture, which consumes a lot of power, this architecture consumes extremely little power. This allows for parallel processing.

[0067] Figure 3A shows the processing capacity (OPS: Operations Per Second) and the consumption This diagram illustrates the relationship with power consumption (W). Note that in Figure 3A, the vertical axis represents processing capacity. The horizontal axis represents power consumption. Also, in Figure 3A, an indicator of computational efficiency is shown. 0.1TOPS / W(Tera Operations Per Second / W), 1TOPS / W, 10TOPS / W, 100TOPS / W, and 1POPS / W (Per Each of the Operations Per Second (W) is clearly indicated with a dashed line. be.

[0068] Furthermore, in Figure 3A, region 910 is a conventional general-purpose AI accelerator (von Neumann type) The regions included are, respectively, the regions in which region 912 includes a semiconductor device according to one aspect of the present invention. This indicates that, for example, area 910 contains the CPU (Central Process). ing Unit), GPU(Graphics Processing Unit), This includes FPGAs (Field-Programmable Gate Arrays), etc. It can be done.

[0069] As shown in Figure 3A, by applying a semiconductor device according to one aspect of the present invention, conventional general-purpose AI It can reduce power consumption by about two orders of magnitude compared to an accelerator (von Neumann type), and Processing performance can be significantly improved (for example, by more than 1000 times). By applying the semiconductor device described above, a computing efficiency of 100 TOPS / W or more can be expected.

[0070] Here, we will discuss specific examples of a conventional configuration and a configuration to which a semiconductor device according to one aspect of the present invention is applied. This will be explained using Figures 3B and 3C. Figure 3B shows a conventional semiconductor configuration for image recognition. Figure 3C shows an illustrative diagram of the power consumption of the device, and the configuration of one embodiment of the present invention in image recognition. This diagram illustrates the power consumption of a semiconductor device using [a specific technology / technology].

[0071] In Figures 3B and 3C, the vertical axis represents power and the horizontal axis represents time. Furthermore, in Figure 3B, power 914 represents leakage power, and power 916 represents CPU power (CP The power consumption of U is shown, and power 918 is shown as memory power. Also, in Figure 3C... Power 914 is leakage power, power 920 is CPU power, and power 922 is accelerator power The following shows the power consumption (power consumption of the accelerator). Note that power 922 is This also includes the power used in the arithmetic circuits and memory circuits.

[0072] Furthermore, in Figures 3B and 3C, arrows a, b, and c indicate image recognition This represents the signals in recognition. Note that when signals from arrows a, b, and c are input... Let's assume that the semiconductor device then starts processing calculations such as image recognition.

[0073] As shown in Figure 3B, in the case of a conventional semiconductor device, the leakage power is constant with respect to time. Power (914) is generated. On the other hand, as shown in Figure 3C, a semiconductor device according to one embodiment of the present invention In configurations where this applies, CPU power (power 920) and accelerator power (power 92 2) While using this, leakage power (power 914) is generated, but CPU power (power 9 20), and during periods when accelerator power (power 922) is not being used, leakage power ( This allows for normally-off operation (period t1 shown in Figure 3C) in which no power (914) is generated. Yes, it is possible. This will significantly reduce power consumption. In other words, extremely low power consumption. We can provide power-efficient semiconductor devices.

[0074] Figure 4 shows the NOSRAM and CP of a semiconductor device according to one embodiment of the present invention described in Figure 3A. U (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field-Programmable DRAM (Dynamic RAM) and SRAM, which are found in gate arrays, etc. Read energy in static RAM and flash memory A graph comparing the cost of ghee and the relative cost per Gbit (cost per Gbit). This indicates.

[0075] Flash memory has a good relative cost per Gbit, but read energy The ghee is high at 100pJ. Also, the relative cost per 1Gbit of DRAM is flash Although inferior to memory, it requires less energy to read. Also, SRAM is 1Gbi Although the relative cost per t is significantly lower than that of DRAM and flash memory, read The energy consumption is significantly lower. This is a major improvement over flash memory, DRAM, and SRAM. One aspect of a semiconductor device has NOSRAM with extremely low read energy, The relative cost per Gbit is also superior to that of SRAM. Therefore, as explained in Figure 3A... As shown above, if you aim for computational efficiency exceeding 100 TOPS / W, a semicircular system with NOSRAM is required. A conductive device would be suitable.

[0076] Figure 5A is applicable to the memory sections 22_1 to 22_N of the semiconductor device 100 of the present invention. This diagram illustrates an example of a possible circuit configuration. In Figure 5A, there are M rows and N columns (where M and N are 2 or more). (Naturally) Bit lines PBL_1 to PBL_N and bit line NBL are arranged in the direction of the matrix. The diagram illustrates _1 to NBL_N and word lines WL_1 to WL_M (where M is a natural number). Furthermore, a memory circuit 24 connected to each word line and bit line is also illustrated.

[0077] Figure 5B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 24. Circuit 24 consists of data holding circuit 31_P, data holding circuit 31_N, and transistor 32_P , having transistor 32_N, transistor 33_P, and transistor 33_N .

[0078] Each transistor in the memory circuit 24 may have a back gate. In this case, the back gate may be connected to the gate, or it may be given a different potential from the gate. This configuration may also be used to control the electrical characteristics of the transistor.

[0079] The data holding circuit 31_P is the node of the wiring connected to the gate of transistor 32_P. It is connected to MN_P. Either the source or drain of transistor 32_P is connected to GND. It is connected to a fixed potential such as the following. Either the source or the drain of transistor 33_P is Connected to the other side of the source or drain of transistor 32_P. Transistor 33_ Either the source or drain of P is connected to the bit line PBL. Transistor 33_ The gate P is connected to the word line WL.

[0080] The data holding circuit 31_N is the node of the wiring connected to the gate of transistor 32_N. It is connected to MN_N. Either the source or drain of transistor 32_N is connected to GND. It is connected to a fixed potential such as the following. Either the source or the drain of transistor 33_N is Connected to the other side of the source or drain of transistor 32_N. Transistor 33_ Either the source or drain of transistor N is connected to the bit line NBL. Transistor 33_ The gate N is connected to the word line WL.

[0081] Data holding circuits 31_P and 31_N are each at an H level or L level. It has a function to hold a signal according to the voltage level. Figure 5C shows the data holding cycle of Figure 5B. The circuit configuration of the data holding circuit 31 applicable to path 31_P and data holding circuit 31_N is To illustrate.

[0082] The data retention circuit 31 is applicable to transistors 32_P and 32_N. 2, and together with transistor 33 applicable to transistors 33_P and 33_N, This corresponds to a 3-transistor (3T) gain cell NOSRAM. In other words, the data retention cycle The path 31 has a transistor 34 and a capacitive element 35, as shown in Figure 5C. Each transistor shown in 5C is an OS transistor. OS transistors are in the OFF state. In this state, the current flowing between the source and drain, i.e., the leakage current, is extremely small. NOSR AM uses its extremely low leakage current characteristic to store data-dependent charges within the memory circuit 24. By storing it in node MN, it can be used as non-volatile memory. The voltage is the voltage held by the data holding circuit 31. The voltage to be applied is given by signal MBL. Signal MBL is applied to the gate of transistor 34. The configuration should be such that the signal MWL is controlled and written to node MN at the appropriate timing. Rangitor-type (3T) gain cell NOSRAMs have two or more voltage values, such as 5-value or 7-value. It is possible to hold it.

[0083] The circuit configuration of the data retention circuit 31 in Figure 5C is shown in Figure 5B, and the circuit configuration of the memory circuit 24 is shown in the same configuration. This is shown in Figure 6A. The truth tables for each signal shown in Figure 6A are as shown in Table 1. In 1, the H level and L level voltages are represented by the logical "1" and "0". "ll P" is a theory that corresponds to the voltage held at node MN_P, i.e., the data holding circuit 31_P. This corresponds to the process. "Cell N" is held in node MN_N, that is, data holding circuit 31_N. This corresponds to the logic corresponding to the voltage being held. "W" is determined by the logic of bit line NBL and PBL. This is data, represented by three values: "0", "+1", or "-1", which are used in TNNs. That is the case. Prohibitions are indicated by "×".

[0084] [Table 1]

[0085] In the configuration shown in Figure 6A, the voltage at node MN_P is kept at the H level, and node MN_ The fixed potential of either the source or drain of N is set to the ground potential (voltage at L level). Then, the voltage read out to the bit line PBL becomes L level, and the held voltage is read out. The voltage will be inverted. Therefore, as shown in Figure 6B, node MN_P and the transistor Connect the gate of transistor 32_N, node MN_N, and the gate of transistor 32_P. A configuration like this is preferable. The truth tables for each signal shown in Figure 6B are as shown in Table 2.

[0086] [Table 2]

[0087] Note that Figure 6A can be transformed into the circuit configuration shown in Figure 7A. As shown in Figure 7A, Replace transistors 33_P and 33_N with transistor 34, and each wiring and transistor This corresponds to a configuration in which the connections between the transistors have been changed. In the circuit configuration of Figure 7A, the true shown in Table 1 You can obtain data from the theoretical value table.

[0088] Similarly, Figure 6B can be transformed into the circuit configuration shown in Figure 7B. As shown in Figure 7B Replace transistors 33_P and 33_N with transistor 34, and each wiring and This corresponds to a configuration in which the connections between transistors have been changed. In the circuit configuration of Figure 7B, see Table 2. You can obtain truth table data.

[0089] Figure 8A shows an example of a circuit configuration applicable to the arithmetic processing unit 21 of the semiconductor device 100 of the present invention. This is a diagram illustrating the following. The arithmetic processing unit 21 has arithmetic circuits 23_1 to 23_N. Each of the N arithmetic circuits 23_1 to 23_N has N bit lines PBL_1 to bit Any one of the bit lines PBL_N, and any of the N bit lines NBL_1 through NBL_N either one, and data input line A IN The input data A1 to A N One of the following: Each of the following signals is input and outputs output signals Q_1 to Q_N. This refers to the data held in the memory circuit 24, and the data input line A IN Drive circuit 15 This corresponds to the data obtained by performing a sum-of-products operation using the input data.

[0090] Figure 8B shows the circuit configuration of the arithmetic circuit 23 applicable to arithmetic circuits 23_1 to 23_N. This is a diagram illustrating an example. Figure 8B shows the execution of computational processing based on the TNN architecture. This is a circuit for performing the operation. The arithmetic circuit 23 consists of a logic circuit 42 for performing the sum-of-accumulate operation and an accumulator. It has a meter 43, a latch circuit 44, and an encoding circuit 45 that outputs an output signal Q. The logic circuit 42 has one of the N bit lines PBL_1 to PBL_N (in the figure) Data PBL), one of the N bit lines NBL_1 to NBL_N (in the figure) , data NBL), and data input line A IN The input data A1 to A N Noi The following signals are input: Data PBL and Data NBL. From the data (data W) which is represented as three values: "0", "+1", or "-1", and "+ Data A is represented by a binary value, either "1" or "-1", and data Y is the product of this value (=W × A). Outputs.

[0091] The truth tables for each signal in the logic circuit in Figure 8A are shown in Table 3. , "+1" in data A is "(0)", and "-1" in data A is "(1)" and 1 It is represented by a bit digital signal. Also, in Table 3, "0" in data Y is represented as "( 00)」, +1 in data Y is represented as (01), -1 in data Y is represented as ( It is represented by a 2-bit digital signal as "11)". Prohibition is represented by "×".

[0092] [Table 3]

[0093] In Figures 8A and 8B, memory access selects one row per clock cycle, so M rows (=1 The product of (bit × M rows) and its sum are performed in M ​​clock cycles. In the arithmetic circuits shown in Figures 8A and 8B, Since the same M products and their sums can be executed in N parallel × 1 bit × M / N rows, M / N clocks are required. Therefore, the configurations of FIGS. 8A and 8B can shorten the operation time by executing the product-sum operation in parallel, thus improving the operation efficiency.

[0094] FIG. 9A illustrates a hierarchical neural network. In FIG. 9A, a fully-connected neural network with neuron 50, one input layer (I1), three intermediate layers (M1 to M3), and one output layer (O1) is illustrated. If the number of neurons in the input layer I1 is 786, the number of neurons in the intermediate layers M1 to M3 is 256, and the number of neurons in the output layer O1 is 10, then the number of connections in each layer (layer 51, layer 52, layer 53, and layer 54) is (786 × 25 6) + (256 × 256) + (256 × 256) + (256 × 10), which is a total of 334,336 connections. That is, since the total number of weight parameters required for neural network calculations is about 330 K bits, it is possible to have a memory capacity that can be sufficiently implemented even in a small-scale system. .

[0095] Next, FIG. 9B shows a detailed block diagram of the semiconductor device 100 capable of performing the operations of the neural network illustrated in FIG. 9A.

[0096] In FIG. 9B, in addition to the arithmetic processing unit 21, the arithmetic circuits 23 corresponding to the arithmetic circuits 23_1 to 23_N described in FIGS. 1A and 1B, the memory units 22 corresponding to the memory units 22_1 to 22_N, the memory circuit 24, and the bit lines NBL and PBL, a configuration example of the drive circuit 15 illustrated in FIGS. 1A and 1B is illustrated.

[0097] In FIG. 9B, as a configuration corresponding to the drive circuit 15 described in FIGS. 1A and 1B, a con​​​ Troller 61, Row Decoder 62, Word Line Driver 63, Column Decoder 64, Write The driver 65, precharge circuit 66, input buffer 71, and arithmetic control circuit 72 are shown in the diagram. It is showing.

[0098] Figure 10A shows the configurations shown in Figure 9B, with the block controlling the memory unit 22 removed. This is the resulting diagram. In Figure 10A, the controller 61, the row decoder 62, and the word line driver are shown. Extract the IBA 63, column decoder 64, writing driver 65, and precharge circuit 66. This is illustrated in the diagram.

[0099] The controller 61 processes the input signal from the outside to control the row decoder 62 and the column Generates control signals for decoder 64. External input signals include the write enable signal and This is a control signal for controlling the memory section 22, such as a read enable signal. The Trolla 61 receives data written to the memory unit 22 via a bus between the CPU 10 and the system. Data is input and output from the memory unit 22.

[0100] The row decoder 62 generates a signal to drive the word line driver 63. The line driver 63 provides the signal MWL to the data holding circuits 31_P and 31_N, as well as the word The column decoder 64 generates a signal to be applied to the line WL. The column decoder 64 drives the write driver 65. Generates a signal for this purpose. The write driver 65 controls the data holding circuits 31_P, 31_N In addition to the signal MBL that is supplied, there is also data input line A IN Input data A1 to A N to produce The pre-charge circuit 66 has the function of pre-charging bit lines such as NBL and PBL. It has the following: The signals read from the memory circuit 24 of the memory unit 22 are bit lines NBL, P The signal is input to the arithmetic circuit 23 via BL.

[0101] Figure 10B shows the blocks that control the arithmetic processing unit 21 for each configuration shown in Figure 9B. This is an extracted diagram.

[0102] The controller 61 processes external input signals and controls the control signals of the arithmetic control circuit 72. It generates. The controller 61 also controls the arithmetic circuit 23 of the arithmetic processing unit 21. It generates various signals such as clock signals. The arithmetic control circuit 72 controls the controller 61. Depending on the output of the control and input buffer 71, data input line A IN The input data given Ta A1 to A N The arithmetic processing unit 21 generates the input buffer 71 and the arithmetic control circuit 7 Through 2, the data related to the calculation result is re-input to the calculation processing unit 21. The calculation processing unit 21 The buffer memory in the input buffer 71 is used to process data according to the calculation result. This allows the data being processed during the calculation to be read into main memory or other external memory outside the accelerator. Without any additional effort, parallel computations with a number of bits exceeding the CPU's data bus width become possible. This reduces the number of times the weight parameters are transferred between the CPU 10 and the CPU 10, thus lowering power consumption. It can be measured.

[0103] As described above, one aspect of the present invention is a semiconductor device equipped with an accelerator and a CPU. In this, a miniaturized semiconductor device can be provided. Alternatively, one aspect of the present invention is In a semiconductor device equipped with an accelerator and a CPU, a low-power semiconductor device is provided. can be provided. Or, one aspect of the present invention is that the number of data transfers in the CPU is a semiconductor device with reduced data transfers can be provided. Or, a semiconductor device with a novel configuration can be provided

[0104] (Embodiment 2) In this embodiment, an example of the operation when a part of the operations of the program executed by the CPU 10 described in the above embodiment is executed by the accelerator 20 will be described.

[0105] FIG. 11 is a diagram for explaining an example of the operation when a part of the operations of the program executed by the CPU is executed by the accelerator.

[0106] The host program is executed by the CPU (step S1). <00​​​​​​​​​​​​​​​​​​​​​​​​​​​​​The system may switch from state to PG state (step S8). In that case, the accelerator will Just before the execution of the program ends, the CPU switches from the PG state to the calculation state. It is replaced (step S9). During the period from step S8 to step S9, the CPU is P By putting the semiconductor device into a G state, power consumption and heat generation can be suppressed for the entire semiconductor device. .

[0111] When the accelerator finishes executing the kernel program, the output data is stored in the memory section mentioned above. It is stored in (step S10).

[0112] After the kernel program finishes executing, the CPU will process the output data stored in memory. If the instruction to send to main memory is confirmed (step S11), the above output data The data is sent to the main memory and stored in the main memory (step S12).

[0113] When the CPU confirms an instruction to release the data area allocated in the memory section, Step S13) The area allocated on the memory section is released (Step S14).

[0114] By repeating the operations from step S1 to step S14 above, the CPU and While suppressing the power consumption and heat generation of the accelerator, a portion of the calculations performed by the CPU is performed by It can be executed using an accelerator.

[0115] This embodiment can be appropriately combined with descriptions of other embodiments.

[0116] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating is described. I will explain.

[0117] Figure 12 shows an example configuration of CPU 10. CPU 10 consists of CPU cores. )200, L1 (Level 1) Cache Memory Device (L1 Cache)202, L2 Cache memory device (L2 Cache) 203, bus interface unit (Bus I It has F)205, power switches 210~212, and level shifter (LS)214. The CPU core 200 has 220 flip-flops.

[0118] The bus interface unit 205 connects the CPU core 200 and L1 cache memory. The device 202 and the L2 cache memory device 203 are interconnected.

[0119] Interrupt signals received from external sources, signals issued by CPU10 In response to signals such as SLEEP1, the PMU193 receives the clock signal GCLK1 and various PGs. (Power gating) Generates control signals (PG control signals). The clock signal GCLK1 and the PG control signal are input to the CPU10. The PG control signal is It controls power switches 210-212 and flip-flop 220.

[0120] Power switches 210 and 211 are connected to a virtual power line V_VDD (hereinafter referred to as the V_VDD line). It controls the supply of voltages VDDD and VDD1 to the following: Power switch 212 is a temporary switch. Controls the supply of voltage VDDH to the power supply line V_VDH (hereinafter referred to as the V_VDH line). The CPU10 and PMU193 receive the VSSS voltage without going through the power switch. The voltage VDDD is input to the PMU193 without going through the power switch.

[0121] Voltages VDDD and VDD1 are drive voltages for CMOS circuits. Voltage VDD1 is equal to voltage VD It is lower than DD and is the drive voltage in sleep mode. Voltage VDDH is for OS transistors. This is the drive voltage, and it is higher than the voltage VDDD.

[0122] L1 cache memory device 202, L2 cache memory device 203, bus interface Each face section 205 has at least one power-gated power domain It has. Power-gated power domains have one or more power switches. These power switches are provided. These power switches are controlled by a PG control signal.

[0123] Flip-flop 220 is used as a register. Flip-flop 220 has a A backup circuit is provided. The flip-flop 220 will be described below.

[0124] Figure 13A shows an example of the circuit configuration of a flip-flop 220. The flip-flop 220 is a scan flip-flop. 1. It has a backup circuit 222.

[0125] Scan flip-flop 221 controls nodes D1, Q1, SD, SE, RT, CK, and It has a lock buffer circuit 221A.

[0126] Node D1 is a data input node, and node Q1 is a data output node. Yes, node SD is the input node for scan test data. Node SE is the signal SC. E is an input node. Node CK is an input node for the clock signal GCLK1. The clock signal GCLK1 is input to the clock buffer circuit 221A. The analog switch of rop 221 is located at node CK1 of the clock buffer circuit 221A, C It is connected to KB1. Node RT is the input node for the reset signal. It is.

[0127] The signal SCE is the scan enable signal and is generated by PMU193. 93 generates signals BK and RC. Level shifter 214 shifts the BK and RC signals to a higher level. Then, signals BKH and RCH are generated. Signals BK and RC are backup signals and recovery signals, respectively. That is the case.

[0128] The circuit configuration of scan flip-flop 221 is not limited to Figure 13. A typical circuit You can apply the flip-flops provided in the library.

[0129] The backup circuit 222 consists of nodes SD_IN, SN11, and transistors M11~M1 3. It has a capacitive element C11.

[0130] Node SD_IN is the input node for scan test data, and scan flip It is connected to node Q1 of rop 221. Node SN11 is connected to backup circuit 222. This is a holding node. Capacitor element C11 is a holding capacitance for holding the voltage of node SN11. be.

[0131] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 This controls the conduction state between node SD_IN and node SD. Transistors M11, M13 The on / off state of is controlled by signal BKH, and the on / off state of transistor M12 is controlled by signal RCH. It will be done.

[0132] Transistors M11 to M13 are part of the data retention circuit 31 of the memory circuit 24 described above. The transistors _N, 31_P, and transistors 32_P, 32_N, 33_ Like P and 33_N, it is an OS transistor. Transistors M11-M13 are The diagram shows a configuration with a back gate. The back gates of transistors M11 to M13 are It is connected to the power line that supplies voltage VBG1.

[0133] It is preferable that at least transistors M11 and M12 are OS transistors. Due to the OS transistor's characteristic of extremely low current, the voltage at node SN11 Because it can suppress degradation and consumes almost no power to retain data, The quap-up circuit 222 has non-volatile properties. Data is collected by charging and discharging the capacitive element C11. Because it can be rewritten, the backup circuit 222 has no limitations on the number of rewrites in principle, and is low energy Data can be written to and read using energy.

[0134] It is very important that all transistors in backup circuit 222 are OS transistors. Preferred. As shown in Figure 13B, a scan flip consisting of a silicon CMOS circuit. A backup circuit 222 can be stacked on top of the flop 221.

[0135] The backup circuit 222 has a significantly smaller number of elements compared to the scan flip-flop 221. Since there are few, scan flip-flops 222 are used to stack backup circuits 222. No changes to the circuit configuration and layout of 1 are necessary. In other words, the backup circuit 222 is This is a highly versatile backup circuit. Also, the scan flip-flop 221 is Since a backup circuit 222 can be provided within the formed region, Even with the incorporation of circuit 222, the area overhead of flip-flop 220 remains zero. Therefore, a backup circuit 222 is provided for the flip-flop 220. This enables power gating of 200 CPU cores. Because it requires less energy, it enables highly efficient power gating of the 200 CPU cores. This is possible.

[0136] By providing the backup circuit 222, the parasitic capacitance of transistor M11 is reduced. This will be added to node Q1, but it will be a parasitic capacitance due to the logic circuit connected to node Q1. Since it is smaller in comparison, it does not affect the operation of scan flip-flop 221. In other words, Even with the backup circuit 222, the performance of the flip-flop 220 does not substantially decrease. stomach.

[0137] For example, a low-power state for CPU core 200 is a clock gating state, power It is possible to set the gated state and the hibernation state. The PMU193 is an interrupt signal Based on signals such as SLEEP1, the low-power mode of CPU core 200 is selected. When transitioning from the normal operating state to the clock gating state, the PMU193 clock Stop generating the GCLK1 signal.

[0138] For example, when transitioning from normal operation to hibernation, the PMU193 will check the voltage and / Alternatively, frequency scaling can be performed. For example, when performing voltage scaling, PMU193 To input voltage VDD1 to the CPU core 200, the power switch 210 is turned off. Turn on power switch 211. Voltage VDD1 is set to scan flip-flop 22 This is the voltage that does not cause data loss. When frequency scaling is performed, the PMU193 is The frequency of the clock signal GCLK1 is reduced.

[0139] When transitioning CPU core 200 from normal operation to power gating state, The data from flip-flop 221 is backed up to backup circuit 222. The operation will be performed. The 200 CPU cores will be returned from power gating to normal operation. In that case, the data from the backup circuit 222 is recovered to the scan flip-flop 221. The action is performed.

[0140] Figure 14 shows an example of the power gating sequence for CPU core 200. In 14, t1 to t7 represent time. Signals PSE0 to PSE2 are power switches. This is a control signal for switches 210-212, generated by PMU193. Signal PSE0 is “H When " / "L", power switch 210 is on / off. Signals PSE1, PSE2 The same applies to this matter.

[0141] Before time t1, it was in normal operation state. Switch 210 is ON, and the voltage VDDD is input to CPU core 200. The flip-flop 221 operates normally. At this time, the level shifter 214 operates. Since there is no need to do so, power switch 212 is off, and signals SCE, BK, RC are “L Therefore, since node SE is "L", scan flip-flop 221 is at node D Store data 1. Note that in the example in Figure 14, at time t1, backup circuit 2 Node SN11 of 22 is "L".

[0142] This explains the operation during backup. At operation time t1, PMU193 is Stop the clock signal GCLK1 and set signals PSE2 and BK to "H". Level shifter 2 14 becomes active and outputs the "H" signal BKH to the backup circuit 222.

[0143] The transistor M11 of backup circuit 222 turns on, and scan flip-flop The data from node Q1 of circuit 221 is written to node SN11 of backup circuit 222. If node Q1 of scan flip-flop 221 is "L", then node SN11 is If it remains "L" and node Q1 is "H", then node SN11 will be "H".

[0144] PMU193 sets signal PSE2, BK to "L" at time t2, and at time t3, signal PSE Set 0 to "L". At time t3, the state of CPU core 200 transitions to power gating. Yes. Alternatively, signal PSE0 may be lowered at the same time that signal BK is lowered.

[0145] This section explains the operation during power-gating. Signal PSE0 Because the voltage becomes "L," the voltage of the V_VDD line decreases, and therefore the data at node Q1 is lost. Node SN11 continues to hold the data from node Q1 at time t3.

[0146] This section describes the operation during recovery. At time t4, PMU193 receives a signal. Setting PSE0 to "H" transitions the system from power gating to recovery mode. Charging of the V_VDD line begins, and the voltage of the V_VDD line becomes VDDD (time t5) ) Then, PMU193 sets signals PSE2, RC, and SCE to "H".

[0147] Transistor M12 turns on, and the charge of capacitive element C11 is transferred to node SN11 and node S It is distributed to D. If node SN11 is "H", the voltage at node SD will rise. Since code SE is "H", the input latch circuit of scan flip-flop 221 is no longer Data is written to the SD card. At time t6, the clock signal GCLK1 is input to node CK. When activated, the data from the input latch circuit is written to node Q1. In other words, node S The data from N11 has now been written to node Q1.

[0148] At time t7, PMU193 sets signals PSE2, SCE, and RC to "L" and performs recovery operation. The process is ending.

[0149] The backup circuit 222 using OS transistors provides both dynamic and static low power consumption. Because it is small, it is very suitable for normally-off computing. The CPU 10 includes a CPU core 200 having a backup circuit 222 using a transistor. It can be called NoffCPU (registered trademark). NoffCPU is a non-volatile polymer. It has a harpoon, and the power supply can be shut off when operation is not required. Flip-flow Even with the 220 CPU core, there is almost no performance degradation or increase in dynamic power consumption compared to the 200 CPU cores. It can be prevented from happening.

[0150] Furthermore, even though CPU Core 200 has multiple power domains capable of power gating... Good. Multiple power domains have one or more power units to control the voltage input. A switch is provided. Also, the CPU core 200 has one or more power gatings. It may have power domains where power gating is not performed. For example, power gating may not be performed. The power domain controls the flip-flop 220 and power switches 210-212. A power gating control circuit may be provided to perform this operation.

[0151] Note that the application of the flip-flop 220 is not limited to the CPU 10. A register located in a power domain that can be power-gated, and a flip-flop 220 can be applied.

[0152] This embodiment can be appropriately combined with descriptions of other embodiments.

[0153] (Embodiment 4) In this embodiment, the semiconductor device 100, CPU 10 and A described in the above embodiment are used. The transistor configuration applicable to the accelerator 20 will be described. As an example, different... A configuration in which transistors having certain electrical characteristics are stacked will be described. This increases the design flexibility of semiconductor devices. Furthermore, it allows for the use of devices with different electrical characteristics. By stacking transistors, the integration density of semiconductor devices can be increased.

[0154] A portion of the cross-sectional structure of a semiconductor device is shown in Figure 15. The semiconductor device shown in Figure 15 is a transistor It has a 550 transistor, a 500 capacitor, and a 600 capacitive element. Figure 16A shows the transistor Figure 16B is a cross-sectional view of transistor 500 in the channel length direction, and Figure 16B shows the channel of transistor 500. This is a cross-sectional view in the width direction of the panel. For example, transistor 500 is the transistor shown in the above embodiment. This corresponds to transistors 32 to 34, and transistor 550 is a Si transistor in the arithmetic circuit 23. This corresponds to a zista. Also, capacitive element 600 corresponds to capacitive element 35.

[0155] Transistor 500 is an OS transistor. OS transistors have a polarity of off-current. It is very small. Therefore, the data voltage written to the memory node via transistor 500 is Therefore, it is possible to retain charge for a long period of time. In other words, the memory node (node ​​MN) Reduce the frequency of refresh operations, or eliminate the need for refresh operations, for semiconductor equipment This can reduce the power consumption of the device.

[0156] In Figure 15, transistor 500 is located above transistor 550, and capacitive element 6 00 is located above transistors 550 and 500.

[0157] The transistor 550 is mounted on the substrate 311. The substrate 311 is, for example, a p-type silicon This is a silicon substrate. Substrate 311 may be an n-type silicon substrate. The oxide layer 314 is a substrate An insulating layer (BO) formed by burried oxide in 311 The X layer (also called the X layer) is preferably made of silicon oxide, for example. Transistor 550 is based Single crystal silicon, so-called SOI (Sil), is provided on plate 311 via an oxide layer 314. (Icon On Insulator) Provided on the circuit board.

[0158] In the SOI substrate, the substrate 311 is provided with an insulator 313 that functions as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a transistor This is a region on the SOI substrate that is given n-type or p-type conductivity depending on the conductivity type of 550. In the single-crystal silicon, the semiconductor region 315 is used as the source region or drain region. Low-resistance regions 316a and 316b are provided that enable this function. Also, on the well layer 312 It has a low-resistance region 316c.

[0159] Transistor 550 is located in a well region 312 to which impurity elements that impart conductivity are added. They can be stacked. The well region 312 independently controls the potential through the low-resistance region 316c. By changing its orientation, it can function as the bottom gate electrode of transistor 550. This is possible. Therefore, the threshold voltage of transistor 550 can be controlled. In particular By applying a negative potential to the well region 312, the threshold voltage of transistor 550 is reduced. It becomes possible to increase the voltage and reduce the off-current. Therefore, well region 31 By applying a negative potential to 2, the potential applied to the gate electrode of the Si transistor becomes 0V. The drain current can be reduced. As a result, the transistor 550 has This reduces power consumption based on through-currents, etc., in the calculation circuit 23, thereby improving calculation efficiency. It is possible.

[0160] Transistor 550 has an insulator 317 on the top surface and side surface in the channel width direction of the semiconductor layer. It is preferable to have a so-called Fin type, where the conductor 318 is covered via a transit. By making the ST550 a Fin type, the effective channel width is increased, thus improving traction. The ON characteristics of the inverter 550 can be improved. Also, the contribution of the electric field of the gate electrode can be improved. Because the value can be increased, the off-state characteristics of transistor 550 can be improved.

[0161] Note that transistor 550 is either a p-channel type transistor or an n-channel type transistor. Any transistor will do.

[0162] Conductor 318 may function as the first gate (also called the top gate) electrode. Furthermore, the well region 312 functions as the second gate (also called the bottom gate) electrode. In some cases, the potential applied to the well region 312 is applied via the low-resistance region 316c. It can be controlled.

[0163] The region where the channel of the semiconductor region 315 is formed, the neighboring region, the source region, or The drain region is a low-resistance region 316a, and the low-resistance region 316b, and the well region 312 In a low-resistance region 316c connected to an electrode that controls the potential, a silicon-based semiconductor It is preferable to include semiconductors such as G e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may also be formed from a material containing GaAlAs (gallium aluminum arsenide), etc. A silicon-based structure in which the effective mass is controlled by applying stress to the particles and changing the lattice spacing. Alternatively, by using GaAs and GaAlAs, the transistor 550 can be made It can also be represented as MT.

[0164] Well region 312, low resistance region 316a, low resistance region 316b, and low resistance region 31 6c is a semiconductor material applied to semiconductor region 315, as well as n-type conductive materials such as arsenic and phosphorus. It contains an element that imparts properties, or an element that imparts p-type conductivity, such as boron.

[0165] The conductor 318, which functions as a gate electrode, imparts n-type conductivity to arsenic, phosphorus, etc. Semiconductor materials such as silicon containing elements, or elements that impart p-type conductivity, such as boron. Conductive materials such as cellulose, metallic materials, alloy materials, or metal oxide materials can be used. Furthermore, the conductor 318 may be a silicide such as nickel silicide.

[0166] Furthermore, since the work function is determined by the material of the conductor, the material of the conductor must be selected accordingly. This allows you to adjust the threshold voltage of the transistor. Specifically, by using nitride in the conductor... It is preferable to use materials such as tan or tantalum nitride. Furthermore, both conductivity and embedding properties are desirable. To achieve this, metal materials such as tungsten and aluminum are used as laminates in the conductive material. This is preferable, and using tungsten is particularly preferable in terms of heat resistance.

[0167] Low-resistance region 316a, low-resistance region 316b, and low-resistance region 316c are made of another conductor For example, a configuration in which silicides such as nickel silicide are laminated may be used. By doing so, the conductivity of the region that functions as an electrode can be increased. , the side of the conductor 318 which functions as the gate electrode, and the insulating film which functions as the gate insulating film The sides of the edge body have an insulator that functions as a sidewall spacer (also called a sidewall insulating layer). A configuration may be provided that includes the conductor 318 and the low-resistance region 316. This prevents a and the low-resistance region 316b from becoming conductive.

[0168] The transistor 550 is covered with insulators 320, 322, 324, and The edge members 326 are arranged in a series of stacked layers.

[0169] For example, acid Silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc., can be used.

[0170] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials with a higher nitrogen content than oxygen content.

[0171] The insulator 322 provides a step created by the transistor 550 and the like located below it. It may also function as a planarizing film that flattens the surface. For example, the upper surface of the insulator 322 is To improve flatness, the surface is flattened using a planarization treatment such as chemical mechanical polishing (CMP). It's fine if you do that.

[0172] Furthermore, the insulator 324 receives transistors from the substrate 311 or transistors 550, etc. A barrier film is provided in the region where the STA500 is installed, so as not to diffuse hydrogen or impurities. It is preferable to use it.

[0173] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD A semiconductor can be used. Here, a semiconductor having an oxide semiconductor such as transistor 500 can be used. The diffusion of hydrogen into the semiconductor element may degrade the characteristics of that semiconductor element. So, a film that suppresses hydrogen diffusion is placed between transistor 500 and transistor 550. It is preferable to use it. Specifically, a membrane that suppresses hydrogen diffusion is one in which the amount of hydrogen desorption is small. It will be called a membrane.

[0174] The amount of hydrogen desorption can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. Yes, it is possible. For example, the amount of hydrogen desorption from insulator 324 can be determined by TDS analysis when the film surface temperature is In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is the area of ​​the insulator 324. Converted to a single win, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 a toms / cm 2 The following is acceptable.

[0175] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, The relative permittivity of the edge material 326 is preferably less than 4, and more preferably less than 3. Also, for example, an insulator... The relative permittivity of 326 is preferably 0.7 times or less, and preferably 0.6 times or less, than the relative permittivity of the insulator 324. This is more preferable. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wiring is reduced. It can be reduced.

[0176] Furthermore, insulators 320, 322, 324, and 326 contain capacitive elements. Conductors 328 and 330, etc., which connect to transistor 600 or transistor 500, are embedded. It is embedded. Note that conductors 328 and 330 are used as plugs or wiring. It has the function of a plug or wiring. In addition, a conductor that has multiple configurations In some cases, the same code may be assigned to multiple components. Also, in this specification, etc., wiring and wiring and The plug to be connected may be an integral part of the device. That is, a part of the conductor may function as wiring. In some cases, a portion of the conductor may function as a plug.

[0177] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials. Conductive materials such as alloy materials, metal nitride materials, or metal oxide materials are used in a single layer or in a multilayer structure. It can be used in this way. High heat resistance and conductivity can be achieved with tungsten, molybdenum, and other materials. It is preferable to use a melting point material, and it is preferable to use tungsten. Alternatively, aluminum It is preferable to form it with a low-resistance conductive material such as aluminum or copper. This can lower the wiring resistance.

[0178] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 15 Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. Conductor 356 functions as a plug or wire connecting to transistor 550. It has the same material as conductors 328 and 330. It can be established.

[0179] Furthermore, for example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, it is preferable to include an insulator 350 that has barrier properties against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0180] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. It would be good to do so. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be made It is possible to suppress the diffusion of hydrogen from transistor 550 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen has barrier properties against hydrogen It is preferable that the insulator 350 having the above characteristics is in contact with the insulator 350.

[0181] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 15 Insulators 360, 362, and 364 are arranged in a series of layers. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. Conductor 366 has the function of a plug or wiring. It can be provided using the same material as conductors 328 and 330.

[0182] Furthermore, for example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0183] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 15 Insulators 370, 372, and 374 are arranged in a sequential stack. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. It is present. Conductor 376 has the function of a plug or wiring. Note that Conductor 376 is It can be provided using the same material as conductors 328 and 330.

[0184] Furthermore, for example, insulator 370, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 376 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 370 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0185] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 15 Insulators 380, 382, ​​and 384 are arranged in a sequential stack. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. It can be provided using the same material as conductors 328 and 330.

[0186] For example, insulator 380, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 386 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 380 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0187] In the above, a wiring layer containing a conductor 356, a wiring layer containing a conductor 366, and a conductor 376 A wiring layer including and a wiring layer including the conductor 386 have been described, but in this embodiment The semiconductor device is not limited to this. Wiring layers similar to those containing the conductor 356 The number of layers may be three or fewer, or the number of wiring layers similar to the wiring layer containing conductor 356 may be five or more. That's fine.

[0188] Insulator 384 is on insulator 510, insulator 512, insulator 514, and insulator 516 However, they are arranged in layers in order. Insulator 510, insulator 512, insulator 514, and It is preferable that one of the insulators 516 be made of a material that has barrier properties against oxygen and hydrogen. It's nice.

[0189] For example, the insulator 510 and the insulator 514 are connected to, for example, the substrate 311 or a transistor. From the area where the transistor 550 is installed, hydrogen and impurities are transferred to the area where the transistor 500 is installed. It is preferable to use a film that has barrier properties against [the substance]. Therefore, similar to insulator 324. These materials can be used.

[0190] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to have a semiconductor device having an oxide semiconductor such as transistor 500. Furthermore, hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 550. This is preferable.

[0191] Furthermore, as a film having barrier properties against hydrogen, for example, insulator 510 and insulator 514 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable to do so.

[0192] In particular, aluminum oxide is a source of oxygen and water, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both elements and impurities such as water from passing through the membrane. Therefore, Aluminum oxide is affected by hydrogen, moisture, etc. during and after the transistor fabrication process. This prevents impurities from entering transistor 500. The release of oxygen from the oxides that make up 00 can be suppressed. Therefore, the transient It is suitable for use as a protective film for Ta500.

[0193] Furthermore, for example, the insulators 512 and 516 are made of the same material as the insulator 320. It can be used. Furthermore, these insulators can be made by applying materials with relatively low dielectric constants. This reduces parasitic capacitance between wires. For example, insulator 512, and As the edge 516, a silicon oxide film or a silicon oxide-nitride film can be used.

[0194] Furthermore, insulators 510, 512, 514, and 516 contain conductive materials. 518, and the conductors (e.g., conductor 503) that make up transistor 500 are embedded It is embedded. Furthermore, the conductor 518 is in contact with the capacitive element 600 or the transistor 550. It functions as a connecting plug or wiring. Conductor 518 is connected to conductor 328, and It can be provided using the same material as the conductor 330.

[0195] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is oxygen, hydrogen Preferably, the material is a conductor that has barrier properties against water. With this configuration, The Rangista 550 and Transistor 500 have barrier properties against oxygen, hydrogen, and water. In the layer having, it can be separated, and hydrogen from transistor 550 to transistor 500 This can suppress the spread of [the substance].

[0196] A transistor 500 is provided above the insulator 516.

[0197] As shown in Figures 16A and 16B, transistor 500 is connected to insulator 514 and insulator A conductor 503 is arranged to be embedded in the edge 516, and the insulator 516 and the conductor An insulator 520 placed on top of 503, and an insulator 522 placed on top of insulator 520 , an insulator 524 placed on top of the insulator 522, and an oxide placed on top of the insulator 524. 530a, oxide 530b placed on oxide 530a, and on oxide 530b Conductors 542a and 542b are arranged at a distance from each other, and conductor 542a and conductor It is placed on the conductive body 542b and superimposed between the conductive body 542a and the conductive body 542b to form an opening. The insulator 580, the insulator 545 positioned on the bottom and sides of the opening, and the insulator 54 It has a conductor 560 arranged on the forming surface of 5.

[0198] Furthermore, as shown in Figures 16A and 16B, oxide 530a, oxide 530b, and conductive An insulator 544 is placed between the body 542a, the conductor 542b, and the insulator 580. This is preferable. Also, as shown in Figures 16A and 16B, the conductor 560 is an insulator 5 A conductor 560a is provided inside 45, and is embedded inside the conductor 560a It is preferable to have a conductor 560b provided. Also, Figures 16A and 16B As shown, an insulator 574 is placed on top of an insulator 580, a conductor 560, and an insulator 545. It is preferable that they be arranged in this manner.

[0199] In this specification, oxides 530a and 530b are collectively referred to as oxidation. There are cases where the item is listed as 530.

[0200] Furthermore, in transistor 500, in the region where the channel is formed and in its vicinity, acid The present invention describes a configuration in which two layers, oxide 530a and oxide 530b, are stacked, but The possibilities are not limited to this. For example, a single layer of oxide 530b, or a layer of three or more layers. A layered configuration may also be used.

[0201] Furthermore, in transistor 500, the conductor 560 is shown as a two-layer stacked structure, The present invention is not limited thereto. For example, the conductor 560 may have a single-layer configuration. Furthermore, a laminated structure of three or more layers is also acceptable. Also, as shown in Figures 15, 16A, and 16B The transistor 500 shown is just one example, and its configuration is not limited to this example; circuit configurations and driving methods may also vary. You should use the appropriate transistor depending on the situation.

[0202] Here, conductor 560 functions as the gate electrode of the transistor, and conductor 542a The conductor 542b functions as either a source electrode or a drain electrode, respectively. Thus, the conductor 560 is located at the opening of the insulator 580, and the conductors 542a and 542b It is formed to be embedded in the region sandwiched between the conductor 560, conductor 542a and The arrangement of the conductor 542b is self-aligned with the opening of the insulator 580. In transistor 500, the gate electrode is placed between the source electrode and the drain electrode. They can be arranged in a self-aligned manner. Therefore, a margin for alignment is provided for the conductor 560. Since it can be formed without any modifications, the occupied area of ​​transistor 500 can be reduced. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0203] Furthermore, the conductor 560 is self-aligned in the region between conductor 542a and conductor 542b. As a result, the conductor 560 is formed in a region that overlaps with the conductor 542a or the conductor 542b. It does not have. As a result, between conductor 560 and conductors 542a and conductor 542b The parasitic capacitance that is formed can be reduced. Therefore, the switching of transistor 500 This allows for improved speed and enhanced frequency response.

[0204] Conductor 560 may function as the first gate (also called the top gate) electrode. Furthermore, when the conductor 503 functions as the second gate (also called the bottom gate) electrode... In that case, the potential applied to the conductor 503 is the same as the potential applied to the conductor 560. By controlling the threshold voltage of transistor 500 independently without moving it, it is possible to control the threshold voltage of transistor 500. This can be done. In particular, by applying a negative potential to the conductor 503, the transistor 500 This makes it possible to increase the threshold voltage and reduce the off-current. Applying a negative potential to the electric element 503 is more effective than not applying a negative potential to the conductor 560. The drain current can be reduced when the potential is 0V.

[0205] The conductor 503 is positioned to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the conductor 560 produces The electric field generated by the conductor 503 connects with the electric field generated by the conductor 503, and a chain reaction is formed in the oxide 530. It can cover the channel formation region.

[0206] In this specification, etc., a pair of gate electrodes (a first gate electrode and a second gate electrode) The electric field of ) electrically surrounds the transistor configuration that forms the channel formation region, This is called a rounded channel (S-channel) configuration. The S-channel configuration disclosed is different from the Fin-type configuration and the Planar-type configuration. By adopting an S-channel configuration, resistance to short-channel effects is increased, in other words This makes it possible to create a transistor that is less susceptible to short-channel effects.

[0207] Furthermore, the conductor 503 has the same configuration as the conductor 518, and the insulator 514 and the insulator A conductor 503a is formed in contact with the inner wall of the opening 516, and a conductor 503b is further inside. It is formed. In transistor 500, conductor 503a and conductor 503b The present invention describes a configuration in which layers are stacked, but is not limited thereto. For example, The conductor 503 may be provided as a single layer or as a laminated structure of three or more layers.

[0208] Here, the conductor 503a diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing (the above-mentioned impurities are less likely to permeate) It is difficult. Or, it inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material that has the function of (being impermeable to the above-mentioned oxygen). In this specification, the function of suppressing the diffusion of impurities or oxygen means the above-mentioned impurities, and This function suppresses the diffusion of any one or all of the above-mentioned oxygen molecules.

[0209] For example, the conductor 503a has the function of suppressing the diffusion of oxygen, This can suppress the oxidation of b, which reduces its conductivity.

[0210] Furthermore, if the conductor 503 also functions as wiring, the conductor 503b may be tungsten or copper. Alternatively, it is preferable to use a highly conductive material, such as one primarily composed of aluminum. In this embodiment, the conductor 503 is shown as a laminate of conductor 503a and conductor 503b. However, the conductor 503 may have a single-layer configuration.

[0211] Insulators 520, 522, and 524 serve as a second gate insulating film. To have the ability.

[0212] Here, the insulator 524 in contact with the oxide 530 is more abundant than the oxygen that satisfies the stoichiometric composition. It is preferable to use an insulator containing oxygen. This oxygen is released from the film by heating. It is easily released. In this specification, the oxygen released by heating is sometimes referred to as "excess oxygen." In other words, the insulator 524 has a region containing excess oxygen (also called the "excess oxygen region"). It is preferable that such an insulator containing excess oxygen is brought into contact with oxide 530. By providing this, oxygen deficiencies (V) in oxide 530 are eliminated. O :oxygen vacancy This reduces (also known as) and improves the reliability of transistor 500. If hydrogen enters the oxygen vacancy in compound 530, the defect (hereinafter referred to as V) O It is sometimes referred to as H. ) can function as a donor, and electrons, which are carriers, can be generated. Also, hydrogen In some cases, it combines with oxygen atoms that bond with metal atoms, generating electrons, which act as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content are normally-on It is prone to becoming a characteristic. Also, hydrogen in oxide semiconductors moves due to stress such as heat and electric fields. Because it is prone to this, if oxide semiconductors contain a lot of hydrogen, the reliability of transistors deteriorates. There is also a risk that V in oxide 530 O Reduce H as much as possible It is preferable to make it highly pure or substantially highly pure. Thus, V O H is ten To obtain an oxide semiconductor with reduced molecular weight, impurities such as water and hydrogen must be removed from the oxide semiconductor. This involves (also called "dehydration" or "dehydrogenation") supplying oxygen to the oxide semiconductor. It is important to compensate for the oxygen deficiency (also called "oxygenation treatment").O H etc. By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor... This allows for the provision of stable electrical characteristics.

[0213] As an insulator having an excess oxygen region, specifically, an acid in which some of the oxygen is removed by heating. It is preferable to use an oxide material. Oxides that desorb oxygen upon heating include TDS(Th In urinary desorption spectroscopy analysis, oxygen atoms were found to The amount of oxygen removed after conversion is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 1.0 ×10 19 atoms / cm 3 More preferably 2.0 × 10 19 ate / c m 3 Above, or 3.0 × 10 20 atoms / cm 3 The above describes the oxide film. The surface temperature of the film during the above TDS analysis is 100°C to 700°C, or 1 A temperature range of 00°C to 400°C is preferred.

[0214] Furthermore, the insulator having the above excess oxygen region and oxide 530 are brought into contact and heat treated, One or more of the following processes may be performed: Kuroh wave processing or RF processing. By doing so, water or hydrogen can be removed from oxide 530. For example, oxide At 530, a reaction occurs in which the VoH bond is broken, or in other words, "V O H→Vo+ The reaction H occurs, which can lead to dehydrogenation. Some of the hydrogen produced at this time is It combines with oxygen to form H2O and is removed from oxide 530 or the insulator near oxide 530. This may happen.

[0215] Furthermore, the above microwave processing is performed using, for example, an apparatus having a power supply that generates high-density plasma. Alternatively, it is preferable to use a device that has a power supply that applies RF to the substrate side. For example, acid By using a gas containing elements and employing a high-density plasma, high-density oxygen radicals are generated. This can be achieved by applying RF to the substrate side, generating high-density plasma. Efficiently introduce oxygen radicals into oxide 530 or an insulator near oxide 530. This can be done. Furthermore, the above microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa. The Pa should be Pa or higher, more preferably 400 Pa or higher. For example, oxygen and argon are used as gases introduced into the apparatus, with an oxygen flow rate ratio (O2 The process should be carried out with (O2+Ar) content of 50% or less, preferably between 10% and 30%.

[0216] Furthermore, during the manufacturing process of transistor 500, the surface of oxide 530 is exposed. Therefore, heat treatment is preferable. This heat treatment is, for example, 100°C to 450°C. More preferably, the heating should be carried out at a temperature of 350°C to 400°C. The heat treatment is performed using nitrogen gas. Alternatively, an inert gas atmosphere, or an oxidizing gas at 10 ppm or more, 1% or more, The procedure should be carried out in an atmosphere containing 10% or more of the substance. For example, heat treatment is preferably carried out in an oxygen atmosphere. This supplies oxygen to oxide 530, thus eliminating oxygen deficiency (V O This can help reduce ) Furthermore, the heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or After heat treatment in an active gas atmosphere, an oxidizing gas is added at 10 pJ to replenish the desorbed oxygen. The procedure may be carried out in an atmosphere containing 1% or more of the substance, or 10% or more of the substance. Alternatively, an oxidizing gas may be used. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, then continuously The heat treatment may be carried out in a nitrogen gas or inert gas atmosphere.

[0217] Furthermore, by performing an oxygenation treatment on oxide 530, the oxygen deficiencies in oxide 530 are supplied. The oxygen used for repair, or in other words, the reaction "Vo + O → null" is promoted. Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530. This allows the hydrogen to be removed as H2O (dehydrated). This eliminates oxidation. The hydrogen remaining in substance 530 recombines with the oxygen vacancy and V O Suppresses the formation of H It is possible.

[0218] Furthermore, if the insulator 524 has an excess oxygen region, the insulator 522 will have oxygen (for example, It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (making it difficult for the above-mentioned oxygen to permeate). This is preferable.

[0219] The insulator 522 has the function of suppressing the diffusion of oxygen and impurities, so the oxide 530 The oxygen present does not diffuse towards the insulator 520, which is preferable. Also, the conductor 503 This suppresses the reaction between the insulator 524 and the oxygen present in the oxide 530.

[0220] The insulator 522 is, for example, aluminum oxide, hafnium oxide, aluminum and Humium-containing oxides (hafnium aluminate), tantalum oxide, zirconium oxide, Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or ( A single layer of insulator containing so-called high-k materials such as Ba,Sr)TiO3(BST) Alternatively, it is preferable to use them in a stacked configuration. As transistors become smaller and more integrated, Thinning the gate insulating film can sometimes lead to problems such as leakage current. By using a high-k material as an insulator that functions in this way, the physical film thickness is maintained while transforming This allows for a reduction in gate potential during DISTRO operation.

[0221] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the above oxygen does not permeate easily). i) An insulator containing an oxide of either aluminum or hafnium, or both, which are insulating materials. It is recommended to use an insulator containing an oxide of either aluminum or hafnium, or both. aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium ( It is preferable to use materials such as hafnium aluminate. When 522 is formed, the insulator 522 prevents the release of oxygen from the oxide 530 and the transient It functions as a layer that suppresses the incorporation of impurities such as hydrogen from the peripheral area of ​​T500 into the oxide 530. ru.

[0222] Alternatively, these insulators may be, for example, aluminum oxide, bismuth oxide, germanium oxide. Umium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated as the insulator. .

[0223] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide Silicon oxide nitride is preferred because it is thermally stable. Also, high-k material By combining the insulator with silicon oxide or silicon oxide nitride, thermal stability can be achieved. This allows us to obtain an insulator 520 or an insulator 526 with a multilayer structure and a high relative dielectric constant.

[0224] Note that the transistor 500 in Figures 16A and 16B has a three-layer stacked structure. Insulators 520, 522, and 524 are shown as gate insulating films of the 2. However, the second gate insulating film has a single-layer, two-layer, or four-layer or more stacked structure. In that case, the laminated structure is not limited to one made of the same material, but can also be made of different materials. "Natural" is also acceptable.

[0225] Transistor 500 is an oxide semiconductor in oxide 530 including a channel formation region. A functional metal oxide is used. For example, as oxide 530, In-M-Zn oxide (original The elements M are aluminum, gallium, yttrium, copper, vanadium, beryllium, and boron. Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from materials such as magnesium, neodymium, hafnium, tantalum, tungsten, or magnesium. It is preferable to use one or more types of metal oxides.

[0226] The formation of metal oxides that function as oxide semiconductors may be carried out by sputtering. Alternatively, the Atomic Layer Deposition (ALD) method may be used. The metal oxides that function as oxide semiconductors will be described in detail in other embodiments. do.

[0227] Furthermore, the metal oxide that functions as a channel-forming region in oxide 530 is bandg It is preferable to use a cap with a voltage of 2 eV or more, preferably 2.5 eV or more. By using metal oxides with a large band gap, the off-current of the transistor can be reduced. It can be reduced.

[0228] Oxide 530 has oxide 530a beneath oxide 530b, so oxide 530a The diffusion of impurities from the components formed below to oxide 530b is suppressed. can.

[0229] Furthermore, oxide 530 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. It is preferable to do so. Specifically, in the metal oxide used in oxide 530a, the constituent elements The atomic ratio of element M in the elementary oxide is the ratio of constituent elements in the metal oxide used in oxide 530b. It is preferable that it is greater than the atomic ratio of element M. Also, the metal oxide used in oxide 530a In the material, the atomic ratio of element M to In is the same as that of the metal oxide used in oxide 530b. It is preferable that the atomic ratio of element M to In is greater than that of In. Also, oxide 530b In the metal oxide used, the atomic ratio of In to element M is used in oxide 530a. It is preferable that the atomic ratio of In to element M in the metal oxide is greater than that of In.

[0230] Furthermore, the energy at the lower end of the conduction band of oxide 530a is equal to the energy at the lower end of the conduction band of oxide 530b. It is preferable that it be higher than the energy. In other words, the electron affinity of oxide 530a. However, it is preferable that it be smaller than the electron affinity of oxide 530b.

[0231] Here, at the junction of oxide 530a and oxide 530b, the energy at the lower end of the conduction band The Ghee level changes smoothly. In other words, the junction of oxide 530a and oxide 530b The energy levels at the lower end of the conduction band at the junction are said to change continuously or form a continuous junction. This can be done. In order to do this, at the interface between oxide 530a and oxide 530b It is desirable to lower the defect level density of the mixed layer that is formed.

[0232] Specifically, oxides 530a and 530b have a common element other than oxygen (main By using it as a component, a mixed layer with a low defect level density can be formed. For example, oxidation If substance 530b is an In-Ga-Zn oxide, then oxide 530a is In-Ga-Zn Oxides, Ga-Zn oxide, and gallium oxide are good choices to use.

[0233] In this case, the main carrier pathway is oxide 530b. Oxide 530a is constructed as described above. By doing so, the defect level density at the interface between oxide 530a and oxide 530b is reduced. This makes it possible. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and traction The 500 inverter can achieve high on-current.

[0234] On the oxide 530b are conductors 542, which function as source and drain electrodes. a and conductor 542b are provided. It is aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum Tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Nium, beryllium, indium, ruthenium, iridium, strontium, lanthanum A metal element selected from the above, or an alloy containing the above metal elements, or the above metal elements It is preferable to use an alloy that combines these elements. For example, tantalum nitride, titanium nitride, t sten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum It is preferable to use oxides containing nitriding and nickel. Also, tantalum nitride, titanium nitride Titanium nitrides containing titanium and aluminum, tantalum nitrides containing tantalum and aluminum, oxides Thenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel Oxides containing Kel are conductive materials that are resistant to oxidation, or that maintain their conductivity even after absorbing oxygen. It is preferable because it is a material that does so. Furthermore, metal nitride films such as tantalum nitride are hydrogen or It is preferable because it has barrier properties against oxygen.

[0235] Furthermore, Figure 16A shows the conductors 542a and 542b as single-layer structures. However, a laminated structure of two or more layers is also possible. For example, a tantalum nitride film and a tungsten film can be laminated. This is a good idea. Alternatively, a titanium film and an aluminum film may be laminated. Also, a tungsten film may be used. A two-layer structure with an aluminum film laminated on top, and copper on a copper-magnesium-aluminum alloy film. Two-layer structure with stacked films, two-layer structure with a copper film stacked on a titanium film, copper film on a tungsten film A two-layer structure with stacked layers is also possible.

[0236] Furthermore, a titanium film or titanium nitride film, and a layer on top of the titanium film or titanium nitride film. A luminium film or copper film is laminated, and then a titanium film or titanium nitride film is formed on top of it. A three-layer structure consisting of a molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the butene film, and then a molybdenum film is laid on top of that. Alternatively, there are three-layer structures that form a molybdenum nitride film. Furthermore, indium oxide, tin oxide, and A transparent conductive material containing zinc oxide may also be used.

[0237] Furthermore, as shown in Figure 16A, the oxide 530 has conductor 542a (conductor 542b) and At the interface and its vicinity, regions 543a and 543b are formed as low-resistance regions. In some cases, this may occur. In this case, region 543a may be either the source region or the drain region. It functions, and region 543b functions as either the source region or the drain region. A channel-forming region is formed in the region sandwiched between region 543a and region 543b.

[0238] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, The oxygen concentration in region 543a (region 543b) may decrease. Also, region 543a ( In region 543b), the metal contained in conductor 542a (conductor 542b) and oxide 530 A metal compound layer containing the component may be formed. In such cases, region 543a (region The carrier density in region 543b increases, and region 543a (region 543b) becomes a low-resistance region. Yes.

[0239] The insulator 544 is provided so as to cover the conductors 542a and 542b, and is conductive The oxidation of body 542a and conductor 542b is suppressed. At this time, the insulator 544 is oxidized. It may be provided so as to cover the side of object 530 and be in contact with the insulator 524.

[0240] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Umium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc., may be used. It can be. Also, as insulator 544, silicon nitride or silicon nitride It can be used in any way.

[0241] In particular, as insulator 544, an oxide of either aluminum or hafnium or both Insulators containing materials, such as aluminum oxide, hafnium oxide, aluminum, and haf It is preferable to use an oxide containing nium (such as hafnium aluminate). In particular, Hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, in subsequent processes... In heat treatment, it is preferable because it does not easily crystallize. Note that conductor 542a and conductive Body 542b is a material that is oxidation-resistant, or whose conductivity does not significantly decrease even when it absorbs oxygen. In some cases, the insulator 544 is not an essential component. Depending on the desired transistor characteristics, it can be configured as appropriate. Just calculate it.

[0242] The presence of the insulator 544 allows water and other impurities such as hydrogen contained in the insulator 580 to be absorbed. Diffusion to oxide 530b via insulator 545 can be suppressed. The excess oxygen present in the insulator 580 can suppress the oxidation of the conductor 560. ru.

[0243] The insulator 545 functions as the first gate insulating film. The insulator 545 is the insulating film as described above. Similar to body 524, an insulator that contains excess oxygen and releases oxygen upon heating is used. It is preferable to form it.

[0244] Specifically, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide containing excess oxygen silicon dioxide, silicon oxide with added fluorine, silicon oxide with added carbon, carbon, Silicon oxide with added nitrogen and porous silicon oxide can be used. Furthermore, silicon oxide and silicon oxide-nitride are preferred because they are stable to heat.

[0245] By providing an insulator containing excess oxygen as insulator 545, acid is released from insulator 545. It can effectively supply oxygen to the channel-forming region of compound 530b. Also, an insulator Similar to 524, the concentration of impurities such as water or hydrogen in the insulator 545 is reduced. It is preferable that the film thickness of the insulator 545 be between 1 nm and 20 nm. Even if the microwave treatment described above is performed before and / or after the formation of the insulator 545, good.

[0246] Furthermore, in order to efficiently supply the excess oxygen contained in the insulator 545 to the oxide 530, A metal oxide may be provided between the edge 545 and the conductor 560. The metal oxide is an insulating material. It is preferable to suppress oxygen diffusion from body 545 to conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. This means that the decrease in the amount of excess oxygen supplied to oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. For the insulator 544, any material suitable for use in the insulator 544 may be used.

[0247] Furthermore, the insulator 545 may be in a laminated configuration, similar to the second gate insulating film. As DISTRS become smaller and more highly integrated, the gate insulating film becomes thinner, reducing leakage current. Because any of these problems may occur, the insulator that acts as the gate insulating film is high-k By creating a laminated structure of one material and a thermally stable material, the physical film thickness is maintained while... This allows for a reduction in gate potential during transistor operation. Furthermore, it offers thermal stability and a high dielectric constant. A laminated structure can be formed.

[0248] The conductor 560, which functions as the first gate electrode, has a two-layer structure in Figures 16A and 16B. Although shown as a single-layer structure, it may also be a laminated structure of three or more layers.

[0249] Conductor 560a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. Conductive material (such as N2O, NO, NO2, etc.) has the function of suppressing the diffusion of impurities such as copper atoms. It is preferable to use a material with low oxygen content. Alternatively, a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that has the function of suppressing the diffusion of (1). Conductor 5 Because 60a has the function of suppressing oxygen diffusion, the oxygen contained in the insulator 545 This suppresses the oxidation of the conductor 560b and the resulting decrease in conductivity. Examples of conductive materials that have the function of suppressing dispersion include tantalum, tantalum nitride, and luteinizing agent. It is preferable to use nium or ruthenium oxide. Also, the conductor 560a is used. Therefore, an oxide semiconductor applicable to oxide 530 can be used. In that case, conductor 5 By depositing 60b using the sputtering method, the electrical resistance of the conductor 560a is reduced. It can be made into a conductor. This is called an OC (Oxide Conductor) electrode. It is possible.

[0250] Furthermore, the conductive material 560b is a conductive material whose main components are tungsten, copper, or aluminum. It is preferable to use a conductive material. Also, since the conductive material 560b also functions as wiring, It is preferable to use a highly conductive material. For example, tungsten, copper, or aluminum. A conductive material mainly composed of nium can be used. In addition, the conductive material 560b has a laminated structure. It may also be a laminated structure of titanium or titanium nitride and the above conductive material. good.

[0251] The insulator 580 is connected to the conductors 542a and 542b via the insulator 544. It is provided. The insulator 580 preferably has an excess oxygen region. For example, insulator 5 As 80, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine silicon oxide with added nitrogen, silicon oxide with added carbon, carbon, and nitrogen Preferably, it has silicon oxide, porous silicon oxide, or a resin. In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Silicon oxide, including porous silicon oxide, readily forms excess oxygen regions in subsequent processes. This is preferable because it allows for this.

[0252] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580, oxygen in the insulator 580 is efficiently supplied to the oxide 530. This is possible. Furthermore, the concentration of impurities such as water or hydrogen in the insulator 580 is reduced. It is preferable to do so.

[0253] The opening in the insulator 580 is formed superimposed on the region between the conductor 542a and the conductor 542b. This allows the conductor 560 to communicate with the opening of the insulator 580 and the conductor 542a. It is formed so as to be embedded in the region sandwiched between body 542b.

[0254] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but the conductor 5 It is necessary to prevent the conductivity of 60 from decreasing. To that end, the film thickness of conductor 560 is increased. As a result, the conductor 560 can have a shape with a high aspect ratio. In this embodiment, In order to embed the body 560 into the opening of the insulator 580, the conductor 560 is aspect ratio Even when forming a shape with a high ratio, it is possible to form the conductive material 560 without causing it to collapse during the process. Cut.

[0255] The insulator 574 is located on the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. It is preferable that it be provided in contact with the surface. The insulator 574 is deposited by sputtering. This allows for the creation of excess oxygen regions in insulators 545 and 580. Therefore, oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0256] For example, as insulator 574, hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium It is possible to use metal oxides containing one or more types of metals selected from nesium, etc. Cut.

[0257] In particular, aluminum oxide has high barrier properties and is suitable for thin films of 0.5 nm to 3.0 nm. However, the diffusion of hydrogen and nitrogen can be suppressed. Therefore, sputtering The aluminum oxide film formed by this method serves as an oxygen source and also acts as a barrier against impurities such as hydrogen. It can also function as a membrane.

[0258] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. i. Insulator 581, like insulator 524, has an impurity concentration of water or hydrogen in the film. It is preferable that this is reduced.

[0259] Furthermore, the insulators 581, 574, 580, and 544 are formed Conductors 540a and 540b are placed in the opening. Body 540b is provided opposite the conductor 560, with the conductor 540a and conductor 54 0b has the same configuration as conductors 546 and 548, which will be described later.

[0260] An insulator 582 is provided on the insulator 581. The insulator 582 is designed to absorb oxygen and hydrogen. In contrast, it is preferable to use a barrier material. Therefore, the insulator 582 is an insulating material. The same material as the edge 514 can be used. For example, aluminum oxide can be used for the insulator 582. It is preferable to use metal oxides such as nium, hafnium oxide, and tantalum oxide.

[0261] In particular, aluminum oxide is a source of oxygen and water, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both elements and impurities such as water from passing through the membrane. Therefore, Aluminum oxide is affected by hydrogen, moisture, etc. during and after the transistor fabrication process. This prevents impurities from entering transistor 500. The release of oxygen from the oxides that make up 00 can be suppressed. Therefore, the transient It is suitable for use as a protective film for Ta500.

[0262] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 is an insulator Similar materials to 320 can be used. In addition, these insulators have a relatively low dielectric constant. By applying a suitable material, parasitic capacitance between wires can be reduced. For example, As the edge element 586, silicon oxide film or silicon oxide nitride film can be used.

[0263] Also, insulator 520, insulator 522, insulator 524, insulator 544, insulator 580, The edge 574, insulator 581, insulator 582, and insulator 586 contain a conductor 546, Conductors such as 548 are embedded within it.

[0264] Conductors 546 and 548 are connected to the capacitive element 600, the transistor 500, or It functions as a plug or wiring for connecting to transistor 550. Conductor 546 , and conductor 548 are provided using the same material as conductor 328 and conductor 330. It is possible.

[0265] Furthermore, after the formation of the transistor 500, an opening is formed to surround the transistor 500. An insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By encasing the transistor 500 in the aforementioned highly barrier-type insulator, moisture from the outside is prevented... And it can prevent hydrogen from entering. Or, multiple transistors 500 They may be encapsulated together in an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, an insulator 522 or an insulator An opening is formed that reaches 514, and the above-mentioned bar is made to contact the insulator 522 or the insulator 514. By forming a highly reflective insulator, it can also serve as part of the manufacturing process for transistor 500. Therefore, it is suitable. Furthermore, an insulator with high barrier properties against hydrogen or water is, for example, Alternatively, the same material as insulator 522 or insulator 514 may be used.

[0266] Next, a capacitive element 600 is provided above the transistor 500. 600 comprises a conductor 610, a conductor 620, and an insulator 630.

[0267] Furthermore, a conductor 612 may be provided on the conductor 546 and the conductor 548. 612 functions as a plug or wire connecting to transistor 500. The electric element 610 functions as an electrode for the capacitive element 600. Furthermore, the conductor 612, and The conductor 610 can be formed simultaneously.

[0268] Conductors 612 and 610 contain molybdenum, titanium, tantalum, and tungsten. Metal film containing elements selected from aluminum, copper, chromium, neodymium, and scandium. , or metal nitride films containing the above-mentioned elements (tantalum nitride film, titanium nitride film, nitride film) Molybdenum film, tungsten nitride film, etc. can be used. Alternatively, indium stinic acid Indium oxides containing tungsten oxide, indium oxides containing tungsten oxide, indium tungsten oxide Lead oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, Suitable conductive materials include indium zinc oxide and indium tin oxide with added silicon dioxide. It can also be used.

[0269] In this embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but The structure is not limited to a single layer, and may consist of two or more layers. For example, a conductive material with barrier properties and a conductive material. A conductor with barrier properties between a highly conductive material and a highly conductive material. A conductive material with high adhesion may be formed.

[0270] The conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630. The conductor 620 uses a conductive material such as a metal material, alloy material, or metal oxide material. High-melting-point materials such as tungsten and molybdenum that offer both heat resistance and conductivity. It is preferable to use a conductor, and it is particularly preferable to use tungsten. When forming with other components, low-resistance metal materials such as Cu (copper) and Al (aluminium) are used. You can use something like "um" (um).

[0271] An insulator 640 is provided on the conductor 620 and the insulator 630. 40 can be provided using the same material as the insulator 320. Also, the insulator 640 is It may also function as a planarizing film that covers the uneven shape below it.

[0272] By using this configuration, semiconductor devices using transistors with oxide semiconductors This allows for miniaturization or high integration.

[0273] <Transistor Variation 1> The transistor 500A shown in Figures 17A, 17B, and 17C is the same as in Figure 16A, Figure 1 Figure 17A shows a modified version of transistor 500 with the configuration shown in 6B. Figure 17B is a top view of the transistor 500A, and Figure 17B is a cross-sectional view of the transistor 500A in the channel length direction. 17C is a cross-sectional view of transistor 500A in the channel width direction. Note that this is the top view of Figure 17A. In the diagrams, some elements have been omitted for clarity. (Figures 17A, 17B, etc.) The configuration shown in Figure 17C includes transistor 550 and other components of a semiconductor device according to one aspect of the present invention. This can also be applied to other transistors.

[0274] The transistor 500A in the configuration shown in Figures 17A, 17B, and 17C is insulator 5 52. The insulator 513 and the insulator 404 are present in the configuration shown in Figures 16A and 16B. It is different from transistor 500. Also, an insulator 552 is provided in contact with the side surface of the conductor 540a. Furthermore, the insulator 552 is provided in contact with the side surface of the conductor 540b, as shown in Figures 16A and 16A. This differs from the transistor 500 with the configuration shown in B. Furthermore, it does not have an insulator 520, as shown in Figure 16A is different from transistor 500, which has the configuration shown in Figure 16B.

[0275] The transistor 500A in the configuration shown in Figures 17A, 17B, and 17C is insulator 5 An insulator 513 is provided on 12. Also, an insulating layer is provided on the insulator 574 and on the insulator 513. A rim 404 is provided.

[0276] In transistor 500A with the configuration shown in Figures 17A, 17B, and 17C, the insulator 514, insulator 516, insulator 522, insulator 524, insulator 544, insulator 580, o The insulator 574 is patterned, and the insulator 404 covers them. In other words, insulator 404 is on the top surface of insulator 574, the side surface of insulator 574, and insulator 58 Side of 0, side of insulator 544, side of insulator 524, side of insulator 522, insulator 51 It is in contact with the side surface of 6, the side surface of insulator 514, and the top surface of insulator 513, respectively. This allows acid The monoxide 530, etc., is isolated from the outside by the insulators 404 and 513.

[0277] Insulators 513 and 404 contain hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). It is preferable that the insulator 51 has a high function of suppressing the diffusion of water molecules. 3 and insulator 404 are materials with high hydrogen barrier properties, such as silicon nitride or nitride It is preferable to use silicon oxide. This allows hydrogen and other elements to diffuse into the oxide 530. Since this can be suppressed, the degradation of the characteristics of the 500A transistor can be suppressed. This can improve the reliability of a semiconductor device according to one aspect of the present invention.

[0278] Insulator 552 is insulator 581, insulator 404, insulator 574, insulator 580, and It is provided in contact with the insulator 544. The insulator 552 suppresses the diffusion of hydrogen or water molecules. It is preferable that the material has a function. For example, the insulator 552 may be a material with high hydrogen barrier properties. Using an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Preferably, silicon nitride is a material with high hydrogen barrier properties, so insulator 55 It is preferable to use it as 2. Use a material with high hydrogen barrier properties as the insulator 552. As a result, impurities such as water or hydrogen are transferred from the insulator 580 to the conductor 540a and conductor 5 Diffusion to oxide 530 through 40b can be suppressed. Also, insulator 58 This suppresses the absorption of oxygen contained in 0 by conductors 540a and 540b. This makes it possible to improve the reliability of a semiconductor device according to one aspect of the present invention.

[0279] <Transistor Variation 2> Figures 18A, 18B, and 18C illustrate an example configuration of transistor 500B. Figure 18A is a top view of transistor 500B. Figure 18B is the same as Figure 18A but with a dashed line. This is a cross-sectional view of the L1-L2 region shown in Figure 18A. Figure 18C shows the W1-W region shown by the dashed line in Figure 18A. These are cross-sectional views of two parts. Note that in the top view of Figure 18A, some elements have been modified for clarity. Details have been omitted.

[0280] Transistor 500B is a modified version of transistor 500, and is a modified version of transistor 500. It is a replaceable transistor. Therefore, to avoid repeating the explanation, mainly the transistor This section explains the differences between the TA500B and the TA500 transistor.

[0281] The conductor 560, which functions as the first gate electrode, is composed of conductor 560a and conductor 56 It has a conductor 560b on 0a. The conductor 560a consists of hydrogen atoms, hydrogen molecules, water molecules, and copper. It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as atoms. Alternatively, it may have a function that inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material.

[0282] The conductor 560a has the function of suppressing oxygen diffusion, thus affecting the material of conductor 560b. Selectivity can be improved. In other words, by having the conductor 560a, the conductor 560 The oxidation of b is suppressed, preventing a decrease in conductivity.

[0283] Furthermore, the insulator 54 covers the top and side surfaces of the conductor 560 and the side surfaces of the insulator 545. It is preferable to provide 4. Note that the insulator 544 is free from impurities such as water or hydrogen, and It is preferable to use an insulating material that has the function of suppressing oxygen diffusion. For example, aluminum oxide It is preferable to use magnesium oxide or hafnium oxide. In addition, for example, magnesium oxide is also preferable. Nesium, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, acid Metal oxides such as lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride or Silicon nitride and other materials can be used.

[0284] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. The presence of the edge body 544 allows impurities such as water and hydrogen present in the insulator 580 to be transmitted. This can suppress diffusion to the ZISTA 500B.

[0285] Transistor 500B has conductor 56 in part of conductor 542a and part of conductor 542b. Because of the overlapping zeros, the parasitic capacitance tends to be larger than that of transistor 500. Therefore, Compared to the 500, the operating frequency tends to be lower. However, the insulator 580 Since there is no need to create openings in such parts and embed conductors 560 and insulators 545, It offers higher productivity compared to the Transistor 500.

[0286] The configuration, structure, and methods shown in this embodiment are not described in other embodiments and examples. It can be used in appropriate combination with the composition, structure, method, etc.

[0287] (Embodiment 5) In this embodiment, the crystal structure of the oxide semiconductor and other related aspects will be described in detail.

[0288] [Classification of crystal structures] First, we will explain the classification of crystal structures in oxide semiconductors using Figure 19A. Figure 19A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). This is a diagram illustrating the classification of the crystal structures of oxides.

[0289] As shown in Figure 19A, oxide semiconductors can be broadly classified into "Amorphous" )」 and 「Crystalline」 and 「Crystal」 and, It is classified. Also, within "Amorphous," there are completely amor It includes phous. Also, within "Crystalline" there is CAAC(ca xis-aligned crystalline), nc(nanocrystall This includes ine, and CAC (cloud-aligned composite). Note that the classification of "Crystalline" includes single crystal, po Ly crystals and completely amorphous molecules are excluded. Furthermore, "Crystal" includes single crystal and poly crystal. It includes ystal.

[0290] Note that the structures within the thick frame shown in Figure 19A are "Amorphous" and "Cr It is an intermediate state between "crystal" and a new boundary region (New crystal This structure belongs to the (linear phase). In other words, this structure is energetically It is completely different from the unstable "Amorphous" or "Crystal" forms. This can be rephrased as a structure.

[0291] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using the ion spectrum. Here, "Crystalline GIXD (Grazing-Incidence) of CAAC-IGZO film, which is classified as " The XRD spectrum obtained by the XRD measurement is shown in Figure 19B. Note that the GIXD method is thin Also known as the membrane method or Seemann-Bohlin method. Hereafter, the GIXD measurement shown in Figure 19B will be used. The XRD spectrum obtained at a constant temperature is simply referred to as the XRD spectrum. (See Figure 19B) The composition of the CAAC-IGZO film is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, the thickness of the CAAC-IGZO film shown in Figure 19B is 500 nm.

[0292] As shown in Figure 19B, the XRD spectrum of the CAAC-IGZO film shows clear crystallinity. A peak indicating this is detected. Specifically, in the XRD spectrum of the CAAC-IGZO film... A peak indicating c-axis orientation is detected near 2θ = 31°. As shown in Figure 19B... Furthermore, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected. .

[0293] Furthermore, the crystal structure of the film or substrate is determined by nano-beam diffraction (NBED). Diffraction patterns observed by electron diffraction (extremely small) It can be evaluated by (also called electron diffraction pattern). The folding pattern is shown in Figure 19C. Figure 19C shows an NB with an electron beam incident parallel to the substrate. This is the diffraction pattern observed by ED. Note that the CAAC-IGZO shown in Figure 19C is also shown. The film composition is approximately In:Ga:Zn=4:2:3 [atomic ratio]. Furthermore, a microelectron beam was used. In diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0294] As shown in Figure 19C, the diffraction pattern of the CAAC-IGZO film shows a complex c-axis orientation. A number of spots are observed.

[0295] [Structure of oxide semiconductors] Note that oxide semiconductors may be classified differently from those shown in Figure 19A when considering their crystal structure. For example, oxide semiconductors include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It can be divided into conductors and non-single-crystal oxide semiconductors, for example, the aforementioned CAAC-OS , and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors and pseudo Amorphous-like oxide semiconductor (a-like OS) This includes semiconductors, amorphous oxide semiconductors, and so on.

[0296] Next, we will discuss the details of the aforementioned CAAC-OS, nc-OS, and a-like OS. Then, I will give an explanation.

[0297] [CAAC-OS] CAAC-OS has multiple crystalline regions, and the c-axis of these crystalline regions is oriented in a specific direction. It is an oriented oxide semiconductor. The specific direction refers to the thickness direction of the CAAC-OS film. , in the direction normal to the surface on which the CAAC-OS film is formed, or in the direction normal to the surface of the CAAC-OS film Yes, there is. Furthermore, a crystalline region is a region in which the atomic arrangement has periodicity. Note that the atomic arrangement is categorized If considered as a child arrangement, a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC- OS has a region in which multiple crystal regions are connected in the ab-plane direction, and this region is strained It may have strain. Note that strain refers to the lattice arrangement in a region where multiple crystal regions are connected. The orientation of the grid arrangement changes between a region with aligned grids and another region with aligned grids. This refers to the location. In other words, CAAC-OS is c-axis oriented and has a clear orientation in the ab-plane direction. It is an oxide semiconductor that does not exist.

[0298] Each of the above multiple crystalline regions is composed of one or more minute crystals (with a maximum diameter of 10 It is composed of crystals smaller than nm. Furthermore, the maximum diameter of the crystalline region is less than 10 nm. If this occurs, the size of the crystalline region may be around several tens of nanometers.

[0299] Also, In-M-Zn oxide (element M is aluminum, gallium, yttrium, sulfite) In one or more types selected from materials such as titanium, CAAC-OS is an indicator. A layer containing um (In) and oxygen (hereinafter referred to as the In layer), and an element M, zinc (Zn), and acid A layered crystalline structure (also called a layered structure) is formed by stacking layers containing an element (hereinafter referred to as (M,Zn) layer). It tends to have (u). Furthermore, indium and element M are mutually substitutable. Therefore The (M,Zn) layer may contain indium. Also, the In layer contains element M. This may occur. Furthermore, the In layer may also contain Zn. This layered structure is, for example, In high-resolution TEM images, it is observed as a grid pattern.

[0300] For example, when structural analysis of a CAAC-OS film is performed using an XRD device, the θ / 2θ scale is obtained. Out-of-plane XRD measurements using the CANR showed two peaks indicating c-axis orientation. It is detected at θ=31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) ) may vary depending on the type and composition of the metal elements that make up CAAC-OS.

[0301] Furthermore, for example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots (spots) (T) is observed. Note that one spot and another spot are separated by the incident electron beam that has passed through the sample. With the spot (also called the direct spot) as the center of symmetry, observations are made at point-symmetric positions. It can be done.

[0302] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is a hexagonal lattice. While this is the basic principle, the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, The above distortion may have a grid arrangement such as a pentagon or heptagon. -In OS, clear grain boundaries were confirmed even near the strain. This is not possible. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This indicates that CAAC-OS has a dense arrangement of oxygen atoms in the ab-plane direction. This is because, for example, the substitution of metal atoms changes the bond distance between atoms. This is thought to be because it allows for distortion to be tolerated.

[0303] Furthermore, a crystal structure in which clear grain boundaries can be observed is known as a polycrystalline structure. It is called al(al). The grain boundaries become recombination centers, trapping carriers and forming transistors. This is likely to cause a decrease in on-current and a decrease in field-effect mobility. CAAC-OS, which lacks visible grain boundaries, has a crystal structure suitable for the semiconductor layer of transistors. It is one of the crystalline oxides that possesses Zn. Furthermore, CAAC-OS requires the presence of Zn. A configuration in which In-Zn oxide and In-Ga-Zn oxide are made of In acid It is preferable because it can suppress the generation of grain boundaries more effectively than oxidized materials.

[0304] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less prone to a decrease in electron mobility caused by grain boundaries. Furthermore, the crystallinity of oxide semiconductors can decrease due to impurities and the formation of defects. Because of this, CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies) It can also be said that oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. C-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors expands the degree of freedom in the manufacturing process. It becomes possible to increase the risk.

[0305] [nc-OS] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. In other words, nc-OS is micro It has small crystals. The size of these minute crystals is, for example, between 1 nm and 10 nm. In particular, because they are between 1 nm and 3 nm in size, these minute crystals are also called nanocrystals. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, the entire film... No orientation is observed. Therefore, nc-OS is a-like depending on the analytical method. It can sometimes be indistinguishable from OS or amorphous oxide semiconductors. For example, compared to nc-OS films When performing structural analysis using an XRD device, out-of-pl using θ / 2θ scans is obtained. In ane XRD measurements, no peak indicating crystallinity was detected. Furthermore, for nc-OS films... Furthermore, electron beam blasts using electron beams with probe diameters larger than those of nanocrystals (e.g., 50 nm or more) When diffraction (also called limited-field electron diffraction) is performed, a diffraction pattern similar to a halo pattern is obtained. Observed. On the other hand, compared to the nc-OS film, the size is close to or smaller than that of nanocrystals. Electron diffraction (nanobeam) using electron beams with probe diameters (e.g., 1 nm to 30 nm). Also called electron diffraction, when this is performed, a ring-shaped region centered on the direct spot appears. In some cases, electron diffraction patterns with multiple spots observed may be obtained.

[0306] [a-like OS] a-like OS is an oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a semiconductor. an a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, it has a-like properties. OS has a higher hydrogen concentration in the membrane compared to nc-OS and CAAC-OS.

[0307] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS is a material composition. Regarding achievement.

[0308] [CAC-OS] CAC-OS refers to, for example, metal oxides in which the elements constituting the metal oxide are between 0.5 nm and 10 nm. Below, preferably, a structure of material that is unevenly distributed with a size of 1 nm to 3 nm or near that size. It is formed. Furthermore, in the following, in metal oxides, one or more metal elements are unevenly distributed. The region containing the metal element is 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A mixture of particles smaller than or near a m in size is also called a mosaic or patchy appearance. .

[0309] Furthermore, CAC-OS is a material that separates into a first region and a second region. This results in a zigzag-like structure, where the first region is distributed within the film (hereinafter also referred to as a cloud-like structure). ) In other words, CAC-OS is a mixture of the first region and the second region. It is a composite metal oxide having the following composition.

[0310] Here, I for the metal elements constituting CAC-OS in In-Ga-Zn oxide The atomic ratios of n, Ga, and Zn are given as [In], [Ga], and [Zn] respectively. To be expressed. For example, in CAC-OS in In-Ga-Zn oxide, the first region This is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. That is. Or, for example, in the first region, [In] is greater than [In] in the second region. It is also a region where the [Ga] is large, and the [Ga] is smaller than the [Ga] in the second region. Furthermore, in the second region, [Ga] is greater than [Ga] in the first region, and [I n] is a region where n is smaller than [In] in the first region.

[0311] Specifically, the first region mentioned above mainly consists of indium oxide, indium zinc oxide, etc. This is a region of minutes. Furthermore, the second region mentioned above is gallium oxide, gallium zinc oxide, etc. This is the region in which In is the main component. In other words, the first region described above can be said to be the region in which In is the main component. It can be replaced. Furthermore, the second region described above can be rephrased as the region with Ga as the main component. It is possible.

[0312] Note that a clear boundary may not be observed between the first region and the second region described above. .

[0313] For example, in CAC-OS in In-Ga-Zn oxide, the energy-dispersive X-ray segment Optical method (EDX:Energy Dispersive X-ray spectrosc) EDX mapping obtained using opy revealed the region with In as its main component (the first region) It has a structure in which a region (the second region) and a region mainly composed of Ga are unevenly distributed and mixed. This can be confirmed.

[0314] When CAC-OS is used in a transistor, the conductivity is due to the first region and the second region The insulating properties due to the region work complementarily to enable the switching function (On The function to turn off CAC-OS can be added to it. In other words, CAC-OS and The material has both conductive and insulating properties in parts, and the entire material Then it has the function of a semiconductor. By separating the conductive function and the insulating function, This allows for the maximum enhancement of both functions. Therefore, CAC-OS is used in transistors. This results in a high on-current (I on ), high field-effect mobility (μ), and good switching This enables smooth operation.

[0315] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and C It may have two or more of the following: AC-OS, nc-OS, and CAAC-OS.

[0316] [Transistors containing oxide semiconductors] Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0317] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility is obtained. This can be achieved. Furthermore, highly reliable transistors can be realized.

[0318] A low-carrier-concentration oxide semiconductor is used in the channel formation region of the transistor. This is preferable. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is preferable to be less than , 1 x 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 less than It is even more preferable that it be 1 × 10 12 cm -3 It is even more preferable that it be less than [a certain value]. Furthermore, when the carrier concentration of the oxide semiconductor film is reduced, the ions in the oxide semiconductor film The solution is to lower the concentration of pure substances and reduce the defect level density. In this specification, the impurity concentration is A low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxide semiconductors with low nitrile concentration are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. There are cases where this happens.

[0319] Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density. Therefore, the trap level density may also be low.

[0320] Furthermore, the time required for charges trapped in the trap levels of an oxide semiconductor to disappear is... It can behave for a long time, almost like a fixed charge. Therefore, the trap level density is high. Transistors in which a channel formation region is formed in an oxide semiconductor have unstable electrical properties. There are cases where this occurs.

[0321] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is Reducing it is effective. Furthermore, in order to reduce the impurity concentration in oxide semiconductors, It is also preferable to reduce the concentration of impurities in the adjacent membrane. Examples of impurities include hydrogen, nitrogen, and Examples include potassium metals, alkaline earth metals, iron, nickel, and silicon.

[0322] 〔impurities〕 Here, we will explain the effects of various impurities in oxide semiconductors.

[0323] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, oxidation occurs. Defect levels are formed in material semiconductors. Therefore, in the channel formation region of oxide semiconductors... The concentration of silicon and carbon in the oxide semiconductor and the silicon near the interface with the channel formation region The concentration of ions and carbon (Secondary Ion Mass Spectrometry (SIMS)) The concentration obtained by ss Spectrometry is 2 × 10 18 atom / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0324] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels are formed. This can result in the generation of carriers. Therefore, alkali metals or alkaline earth metals may be present. Transistors using oxide semiconductors tend to exhibit normally-on characteristics. Therefore, alkali metals or a in the channel formation region of oxide semiconductors obtained by SIMS The concentration of rutile earth metals is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 1 6 atoms / cm 3 Do the following:

[0325] Furthermore, in oxide semiconductors, when nitrogen is present, electrons, which are carriers, are generated. As the nitrogen concentration increases, it becomes easier to convert to n-type semiconductors. As a result, oxide semiconductors containing nitrogen become semiconductors. The transistor used tends to exhibit normally-on characteristics. Alternatively, oxide semiconductors Furthermore, when nitrogen is present, trap levels may be formed. As a result, transistor The electrical properties of the oxide semiconductor obtained by SIMS may become unstable. The nitrogen concentration in the channel formation region is 5 × 10 19 atoms / cm 3 Less than, preferably 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0326] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen bonded to the metal atoms to form water. Therefore, an oxygen deficiency may form. When hydrogen enters this oxygen deficiency, the carrier electrons In some cases, a child may be produced. Also, some of the hydrogen combines with the metal atom and oxygen, resulting in a crystal. It can generate electrons that act as carriers. Therefore, an oxide semiconductor containing hydrogen is used. Transistors that have been modified tend to exhibit normally-on characteristics. For this reason, the channels of oxide semiconductors It is preferable that the amount of hydrogen in the hydrogen-forming region be reduced as much as possible. Specifically, In the channel formation region of an oxide semiconductor, the hydrogen concentration obtained by SIMS is 1 × 1 0 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than, Preferably 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 ato ms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0327] Using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor. This allows for the provision of stable electrical characteristics.

[0328] The configuration, structure, and methods shown in this embodiment are not described in other embodiments and examples. It can be used in appropriate combination with the composition, structure, method, etc.

[0329] (Embodiment 6) In this embodiment, the integrated circuit includes the configuration of the semiconductor device 100 described in the above embodiment. The configuration will be explained with reference to Figures 20 and 21.

[0330] Figure 20 is a block diagram illustrating an example of an integrated circuit configuration, including the configuration of semiconductor device 100. This is an example of a diagram.

[0331] The integrated circuit 390 shown in Figure 20 includes a CPU 10, an accelerator 20, and an on-chip motor. Mori 131, DMAC (Direct Memory Access Control) er)141, power supply circuit 160, power management unit (PMU) 142, security Retard circuit 147, memory controller 143, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Acc ess Memory) Controller 144, USB (Universal Series (Bus) interface circuit 145, display interface circuit 146, Bridge circuit 150, interrupt control circuit 151, interface circuit 152, battery - Control circuit 153, and ADC (Analog-to-digital converter) ter) / DAC (Digital-to-analog converter) interface It has a face circuit 154.

[0332] CPU10, for example, consists of CPU cores 111, instruction cache 112, and data cache... It has a channel 113 and a bus interface circuit 114. The accelerator 20 is It has a memory circuit 121, an arithmetic circuit 122, and a drive circuit 123.

[0333] The CPU core 111 has multiple CPU cores. The instruction cache 112 is a CPU core The circuit configuration should be such that it temporarily stores the instruction to be executed at A111. Data cache 1 13 temporarily stores data to be processed by CPU core 111 or data obtained through processing. The circuit configuration should be such that it stores the data. The bus interface circuit 114 connects to the CPU 10 and A bus for connecting to other circuits within a semiconductor device, and for sending and receiving signals such as data and addresses. Any circuit configuration that allows this is acceptable.

[0334] The memory circuit 121 corresponds to the memory circuit 24 described in Embodiment 1. 121 should be a circuit configuration that stores the data to be processed by accelerator 20. Circuit 122 corresponds to the arithmetic circuit 23 described in Embodiment 1. The arithmetic circuit 122 is The circuit configuration should be such that it performs calculations on the data held in the Mori circuit 121. 3 corresponds to a configuration equipped with the drive circuit 15 described in Embodiment 1. The drive circuit 123 is As shown in Figure 9B, the circuit configuration for controlling each circuit within the accelerator 20 and That's all you need to do.

[0335] High-speed bus 140A has CPU 10, accelerator 20, on-chip memory 131, D MAC141, Power Management Unit 142, Security Circuit 147, Memory Controller 143, DDR SDRAM controller 144, USB interface Various signals between circuit 145 and display interface circuit 146 are transmitted at high speed. It is a bus for receiving data. One example is AMBA (Advanced Microphone). ontoroller Bus Artcitecture)-AHB(Advance A high-performance bus can be used as a bus.

[0336] The on-chip memory 131 is a circuit of the integrated circuit 390, for example, the CPU 10 or The accelerator 20 has a circuit configuration for storing data or programs to be input or output to it. ru.

[0337] The DMAC141 is a direct memory access controller. By having this, peripheral devices other than CPU10 can access on-chip memory 1 without going through CPU10. You can access 31.

[0338] The power management unit 142 controls the circuits of the integrated circuit 390, such as the CPU core. It has a circuit configuration for controlling power gating.

[0339] The security circuit 147 encrypts signals between the integrated circuit 390 and external circuits. It has a circuit configuration that enhances the confidentiality of signals, such as for sending and receiving signals.

[0340] The memory controller 143 receives the CP from the program memory located outside the integrated circuit 390. Write or read programs to run on U10 or accelerator 20. It has a circuit configuration for performing this task.

[0341] The DDR SDRAM controller 144 controls the DRAM and other components located outside the integrated circuit 390. It has a circuit configuration for writing or reading data to and from main memory.

[0342] The USB interface circuit 145 is located outside the integrated circuit 390 and includes a USB terminal. It has a circuit configuration for transmitting and receiving data via [a specific method / device].

[0343] The display interface circuit 146 is located outside the integrated circuit 390. It has a circuit configuration for transmitting and receiving data with an electronic device.

[0344] The power supply circuit 160 is a circuit for generating the voltage used within the integrated circuit 390. If a negative voltage is applied to the back gate of the OS transistor to stabilize its electrical characteristics, It is a circuit that generates data.

[0345] The low-speed bus 140B includes an interrupt control circuit 151, an interface circuit 152, and a battery. Various signals between the Lee control circuit 153 and the ADC / DAC interface circuit 154 It is a bus for sending and receiving data at low speed. One example is AMBA-APB (Advanced (ed Peripheral Bus) can be used as a bus. Express bus 14 The transmission and reception of various signals between 0A and the low-speed bus 140B are performed via the bridge circuit 150. .

[0346] The interrupt control circuit 151 performs interrupt processing in response to requests received from peripheral devices. It has a circuit configuration for this purpose.

[0347] Interface circuit 152 is UART (Universal Asynchronization ous Receiver / Transmitter), I2C (Inter-Int egrated Circuit), SPI (Serial Peripheral I It has a circuit configuration for enabling interfaces such as an interface to function.

[0348] The battery control circuit 153 is located outside the integrated circuit 390 and relates to the charging and discharging of the battery. It has a circuit configuration for sending and receiving data.

[0349] The ADC / DAC interface circuit 154 is located outside the integrated circuit 390 and uses MEMS. (Micro Electro Mechanical Systems) devices, etc. It has a circuit configuration for sending and receiving data to and from a device that outputs analog signals.

[0350] Figures 21A and 21B show examples of circuit block arrangements when implemented as an SoC. Each component shown in the block diagram of Figure 20, such as the integrated circuit 390 shown in Figure 21A, is a Areas can be divided and arranged on the map.

[0351] The on-chip memory 131 described in Figure 20 is a memory composed of OS transistors. It can be constructed with a circuit, for example, NOSRAM. In other words, the on-chip memory 131 and The memory circuit 121 has the same circuit configuration. Therefore, when it is made into an SoC, Figure 21B shows As shown in the diagram, the on-chip memory 131 and the memory circuit 121 are integrated It is also possible to convert them and place them within the same area.

[0352] The present invention, according to one aspect described above, provides a novel semiconductor device and electronic device. This is possible. Alternatively, according to one aspect of the present invention, semiconductor devices and electronic devices with low power consumption can be made. It can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of suppressing heat generation. We can provide electronic equipment.

[0353] This embodiment can be appropriately combined with descriptions of other embodiments.

[0354] (Embodiment 7) In this embodiment, the integrated circuit 390 described in the above embodiment can be applied. Electronic devices, mobile devices, and computing systems will be explained with reference to Figures 22 through 25.

[0355] Figure 22A shows an external view of an automobile as an example of a mobile device. Figure 22B shows an automobile. This is a simplified diagram illustrating the data exchange within the vehicle. The vehicle 590 has multiple cameras 591, etc. It has infrared radar, millimeter-wave radar, and laser radar. It is equipped with various sensors (not shown), etc.

[0356] In the automobile 590, the above-mentioned integrated circuit 390 can be used in the camera 591, etc. The automobile 590 uses a camera 591 to capture multiple images in multiple imaging directions 592, and then implements the above-mentioned method. The processing is performed by the integrated circuit 390 described in the form shown, and then transmitted via bus 593, etc., to the host controller 5 By analyzing multiple images together using methods such as 94, it is possible to determine the presence or absence of guardrails and pedestrians, etc. It can assess surrounding traffic conditions and perform autonomous driving. It can also provide road guidance and hazard prediction. It can be used in systems that perform this task.

[0357] The integrated circuit 390 processes the obtained image data using computational methods such as neural networks. By doing so, for example, image resolution can be increased, image noise can be reduced, and facial recognition (for security purposes, etc.) can be performed. Object recognition (for purposes such as autonomous driving), image compression, image correction (wide dynamic range), Image restoration, positioning, character recognition, and reflection reduction processing for lensless image sensors. It is possible to do so.

[0358] In the above, an automobile was described as an example of a moving object, but the moving object is an automobile. It is not limited to these. For example, examples of moving objects include trains, monorails, ships, and aircraft (helicopters). Other examples include unmanned aerial vehicles (drones), airplanes, and rockets, and these can be moved A semiconductor device according to one aspect of the present invention is applied to a moving object to provide it with a system utilizing artificial intelligence. It is possible.

[0359] Figure 23A is an external view showing an example of a portable electronic device. Figure 23B is a portable electronic device. This is a simplified diagram of data exchange within the device. The portable electronic device 595 uses printed circuit boards. It includes a circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0360] In the portable electronic device 595, the above integrated circuit 390 is provided on the printed wiring board 596. It is possible. The portable electronic device 595 has a speaker 597, a camera 598, and a micro Multiple data obtained from Phon 599, etc., are used with the integrated circuit 390 described in the above embodiment. By processing and analyzing the data, user convenience can be improved. Additionally, voice guidance is available. It can be used in systems that perform image searches and other similar tasks.

[0361] The integrated circuit 390 processes the obtained image data using computational methods such as neural networks. By doing so, for example, image resolution can be increased, image noise can be reduced, and facial recognition (for security purposes, etc.) can be performed. Object recognition (for purposes such as autonomous driving), image compression, image correction (wide dynamic range), Image restoration, positioning, character recognition, and reflection reduction processing for lensless image sensors. It is possible to do so.

[0362] The portable game console 1100 shown in Figure 24A consists of a casing 1101, a casing 1102, and a casing 110 3. It has a display unit 1104, a connection unit 1105, an operation key 1107, etc. Housing 1101, enclosure Body 1102 and housing 1103 are removable. Provided in housing 1101 By attaching the connection part 1105 to the housing 1108, the output is displayed on the display unit 1104. The video can be output to another video device. On the other hand, housing 1102 and housing 1103 By attaching it to housing 1109, housings 1102 and 1103 are integrated, and operation To function as a part. Chips provided on the circuit boards of housing 1102 and housing 1103 The integrated circuit 390 shown in the previous embodiment can be incorporated into any of these.

[0363] Figure 24B shows a USB-connected stick-type electronic device 1120. Electronic device 11 20 consists of the housing 1121, the cap 1122, the USB connector 1123, and the circuit board 1124. The circuit board 1124 is housed in the housing 1121. For example, the circuit board 1124 has A memory chip 1125 and a controller chip 1126 are mounted on board 11. The 24 controller chips 1126 and the like incorporate the integrated circuit 390 shown in the previous embodiment. It is possible.

[0364] Figure 24C shows a humanoid robot 1130. The robot 1130 is equipped with sensors 2101 to It has 2106 and a control circuit 2110. For example, the control circuit 2110 has a previous embodiment The integrated circuit 390 shown in the form can be incorporated.

[0365] The integrated circuit 390 described in the above embodiment is not built into an electronic device, but rather... It can also be used as a server to communicate with. In this case, it is performed by electronic devices and the server. The calculation system is configured. Figure 25 shows an example of the configuration of system 3000.

[0366] System 3000 consists of electronic equipment 3001 and server 3002. Communication between the child device 3001 and the server 3002 is performed via the internet connection 3003. It is possible.

[0367] Server 3002 has multiple racks 3004. Multiple racks contain multiple bases A board 3005 is provided, and the integrated circuit 390 described in the above embodiment is placed on the substrate 3005. This allows the server 3002 to be equipped with a neural network. And the server 3002 connects to the internet line 30 from the electronic device 3001. The neural network can perform calculations using the data input via 03. The results of the calculations performed by server 3002 will be transmitted to the internet connection 3003 as needed. This allows it to be transmitted to the electronic device 3001 via. This can reduce the computational burden.

[0368] This embodiment can be appropriately combined with descriptions of other embodiments. [Examples]

[0369] In this embodiment, the accelerator having the excellent processing performance described in Embodiment 1 above is used Regarding the data, we will explain the simulation results used to estimate computational efficiency.

[0370] The data used in the simulation showed that the Si of the transistors that make up the accelerator The technology assumes a 55nm process, while the IGZO technology assumes a 60nm process. Parasitic capacity was added in the output. In the neural network, all neurons ( The Mori circuit is activated, meaning it consumes more energy in multiply-accumulate operations by neural networks. The computational efficiency was estimated assuming high power consumption. The number of Mori circuits (memory cells) was estimated for 16 cells, 32 cells, 64 cells, and 128 cells. .

[0371] As a concrete example of calculation, for example, in the case of 32 cells / bit line, (2048(PE) × 2 (Two types of operations: product and sum) × (50MHz)) / (2048(PE) × 20.2fJ × ( It can be estimated that 50MHz = 99 TOPS / W. Note that 2048(PE) and This corresponds to the number of arithmetic circuits that can perform calculations at once, i.e., the number of columns in the memory cell array. 20 0.2fJ is the energy required for the sum-of-products operation on the read energy from the memory cell (13.9fJ). This is the total energy obtained by adding up the sum-of-products energy (6.3 fJ).

[0372] In other words, in the circuit diagram shown in Figure 26, the number of columns in the memory circuit 24 (PE) is 2048. The computational efficiency in a certain case was estimated. In the case of Figure 26, bit lines PBL_1 to PBL_N, And charge and discharge two bit lines, NBL_1 to NBL_N, and one bit The larger the number of memory cells connected to the line, the greater the read energy from the memory cells (Note The R section (corresponding to section 22) becomes larger. The sum-of-products calculation energy (corresponding to the calculation processing unit 21) is one Regardless of the number of memory cells connected to the bit line, it can be estimated to be 6.3 fJ. .

[0373] Figure 26 also illustrates other components, name lines WL_1 to WL_M. Furthermore, the arithmetic processing unit that performs the sum-of-products operation has multiple logical blocks that perform multiplication and a unit that performs addition. Multiple logic blocks and a diagram are shown. In the logic block that performs multiplication, the bit line P Given signals from BL and NBL, and input data A1, the multiplied data Y1 is ToY N The data Y1 to Y N The data Y is obtained by adding the two items together and performing a sum-of-products operation. AS The diagram shows the configuration to obtain this result.

[0374] The above is summarized in Table 4. As shown in Table 4, the number of memory cells can be 16 cells, 32 cells, We obtained calculation efficiency estimates for both 64-cell and 128-cell systems.

[0375] [Table 4]

[0376] As shown in Table 4, by applying a semiconductor device according to one aspect of the present invention, 100 TOPS / It was found that computational efficiency of W or higher can be expected.

[0377] (Notes regarding the descriptions in this specification, etc.) The above embodiments and a description of each component in those embodiments are provided below. .

[0378] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments or examples. This can be one embodiment of the present invention. Furthermore, multiple configurations can be included in one embodiment. When examples are provided, it is possible to combine the example configurations as appropriate.

[0379] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other content (even partial content) described in form, and / or one or more other The contents described in the embodiment (even if only some of the contents) may be applied, combined, or It is possible to perform substitutions, etc.

[0380] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0381] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. , another figure (even a part of it) described in that embodiment, and / or one or This involves combining the figures (or even just some of them) described in multiple other embodiments. This allows for the creation of even more diagrams.

[0382] Furthermore, in this specification, etc., block diagrams classify components according to their function and treat them as independent of each other. It is shown as a block. However, in actual circuits, the components are divided by function. It is difficult to separate the functions, and when multiple functions are involved in a single circuit, or when multiple circuits are involved... In some cases, one function may be involved. Therefore, the blocks in the block diagram are specified in the specification. The components described are not limited to those explained, and can be appropriately rephrased depending on the situation.

[0383] Furthermore, in the drawings, the size, layer thickness, or area may be arbitrarily depicted for the sake of explanation. This is what is shown. Therefore, it is not necessarily limited to that scale. Note that the drawings are for clarity. This is a schematic representation for illustrative purposes only and is not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or timing discrepancies. This can include variations in signals, voltages, or currents.

[0384] Furthermore, the positional relationships of the components shown in drawings are relative. Therefore, drawings When referring to and explaining the components, terms such as "above" and "below" that indicate positional relationships are for convenience. It may be used in this way. The positional relationship of the components is not limited to what is described herein, and may vary. It can be rephrased appropriately depending on the situation.

[0385] In this specification and other documents, when describing the connection relationships of transistors, the term "source or drain" is used. "One side of" (or the first electrode, or the first terminal), "the other side of the source or drain" (and The notation used is "second electrode" or "second terminal." This refers to the source and terminal of a transistor. Rain varies depending on the transistor's structure or operating conditions. Regarding the terminology for the source and drain of the ZISTA, the source (drain) terminal and the source (drain) terminal are used. The term "electrode," etc., can be appropriately rephrased depending on the situation.

[0386] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0387] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is a base This refers to the potential difference from a reference potential. For example, the reference potential is the ground voltage (earth). If we consider voltage as a unit of measurement, then voltage can be rephrased as potential. Ground potential is not necessarily 0V. This does not necessarily mean that. Furthermore, electric potential is relative, and depending on the reference potential, This may change the potential supplied to wiring, etc.

[0388] Furthermore, in this specification, a node is defined as having terminals and wiring, depending on the circuit configuration and device structure. These can be rephrased as electrodes, conductive layers, conductors, impurity regions, etc. Also, terminals, distribution Lines and other elements can be rephrased as nodes.

[0389] In this specification, etc., "A and B are connected" means that A and B are electrically connected. This refers to things that are electrically connected. Here, A and B are said to be electrically connected to each other. The object (a switch, transistor element, or diode or other element, or said element and A connection (referring to a circuit including wiring, etc.) that allows electrical signals to be transmitted between A and B is possible when such a connection exists. This refers to a continuation. Furthermore, if A and B are electrically connected, then A and B are directly connected. This includes cases where A and B are directly connected. Here, A and B are said to be directly connected via the above-mentioned object. However, it is possible to transmit electrical signals between A and B via wiring (or electrodes), etc. It refers to a certain type of connection. In other words, a direct connection is a connection that, when represented in an equivalent circuit, looks like the same circuit diagram. It refers to a connection that can be made.

[0390] In this specification, a switch means a conductive state (on state) or a non-conductive state (off state). It refers to a device that enters a state (F) and has the function of controlling whether or not to allow current to flow. Or, A switch is a device that has the function of selecting and switching the path through which electric current flows.

[0391] In this specification, channel length refers, for example, to the length of a semiconductor in a top view of a transistor. The body (or the part of the semiconductor through which current flows when the transistor is ON) and the gate The distance between the source and drain in the region where they overlap, or in the region where a channel is formed. It means separation.

[0392] In this specification, channel width refers to, for example, the state in which a semiconductor (or transistor) is ON. The region where the part of the semiconductor through which current flows (when in a certain state) and the gate electrode overlap, or channel This refers to the length of the portion where the source and drain face each other in the region where the drain is formed. .

[0393] In this specification, the terms "membrane," "layer," etc. may be used in some cases, or in a manner. Depending on the situation, they can be interchanged. For example, the term "conductive layer" can be replaced with " In some cases, the term can be changed to "conductive film." Or, for example, "insulating film." In some cases, it is possible to change the term "insulating layer" to "insulating layer." [Explanation of Symbols]

[0394] :M11: Transistor, M12: Transistor, M13: Transistor, 10: CPU 11: CPU core, 12: Backup circuit, 15: Drive circuit, 20: Accelerator ,21: Arithmetic processing unit, 22: Memory unit, 22_N: Memory unit, 22_1: Memory unit, 22 _6: Memory section, 23: Arithmetic circuit, 23_N: Arithmetic circuit, 23_1: Arithmetic circuit, 23_6 : Arithmetic circuit, 24: Memory circuit, 25: Transistor, 27: Transistor, 29: Semiconductor Body layer, 30: bus, 31: data retention circuit, 31_N: data retention circuit, 31_P: data Transistor holding circuit, 32: transistor, 32_N: transistor, 32_P: transistor, 33: Transistor, 33_N: Transistor, 33_P: Transistor, 34: Transistor 35: Capacitive element, 42: Logic circuit, 43: Accumulator, 44: Latch circuit, 45: Encoding circuit, 50: Neuron, 51: Layer, 52: Layer, 53: Layer, 54: Layer, 61 : Controller, 62: Row Decoder, 63: Word Line Driver, 64: Column Decoder 65: Write driver, 66: Precharge circuit, 71: Input buffer, 72: Arithmetic operations Control circuit, 100: Semiconductor device, 111: CPU core, 112: Instruction cache, 113 :Data cache, 114:Bus interface circuit, 121:Memory circuit, 122 : Arithmetic circuit, 123: Drive circuit, 131: On-chip memory, 140A: High-speed bus, 14 0B: Low-speed bus, 141: DMAC, 142: Power management unit, 143: Me Mori controller, 144: controller, 145: interface circuit, 146: de Display interface circuit, 147: security circuit, 150: bridge circuit , 151: control circuit, 152: interface circuit, 153: battery control circuit, 1 54: Interface circuit, 160: Power supply circuit, 193: PMU, 200: CPU core , 202: Cache memory device, 203: Cache memory device, 205: Bus interface - Face section, 210: Power switch, 211: Power switch, 212: Power switch 214: Level shifter, 220: Flip-flop, 221: Scan flip-flop rop, 221A: clock buffer circuit, 222: backup circuit, 311: circuit board, 312: Well region, 313: Insulator, 314: Oxide layer, 315: Semiconductor region, 316 a: Low resistance region, 316b: Low resistance region, 316c: Low resistance region, 317: Insulator, 31 8: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 32 8: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 35 6: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 37 0: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 38 2: Insulator, 384: Insulator, 386: Conductor, 390: Integrated circuit, 390E: Integrated circuit 404: insulator, 500: transistor, 500A: transistor, 500B: transistor Zista, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 51 2: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 52 0: Insulator, 522: Insulator, 524: Insulator, 526: Insulator, 530: Oxide, 53 0a: Oxide, 530b: Oxide, 540a: Conductor, 540b: Conductor, 542: Conductor body, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: Insulator, 545: Insulator, 546: Conductor, 548: Conductor, 550: Transistor, 5 52: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 590: Automobile , 591: Camera, 592: Imaging direction, 593: Bus, 594: Host controller, 5 95: Portable electronic devices, 596: Printed circuit boards, 597: Speakers, 598: Turtles Ra, 599: microphone, 600: capacitive element, 610: conductor, 612: conductor, 6 20: Conductor, 630: Insulator, 640: Insulator, 910: Region, 912: Region, 914 : Power, 916: Power, 918: Power, 920: Power, 922: Power, 1100: Portable Game console, 1101: cabinet, 1102: cabinet, 1103: cabinet, 1104: display unit, 11 05: Connection part, 1107: Operation key, 1108: Housing, 1109: Housing, 1120: Electronic Device, 1121: Housing, 1122: Cap, 1123: USB connector, 1124: Base Board, 1125: Memory chip, 1126: Controller chip, 1130: Robot, 2 101: Sensor, 2106: Sensor, 2110: Control circuit, 3000: System, 300 1: Electronic equipment, 3002: Server, 3003: Internet connection, 3004: Rack ,3005: Circuit board

Claims

[Claim 1] CPU and, It has an accelerator, The accelerator includes a first memory circuit, a drive circuit, and a multiply-accumulate circuit. The first memory circuit includes a first data storage unit, a second data storage unit, and a data reading unit. The first data held in the first data holding unit and the second data held in the second data holding unit are weight data input to the sum-of-accumulate circuit. The sum-of-products circuit has the function of performing a sum-of-products operation on the weight data and the input data input via the drive circuit. The first data holding unit includes a first transistor and a first capacitive element, The second data holding unit comprises a second transistor and a second capacitive element, The data reading unit has a third transistor to a sixth transistor, The source or drain of the first transistor is electrically connected to one electrode of the first capacitive element and to the gate of the fourth transistor. Either the source or drain of the third transistor is electrically connected to either the source or drain of the fourth transistor. The source or drain of the second transistor is electrically connected to one electrode of the second capacitive element and to the gate of the fifth transistor. The source or drain of the sixth transistor is electrically connected to the source or drain of the fifth transistor. Each of the first to sixth transistors has a channel formation region in a first semiconductor layer containing a metal oxide. Each of the sum-of-accumulate circuit and the drive circuit has a seventh transistor, The seventh transistor is a semiconductor device having a channel formation region in a second semiconductor layer containing silicon.

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