Junction field-effect transistors and switching circuits

Abstract

The present invention provides a junction field-effect transistor comprising an n-type semiconductor layer made of a β-type gallium oxide semiconductor and a gate structure that does not include a gate insulating film and has a gate electrode provided on the n-type semiconductor layer, and a switching circuit including the junction field-effect transistor. [Solution] A junction field-effect transistor 1 is provided, comprising an n-type semiconductor layer 11 made of a β-type gallium oxide semiconductor, a current path limiting region 14 provided within the n-type semiconductor layer 11 having an opening 140 and containing acceptor impurities, and a gate electrode 15 made of a p-type semiconductor provided on the n-type semiconductor layer 11, wherein the current path limiting region 14 restricts the current path between the drain electrode 18 and the source electrode 16 to pass through the inside of the opening 140 and between the current path limiting region 14 and the upper surface 111, and the current path limited by the current path limiting region 14 is opened and closed by a depletion layer extending from the gate electrode 15.

Description

[Technical Field]

[0001] This invention relates to a junction field-effect transistor and a switching circuit. [Background technology]

[0002] Conventionally, normally-off vertical MOS field-effect transistors are known in which a current-blocking layer is provided within an n-type semiconductor layer made of β-type gallium oxide, and a gate electrode is provided on the n-type semiconductor layer (see Non-Patent Literature 1).

[0003] The current blocking layer is a layer formed by implanting nitrogen ions into an n-type semiconductor layer and is used to restrict the current path between the source and drain. By providing a gate electrode in contact with a portion of this restricted current path and controlling the depletion layer thickness by applying a gate bias, switching operation becomes possible. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Man Hoi Wong et al., “Enhancement-Mode β-Ga2O3Current Aperture Vertical MOSFETs with N-Ion-Implanted Blocker”, IEEE Electron Device Letters, February 2020, Volume: 41, Issue: 2, 296-299 [Overview of the project] [Problems that the invention aims to solve]

[0005] The MOS field-effect transistor described in Non-Patent Literature 1 uses a gate insulating film made of Al2O3 or the like in its MOS-type gate structure. The mobility of electrons flowing through the channel is strongly influenced by interface states at the interface between the gate insulating film and the n-type semiconductor. However, it is not easy to achieve a state without these interface states, making it difficult to obtain sufficiently large mobility and achieve low on-resistance.

[0006] Furthermore, when using high-k materials such as HfO2 for the gate insulating film to achieve high breakdown voltage performance, the interface state at the interface between the gate insulating film and the n-type semiconductor may become higher, leading to more pronounced problems such as reduced electron mobility and the occurrence of hysteresis in the current-voltage characteristics.

[0007] Furthermore, since radiation strikes the insulating film, generating an electric charge and altering the device characteristics, devices using insulating films, such as the MOS field-effect transistor described in Non-Patent Document 1, cannot be used in environments exposed to radiation, such as outer space or inside a nuclear reactor.

[0008] The object of the present invention is to provide a junction field-effect transistor comprising an n-type semiconductor layer made of a β-type gallium oxide semiconductor and a gate structure that does not include a gate insulating film and has a gate electrode provided on the n-type semiconductor layer, and a switching circuit including the junction field-effect transistor. [Means for solving the problem]

[0009] One aspect of the present invention provides the following junction field-effect transistor and switching circuit to achieve the above objective.

[0010] [1]An n-type semiconductor layer made of a β-gallium oxide-based semiconductor, a source electrode connected to the upper surface of the n-type semiconductor layer, a drain electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer, and an acceptor impurity provided in the n-type semiconductor layer and having an opening. A current path limiting region, and a gate electrode made of a p-type semiconductor provided on the upper surface of the n-type semiconductor layer, wherein the current path limiting region restricts the current path between the drain electrode and the source electrode to pass through the inside of the opening and between the current path limiting region and the upper surface, and the current path restricted by the current path limiting region is opened and closed by a depletion layer extending from the gate electrode. A junction field effect transistor. [2]The junction field effect transistor according to [1] above, wherein the current path limiting region contains Mg and N or Zn and N as the acceptor impurity. [3]The junction field effect transistor according to [1] above, wherein the p-type semiconductor is p-type NiO or p-type Cu2O. [4]A switching circuit including the junction field effect transistor according to any one of [1] to [3] above, and an n-type MOS field effect transistor cascode-connected to the junction field effect transistor. [Effects of the Invention]

[0011] According to the present invention, there can be provided a junction field effect transistor including an n-type semiconductor layer made of a β-gallium oxide-based semiconductor and a gate structure in which a gate insulating film is not included and a gate electrode is provided on the n-type semiconductor layer, and a switching circuit including the junction field effect transistor. [Brief Description of the Drawings]

[0012] [Figure 1] FIG. 1 is a vertical cross-sectional view of a junction field effect transistor according to an embodiment of the present invention. [Figure 2]Figures 2(a) to 2(c) are cross-sectional views illustrating an example of the manufacturing process of a junction field-effect transistor according to an embodiment of the present invention. [Figure 3] Figures 3(a) to 3(c) are cross-sectional views illustrating an example of the manufacturing process of a junction field-effect transistor according to an embodiment of the present invention. [Figure 4] Figures 4(a) and 4(b) are cross-sectional views illustrating an example of the manufacturing process of a junction field-effect transistor according to an embodiment of the present invention. [Figure 5] Figure 5 is a circuit diagram of a switching circuit in which a normally-on type junction field-effect transistor and an n-type MOS field-effect transistor are connected in a cascode configuration. [Modes for carrying out the invention]

[0013] (Configuration of a junction field-effect transistor) Figure 1 is a vertical cross-sectional view of a junction field-effect transistor 1 according to an embodiment of the present invention. The junction field-effect transistor 1 is a vertical junction field-effect transistor having a planar gate structure.

[0014] The junction field-effect transistor 1 is an n-type transistor and comprises an n-type semiconductor layer 11 made of a β-type gallium oxide semiconductor, a source electrode 16 connected to the upper surface 111 of the n-type semiconductor layer 11, a drain electrode 18 directly or indirectly connected to the lower surface 112 of the n-type semiconductor layer 11, a current path limiting region 14 having an opening 140 and containing acceptor impurities provided within the n-type semiconductor layer 11, and a gate electrode 15 made of a p-type semiconductor provided on the upper surface 111 of the n-type semiconductor layer 11.

[0015] Gallium oxide semiconductors are Ga2O3 or Ga2O3 in which part of the Ga is replaced with Al, In, or both, (Ga x Al y In (1-x-y)) It has a composition represented by 2O3 (0 < x ≤ 1, 0 ≤ y < 1, 0 < x + y ≤ 1). When a part of Ga in Ga2O3 is replaced by Al, the bandgap widens, and when replaced by In, the bandgap narrows.

[0016] Moreover, the β-type gallium oxide-based semiconductor is a gallium oxide-based semiconductor having a β-type crystal structure. Since the β-type gallium oxide-based semiconductor can grow a bulk crystal by a melt growth method, a substrate 10 made of the β-type gallium oxide-based semiconductor described later can be made as cheaply and simply as a silicon substrate or a gallium arsenide substrate.

[0017] There also exists an α-type gallium oxide-based semiconductor having an α-type crystal structure among gallium oxide-based semiconductors. However, the α-type gallium oxide-based semiconductor can only be made by epitaxially depositing a film on a heterogeneous substrate made of a material that is not a gallium oxide-based semiconductor. Therefore, in order to obtain a substrate made of the α-type gallium oxide-based semiconductor, after epitaxially depositing a thick film on the heterogeneous substrate, it is necessary to remove the substrate by some method, which incurs additional costs. In addition, the epitaxial film on the heterogeneous substrate has a dislocation density (defect density) about 100,000 times higher than that of a bulk crystal by melt growth, and it is difficult to fabricate a large-sized device such as a general power device (for example, a device with a size of 1 mm square or more) with a high yield using the α-type gallium oxide-based semiconductor. Furthermore, the α-type gallium oxide-based semiconductor is a metastable phase and changes to the β-type gallium oxide-based semiconductor when heated at a temperature of 800 °C or higher. Therefore, an ion implantation technique that requires an activation annealing treatment at 900 °C or higher cannot be used for a layer made of the α-type gallium oxide-based semiconductor. Therefore, the α-type gallium oxide-based semiconductor cannot be used as the material for the n-type semiconductor layer 11 of the junction field effect transistor 1.

[0018] In the junction field-effect transistor 1, the current path limiting region 14 restricts the current path between the drain electrode 18 and the source electrode 16 to pass through the inside of the opening 140 and between the current path limiting region 14 and the top surface 111. The current path limited by the current path limiting region 14 is then opened and closed by the depletion layer extending from the gate electrode 15.

[0019] In the case of a normally-on junction field-effect transistor 1, when no voltage is applied to the gate electrode 15, a conductor exists in the current path within the n-type semiconductor layer 11 (the channel is open). When a voltage is applied between the drain electrode 18 and the source electrode 16, current flows from the drain electrode 18 to the source electrode 16 (the ON state).

[0020] Then, when a negative voltage greater than the threshold is applied to the gate electrode 15, the depletion layer caused by the pn junction between the gate electrode 15 and the n-type semiconductor layer 11 expands from the gate electrode 15 into the inside of the n-type semiconductor layer 11, driving out conduction electrons (the channel closes), and in this state, even if a voltage is applied between the drain electrode 18 and the source electrode 16, no current flows from the drain electrode 18 to the source electrode 16 (off state).

[0021] Furthermore, if the junction field-effect transistor 1 is of the normally-off type, when no voltage is applied to the gate electrode 15, the channel is closed because the depletion layer caused by the pn junction between the gate electrode 15 and the n-type semiconductor layer 11 extends from the gate electrode 15 to the inside of the n-type semiconductor layer 11. Therefore, even if a voltage is applied between the drain electrode 18 and the source electrode 16, no current flows from the drain electrode 18 to the source electrode 16 (off state).

[0022] Then, when a positive voltage greater than or equal to the threshold is applied to the gate electrode 15, the depletion layer shrinks and the channel opens. In this state, when a voltage is applied between the drain electrode 18 and the source electrode 16, current flows from the drain electrode 18 to the source electrode 16 (ON state).

[0023] The current path limiting region 14 is a region whose resistance is increased by acceptor impurities, and it electrically isolates the drain electrode 18 and the source electrode 16 in the portion other than the opening 140. Therefore, in the junction field-effect transistor 1, the current flowing from the drain electrode 18 to the source electrode 16 passes inside the opening 140 of the current path limiting region 14, that is, it passes through the region 110 inside the opening 140 of the n-type semiconductor layer 11, and reaches the source electrode 16 through the region between the upper surface 111 of the n-type semiconductor layer 11 and the current path limiting region 14 (the channel layer 12, which will be described later).

[0024] In the junction field-effect transistor 1, the operating state of the junction field-effect transistor 1 can be turned off mainly by closing the current path, which is the channel inside the opening 140 of the current path limiting region 14 and above the opening 140, with a depletion layer extending from the gate electrode 15.

[0025] Thus, in the junction field-effect transistor 1, by limiting the current path using the current path limiting region 14, switching operation can be performed without using a structure in which the gate electrode is embedded inside the n-type semiconductor layer 11, or a fin structure in which the gate electrode is placed on the inner surface of a fin provided on the n-type semiconductor layer 11.

[0026] Furthermore, gallium oxide semiconductors are difficult to convert to p-type semiconductors with good electrical conductivity, making it impossible to form a p-type gate electrode by injecting acceptor impurities into the n-type semiconductor layer 11. Therefore, embedding a gate electrode in the n-type semiconductor layer 11 requires a complex process of forming trenches in the n-type semiconductor layer 11 and embedding p-type semiconductors other than gallium oxide semiconductors into them. Similarly, forming a fin structure also requires complex processes such as fin processing of the n-type semiconductor layer 11. For these reasons, the junction field-effect transistor 1, which uses a gate electrode 15 provided on the upper surface 111 of the n-type semiconductor layer 11, is superior in terms of manufacturing yield and manufacturing cost.

[0027] Furthermore, in order to efficiently close the current path inside the opening 140 of the current path limiting region 14 and the current path above the opening 140 with the depletion layer extending from the gate electrode 15, it is preferable that the opening 140 of the current path limiting region 14 is located inside the contour of the gate electrode 15 when viewed from above (when viewed from the top of Figure 1), as shown in Figure 1.

[0028] Furthermore, the fact that switching operation is possible in the junction field-effect transistor 1, which does not include a gate insulating film in its gate structure, is a result of the inventors' diligent research.

[0029] The junction field-effect transistor 1, which does not include a gate insulating film in its gate structure, does not have problems such as a decrease in electron mobility or the occurrence of hysteresis in the current-voltage characteristics caused by interface states at the interface between the gate insulating film and the n-type semiconductor layer 11, and therefore can be operated as designed.

[0030] Furthermore, the junction field-effect transistor 1, which does not include a gate insulating film in its gate structure, does not contain radiation-sensitive insulators and can therefore be suitably used in environments exposed to radiation, such as outer space or inside a nuclear reactor. The gallium oxide-based semiconductor, which is the material for the n-type semiconductor layer 11, has higher resistance to radiation compared to other semiconductor materials such as silicon. Therefore, when using the junction field-effect transistor 1 in environments exposed to radiation, the properties of this gallium oxide-based semiconductor can be effectively utilized.

[0031] The n-type semiconductor layer 11 is an n-type layer containing donor impurities such as Si. In the junction field-effect transistor 1, the breakdown voltage is mainly maintained by the pn junction between the current path limiting region 14 and the n-type semiconductor layer 11 below it. Therefore, the region of the n-type semiconductor layer 11 below the current path limiting region 14 functions as a breakdown voltage maintenance layer, and its donor concentration and thickness are adjusted as appropriate to obtain the desired breakdown voltage.

[0032] For example, in order to obtain a breakdown voltage of 600V, the donor concentration and thickness of the region below the current path limiting region 14 of the n-type semiconductor layer 11 are 5×10 16 ~5×10 17 cm -3 and 1.5 - 3μm, respectively. Also, in order to obtain a breakdown voltage of 1200V, the donor concentration and thickness of the region below the current path limiting region 14 of the n-type semiconductor layer 11 are 3.7×10 16 ~1.5×10 17 cm -3 and 3 - 6μm, respectively. Also, in order to obtain a breakdown voltage of 3300V, the donor concentration and thickness of the region below the current path limiting region 14 of the n-type semiconductor layer 11 are 1.3×10 16 ~5.3×10 16 cm -3 and 8.3 - 16.5μm, respectively. Also, in order to obtain a breakdown voltage of 6600V, the donor concentration and thickness of the region below the current path limiting region 14 of the n-type semiconductor layer 11 are 6.7×10 15 ~2.7×10 16 cm -3 and 16.5 - 33μm, respectively. Also, in order to obtain a breakdown voltage of 10000V, the donor concentration and thickness of the region below the current path limiting region 14 of the n-type semiconductor layer 11 are 4.4×10 15 ~1.8×10 16 cm -3 and 25 - 50μm, respectively. Also, in order to obtain a breakdown voltage of 20000V, the donor concentration and thickness of the region below the current path limiting region 14 of the n-type semiconductor layer 11 are 2.2×10 15 ~8.8×10 16 cm -3 and 50 - 100μm, respectively.

[0033] The n-type semiconductor layer 11 is typically laminated on the substrate 10 as shown in FIG. 1. For example, the substrate 10 is a substrate made of an n-type β-gallium oxide-based semiconductor containing donor impurities such as Sn, and the n-type semiconductor layer 11 is an epitaxial film formed by epitaxial growth on the substrate 10.

[0034] The substrate 10 has a higher donor concentration than the n-type semiconductor layer 11, for example, 1 × 10⁻¹⁶. 18 ~1 × 10 20 cm -3 , has . When substrate 10 is used, the drain electrode 18 is indirectly connected to the lower surface 112 of the n-type semiconductor layer 11 via substrate 10.

[0035] The region above the opening 140 of the current path limiting region 14 in the n-type semiconductor layer 11 is the region where channel opening and closing mainly occurs, and a channel layer 12 containing a higher concentration of donor impurities is provided in this region than in the region below the opening 140 in the n-type semiconductor layer 11. The channel layer 12 is formed, for example, by implanting donor impurities such as Si into the n-type semiconductor layer 11.

[0036] The donor concentration and thickness of the channel layer 12 determine the operating characteristics of the junction field-effect transistor 1. For example, when manufacturing a normally-on type junction field-effect transistor 1, the donor concentration and thickness of the channel layer 12 are 5 × 10⁻¹⁰, respectively. 17 ~5×10 18 cm -3 The degree is set to approximately 30-300 nm. Also, when manufacturing a normally-off type junction field-effect transistor 1, the donor concentration and thickness of the channel layer 12 are set to 5 × 10⁻¹⁰, respectively. 16 ~5×10 17 cm -3 The wavelength is set to approximately 30-200 nm.

[0037] A portion of the surface layer on the upper side 111 of the n-type semiconductor layer 11, i.e., a portion of the channel layer 12, typically has a higher donor concentration than the channel layer 12, for example, 6 × 10⁻¹⁶, in order to lower the contact resistance between the source electrode 16 and the n-type semiconductor layer 11. 18 ~6×10 20 cm -3A source contact region 13 is provided, which has the following characteristics. In this case, the source electrode 16 is connected to the source contact region 13. The source contact region 13 is formed, for example, by implanting donor impurities such as Si into the n-type semiconductor layer 11. The source electrode 16 is made of a single material or a laminate of two or more materials such as Ti, Al, Au, Ni, Pt, and Pd.

[0038] Acceptor impurities included in the current path limiting region 14 can include, for example, Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, and P. Of these, Mg, Zn, N, and P are particularly preferred because they form shallower acceptor levels compared to other acceptor impurities.

[0039] Furthermore, when N is doped together with any of the acceptor impurities other than N (co-doping), the acceptor level becomes shallower than when doping with only one type of acceptor impurity. Therefore, it is preferable that the current path limiting region 14 contains N and other acceptor impurities. In particular, when a combination of Mg and N or a combination of Zn and N is used, a particularly shallow acceptor level is formed. Therefore, it is preferable that the current path limiting region 14 contains Mg and N or Zn and N as acceptor impurities.

[0040] The acceptor concentration in the current path limiting region 14 is, for example, 1 × 10⁻⁶. 18 ~5×10 20 cm -3 The current path limiting region 14 is formed, for example, by injecting the above-mentioned acceptor impurities into the n-type semiconductor layer 11.

[0041] The current path limiting region 14 typically includes a region 141 extending in the planar direction of the n-type semiconductor layer 11, which contains an aperture 140, and a region 142 located outside the source contact region 13 above region 141. The thickness of region 141 is, for example, 100 to 2000 nm. The planar shape of the aperture 140 is, for example, a rectangle with one side (the horizontal side in Figure 1) having a length of 10 to 1000 μm and the other side (the side perpendicular to the plane of the paper in Figure 1) having a length of 0.1 to 10 mm.

[0042] For the p-type semiconductor material of the gate electrode 15, for example, p-type oxides such as p-type NiO and p-type Cu2O can be used.

[0043] A gate electrode 17 made of a conductor is provided on the gate electrode 15, which is made of a p-type semiconductor, to reduce the contact resistance between the wiring and the gate. The gate electrode 17 is made of one or more materials selected from materials such as Ti, Al, Au, Ni, Pt, and Pd. It is preferable to design the gate electrode 17 to be made of the same material and to the same film thickness as the source electrode 16, as this allows both to be formed in a single process, thereby reducing manufacturing costs.

[0044] (Manufacturing method for junction field-effect transistors) Figures 2(a)-(c), 3(a)-(c), and 4(a)-(b) are cross-sectional views illustrating an example of the manufacturing process of a junction field-effect transistor 1 according to an embodiment of the present invention.

[0045] First, as shown in Figure 2(a), a single crystal film of a β-type gallium oxide semiconductor is epitaxially grown on a substrate 10 by methods such as halide vapor deposition or organometallic vapor deposition to form an n-type semiconductor layer 11.

[0046] Next, as shown in Figure 2(b), donor impurities such as Si are ion-implanted into the surface layer of the n-type semiconductor layer 11, and then the channel layer 12 is formed by performing activation annealing at 900-1100 degrees Celsius for about 30-60 minutes.

[0047] Next, as shown in Figure 2(c), an acceptor impurity such as N is ion-implanted into the n-type semiconductor layer 11 from above using a mask 51 formed on the n-type semiconductor layer 11 by photolithography. Subsequently, activation annealing is performed at 900-1200 degrees Celsius for 30-60 minutes to form the current path limiting region 141.

[0048] Next, as shown in Figure 3(a), an acceptor impurity such as N is ion-implanted into the n-type semiconductor layer 11 from above using a mask 52 formed on the n-type semiconductor layer 11 by photolithography. Subsequently, activation annealing is performed at 900-1200 degrees Celsius for 30-60 minutes to form the region 142 of the current path limiting region 14.

[0049] Next, as shown in Figure 3(b), a mask 53 formed on the n-type semiconductor layer 11 by photolithography is used to ion-implant donor impurities such as Si into the n-type semiconductor layer 11 from above. Subsequently, activation annealing is performed at 900-1100 degrees Celsius for approximately 30-60 minutes to form the source contact region 13. The steps for forming the channel layer 12, region 141, region 142, and source contact region 13 can be freely rearranged. Furthermore, activation annealing can be performed all at once after several ion implantation steps.

[0050] Next, as shown in Figure 3(c), a p-type semiconductor film 150 is formed on the n-type semiconductor layer 11 by sputtering or the like.

[0051] Next, as shown in Figure 4(a), the p-type semiconductor film 150 is patterned using photolithography or the like to form the gate electrode 15.

[0052] Next, as shown in Figure 4(b), the source electrode 16, gate electrode 17, and drain electrode 18 are formed by sputtering, evaporation, or other methods.

[0053] (Configuration of switching circuits) Figure 5 is a circuit diagram of a switching circuit 2 in which a normally-on type junction field-effect transistor 1 and an n-type MOS field-effect transistor 21 are connected in a cascode configuration.

[0054] Although the normally-on type junction field-effect transistor 1 is difficult to handle as a power device, it can be combined with the n-type MOS field-effect transistor 21 to form a switching circuit 2 that operates as a pseudo-normally-off type device.

[0055] In the switching circuit 2, the drain 213 of the n-type MOS field-effect transistor 21 is connected to the source electrode 16 of the junction field-effect transistor 1, and the source 211 of the n-type MOS field-effect transistor 21 is connected to the gate electrode 17 of the junction field-effect transistor 1. The source 211 is connected to ground 23, and the drain 213 and source electrode 16 are connected to ground 24 via an inductor 25 and a capacitor 26.

[0056] Looking at the circuit as a whole, the switching circuit 2 can be considered a three-terminal element with three terminals: the source 211 of the n-type MOS field-effect transistor 21, the drain (drain electrode 18) of the junction field-effect transistor 1, and the gate 212 of the n-type MOS field-effect transistor 21.

[0057] When a positive voltage is applied to the gate of the switching circuit 2, that is, the gate 212 of the n-type MOS field-effect transistor 21, the channel of the n-type MOS field-effect transistor 21 opens and turns on. At this time, since the junction field-effect transistor 1 is normally-on, the current that flows through the n-type MOS field-effect transistor 21 also passes through the channel of the junction field-effect transistor 1 and reaches the drain electrode 18 (the switching circuit 2 turns on).

[0058] Furthermore, when a voltage of 0V or negative is applied to the gate of the switching circuit 2, i.e., the gate 212 of the n-type MOS field-effect transistor 21, the n-type MOS field-effect transistor 21 turns off. At this moment, the source 211 of the n-type MOS field-effect transistor 21 is at 0V, and an off voltage (e.g., 600V) is applied to the drain electrode 18 of the junction field-effect transistor 1. In the next moment, the voltage between the source 211 and drain 213 of the n-type MOS field-effect transistor 21, which are connected in parallel, and the voltage between the gate electrode 17 and drain electrode 18 of the junction field-effect transistor 1 both rise until they reach approximately 10V (after the junction field-effect transistor 1 turns off), at which point the remaining voltage is applied between the gate electrode 17 and drain electrode 18 of the junction field-effect transistor 1, and the entire circuit turns off (the switching circuit 2 turns off).

[0059] It has already been demonstrated that a pn junction made of a p-type oxide and an n-type gallium oxide semiconductor has a high reverse bias breakdown voltage. Therefore, a junction field-effect transistor 1 in which a gate electrode 15 made of a p-type semiconductor and an n-type semiconductor layer 11 form a pn junction is more likely to achieve a higher breakdown voltage compared to a transistor such as the MOS field-effect transistor described in Non-Patent Document 1, in which a gate insulating film is sandwiched between the gate electrode and the semiconductor layer.

[0060] In the switching circuit 2, the breakdown voltage is ensured by the junction field-effect transistor 1, so the breakdown voltage of the n-type MOS field-effect transistor 21 can be low. For this reason, for example, an inexpensive Si-MOSFET (a MOS field-effect transistor using a semiconductor layer made of Si) can be used as the n-type MOS field-effect transistor 21.

[0061] Furthermore, as shown in Figure 5, the switching circuit 2 may have a snubber circuit 22, which is a series connection circuit of a capacitor and a resistor, between the source 211 and drain 213 of the n-type MOS field-effect transistor 21. By using this snubber circuit 22, malfunctions in the off state of the junction field-effect transistor 1, which has a low threshold voltage, caused by high-frequency noise from the outside can be suppressed.

[0062] (Effects of the embodiment) According to the above-described embodiment of the present invention, it is possible to provide a junction field-effect transistor 1 comprising an n-type semiconductor layer 11 made of a β-type gallium oxide semiconductor and a gate structure in which a gate electrode 15 is provided on the n-type semiconductor layer 11 without a gate insulating film, and a switching circuit 2 including the junction field-effect transistor 1. The junction field-effect transistor 1, which does not include a gate insulating film in its gate structure, does not have problems such as a decrease in electron mobility or the occurrence of hysteresis in the current-voltage characteristics caused by the interface state at the interface between the gate insulating film and the n-type semiconductor layer 11, and can therefore be operated as designed.

[0063] Although embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Furthermore, the components of the above embodiments can be arbitrarily combined without departing from the spirit of the invention. Moreover, the embodiments described above do not limit the invention as claimed. It should also be noted that not all combinations of features described in the embodiments are necessarily essential for solving the problem of the invention. [Explanation of Symbols]

[0064] 1...Junction field-effect transistor, 11...n-type semiconductor layer, 14...Current path limiting region, 140...Aperture, 15...Gate electrode, 16...Source electrode, 18...Drain electrode, 2...Switching circuit, 21...n-type MOS field-effect transistor

Claims

1. An n-type semiconductor layer made of a β-type gallium oxide semiconductor, A source electrode connected to the upper surface of the n-type semiconductor layer, A drain electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer, A current path limiting region having an opening and containing acceptor impurities is provided within the n-type semiconductor layer, A gate electrode made of a p-type semiconductor is provided on the upper surface of the n-type semiconductor layer, Equipped with, The current path limiting region restricts the current path between the drain electrode and the source electrode to pass through the inside of the opening and between the current path limiting region and the upper surface. The current path restricted by the current path restriction region is opened and closed by the depletion layer extending from the gate electrode. Junction field-effect transistor.

2. The current path limiting region includes Mg and N or Zn and N as the acceptor impurities. The junction field-effect transistor according to claim 1.

3. The aforementioned p-type semiconductor is p-type NiO or p-type Cu ２ It is O. The junction field-effect transistor according to claim 1.

4. A junction field-effect transistor according to any one of claims 1 to 3, The junction field-effect transistor and the n-type MOS field-effect transistor are connected in cascode, A switching circuit, including one.

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