Thin-film transistor substrate and display device including the same

Abstract

Reduces stress on thin-film transistors. [Solution] One embodiment of the present disclosure provides a thin-film transistor substrate comprising a base substrate and a first thin-film transistor and a second thin-film transistor arranged on the base substrate and connected in series with each other, wherein the first thin-film transistor comprises a first active layer having a first channel portion, a first gate electrode disposed at a distance from the first active layer and superimposed on the first active layer, and a first source electrode and a first drain electrode in contact with the first active layer and disposed at a distance from each other, and the second thin-film transistor comprises a second active layer having a second channel portion, a second gate electrode disposed at a distance from the second active layer and superimposed on the second active layer, and a second source electrode and a second drain electrode in contact with the second active layer and disposed at a distance from each other, wherein the second channel portion has a larger area than the first channel portion on a plane.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor substrate and a display device including the same.

Background Art

[0002] Since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is widely used as a switching element or a driving element of a display device such as a liquid crystal display device or an organic light emitting device.

[0003] Thin film transistors can be classified into amorphous silicon thin film transistors using amorphous silicon as an active layer, polycrystalline silicon thin film transistors using polycrystalline silicon as an active layer, and oxide semiconductor thin film transistors using an oxide semiconductor as an active layer, based on the material constituting the active layer.

[0004] As the driving time of a thin film transistor becomes longer, deterioration may occur. When deterioration of the thin film transistor occurs, the element reliability of the thin film transistor may decrease. When the element reliability decreases due to deterioration of the thin film transistor, the image quality of the display device may also decrease.

[0005] In recent years, research for improving the deterioration of thin film transistors has been continuously conducted.

Summary of the Invention

Problems to be Solved by the Invention

[0006] One embodiment of the present disclosure can provide a thin film transistor substrate in which stress applied by a high drain bias is reduced by widely forming the channel portion area of a thin film transistor to which a high potential voltage is applied.

[0007] One embodiment of the present disclosure provides a thin-film transistor substrate in which the drain electrode of a thin-film transistor to which a high potential voltage is applied has a larger surface area on the plane than the source electrode, thereby reducing the stress applied by high drain bias.

[0008] One embodiment of the present disclosure provides a thin-film transistor substrate equipped with a narrow bezel, having a circular structure in which the drain and source electrodes of different thin-film transistors are shared with each other. [Means for solving the problem]

[0009] One embodiment of the present disclosure for achieving the aforementioned technical problems includes a base substrate and a first thin-film transistor and a second thin-film transistor arranged on the base substrate and connected in series with each other, wherein the first thin-film transistor includes a first active layer having a first channel portion, a first gate electrode disposed at a distance from the first active layer and superimposed on the first active layer, and a first source electrode and a first drain electrode in contact with the first active layer and disposed at a distance from each other, and the second thin-film transistor includes a second active layer having a second channel portion, a second gate electrode disposed at a distance from the second active layer and superimposed on the second active layer, and a second source electrode and a second drain electrode in contact with the second active layer and disposed at a distance from each other, wherein the second channel portion has a larger area than the first channel portion on a plane, providing a thin-film transistor substrate.

[0010] The first gate electrode is U-shaped, the second gate electrode is U-shaped rotated 180°, and the first and second gate electrodes can form a ring shape together.

[0011] The first drain electrode and the second source electrode are integral, and the first drain electrode and the second source electrode can be positioned inside the first gate electrode and the second gate electrode, which are integrally formed on a plane.

[0012] The first active layer includes a first source conductor portion disposed on one side of the first channel portion and a first drain conductor portion disposed on the other side of the first channel portion, the second active layer includes a second drain conductor portion disposed on the other side of the second channel portion and a second drain conductor portion disposed on the other side of the second channel portion, the first channel portion is U-shaped and the second channel portion is U-shaped rotated 180°, and the first channel portion and the second channel portion may be arranged with an open portion between them.

[0013] The first channel portion has a first length and a first width perpendicular to the first length and extending along the first channel portion, and the second channel portion has a second length and a second width perpendicular to the second length and extending along the second channel portion, the second width may be longer than the first width.

[0014] The first length and the second length may be the same.

[0015] On a plane, the first width may narrow as it moves from the first source conductor portion toward the first drain conductor portion, and the second width may widen as it moves from the second source conductor portion toward the second drain conductor portion.

[0016] The first source electrode is U-shaped, the second drain electrode is U-shaped rotated 180°, the second drain electrode has a larger surface area on a plane than the first source electrode, and the first source electrode and the second drain electrode can be arranged with the empty space between them.

[0017] On a plane, the second drain electrode may have a larger area than the first source electrode, and the first source electrode may have a larger area than the first drain electrode.

[0018] On a plane, the first gate electrode and the second gate electrode integrally form one of a circular ring, an elliptical ring, or a square ring with rounded vertices, and the corners of the inner surface of the first source electrode and the inner surface of the second drain electrode on the plane may have a rounded shape.

[0019] The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may be arranged on the same layer.

[0020] The first active layer may be disposed between the base substrate and the first gate electrode, and the second active layer may be disposed between the base substrate and the second gate electrode.

[0021] The first thin-film transistor includes a first light-shielding layer disposed between the base substrate and the first active layer, and the second thin-film transistor may include a second light-shielding layer disposed between the base substrate and the second active layer.

[0022] The first light-shielding layer and the second light-shielding layer can each be gate electrodes.

[0023] The first gate electrode may be disposed between the base substrate and the first active layer, and the second gate electrode may be disposed between the base substrate and the second active layer.

[0024] Another embodiment of this disclosure can provide a display device including a thin-film transistor.

[0025] A gate driver and a pixel driving circuit having a plurality of stages for driving a plurality of gate lines respectively. Each of the plurality of stages includes a pull-up transistor that is pulled up by the control of a first node (hereinafter referred to as the Q node) and outputs a first clock signal input via a first clock terminal of the plurality of clocks to an output terminal, a pull-down transistor that pulls down the output terminal by the control of a second node (hereinafter referred to as the QB node), and a control unit that charges and discharges the Q node and charges and discharges the QB node so as to be opposite to the Q node. The control unit includes a QB charging transistor that charges the QB node with a high potential voltage. The QB charging transistor includes a first QB charging transistor and a second QB charging transistor. The high potential voltage is applied to the drain electrode of the first QB charging transistor. The source electrode of the second QB charging transistor is connected to the QB node. The first QB charging transistor may be the second thin film transistor, and the second QB charging transistor may be the first thin film transistor.

[0026] The control unit includes a Q discharge transistor that discharges the Q node to a gate off voltage by the control of the QB node. The Q discharge transistor includes a third thin film transistor and a fourth thin film transistor connected in series with each other. The third thin film transistor includes a third active layer having a third channel portion, a third gate electrode disposed apart from the third active layer and overlapping the third active layer, and a third source electrode and a fourth drain electrode that are in contact with the third active layer and disposed apart from each other. The fourth thin film transistor includes a fourth active layer having a fourth channel portion, a fourth gate electrode disposed apart from the fourth active layer and overlapping the fourth active layer, and a fourth source electrode and a fourth drain electrode that are in contact with the fourth active layer and disposed apart from each other. On a plane, the third channel portion may have the same area as the fourth channel portion.

Advantages of the Invention

[0027] According to an embodiment of the present disclosure, a thin film transistor substrate can reduce the stress applied to the thin film transistor due to High Drain Bias by widely forming the channel area of the thin film transistor to which a high potential voltage is applied.

[0028] According to an embodiment of the present disclosure, a thin film transistor substrate can reduce the stress applied to the thin film transistor due to High Drain Bias by making the drain electrode of the thin film transistor to which a high potential voltage is applied have a wider area on the plane than the source electrode.

[0029] According to an embodiment of the present disclosure, a thin film transistor substrate can implement a narrow bezel by having a circular structure in which the drain electrodes and source electrodes of different thin film transistors are shared with each other.

Brief Description of the Drawings

[0030] [Figure 1] It is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure. [Figure 2] It is a cross-sectional view taken along the line I-I' of FIG. 1. [Figure 3] It is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. [Figure 4] It is a cross-sectional view of a thin film transistor substrate according to still another embodiment of the present disclosure. [Figure 5] It is a cross-sectional view of a thin film transistor substrate according to still another embodiment of the present disclosure. [Figure 6A] It is a plan view of a thin film transistor substrate according to still another embodiment of the present disclosure. [Figure 6B] It is a plan view of a thin film transistor substrate according to still another embodiment of the present disclosure. [Figure 6C] It is a plan view of a thin film transistor substrate according to still another embodiment of the present disclosure. [Figure 6D]This is a plan view of a thin-film transistor substrate according to another embodiment of the present disclosure. [Figure 7] This is a schematic diagram of a display device according to another embodiment of the present disclosure. [Figure 8] This is a block diagram schematically showing some of the stages of the gate driver described herein. [Figure 9] This is a circuit diagram showing the configuration of each stage according to this disclosure. [Figure 10] This is the circuit diagram for one of the pixels in Figure 7. [Modes for carrying out the invention]

[0031] The advantages and features of the present invention, and the methods for achieving them, will become clearer by referring to an example described in detail below with accompanying figures. However, the present invention is not limited to the example disclosed below, but can be embodied in a variety of different forms, and the example provided is merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the present invention of the scope of the invention. The present invention is defined solely by the claims.

[0032] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the diagrams illustrating an example of the present invention are illustrative and not limited to the matters shown in the diagrams of the present invention. Throughout the specification, the same components may refer to the same reference numerals. In describing an example of the present invention, if it is determined that a specific explanation of related prior art would unnecessarily obscure the gist of the application, such detailed explanation will be omitted.

[0033] Where the words "includes," "has," "consists of," etc., as referred to in this specification, other parts may be added unless "only" is used. This includes cases where a singular component includes multiple components unless otherwise explicitly stated.

[0034] In interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0035] For example, when the positional relationship between two parts is described using phrases such as "on top," "above," "below," or "next to," one or more other parts may be located between the two parts unless expressions such as "immediately" or "directly" are used.

[0036] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" can be used to easily describe the correlation between one element or component and another, as shown in the diagram. Spatially relative terms should be understood as terms that include different directions in use or operation, in addition to the directions shown in the diagram. For example, if the elements shown in the diagram are flipped over, the element described as "below" or "down" of another element may be placed "above" of the other element. Thus, the exemplary term "below" may include both downward and upward directions. Similarly, the exemplary term "upper" or "upper" may include both upward and downward directions.

[0037] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it may include cases that are not continuous unless "immediately" or "directly" is used.

[0038] While terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from others. Therefore, the first component referred to below may also be the second component within the technical concept of the present invention.

[0039] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of item 1, item 2, and item 3" could mean not just each of item 1, item 2, or item 3 individually, but all possible combinations of items that can be presented from two or more of items 1, item 2, and item 3.

[0040] The features of some examples of the present invention can be combined or linked together in part or as a whole, enabling various technically interconnected and driven configurations, and each embodiment can be implemented independently of others or in association with each other.

[0041] When adding reference numerals to the components of each figure illustrating an embodiment of the present invention, the same component may, as far as possible, have the same reference numeral, even if it is shown in a different figure.

[0042] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished only for the sake of explanation, and the source electrode and the drain electrode can be interchangeable. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Furthermore, the source electrode in one embodiment can become the drain electrode in another embodiment, and the drain electrode in one embodiment can become the source electrode in another embodiment.

[0043] In some embodiments of the present invention, for the sake of explanation, the source region and source electrode may be distinguished, and the drain region and drain electrode may be distinguished, but embodiments of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0044] Figure 1 is a plan view of a thin-film transistor substrate 100 according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II' of Figure 1. Figure 3 is a cross-sectional view of a thin-film transistor substrate 200 according to another embodiment of the present invention. Figure 4 is a cross-sectional view of a thin-film transistor substrate 300 according to yet another embodiment of the present invention. Figure 5 is a cross-sectional view of a thin-film transistor substrate 400 according to yet another embodiment of the present invention.

[0045] A thin-film transistor substrate 100 according to one embodiment of the present invention is placed on a base substrate 110.

[0046] A thin-film transistor substrate 100 according to one embodiment of the present invention may include a first thin-film transistor (T11) and a second thin-film transistor (T12) connected in series with respect to each other.

[0047] A first thin-film transistor (T11) according to one embodiment of the present invention includes a first active layer 131, a first gate electrode 151, a first source electrode 171, and a first drain electrode 172. A second thin-film transistor (T12) includes a second active layer 132, a second gate electrode 152, a second source electrode 173, and a second drain electrode 174.

[0048] The components of the first thin-film transistor (T11) and the second thin-film transistor (T12) will be described in detail later.

[0049] Glass or plastic can be used as the base substrate 110. A transparent plastic with flexible properties, such as polyimide, can be used as the plastic.

[0050] A first light-shielding layer 105 and a second light-shielding layer 106 may be placed on the base substrate 110 (see Figure 4). The first light-shielding layer 105 and the second light-shielding layer 106 block light incident from the base substrate 110 and protect the first active layer 131 and the second active layer 132. The first light-shielding layer 105 and the second light-shielding layer 106 may be omitted if other structures function as light shields.

[0051] According to one embodiment of the present invention, the first light-shielding layer 105 may have a closed-loop shape while superimposed on the first gate electrode 151. Furthermore, the second light-shielding layer 106 may have a closed-loop shape while superimposed on the second gate electrode 152.

[0052] According to one embodiment of the present invention, a buffer layer 120 can be placed on a base substrate 110.

[0053] The buffer layer 120 is insulating and protects the first active layer 131 and the second active layer 132. The buffer layer 120 may contain at least one of the insulating materials silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide.

[0054] Figures 2 to 5 show the buffer layer 120 as a single layer, but the embodiment of the present invention is not limited to this, and can consist of multiple layers. Furthermore, other layers can be placed between the base substrate 110 and the buffer layer 120, and yet another layer can be placed between the buffer layer 120 and the first active layer 131 and the second active layer 132.

[0055] According to one embodiment of the present invention, the first active layer 131 and the second active layer 132 are arranged on the buffer layer 120.

[0056] The first active layer 131 includes a first channel portion 131n, a first source conductor portion 131a located on one side of the first channel portion 131n, and a first drain conductor portion 131b located on the other side of the first channel portion 131n. The second active layer 132 includes a second channel portion 132n, a second source conductor portion 132a located on one side of the second channel portion 132n, and a second drain conductor portion 132b located on the other side of the second channel portion 132n.

[0057] For example, the first channel portion 131n is positioned between the first source conductor portion 131a and the first drain conductor portion 131b, and the second channel portion 132n is positioned between the second source conductor portion 132a and the second drain conductor portion 132b.

[0058] The first active layer 131 may further include a first source coupling portion 131c disposed between the first channel portion 131n and the first source conductor portion 131a, and a first drain coupling portion 131d disposed between the first channel portion 131n and the first drain conductor portion 131b.

[0059] The second active layer 132 may further include a second source coupling portion 132c disposed between the second channel portion 132n and the second source conductor portion 132a, and a second drain coupling portion 132d disposed between the second channel portion 132n and the second drain conductor portion 132b.

[0060] The first active layer 131 and the second active layer 132 may contain oxide semiconductor material.

[0061] The oxide semiconductor material may include, for example, at least one of the following: IZO(InZnO)-based oxide semiconductor material, IGO(InGaO)-based oxide semiconductor material, ITO(InSnO)-based oxide semiconductor material, IGZO(InGaZnO)-based oxide semiconductor material, IGZTO(InGaZnSnO)-based oxide semiconductor material, GZTO(GaZnSnO)-based oxide semiconductor material, GZO(GaZnO)-based oxide semiconductor material, ITZO(InSnZnO)-based oxide semiconductor material, and FIZO(FeInZnO)-based oxide semiconductor material. However, the embodiment of the present invention is not limited thereto, and the first active layer 131 and the second active layer 132 can also be made from other oxide semiconductor materials known in the industry.

[0062] The first source connection portion 131c and the first drain connection portion 131d of the first active layer 131 can be formed by selective conductor formation of the first active layer 131, which is made of a semiconductor material. According to one embodiment of the present invention, selective conductor formation refers to imparting conductivity to a specific portion of the first active layer 131 so that it can function like a conductor. The second source connection portion 132c and the second drain connection portion 132d of the second active layer 132 can be formed by selective conductor formation of the second active layer 132, which is made of a semiconductor material.

[0063] For example, the first active layer 131 and the second active layer 132 can be selectively made conductive by ion doping. As a result, the first source connector 131c, the first drain connector 131d, the second source connector 132c, and the second drain connector 132d can be formed. However, the embodiment of the present invention is not limited thereto, and the first active layer 131 and the second active layer 132 can also be selectively made conductive by other methods known in the art.

[0064] The first source connection 131c, the first drain connection 131d, the second source connection 132c, and the second drain connection 132d do not overlap with the first gate electrode 151 and the second gate electrode 152. The first source connection 131c, the first drain connection 131d, the second source connection 132c, and the second drain connection 132d have superior conductivity and high mobility compared to the first channel 131n and the second channel 132n. Therefore, the first source connection 131c, the first drain connection 131d, the second source connection 132c, and the second drain connection 132d can each serve as wiring.

[0065] According to one embodiment of the present invention, the first drain conductor portion 131b and the second source conductor portion 132a may be integrally formed.

[0066] The first active layer 131 and the second active layer 132 may have a multilayer structure.

[0067] According to one embodiment of the present invention, the first thin-film transistor (T11) may further include a first source electrode 171 and a first drain electrode 172 arranged in contact with the first active layer 131 and spaced apart from each other. The second thin-film transistor (T12) may also include a second source electrode 173 and a second drain electrode 174 arranged in contact with the second active layer 132 and spaced apart from each other.

[0068] For example, the first source electrode 171 and the first drain electrode 172 are arranged to be separated from each other while in contact with the first source conductor portion 131a and the first drain conductor portion 131b of the first active layer 131, respectively, and the second source electrode 173 and the second drain electrode 274 are arranged to be separated from each other while in contact with the conductor portion 132a and the second drain conductor portion 132b, respectively.

[0069] According to one embodiment of the present invention, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may each contain at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), and barium (Ba).

[0070] The first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may be reducing. The first active layer 131 can be selectively made conductive by the first source electrode 171 and the first drain electrode 172. The second active layer 132 can be selectively made conductive by the second source electrode 173 and the second drain electrode 174. According to one embodiment of the present invention, the first source conductor portion 131a and the first drain conductor portion 131b are in contact with the first source electrode 171 and the first drain electrode 172, respectively. The regions of the first active layer 131 that are in contact with the first source electrode 171 and the first drain electrode 172 are made conductive, and the first source conductor portion 131a and the first drain conductor portion 131b can be formed, respectively.

[0071] Specifically, according to one embodiment of the present invention, the portions of the first active layer 131 that are in contact with the first source electrode 171 and the first drain electrode 172 are reduced, respectively, to form the first source conductor portion 131a and the first drain conductor portion 131b. In addition, the portions of the second active layer 132 that are in contact with the second source electrode 173 and the second drain electrode 174 are reduced, respectively, to form the second source conductor portion 132a and the second drain conductor portion 132b.

[0072] For example, when a portion of the first active layer 131 and the second active layer 132 that are in contact with and superimposed on the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 are reduced, oxygen vacancies are generated in the first active layer 131 and the second active layer 132, thereby selectively making the first active layer 131 and the second active layer 132 conductive. Through such selective reduction of the first active layer 131 and the second active layer 132, the first source conductor portion 131a, the first drain conductor portion 131b, the second source conductor portion 132a, and the second drain conductor portion 132b can be formed.

[0073] Generally, dual-gate structures have been used to overcome the stress conditions of high-drain bias within transistors. Specifically, dual-gate structures have been used in which two gates are arranged in series to distribute the voltage.

[0074] In a dual-gate structure where two gates are connected in series, the voltage across each gate may not always be equal. For example, a high voltage may be applied to the gate of one of the two transistors to which a high potential voltage is applied. In other words, the electric field may concentrate in the active layer of the transistor to which the high potential voltage is applied, causing degradation. Specifically, the electric field may concentrate in the drain region of the active layer of the transistor to which the high potential voltage is applied, causing degradation.

[0075] According to one embodiment of the present invention, in order to prevent degradation concentration in the drain region of a transistor to which a high potential voltage is applied, the second drain electrode 174 may have a larger area on a plane than the second source electrode 173. Here, a high potential voltage is applied to the second thin-film transistor (T12).

[0076] Specifically, the second drain electrode 174 of the second thin-film transistor (T12), to which a high potential voltage is applied, can be formed relatively wider than the second source electrode 173, thereby reducing the voltage applied to the second gate electrode 152 of the second thin-film transistor (T12). As a result, the electric field effect concentrated in the second drain conductor portion 132b and the second drain connecting portion 132d of the second active layer 132 can be reduced, and degradation in the second thin-film transistor (T12) can be prevented or suppressed.

[0077] According to one embodiment of the present invention, the first source electrode 171 of the first thin-film transistor (T11) may have a larger area on a plane than the first drain electrode 172. Specifically, the first drain electrode 172 of the first thin-film transistor (T11) can be formed relatively narrower than the first source electrode 171 to increase the voltage applied to the first gate electrode 151 of the first thin-film transistor (T11). As a result, the voltage applied to the second gate electrode 152 of the second thin-film transistor (T12) can be decreased by the amount by which the voltage applied to the first gate electrode 151 of the first thin-film transistor (T11) increases.

[0078] Therefore, the electric field effect concentrated in the second drain conductor portion 132b and the second drain connecting portion 132d of the second active layer 132 can be reduced, and degradation in the second thin-film transistor (T12) can be prevented or suppressed.

[0079] According to one embodiment of the present invention, the first drain electrode 172 and the second source electrode 173 are integrally formed. Specifically, the first drain electrode 172 and the second source electrode 173 may be circular in shape.

[0080] According to one embodiment of the present invention, the area occupied by the thin-film transistor substrate 100 can be reduced by integrating the first drain electrode 172 and the second source electrode 173. For example, when the thin-film transistor substrate 100 according to one embodiment of the present invention is provided in the gate driver of a display device, the display device of the present invention can implement a narrow bezel.

[0081] According to one embodiment of the present invention, the first source electrode 171 may be U-shaped, and the second drain electrode 174 may be a U-shaped shape rotated 180°. For example, the second drain electrode 174 may have a U-shaped shape that is inverted 180°. In such a case, the second drain electrode 174 may have a larger surface area on a plane compared to the first source electrode 171.

[0082] According to one embodiment of the present invention, the first thin-film transistor (T11) may further include a first gate electrode 151 that is disposed apart from the first active layer 131 and superimposed on the first active layer 131. The second thin-film transistor (T12) may further include a second gate electrode 152 that is disposed apart from the second active layer 132 and superimposed on the second active layer 132.

[0083] The first gate electrode 151 and the second gate electrode 152 may each contain at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloys; silver-based metals such as silver (Ag) or silver alloys; copper-based metals such as copper (Cu) or copper alloys; molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). Although not shown in the figure, the first gate electrode 151 and the second gate electrode 152 may have a multilayer structure containing two conductive films with different physical properties.

[0084] According to one embodiment of the present invention, the first gate electrode 151 may be U-shaped. The second gate electrode 152 may be U-shaped rotated 180°.

[0085] Referring to Figure 1, the first gate electrode 151 and the second gate electrode 152 can together form a gate electrode 150. For example, the gate electrode 150 may include the first gate electrode 151 and the second gate electrode 152. The gate electrode 150 can have a ring shape. For example, the gate electrode 150 can have a circular or elliptical ring shape. For example, the gate electrode 150 can have a closed loop shape. For example, the first gate electrode 151 and the second gate electrode 152 can together form a closed loop shape.

[0086] Referring to Figure 1, the first gate electrode 151 represents the region that overlaps with the first active layer 131 on a plane. The second gate electrode 152 represents the region that overlaps with the second active layer 132 on a plane. Here, the gate electrode 150 may include a connecting portion that does not overlap with the first active layer 131 and the second active layer 132.

[0087] For example, the region of the gate electrode 150 that overlaps with the first active layer 131 can be designated as the first gate electrode 151, and the region that overlaps with the second active layer 132 can be designated as the second gate electrode 152.

[0088] According to one embodiment of the present invention, the second gate electrode 152 may have a larger area than the first gate electrode 151. When the area of ​​the second gate electrode 152 of the second thin-film transistor (T12) is larger than the area of ​​the first gate electrode 151 of the first thin-film transistor (T11), it is possible to prevent the electric field from concentrating in the second active layer 132 of the second thin-film transistor (T12). As a result, it is possible to prevent degradation of the thin-film transistor substrate 100 according to the present invention.

[0089] According to one embodiment of the present invention, the first drain electrode 172 and the second source electrode 173 are arranged on a plane inside a single integrated first gate electrode 151 and second gate electrode 152. For example, the first drain electrode 172 and the second source electrode 173 are arranged on a plane inside a single integrated first gate electrode 151 and second gate electrode 152.

[0090] By arranging the first drain electrode 172 and the second source electrode 173 inside the first gate electrode 151 and the second gate electrode 152, which are integrally formed, the area occupied by the thin-film transistor substrate 100 can be reduced. For example, when the thin-film transistor substrate 100 according to one embodiment of the present invention is incorporated into the gate driver of a display device, the display device of the present invention can implement a narrow bezel.

[0091] According to one embodiment of the present invention, the second channel portion 132n may have a larger area on a plane than the first channel portion 131n. For example, if the area of ​​the second channel portion 132n is larger than the area of ​​the first channel portion 131n, the resistance in the second channel portion 132n will be lower than the resistance in the first channel portion 131n, thereby reducing the occurrence of degradation in the second thin-film transistor (T12).

[0092] For example, referring to Figure 1, the first channel portion 131n may have a first length (L1) and a first width (W1) perpendicular to the first length (L1) and extending along the first channel portion 131n. The second channel portion 132n may have a second length (L2) and a second width (W2) perpendicular to the second length (L2) and extending along the second channel portion 132n. Here, the second width (W2) of the second channel portion 132n may be longer than the first width (W1) of the first channel portion 131n.

[0093] The first length (L1) according to the present invention may be the shortest length between the first source connection portion 131c and the first drain connection portion 131d. For example, if the first source connection portion 131c and the first drain connection portion 131d are not present, it may be the shortest length between the first source conductor portion 131a and the first drain conductor portion 131b. The explanation for the second length (L2) according to the present invention is omitted as it overlaps with the explanation for the first length (L1).

[0094] The first width (W1) according to the present invention may be the length of a region perpendicular to the first length (L1) and extending along the first channel portion 131n. The description of the second width (W2) according to the present invention is omitted as it overlaps with that of the first width (W1).

[0095] According to one embodiment of the present invention, the first length (L1) and the second length (L2) may be the same.

[0096] According to one embodiment of the present invention, the first width (W1) on a plane can be made narrower as it approaches the first drain conductor portion 131b. The second width (W2) on a plane can be made wider as it approaches the second drain conductor portion 132b. For example, the first width (W1) can be made shorter as it moves away from the first source conductor portion 131a or closer to the first drain conductor portion 131b. For example, the second width (W2) can be made longer as it moves away from the second source conductor portion 132a or closer to the second drain conductor portion 132b.

[0097] The electric field concentrates on the second drain conductor portion 132b side, where a relatively high voltage is applied. Physical or electrical degradation may occur in the region where such electric field concentration occurs. If the second width (W2) on the plane widens towards the second drain conductor portion 132b, the electric field concentration at the second drain conductor portion 132b can be mitigated.

[0098] According to one embodiment of the present invention, the first channel portion 131n may be U-shaped. The second channel portion 132n may be U-shaped rotated 180°. The first channel portion 131n is superimposed on the first gate electrode 151 on a plane, and the second channel portion 132n is superimposed on the second gate electrode 152 on a plane.

[0099] According to one embodiment of the present invention, the first channel portion 131n and the second channel portion 132n may be arranged with an empty region (OP1, OP2) in between them. Specifically, the empty region (OP1, OP2) includes a first empty region (OP1) and a second empty region (OP2). The first empty region (OP1) and the second empty region (OP2) are spaced apart from each other with the first drain electrode 172 and the second source electrode 173 in between. Figure 1 shows that the first empty region (OP1) and the second empty region (OP2) are not parallel to each other, but are symmetrical with respect to the first drain electrode 172 and the second source electrode 173. However, the present invention is not limited thereto, and the first empty region (OP1) and the second empty region (OP2) can be parallel to each other while being symmetrical with respect to the first drain electrode 172 and the second source electrode 173 (see Figure 6C). For example, the first empty region (OP1) and the second empty region (OP2) can be placed on the same line.

[0100] According to one embodiment of the present invention, the first source electrode 171 and the second drain electrode 174 are arranged on a plane with an empty region (OP1, OP2) in between them.

[0101] According to one embodiment of the present invention, a gate insulating film 140 is arranged on a first active layer 131 and a second active layer 132. Specifically, the gate insulating film 140 is arranged between the first active layer 131 and the first gate electrode 151, and between the second active layer 132 and the second gate electrode 152. However, the present invention is not limited thereto, and in the case of a bottom gate structure in which the first gate electrode 151a is arranged between the base substrate 110 and the first active layer 133, and the second gate electrode 152a is arranged between the base substrate 110 and the second active layer 134, the gate insulating film 140a can also be arranged on the first gate electrode 151a and the second gate electrode 152a (see Figure 5).

[0102] According to one embodiment of the present invention, the gate insulating film 140 can cover the entire upper surface of the first active layer 131 and the second active layer 132. Figure 2 shows how the gate insulating film 140 covers the entire upper surface of the first active layer 131 and the second active layer 132. However, the present invention is not limited thereto, and the gate insulating film 140 can expose a portion of the upper surface of the first active layer 131 and the second active layer 132. For example, the first gate insulating film 141 and the second gate insulating film 142 can expose the first source connection portion 131c, the first drain connection portion 131d, the second source connection portion 132c, and the second drain connection portion 132d (see Figure 3).

[0103] The gate insulating film 140 may contain at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single-film structure or a multilayer structure. The gate insulating film 140 protects the first active layer 131 and the second active layer 132.

[0104] According to one embodiment of the present invention, a first gate electrode 151 and a second gate electrode 152 can be arranged on the gate insulating film 140. However, the present invention is not limited thereto, and in the case of a bottom gate structure, a first active layer 133 and a second active layer 134 can also be arranged on the gate insulating film 140a (see Figure 5).

[0105] An interlayer insulating film 160 is placed on the first gate electrode 151 and the second gate electrode 152. The interlayer insulating film 160 is an insulating layer made of an insulating material. Specifically, the interlayer insulating film 160 may be made of organic material, inorganic material, or a laminate of an organic layer and an inorganic layer.

[0106] According to one embodiment of the present invention, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may be arranged on the same layer. For example, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may be arranged on the first active layer 131 and the second active layer 132, respectively. For example, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may be arranged on layers different from the first gate electrode 151 and the second gate electrode 152.

[0107] According to one embodiment of the present invention, the first thin-film transistor (T11) may further include a first light-shielding layer 105 disposed between the base substrate 110 and the first active layer 131. The second thin-film transistor (T12) may further include a second light-shielding layer 106 disposed between the base substrate 110 and the second active layer 132.

[0108] For example, referring to Figure 4, a top gate structure can be used in which the first active layer 131 is placed between the base substrate 110 and the first gate electrode 151, and the second active layer 132 is placed between the base substrate 110 and the second gate electrode 152, with the first light-shielding layer 105 and the second light-shielding layer 106 arranged on the base substrate 110. The first light-shielding layer 105 and the second light-shielding layer 106 can protect the first channel portion 131n and the second channel portion 132n from the outside, respectively.

[0109] According to one embodiment of the present invention, the first light-shielding layer 105 and the second light-shielding layer 106 can each be gate electrodes. For example, the first light-shielding layer 105 and the second light-shielding layer 106 can function as lower gate electrodes. Here, the first light-shielding layer 105 may be electrically connected to the first gate electrode 151, and the second light-shielding layer 106 may be electrically connected to the second gate electrode 152. In other words, the first thin-film transistor (T11) and the second thin-film transistor (T12) can each be double-gate structures.

[0110] Referring to Figure 5, the first thin-film transistor (T11) may include a first active layer 133 and a first gate electrode 151a, and the second thin-film transistor (T12) may include a second active layer 134 and a second gate electrode 152a. The first active layer 133 may include a first channel portion 133n, a first source conductor portion 133a located on one side of the first channel portion 133n, and a first drain conductor portion 133b located on the other side of the first channel portion 133n. The second active layer 134 may include a second channel portion 134n, a second source conductor portion 134a located on one side of the second channel portion 134n, and a second drain conductor portion 134b located on the other side of the second channel portion 134n. The first channel portion 133n, first source conductor portion 133a, first drain conductor portion 133b, second channel portion 134n, second source conductor portion 134a, and second drain conductor portion 134b shown in Figure 5 may correspond to the first channel portion 131n, first source conductor portion 131a, first drain conductor portion 131b, second channel portion 132n, second source conductor portion 132a, and second drain conductor portion 132b shown in Figure 2, respectively. Also, the first source electrode 171, first drain electrode 172, second source electrode 173, and second drain electrode 174 shown in Figure 5 may correspond to the first source electrode 171, first drain electrode 172, second source electrode 173, and second drain shown in Figure 2, respectively.

[0111] Figures 6A to 6D are plan views of thin-film transistor substrates 500, 600, 700, and 800 according to other embodiments of the present invention.

[0112] According to one embodiment of the present invention, the first gate electrode 151 and the second gate electrode 152 can integrally form one of a circular ring, an elliptical ring, or a square ring with rounded vertices on a plane. For example, the gate electrode 150, consisting of the first gate electrode 151 and the second gate electrode 152, can be formed as one of a circular ring, an elliptical ring, or a square ring with rounded vertices.

[0113] Figure 1 shows how the first gate electrode 151 and the second gate electrode 152 form a single quadrangular ring with rounded vertices. Figures 6A to 6C show how the first gate electrode 151 and the second gate electrode 152 form a single elliptical ring.

[0114] When the first gate electrode 151 and the second gate electrode 152 form a polygonal ring shape as a whole, the lengths of the first channel portion 131n and the second channel portion 132n may increase at the vertices of the polygon. As a result, the electric field may concentrate at the vertices of the first gate electrode 151 and the second gate electrode 152, which may lead to degradation at the vertices of the first gate electrode 151 and the second gate electrode 152.

[0115] According to one embodiment of the present invention, the first source electrode 171 may have an inner surface 171a and an outer surface 171b. The second drain electrode 174 may have an inner surface 174a and an outer surface 174b.

[0116] According to one embodiment of the present invention, the corners of the inner surface 171a of the first source electrode 171 and the inner surface 174a of the second drain electrode 174 may have a rounded or curved shape. In the present invention, the inner surface may mean the surface facing the gate electrode on a plane.

[0117] Referring to Figures 6A to 6C, the inner surfaces 171a of the first source electrode 171 and 174a of the second drain electrode 174 may have rounded corners. For example, even if the first gate electrode 151 and the second gate electrode 152 are integrally circular ring-shaped, if the inner surfaces 171a of the first source electrode 171 and 174a of the second drain electrode 174 have a certain angle, the length of the conductive region may increase from the region with the certain angle, which can lead to a problem of increased resistance.

[0118] However, the outer surface 171b of the first source electrode 171 and the outer surface 174b of the second drain electrode 174 may each have a rounded shape or a certain angle.

[0119] For example, Figures 6A and 6C show that the outer surface 171b of the first source electrode 171 and the outer surface 174b of the second drain electrode 174 each have a rounded shape.

[0120] For example, Figure 6B shows that the outer surface 171b of the first source electrode 171 and the outer surface 174b of the second drain electrode 174 are at a perpendicular angle.

[0121] Referring to Figure 6D, the thin-film transistor substrate 800 may include a third thin-film transistor (T13) and a fourth thin-film transistor (T14) connected in series with each other.

[0122] The third thin-film transistor (T13) includes a third active layer 231 having a third channel portion 231n, a third gate electrode 251 disposed at a distance from the third active layer 231 and superimposed on the third active layer 231, and a third source electrode 271 and a third drain electrode 272 disposed in contact with the third active layer 231 and at a distance from each other.

[0123] The fourth thin-film transistor (T14) includes a fourth active layer 232 having a fourth channel portion 232n, a fourth gate electrode 252 positioned apart from and superimposed on the fourth active layer 232, and a fourth source electrode 273 and a fourth drain electrode 274 positioned in contact with and separated from the fourth active layer 232.

[0124] Compared to the thin-film transistor substrate 100 shown in Figure 1, the thin-film transistor substrate 800 shown in Figure 6D allows the third channel portion 231n to have the same area as the fourth channel portion 232n on a planar surface, the first source electrode 271 and the second drain electrode 274 to have the same area on a planar surface, and the first gate electrode 251 and the second gate electrode 252 to have the same area on a planar surface.

[0125] On a plane, the first source electrode 271 may have the same area as the second drain electrode 274. For example, the first gate electrode 251 and the second gate electrode 252 may have the same area on a plane. For example, the first active layer 231 and the second active layer 232 may have the same area on a plane.

[0126] Figure 7 is a schematic diagram of a display device 1000 according to another embodiment of the present invention. Figure 8 is a schematic block diagram showing some of the stages of the gate driver 320 according to the present invention. Figure 9 is a circuit diagram showing the configuration of each stage (STn) according to the present invention. Figure 10 is a circuit diagram of any one pixel (P) in Figure 7.

[0127] Referring to Figure 7, the display device 1000 may include a display panel 310, a GIP-type gate driver 320, a data driver 330, a timing controller 340, a level shifter 360, a gamma voltage generation unit 370, a power management circuit 350, and the like.

[0128] The power management circuit 350 can generate and output various drive voltages necessary for the operation of all components of the display device 1000, namely the display panel 310, gate driver 320, data driver 330, timing controller 340, level shifter 360, gamma voltage generation unit 370, etc., using an input voltage supplied from an external source.

[0129] The timing controller 340 can receive video data and synchronization signals from an external host system. The timing controller 340 can perform various video processing on the video data, such as brightness correction to reduce power consumption and image quality correction, and supply the processed video data to the data driver 330. The timing controller 340 can generate multiple data control signals using the synchronization signal and internally stored timing setting information (start timing, pulse width, etc.) and supply them to the data driver 330, and generate multiple control signals and supply them to the level shifter 360.

[0130] The gamma voltage generation unit 370 can generate a set of reference gamma voltages, including multiple reference gamma voltages with different voltage levels, and supply them to the data driver 330.

[0131] The data driver 330 is controlled according to data control signals supplied from the timing controller 340, converts the digital data supplied from the timing controller 340 into analog data signals, and supplies the corresponding data signals to each of the data lines of the display panel 310.

[0132] The level shifter 360 can generate multiple gate control signals based on multiple control signals supplied from the timing controller 340 and supply them to the gate driver 320. The level shifter 360 can also level-shift start signals, reset signals, etc., supplied from the timing controller 340 and supply them to the gate driver 320.

[0133] The display panel 310 displays images via a display area (AA) in which pixels (P) are arranged in a matrix. Each pixel (P) may consist of a combination of a red (R) subpixel that emits red light, a green (G) subpixel that emits green light, a blue (B) subpixel that emits blue light, and a white (W) subpixel that emits white light.

[0134] The gate driver 320 consists of thin-film transistors located in the display area (AA) of the display panel 310, and can be arranged in a GIP (Gate In Panel) type configuration in the bezel area on both sides or one side of the display panel 310. Specifically, the gate driver 320 can be arranged on the base substrate 110 in a GIP (Gate In Panel) type configuration.

[0135] The gate driver 320 receives multiple gate control signals from the level shifter 360, performs a shift operation, and can individually drive the gate lines (GL) of the display panel 310. The gate driver 320 is composed of a shift register having multiple stages that are connected dependently to each other to generate individual gate outputs in order to drive each of the multiple gate lines (GL).

[0136] In Figure 8, for convenience, only the three stages (STn-1, STn, STn+1, where n is a natural number) that generate the three gate outputs (OUTn-1, OUTn, OUTn+1) from among the multiple stages that make up the gate driver 320 are schematically shown.

[0137] Each stage (STn) can receive a clock signal from at least one of several clock signals (CLKs) having different phases. Each stage (STn) may output an input clock pulse as a scan pulse at its gate output (OUTn) in response to either a start signal or the output of a preceding stage (set signal). Each stage (STn) may output a gate-off voltage at its gate output (OUTn) in response to either a reset signal or the output of a following stage (reset signal). The gate output (OUTn) or carry output of each stage (STn) can be used as a carry signal and supplied to other stages as a set signal or reset signal. A preceding stage means any stage located before (above) the stage in question, or any stage that outputs a scan pulse before the stage in question, and a following stage means any stage located after (below) the stage in question, or any stage that outputs a scan pulse after the stage in question.

[0138] A display device 1000 according to one embodiment of the present invention may include the thin-film transistor substrates 100, 200, 300, 400, 500, 600, 700, and 800 described above. According to one embodiment of the present invention, a gate driver 320 may include the thin-film transistor substrates 100, 200, 300, 400, 500, 600, 700, and 800 described above.

[0139] Referring to Figure 9, each stage (STn) may comprise a first charging unit 10, a first discharging unit 20, a second charging unit 30, a second discharging unit 40, an output unit 50, and a QB stabilization circuit 60. The first charging unit 10, the first discharging unit 20, the second charging unit 30, the second discharging unit 40, and the QB stabilization circuit 60 can all be defined as control units that control the Q node and QB node of the output unit 50. The Q node can be defined as the first control node, and the QB node as the second control node. For example, the control unit may charge and discharge the Q node and charge and discharge the QB node in opposition to the Q node.

[0140] Each stage (STn) may include a set terminal 2 to which either the start signal (VST) or the output of the preceding stage (CRn-4) is applied as a set signal, a first power supply terminal 4 to which a high potential voltage (VDD) is applied, a second power supply terminal 8 to which the gate off voltage (VSS) is applied, a first clock terminal 12 to which the clock signal (CLKn) is applied, an output terminal 14 to which the gate output (OUTn) is applied, a reset terminal 16 to which either the reset signal or the output of the following stage (CRn+4) is applied as a reset signal, a second clock terminal 5 to which an inverting clock signal (CLK_B) is applied, a control terminal 7 to which the output of another preceding stage (CRn-2) is applied, and a stabilization terminal 18 to which a stabilization signal (STB) is applied. The gate off voltage (VSS) may be defined as the gate low voltage. The gate output (OUTn) of each stage (STn) may be output to other stages as a carry signal (CRn).

[0141] The first charging unit 10 can receive a start signal (VST) or the output of a preceding stage (CRn-4) as a set signal via the set terminal 2, and can charge the Q node with that set signal. The output of a preceding stage (CRn-4) may be the gate output (OUTn-4) output from the (n-4th) preceding stage.

[0142] The first charging section 10 includes a first-first-quarter charging transistor (T1_a) whose gate electrode and drain electrode are connected to the set terminal 2, and whose source electrode is connected to the drain electrode of the first-second-quarter charging transistor (T1_b). It may also include a first-second-quarter charging transistor (T1_b) whose gate electrode is connected to the set terminal 2, whose drain electrode is connected to the source electrode of the first-first-quarter charging transistor (T1_a), and whose source electrode is connected to the Q node.

[0143] The first discharge unit 20 can discharge the Q node to the gate-off voltage (VSS) of the second power supply terminal 8 in response to control of the QB node. The first discharge unit 20 can receive a reset signal or the output of a successor stage (CRn+4) as a reset signal via the reset terminal 16 and discharge the Q node to the gate-off voltage (VSS) of the second power supply terminal 8. The output of a successor stage (CRn+4) may be the gate output (OUTn+4) output from the (n+4) successor stage. For example, the first discharge unit 20 may include Q discharge transistors (T3_a, T3_b) that discharge the Q node to the gate-off voltage (VSS) in response to control of the QB node. For example, the Q discharge transistors (T3_a, T3_b) may include a 1-1 Q discharge transistor (T3_a) and a 1-2 Q discharge transistor (T3_b).

[0144] The first discharge section 20 may include a first-first-Q discharge transistor (T3_a) in which the gate electrode is connected to the QB node, the source electrode is connected to the drain electrode of the first-second-Q discharge transistor (T3_b), and the drain electrode is connected to the Q node, and a first-second-Q discharge transistor (T3_b) in which the gate electrode is connected to the QB node, the drain electrode is connected to the source electrode of the first-first-Q discharge transistor, and the source electrode is connected to the second power supply terminal 8. The first discharge section 20 includes a second-first-Q discharge transistor (T3n_a) whose gate electrode is connected to a reset terminal 16 to which the output signal (CRn+4) or reset signal of the subsequent stage is supplied, whose source electrode is connected to the drain electrode of the second-second-second-Q discharge transistor, and whose drain electrode is connected to the Q node. It may also include a second-second-second-Q discharge transistor (T3n_b) whose gate electrode is connected to a reset terminal 16 to which the output signal (CRn+4) or reset signal of the subsequent stage is supplied, whose drain electrode is connected to the source electrode of the second-first-Q discharge transistor (T3n_a), and whose source electrode is connected to the second power supply terminal 8.

[0145] When Q-discharge transistors (T3_a, T3_b) are subjected to positive bias and high-temperature stress conditions, such as PBTS (Positive Bias Temperature Stress) conditions, the active layers of the 1-1Q discharge transistor (T3_a) and the 1-2Q discharge transistor (T3_b) must be formed identically so that PBTS degradation is applied evenly to both transistors.

[0146] According to one embodiment of the present invention, the Q-discharge transistors (T3_a, T3_b) may include the thin-film transistor substrate 800 shown in Figure 6D. For example, the 1-1 Q-discharge transistor (T3_a) may be the 4th thin-film transistor (T14) of the thin-film transistor substrate 800, and the 1-2 Q-discharge transistor (T3_b) may be the 3rd thin-film transistor (T13) of the thin-film transistor substrate 800. The 3rd thin-film transistor (T13) and the 4th thin-film transistor (T14) may be connected in series with each other.

[0147] When the first-first Q discharge transistor (T3_a) is the fourth thin-film transistor (T14) of the thin-film transistor substrate 800, and the first-second Q discharge transistor (T3_b) is the third thin-film transistor (T13) of the thin-film transistor substrate 800, the area of ​​the third channel portion 231n and the fourth channel portion 232n are made the same on a plane, and PBTS degradation can be applied evenly to the first-first Q discharge transistor (T3_a) and the first-second Q discharge transistor (T3_b).

[0148] The second charging unit 30 can charge the QB node to a high potential voltage (VDD) in response to a high potential voltage (VDD) applied to the first power supply terminal 4. Specifically, the second charging unit 30 may include QB charging transistors (T4_a, T4_b) that charge the QB node to a high potential voltage (VDD). For example, the second charging unit 30 may include a first QB charging transistor (T4_a) whose gate electrode and drain electrode are connected to the first power supply terminal 4, and whose source electrode is connected to the drain electrode of the second QB charging transistor (T4_b). For example, the drain electrode of the first QB charging transistor (T4_a) is subjected to a high potential voltage (VDD). The second charging unit 30 may also include a second QB charging transistor (T4_b) whose gate electrode is connected to the first power supply terminal 4, whose drain electrode is connected to the source electrode of the first QB charging transistor (T4_a), and whose source electrode is connected to the QB node.

[0149] According to one embodiment of the present invention, the QB charging transistors (T4_a, T4_b) may include the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700 shown in Figures 1 to 6C. For example, the first QB charging transistor (T4_a) may be the second thin-film transistor (T12) of the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700. The second QB charging transistor (T4_b) may be the first thin-film transistor (T11) of the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700.

[0150] The first QB charging transistor (T4_a) is the second thin-film transistor (T12) on thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700, and the second QB charging transistor (T4_b) is the first thin-film transistor (T11) on thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700. In this case, degradation of the first QB charging transistor (T4_a), to which a high potential voltage is applied, can be prevented.

[0151] The second discharge unit 40 can discharge the QB node to the gate-off voltage (VSS) of the second power supply terminal 8 in response to control of the Q node. The second discharge unit 40 can discharge the QB node to the gate-off voltage (VSS) of the second power supply terminal 8 in response to control of the set terminal 2 to which a start signal (VST) or the output of a preceding stage (CRn-4) is supplied. The output of a preceding stage (CRn-4) may be the gate output (OUTn-4) output from the (n-4th) preceding stage.

[0152] The second discharge section 40 may include a first QB discharge transistor (T5q) in which the gate electrode is connected to the Q node, the source electrode is connected to the second power supply terminal 8, and the drain electrode is connected to the QB node. The second discharge section 40 may further include a second QB discharge transistor (T5c) in which the gate electrode is connected to the set terminal 2, the source electrode is connected to the second power supply terminal 8, and the drain electrode is connected to the QB node.

[0153] The output section 50 includes a pull-up transistor (T6) that is pulled up by the control of the Q node and outputs the clock signal (CLKn) applied to the first clock terminal 12 to the gate output (OUTn) via the output terminal 14, and a pull-down transistor (T7) that is pulled down by the control of the QB node, which is opposed to the Q node, and outputs the gate off voltage (VSS) from the second power supply terminal 8 to the gate output (OUTn) via the output terminal 14. The pull-up transistor (T6) may have its gate electrode connected to the Q node, its source electrode connected to the output terminal 14, and its drain electrode connected to the first clock terminal 12. For example, the pull-up transistor (T6) may be turned on during the on period of the Q node and output the clock signal (CLKn) from the first clock terminal 12 to the scan signal of the gate output (OUTn) via the output terminal 14. For example, the pull-up transistor (T6) is pulled up by the control of the Q node, and the clock signal (CLKn) input via the first clock terminal 12 can be output to the output terminal 14.

[0154] The output section 50 further includes a first capacitor (CB) connected between the gate electrode (Q node) and the source electrode (output terminal 14) of the pull-up transistor (T6).

[0155] The pull-down transistor (T7) may have its gate electrode connected to the QB node, its source electrode connected to the second power supply terminal 8, and its drain electrode connected to the output terminal 14. For example, the pull-down transistor (T7) may be turned on during the on and off periods of the QB node corresponding to the off period of the Q node, and may output the gate off voltage (VSS) from the second power supply terminal 8 to the off voltage of the gate output (OUTn) via the output terminal 14. For example, the pull-down transistor (T7) may have its output terminal 14 pulled down by controlling the QB node.

[0156] The QB stabilization circuit 60 responds to the inverting clock signal (CLK_B) applied via the second clock terminal 5 and the output (CRn-2) of the preceding stage (n-2th) applied via the control terminal 7, and can stably discharge the QB node to the gate-off voltage (VSS) during the Q node's on-period (Qon).

[0157] The QB stabilization circuit 60 may include two transistors (T8, T9) and two capacitors (C1, C2). The QB stabilization circuit 60 may include a first capacitor (C1) connected between the second clock terminal 5 and the connection node (A) to transmit the inverted clock signal (CLK_B) to the connection node (A), and a second capacitor (C2) connected between the control terminal 7 and the connection node (A) to transmit the output of the (n-2) preceding stage (CRn-2) to the connection node (A).

[0158] The QB stabilization circuit 60 may include a QB discharge transistor (T9) controlled by a connection node (A) to discharge the QB node to the gate-off voltage (VSS) of the second power supply terminal 8, and an initialization transistor (T8) controlled by a stabilization signal (STB) applied to the stabilization terminal 18 to initialize the connection node (A) to the gate-off voltage (VSS) of the second power supply terminal 8. The QB discharge transistor (T9) may have its gate electrode connected to the connection node (A), its source electrode connected to the second power supply terminal 8, and its drain electrode connected to the QB node. The initialization transistor (T8) may have its gate electrode connected to the stabilization terminal 18, its source electrode connected to the second power supply terminal 8, and its drain electrode connected to the connection node (A).

[0159] Figure 10 is an equivalent circuit diagram for a pixel (P) of a display device 1000 that includes an organic light-emitting diode (OLED) as the display element 710.

[0160] Referring to Figure 10, a pixel (P) includes a display element 710 and a pixel driving circuit (PDC) that drives the display element 710. Specifically, a display device 1000 according to one embodiment of the present invention may include a pixel driving circuit (PDC) on a base substrate 110.

[0161] The pixel driver circuit (PDC) in Figure 10 includes a first thin-film transistor (TR1), which is a switching transistor, and a second thin-film transistor (TR2), which is a driving transistor.

[0162] According to one embodiment of the present invention, current can flow in one direction in a drive transistor, and current can flow in both directions in a switching transistor. According to yet another embodiment of the present invention, the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above can be used as drive transistors in the pixel drive circuit (PDC) shown in Figure 10. The thin-film transistor substrate 800 described above can be used as a switching transistor in the pixel drive circuit (PDC) shown in Figure 10. Specifically, asymmetrical thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700 can be used as drive transistors in which current flows in one direction, and symmetrical thin-film transistor substrate 800 can be used as a switching transistor in which current flows in both directions.

[0163] According to yet another embodiment of the present invention, the thin-film transistors 100, 200, 300, and 400 described above can be used as driving transistors for the pixel drive circuit (PDC) shown in Figure 10.

[0164] The present invention described above is not limited to the embodiments and accompanying figures, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical matters of the present invention. Accordingly, the scope of the present invention is indicated by the claims described below, and all modified or altered forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included within the scope of the present invention. [Explanation of symbols]

[0165] T11, T12, T13, T14: 1st, 2nd, 3rd, and 4th thin-film transistors 110: Base board 120: Buffer layer 131, 132, 231, 232: Active layers 1, 2, 3, and 4 131n, 132n, 231n, 232n: 1st, 2nd, 3rd, and 4th channel sections 131a, 132a: First and second source conductor sections 131b, 132b: First and second drain conductor sections 131c, 132c: First and second source connection section 131d, 132d: First and second drain connection section 140: Gate Insulator 150: Gate Shutdown 151, 152: 1st and 2nd gates 160: Interlayer insulating film 171, 173, 271, 273: 1st, 2nd, 3rd, and 4th source electrodes 172, 174, 272, 274: 1st, 2nd, 3rd, and 4th drain electrodes

Claims

1. Base board and It includes a first thin-film transistor and a second thin-film transistor arranged on the base substrate and connected in series with each other, The first thin-film transistor, A first active layer having a first channel section, A first gate electrode is disposed at a distance from the first active layer and superimposed on the first active layer, It includes a first source electrode and a first drain electrode, which are in contact with the first active layer and spaced apart from each other, The second thin-film transistor is A second active layer having a second channel section, A second gate electrode is positioned separately from the second active layer and superimposed on the second active layer, It includes a second source electrode and a second drain electrode, which are in contact with the second active layer and spaced apart from each other, The first gate electrode and the second gate electrode are integrally formed and arranged on the same layer. A thin-film transistor substrate in which the first drain electrode and the second source electrode are integrally formed and arranged on the same layer.

2. The thin-film transistor substrate according to claim 1, wherein the first gate electrode and the second gate electrode integrally form a closed-loop shape.

3. The thin-film transistor substrate according to claim 2, wherein the first drain electrode and the second source electrode are integrally formed on a plane and are arranged inside the first gate electrode and the second gate electrode.

4. The first active group is, A first source conductor portion is disposed on one side of the first channel portion, It includes a first drain conductor portion located on the other side of the first channel portion, The aforementioned second active layer is, A second source conductor portion is arranged on one side of the second channel portion, It includes a second drain conductor portion located on the other side of the second channel portion, The thin-film transistor substrate according to claim 1, wherein the first channel portion and the second channel portion are arranged with an empty region between them.

5. The first channel portion has a first length and a first width perpendicular to the first length and extending along the first channel portion, The second channel portion has a second length and a second width perpendicular to the second length and extending along the second channel portion. The second width is longer than the first width. The thin-film transistor substrate according to claim 4, wherein the first length and the second length are the same.

6. On a plane, the first width becomes narrower as it moves from the first source conductor portion toward the first drain conductor portion. The thin-film transistor substrate according to claim 5, wherein the second width on a plane increases from the second source conductor portion toward the second drain conductor portion.

7. The thin-film transistor substrate according to claim 1, wherein the second channel portion has a larger area than the first channel portion on a plane.

8. On a plane, the second drain electrode has a larger area than the first source electrode, The thin-film transistor substrate according to claim 4, wherein the first source electrode and the second drain electrode are arranged with the air region between them.

9. The first channel portion is U-shaped, The thin-film transistor substrate according to claim 1, wherein the second channel portion is a U-shape rotated 180°.

10. The first electrode is U-shaped, The thin-film transistor substrate according to claim 1, wherein the second gate electrode is U-shaped and rotated 180°.

11. The first source electrode is U-shaped, The thin-film transistor substrate according to claim 4, wherein the second drain electrode is U-shaped and rotated 180°.

12. On a plane, the first gate electrode and the second gate electrode integrally form one of the following: a circular ring, an elliptical ring, or a square ring with rounded vertices. The thin-film transistor substrate according to claim 1, wherein the inner surface of the first source electrode and the inner surface of the second drain electrode, respectively, have rounded corners on a planar surface.

13. The thin-film transistor substrate according to claim 1, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are arranged on the same layer and on a different layer from the first gate electrode and the second gate electrode.

14. The first active layer is disposed between the base substrate and the first gate electrode. The thin-film transistor substrate according to claim 13, wherein the second active layer is disposed between the base substrate and the second gate electrode.

15. The first thin-film transistor includes a first light-shielding layer disposed between the base substrate and the first active layer, The second thin-film transistor includes a second light-shielding layer disposed between the base substrate and the second active layer. The first light-shielding layer has a closed-loop shape while superimposed on the first gate electrode, The thin-film transistor substrate according to claim 14, wherein the second light-shielding layer has a closed-loop shape while superimposed on the second gate electrode.

16. The first light-shielding layer is electrically connected to the first gate electrode, The thin-film transistor substrate according to claim 15, wherein the second light-shielding layer is electrically connected to the second gate electrode.

17. The first gate electrode is disposed between the base substrate and the first active layer. The thin-film transistor substrate according to claim 1, wherein the second gate electrode is disposed between the base substrate and the second active layer.

18. A display device comprising a thin-film transistor substrate according to any one of claims 1 to 17.

19. It includes a gate driver and pixel driving circuit having multiple stages that drive multiple gate lines, respectively. Each of the aforementioned multiple stages is An output section including a pull-up transistor that is pulled up by the control of the Q node and outputs a first clock signal input via the first clock terminal of multiple clocks to the output terminal, and a pull-down transistor that pulls down the output terminal by the control of the QB node, The system includes a control unit that charges and discharges the Q node and charges and discharges the QB node in opposition to the Q node, The control unit includes a QB charging transistor that charges the QB node to a high potential voltage. The QB charging transistor includes a first QB charging transistor and a second QB charging transistor, The high potential voltage is applied to the drain electrode of the first QB charging transistor, and the source electrode of the second QB charging transistor is connected to the QB node. The display device according to claim 18, wherein the first QB charging transistor is the second thin-film transistor, and the second QB charging transistor is the first thin-film transistor.

20. The control unit includes a Q-discharge transistor that discharges the Q node to a gate-off voltage by controlling the QB node, The Q-discharge transistor includes a third thin-film transistor and a fourth thin-film transistor connected in series with each other. The third thin-film transistor is A third active layer having a third channel portion, A third gate electrode is positioned separately from the third active layer and superimposed on the third active layer, It includes a third source electrode and a fourth drain electrode that are in contact with the third active layer and are arranged apart from each other, The fourth thin-film transistor is A fourth active layer having a fourth channel portion, A fourth gate electrode is positioned separately from the fourth active layer and superimposed on the fourth active layer, It includes a fourth source electrode and a fourth drain electrode that are in contact with the fourth active layer and are arranged apart from each other, The third gate electrode and the fourth gate electrode are integrally formed and arranged on the same layer. The third drain electrode and the fourth source electrode are integrally formed, The display device according to claim 19, wherein the third channel portion has the same area as the fourth channel portion on a plane.

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