Semiconductor memory

Abstract

To improve the integration density of semiconductor memory devices. [Solution] The semiconductor memory device according to the embodiment comprises: two first conductive pillars extending in a first direction intersecting the substrate and aligned in a second direction intersecting the first direction; a first semiconductor layer and a second semiconductor layer provided in a first plane parallel to the substrate so as to sandwich the two first conductive pillars in a third direction intersecting the first and second directions; a first insulator provided between the two first conductive pillars to insulate the two first conductive pillars from each other and to insulate the first semiconductor layer and the second semiconductor layer in the first plane; two first charge storage films provided in the first plane between the two first conductive pillars and the first semiconductor layer, respectively; and two second charge storage films provided in the first plane between the two first conductive pillars and the second semiconductor layer, wherein the portion of the first insulator that contacts the first and second semiconductor layers in the first plane is formed in a concentric circular or concentric elliptical shape with its center between the two first conductive pillars.

Description

Technical Field

[0001] Embodiments relate to semiconductor memory devices.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatiley, a NAND type flash memory is known. In a NAND type flash memory, a three-dimensional memory structure may be adopted for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the integration degree of the semiconductor memory device.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment comprises: two first conductive pillars extending in a first direction intersecting the substrate and aligned in a second direction intersecting the first direction; a first semiconductor layer and a second semiconductor layer provided in a first plane parallel to the substrate so as to sandwich the two first conductive pillars in a third direction intersecting the first and second directions; a first insulator provided between the two first conductive pillars to insulate the two first conductive pillars from each other and to insulate the first semiconductor layer and the second semiconductor layer in the first plane; two first charge storage films provided in the first plane between the two first conductive pillars and the first semiconductor layer, respectively; and two second charge storage films provided in the first plane between the two first conductive pillars and the second semiconductor layer, wherein the portion of the first insulator that contacts the first semiconductor layer and the second semiconductor layer in the first plane is formed in a concentric circular or concentric elliptical shape with its center between the two first conductive pillars. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 3] Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to this embodiment. [Figure 4] Figure 4 is a plan view showing an example of a planar layout in the memory cell region of a memory cell array provided in a semiconductor memory device according to this embodiment. [Figure 5] Figure 5 is a cross-sectional view showing an example of the cross-sectional structure in the memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment, along the VV line in Figure 4. [Figure 6] Figure 6 is a cross-sectional view showing an example of the cross-sectional structure in the memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment, along the line VI-VI in Figure 4. [Figure 7]Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a conductive pillar in a semiconductor memory device according to the embodiment. [Figure 8] Figure 8 is a cross-sectional view along line VIII-VIII in Figure 6, showing an example of the cross-sectional structure of a conductive pillar in a semiconductor memory device according to the embodiment. [Figure 9] Figure 9 is a cross-sectional view along the line IX-IX in Figure 6, showing an example of the cross-sectional structure of a conductive pillar in a semiconductor memory device according to the embodiment. [Figure 10] Figure 10 is a flowchart showing an example of the manufacturing process for a memory cell region of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 11] Figure 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment, during the manufacturing process. [Figure 12] Figure 12 is a plan view showing an example of a planar layout of a memory cell region of a memory cell array in a semiconductor memory device according to the embodiment, during the manufacturing process. [Figure 13] Figure 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell region of a memory cell array in a semiconductor memory device according to the embodiment during the manufacturing process. [Figure 14] Figure 14 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell region of a memory cell array in a semiconductor memory device according to the embodiment during the manufacturing process. [Figure 15] Figure 15 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment. [Figure 16] Figure 16 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment, during the manufacturing process. [Figure 17] Figure 17 is a plan view showing an example of a planar layout of a memory cell region of a memory cell array in a semiconductor memory device according to an embodiment, during the manufacturing process. [Figure 18] Figure 18 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 26] FIG. 26 is a plan view showing an example of a planar layout in a memory cell region of a memory cell array included in the semiconductor memory device according to the first modification of the embodiment. [Figure 27] FIG. 27 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor memory device according to the second modification of the embodiment. [Figure 28] FIG. 28 is a cross-sectional view showing an example of a cross-sectional structure of a word line switch included in the semiconductor memory device according to the second modification of the embodiment. [Figure 29] FIG. 29 is a perspective view showing an example of a structure of a word line switch included in the semiconductor memory device according to the second modification of the embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Embodiments are described below with reference to the drawings. The drawings are schematic, and the dimensions and proportions shown are not necessarily the same as those of actual objects. In the following description, components having substantially the same function and configuration are denoted by the same reference numeral. When elements with similar configurations are to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0009] 1. Structure 1.1 Memory System A semiconductor memory device according to an embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0011] The semiconductor memory device 3 is, for example, a NAND flash memory capable of storing data non-volatilely.

[0012] Communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0013] 1.2 Semiconductor Memory Devices Next, the internal configuration of the semiconductor memory device 3 according to this embodiment will be described with reference to the block diagram shown in Figure 1. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0014] The memory cell array 10 is a collection of memory cell transistors and components connected to the memory cell transistors. The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as an erasure unit when erasing data stored by a memory cell transistor. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals between it and the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address information ADD, each transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2.

[0016] The logic control circuit 12 receives control signals input from the memory controller 2. Based on these control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal it has received is a command CMD or address information ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. The logic control circuit 12 also outputs a signal to the memory controller 2 indicating whether the semiconductor memory device 3 is ready or busy.

[0017] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read, write, erase, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used for selecting block BLK, word lines, and bit lines, respectively. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0018] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, based on the command CMD stored in register 13, the sequencer 14 controls the driver module 15, the row decoder module 16, and the sense amplifier module 17, etc., to perform read operations, write operations, erase operations, etc.

[0019] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0020] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0021] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0022] 1.3 Circuit configuration of memory cell array Figure 2 is a schematic diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. Figure 2 shows one block BLK. The block BLK includes, for example, four string units SU0 to SU3.

[0023] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0025] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 within string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gate of selection transistor ST2 is connected to selection gate line SGS.

[0026] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared by a NAND string NS, which is assigned the same column address CA across multiple block BLKs. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0028] A collection of multiple memory cell transistors MT connected to a common bit line BL within a single block BLK is called, for example, a layer unit LU. A single layer unit LU contains multiple NAND strings NS, corresponding to the number of string units SU contained in a single block BLK. In the example shown in Figure 2, a single layer unit LU contains four NAND strings NS. Each NAND string NS contained in a single layer unit LU belongs to string units SU0 to SU3.

[0029] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to this embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0030] 1.4 Structure of a memory cell array 1.4.1 Overview Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to an embodiment. As shown in Figure 3, the memory cell array 10 includes a plurality of bit lines BL, a plurality of word lines WL, a plurality of memory cell regions MCR, a plurality of contact regions CCR, a plurality of wiring layers LBI, and a plurality of insulators INS.

[0031] Multiple bit lines BL and multiple word lines WL extend parallel to the semiconductor substrate, intersecting each other. In the following description, the direction in which the word lines WL extend is defined as the X direction, and the direction in which the bit lines BL extend is defined as the Y direction. The direction perpendicular to the semiconductor substrate is defined as the Z direction, and the direction in which the bit lines BL and word lines WL are provided relative to the semiconductor substrate is defined as the upward direction. The opposite direction of the upward direction is defined as the downward direction.

[0032] The memory cell array 10 has a structure in which multiple semiconductor layers are stacked spaced apart from each other in the Z direction. The number of stacked semiconductor layers corresponds to the number of bit lines BL in one block BLK.

[0033] The memory cell region (MCR) is a region where memory cell transistors (MT) and related structures are provided. Multiple memory cell regions (MCRs) are aligned in the Y direction via the wiring layer (LBI) and insulator (INS), which will be described later, forming a column. The column of multiple memory cell regions (MCRs) is arranged with spacing in the X direction.

[0034] Each of the multiple memory cell regions (MCRs) includes multiple pillar rows (PLs) and a source line region (SLR). The multiple pillar rows (PLs) are rows containing multiple pillars connected in the Y direction in a plan view. The multiple pillar rows (PLs) are arranged in the X direction. Source lines (SLs) are provided in the source line region (SLR). The multiple source lines (SLs) are provided so as to penetrate the stacked semiconductor layers in the Z direction. Each memory cell region (MCR) has a shape that is substantially symmetrical in the Y direction with respect to the source line region (SLR) as the axis of symmetry. The detailed configuration of the memory cell regions (MCRs) will be described later.

[0035] The contact region CCR is the region used to connect each stacked semiconductor layer to multiple bit lines BL. For example, one contact region CCR is provided for each of multiple memory cell regions MCR aligned in the Y direction.

[0036] Multiple conductive pillars CP are provided in the contact region CCR. Each conductive pillar CP is provided corresponding to each stacked semiconductor layer, is electrically connected to that semiconductor layer, and is electrically insulated from the other semiconductor layers. Each conductive pillar CP is connected to the corresponding bit line BL via a contact CPP.

[0037] Multiple wiring layers (LBIs) connect semiconductor layers in multiple memory cell regions (MCRs) and contact regions (CCRs) arranged in the same row in the Y direction at the same height. Each wiring layer LBI has a first portion extending in the Y direction and multiple second portions extending in the X direction. The first portion of each wiring layer LBI is arranged in the X direction in one row of memory cell regions (MCRs). In the example shown in Figure 3, the first portion of each wiring layer LBI is located on the left side of the row of memory cell regions (MCRs). The second portion of each wiring layer LBI is in contact with the first portion of the wiring layer LBI at its end and is provided between and at the ends of multiple memory cell regions (MCRs) and multiple contact regions (CCRs) arranged in the Y direction. That is, the second portion of each wiring layer LBI divides multiple memory cell regions (MCRs) and multiple contact regions (CCRs). Multiple wiring layers LBIs include, for example, titanium nitride (TiN).

[0038] Multiple insulators (INS) are used to insulate each region. For example, multiple insulators (INS) insulate the first portion of the wiring layer (LBI) from the wiring layer provided in the memory cell region (MCR) in the X direction. Also, multiple insulators (INS) insulate the first portion of the wiring layer (LBI) from the semiconductor layer provided in the contact region (CCR) in the X direction.

[0039] 1.4.2 Memory cell area Figure 4 is a plan view showing an example of a planar layout in the memory cell region of a memory cell array provided in a semiconductor memory device according to the embodiment. As shown in Figure 4, the memory cell region in one semiconductor layer functions as a layer unit LU. The memory cell array 10 includes a channel layer CL, diffusion layers DL1 and DL2, a plurality of conductive pillars GP, a plurality of insulating pillars RP and LB, and a plurality of contacts MPP in the memory cell region MCR.

[0040] The channel layer CL is a semiconductor layer made of semiconductor material extending in the XY plane. The channel layer CL may contain, for example, silicon. The silicon provided in the channel layer CL may contain donor impurities such as phosphorus (P) or acceptor impurities such as boron (B), or it may not contain any impurities.

[0041] Diffusion layers DL1 and DL2 are semiconductor layers extending in the XY plane. Diffusion layers DL1 and DL2 contain silicon containing, for example, donor impurities such as phosphorus. Diffusion layer DL1 is positioned between the wiring layer LBI and the channel layer CL in the Y direction and is in contact with both. Diffusion layer DL2 is positioned in the source line region SLR so as to surround the source line SL and is in contact with the source line SL, and is in contact with the channel layer CL in the Y direction.

[0042] The planar structure, consisting of a channel layer CL and diffusion layers DL1 and DL2, is provided for each semiconductor layer spaced apart in the Z direction. That is, in each layer of stacked semiconductor layers, a channel layer CL and diffusion layers DL1 and DL2 are provided, and the layers are stacked so that they overlap in the Z direction. A voltage is applied to each of the stacked diffusion layers DL1 from the corresponding bit line BL, and their potentials may differ. The stacked diffusion layers DL2 are electrically connected via a source line SL and have approximately the same potential.

[0043] Multiple insulating pillars RP and multiple conductive pillars GP extend in the Z direction so as to intersect with the stacked semiconductor layer, and partially overlap to form multiple pillar rows PL that are alternately linked in a chain in the Y direction. For example, the multiple insulating pillars RP and multiple conductive pillars GP are arranged alternately so as to be staggered in the Y direction. The number of rows of multiple insulating pillars RP and multiple conductive pillars may vary depending on the number of word lines WL and the number of selection gate lines SGD and SGS. In the channel layer CL, multiple linear portions separated in the X direction by the multiple pillar rows PL are defined as channels CH. Channels CH function as channels for the NAND string NS.

[0044] Each insulating pillar RP includes an insulator 40 having a first portion 40-1 and a plurality of second portions 40-2. The first portion 40-1 of the insulator 40 is a cylindrical or elliptical cylindrical portion extending in the Z direction, or a frustoconical or elliptical frustoconical portion having a taper on its side that narrows toward the semiconductor substrate, and is the portion shown inside the area enclosed by the dashed line in Figure 4. The following description will focus on the case where the first portion 40-1 of the insulator 40 is frustoconical. In the plane shown in Figure 4, the first portion 40-1 of the insulator 40 is circular with radius R1. The second portion 40-2 of the insulator 40 is a portion that extends radially in the XY plane in the portion where the insulating pillar RP intersects each semiconductor layer in the Z direction, and is the portion shown outside the area enclosed by the dashed line in Figure 4. Specifically, in an XY plane containing a semiconductor layer, the cross-section of the corresponding second portion 40-2 of the insulator 40 shows a ring shape obtained by cutting out a circle of radius R1 from a circle of radius R2 (R2 > R1). A second portion 40-2 of each insulator 40 is provided for each semiconductor layer. However, the insulator 40 in each insulating pillar RP shows a shape in which the overlapping portion is missing in the portion that overlaps with a plurality of conductive pillars GP in the Z direction. The insulator 40 includes, for example, silicon oxide. The silicon oxide contained in the insulator 40 may be doped with impurities such as phosphorus (P) or nitrogen (N).

[0045] Each of the multiple conductive pillars GP includes a conductive film 30 and an insulating film 31. The conductive film 30 includes, for example, tungsten (W), molybdenum (Mo), titanium nitride (TiN), or phosphorus-doped silicon. The conductive film 30 has a cylindrical or elliptical cylindrical shape, or a frustoconical or frustoconical shape with a taper that narrows toward the semiconductor substrate side. The insulating film 31 includes, for example, silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (AlO), or hafnium oxide (HfO), and is composed of a single or multiple layers. The insulating film 31 is provided so as to cover the sides of the conductive film 30. The following description will focus on the case where the conductive film 30 and the insulating film 31 have a frustoconical shape. In the plane shown in Figure 4, the combined shape of the conductive film 30 and the insulating film 31 is a circle with radius R3. For example, R3 is approximately equal in length to R1. Note that the lengths of R1 and R3 may be different. Also, some of the multiple conductive pillars GP include a functional film 32. The functional film 32 is provided between the insulating film 31 of the corresponding conductive pillar GP and each semiconductor layer. The functional film 32 is not provided between the insulating pillar RP and the conductive pillar GP. That is, the functional film 32 has an arch shape in plan view. More specifically, in the XY plane including a certain semiconductor layer, the functional film 32 has an arch shape obtained by subtracting a sector shape with radius R3 and the same central angle as the sector shape from a sector shape with radius R4 (R4>R3). Two functional films 32 are provided for each conductive pillar GP. The two functional films 32 provided on one conductive pillar GP are insulated from each other by the insulating film 31 and the insulating pillar RP. In the following description, a conductive pillar GP including a functional film 32 is called a conductive pillar CGP, and a conductive pillar GP not including a functional film 32 is called a conductive pillar SGP. Furthermore, all conductive pillars GP may be conductive pillars CGP containing the functional film 32. In this case, some conductive pillars CGP will perform the same role as conductive pillars SGP as described below.

[0046] Multiple conductive pillars SGP are provided at positions corresponding to the conductive pillar GP closest to the diffusion layer DL1 and the conductive pillar GP closest to the diffusion layer DL2 in the pillar row PL (the Y-direction ends of the pillar row PL). In the example in Figure 4, one conductive pillar SGP is provided at the end on the diffusion layer DL1 side and one at the end on the diffusion layer DL2 side in each pillar row PL, but multiple SGPs may be provided at each end. In each channel CH, each portion of the multiple conductive pillars SGP provided on the diffusion layer DL1 side included in two adjacent pillar rows PLs that contacts the channel CH functions as a selection transistor ST1. In each channel CH, each portion of the multiple conductive pillars SGP provided on the diffusion layer DL2 side included in two adjacent pillar rows PLs that contacts the channel CH functions as a selection transistor ST2. That is, in each channel, the combination of voltages applied to the conductive pillars SGP included in two adjacent pillar rows PLs determines whether the NAND string NS containing that channel is selected or deselected.

[0047] Multiple conductive pillars CGP are positioned in the central part of the pillar row PL (not at the Y-direction end) corresponding to the conductive pillar GP. For example, multiple conductive pillars CGP are positioned side by side in the Y-direction between two conductive pillars SGP located at each Y-direction end of each pillar row PL. The portion of the multiple conductive pillars CGP that is in contact with the channel CH functions as memory cell transistors MT0 to MT7.

[0048] In the example shown in Figure 4, in the channel layer CL, one channel CH, along with four conductive pillars SGP and eight conductive pillars CGP adjacent to the channel CH, functions as one NAND string NS.

[0049] A portion of the conductive pillar SGP provided at the end of each pillar row PL on the diffusion layer DL1 side has a portion that overlaps with the diffusion layer DL1 in the Z direction. A portion of the conductive pillar SGP provided at the end of each pillar row PL on the diffusion layer DL2 side has a portion that overlaps with the diffusion layer DL2 in the Z direction. By providing the conductive pillar SGP in a position that overlaps with the diffusion layer DL1 or DL2 in the Z direction, the electrical resistance can be reduced when the conductive pillar SGP functions as a selection transistor ST1 or ST2 in the portion that contacts the channel CH. In each NAND string NS, at least one conductive pillar SGP overlapping with the diffusion layer DL1 in the Z direction and at least one conductive pillar SGP overlapping with the diffusion layer DL2 in the Z direction are provided.

[0050] Multiple contact MPPs are provided, one for each of the multiple conductive pillars GP. Of these, the contact MPP corresponding to conductive pillar SGP extends in the Z direction, contacts the conductive film 30 of conductive pillar SGP on its lower surface, and contacts the corresponding selection gate line SGD or SGS on its upper surface. The contact MPP corresponding to conductive pillar CGP extends in the Z direction, contacts the conductive film 30 of conductive pillar CGP on its lower surface, and contacts the corresponding word line WL on its upper surface.

[0051] The multiple insulating pillars LB contain an insulator (e.g., silicon oxide). Furthermore, during the manufacturing of the memory cell array 10, holes provided at positions corresponding to the multiple insulating pillars LB are used to form the wiring layer LBI and the diffusion layer DL1.

[0052] Figures 5 and 6 are cross-sectional views showing an example of the cross-sectional structure in the memory cell region of a memory cell array provided in a semiconductor memory device according to an embodiment. Figures 5 and 6 show cross-sections along the VV line and VI-VI line in Figure 4, respectively. As shown in Figures 5 and 6, the memory cell array 10 further includes a semiconductor substrate 20, insulating layers 21, 23, 24, and 25, a semiconductor layer 22, wiring layers 26 and 27, and a plurality of conductors 38.

[0053] An insulating layer 21 is stacked on top of the semiconductor substrate 20, and above that, multiple semiconductor layers 22 and multiple insulating layers 23 are stacked alternately. Each semiconductor layer 22 is formed in a plate shape stretched on the XY plane. Insulating layers 24 and 25 are stacked in this order on top of the uppermost semiconductor layer 22. Each semiconductor layer 22 corresponds to a channel layer CL. The multiple insulating layers 21, 23, 24, and 25 include, for example, silicon oxide (SiO). The film types (materials) included in the multiple insulating layers 21, 23, and 24 and the film types (materials) included in the insulator 40 may be different. However, the film types included in the multiple insulating layers 21, 23, and 24 and the insulator 40 may be the same.

[0054] Multiple wiring layers 26 and 27 are provided above the insulating layer 25. The multiple wiring layers 26 are provided above the conductive pillar CGP, corresponding to the conductive pillar CGP, and are aligned along the Y direction. The multiple wiring layers 26 are used as word lines WL. The multiple wiring layers 27 are provided above the conductive pillar SGP, corresponding to the conductive pillar SGP, and are aligned along the Y direction. The multiple wiring layers 27 are used as selection gate lines SGD and SGS. The multiple wiring layers 26 and 27 include, for example, tungsten (W).

[0055] Multiple conductors 38 are provided so as to extend in the Z direction within the insulating layer 25. Each conductor 38 is provided in correspondence with the conductive pillars CGP and SGP, and is in contact with the conductive film 30 of the conductive pillar CGP or SGP on its lower surface and in contact with the corresponding wiring layer 26 or 27 on its upper surface. Multiple conductors 38 function as contact MPPs connecting the word line WL to the conductive pillar CGP, or the selection gate lines SGD and SGS to the conductive pillar SGP.

[0056] As shown in Figure 5, a semiconductor layer 22 is provided between adjacent insulating pillars RP and conductive pillars CGP or SGP in the X direction. This portion corresponds to a channel CH and functions as a channel in the NAND string NS.

[0057] As shown in Figure 6, no portion corresponding to the semiconductor layer 22 is provided between adjacent insulating pillars RP and conductive pillars CGP or SGP in the Y direction. That is, each channel CH in each NAND string NS is separated from adjacent channels CH in the X direction.

[0058] Figures 7, 8, and 9 are cross-sectional views showing an example of the cross-sectional structure of a conductive pillar in a semiconductor memory device according to an embodiment. Figure 7 corresponds to a cross-sectional view of the conductive pillar CGP in a cross-section including the uppermost semiconductor layer 22 along VII-VII in Figure 6. Figure 8 corresponds to a cross-sectional view of the conductive pillar SGP in a cross-section including the uppermost semiconductor layer 22 along VIII-VIII in Figure 6. Figure 9 corresponds to a cross-sectional view of the conductive pillar CGP in a cross-section including the lowermost semiconductor layer 22 along IX-IX in Figure 6. As shown in Figures 7, 8, and 9, the insulating film 31 includes block insulating films 33 and 34. Also, as shown in Figures 7 and 9, the functional film 32 includes a block insulating film 35, a charge storage film 36, and a tunnel insulating film 37.

[0059] In a cross-section including the semiconductor layer 22, the conductive film 30 is provided, for example, in the central part of the conductive pillars CGP and SGP. The block insulating film 33 surrounds the sides of the conductive film 30. The block insulating film 33 contains, for example, aluminum oxide (AlO). The block insulating film 34 surrounds the sides of the block insulating film 33. The block insulating film 34 contains, for example, silicon oxide. With the above configuration, the conductive pillar SGP can function as a selective transistor ST1 or ST2 in the portion in contact with the semiconductor layer 22.

[0060] In the conductive pillar CGP shown in Figures 7 and 9, the block insulating film 35 surrounds the side surface of the block insulating film 34 that is not covered by the insulator 40. The block insulating film 35 includes, for example, hafnium oxide (HfO) or hafnium silicate (HfSiO). The charge storage film 36 surrounds the side surface of the block insulating film 35. The charge storage film 36 has the function of storing charge and includes, for example, polysilicon. The tunnel insulating film 37 surrounds the side surface of the charge storage film 36. The tunnel insulating film 37 includes, for example, silicon oxide. With the above configuration, the conductive pillar CGP can function as a memory cell transistor MT in the portion in contact with the semiconductor layer 22.

[0061] If the insulating pillar RP and conductive pillar GP have a tapered shape that narrows toward the semiconductor substrate 20, the diameter of the cross-section of the insulating pillar RP and conductive pillar GP in a cross-section including the uppermost semiconductor layer 22 may differ from the diameter of the cross-section of the insulating pillar RP and conductive pillar GP in a cross-section including the lowermost semiconductor layer 22. Specifically, in a cross-section including the uppermost semiconductor layer 22, as shown in Figures 7 and 8, the conductive film 30 and insulating film 31 have portions that overlap with both the first portion 40-1 and the second portion 40-2 of the insulator 40 in the Z direction. In other words, in a cross-section including the uppermost semiconductor layer 22, the conductive pillar GP is in contact with both the first portion 40-1 and the second portion 40-2 of the insulator 40. This indicates that, in the upper part of the semiconductor layer stacking, the pillar-like structure portion of the insulating pillar RP and the pillar-like structure portion of the conductive pillar GP overlap. On the other hand, in a cross-section including the bottom semiconductor layer 22, as shown in Figure 9, the conductive film 30 and the insulating film 31 do not overlap with the first portion 40-1 of the insulator 40 in the Z direction, but only overlap with the second portion 40-2 in the Z direction. In other words, in a cross-section including the bottom semiconductor layer 22, the conductive pillar GP does not contact the first portion 40-1 of the insulator 40, but contacts the second portion 40-2 of the insulator 40. This means that, in the lower part of the semiconductor layer stacking, the pillar-shaped structure of the insulating pillar RP and the pillar-shaped structure of the conductive pillar GP do not overlap.

[0062] Thus, when the insulating pillar RP and conductive pillar GP have a tapered shape that narrows toward the semiconductor substrate 20, the first portion 40-1 of the insulator 40, which is the pillar-shaped structural part of the insulating pillar RP, may not be able to achieve insulation between adjacent channels CH in the X direction. As a countermeasure, by providing a second portion 40-2 of the insulator 40, which is a ring-shaped structure, the semiconductor layer 22 is divided, and insulation between adjacent channels CH in the X direction is achieved.

[0063] The length of the second portion of the insulator 40 extending radially (the ring width of the ring-shaped structure) is designed such that, in a cross-section including the bottom semiconductor layer 22, it overlaps in the Z direction with the conductive pillar GP adjacent in the Y direction, and in a cross-section including the top semiconductor layer 22, the channel CH provided in the semiconductor layer 22 between it and the conductive pillar GP adjacent in the X direction has a width in the X direction that allows sufficient current to flow during various operations. Furthermore, the spacing in the Y direction between insulating pillars RP or conductive pillars GP in a pillar row PL, and the spacing between adjacent pillar rows PL in the X direction are determined so as to satisfy the above conditions.

[0064] Furthermore, if the insulating pillar RP and conductive pillar GP do not have a tapered shape, or if the taper angle is sufficiently small, and the pillar-shaped structural parts overlap in the Z direction even in the lower part of the semiconductor layer stacking, the structure corresponding to the second part 40-2 of the insulator 40 can be omitted.

[0065] 2. Manufacturing method The following shows an example of the manufacturing process for the structure of the memory cell region of a memory cell array in a semiconductor memory device according to the embodiment. Figure 10 is a flowchart showing an example of the manufacturing process for the memory cell region of a memory cell array in a semiconductor memory device according to the embodiment. Figures 11 to 25 are plan views or cross-sectional views showing an example of a planar layout or cross-sectional structure during the manufacturing process of a memory cell region of a memory cell array in a conductive memory device according to the embodiment. Figures 12 and 17 are plan views corresponding to the XY plane of the memory cell array 10 shown in Figure 4. Figures 11, 13 to 15, 18, and 20 to 24 are cross-sectional views corresponding to the XZ cross-section of the memory cell array 10 shown in Figure 5. Figures 16, 19, and 25 are cross-sectional views corresponding to the YZ cross-section of the memory cell array 10 shown in Figure 6.

[0066] As shown in Figure 10, in the manufacturing process of the memory cell region MCR, processes S101 to S111 are executed in order. An example of the manufacturing process of the memory cell region MCR will be described below with reference to Figures 11 to 25 as appropriate.

[0067] In this embodiment, a method for forming multiple semiconductor layers 22 is described in which a structure corresponding to each semiconductor layer 22 is formed using a sacrificial member 50, and then the sacrificial member 50 is replaced with a semiconductor material to form each semiconductor layer 22 (hereinafter referred to as "replacement").

[0068] First, the process in S101 is executed, and a laminated semiconductor layer structure is formed as shown in Figure 11. Specifically, an insulating layer 21 is first laminated on the semiconductor substrate 20, and then sacrificial members 50 and insulating layers 23 are alternately laminated one layer at a time above it. The multiple sacrificial members 50 include, for example, silicon nitride (SiN). An insulating layer 24 is laminated above the uppermost sacrificial member 50.

[0069] Next, processes S102 to S104 are executed in order to form the insulating pillar RP.

[0070] First, as shown in Figures 12 and 13, holes RH are formed (S102). Specifically, a mask with openings corresponding to the insulating pillar RP is formed by photolithography or the like. Then, multiple holes RH are formed by anisotropic etching using this mask. The multiple holes RH penetrate multiple insulating layers 21, insulating layer 23, and multiple sacrificial members 50, excluding the bottom insulating layer 21. At the bottom of each hole RH, a portion of the bottom insulating layer 21 is exposed.

[0071] Next, as shown in Figure 14, the peripheral portion of the sacrificial member 50 exposed on the side surface of each hole RH is removed by wet etching or the like through multiple holes RH (S103). As a result, multiple grooves are formed on the side surface of each hole RH, in which the sacrificial member 50 is recessed radially along the XY plane relative to the insulating layers 21 and 23.

[0072] Subsequently, as shown in Figures 15 and 16, an insulator 40 is embedded in each hole RH to form an insulating pillar RP (S104). The insulator 40 is in contact with the sacrificial member 50 in the lateral direction at the portion of the multiple grooves and in contact with the bottom insulating layer 21 at the bottom. At this time, the insulator 40 embedded in the multiple holes RH formed in S102 corresponds to the first portion 40-1, and the insulator 40 embedded in the multiple grooves formed in S103 corresponds to the second portion 40-2. In the example shown in Figure 16, the sacrificial member 50 remains between adjacent insulating pillars RP in the Y direction, but the insulators 40 corresponding to adjacent insulating pillars RP in the Y direction may be in contact with each other. However, a sufficient gap is provided between adjacent insulating pillars RP in the X direction, and a sacrificial member 50 is included in between. Subsequently, the insulator 40 formed on the upper surface of the insulating layer 24 is removed, for example, by CMP (Chemical Mechanical Polishing).

[0073] Next, processes S105 to S109 are executed in order to form multiple conductive pillars SGP and CGP.

[0074] First, as shown in Figures 17 to 19, multiple holes MH, LBH, and SLH are formed (S105). Specifically, a mask is formed by photolithography or the like, with openings corresponding to the conductive pillars SGP and CGP, the insulating pillar LB, and the source line SL. Then, multiple holes MH, LBH, and SLH are formed by anisotropic etching using this mask. At this time, each hole MH is provided so as to be connected in a chain with the insulating pillars RP aligned in the Y direction, and partially overlaps with the adjacent insulating pillars RP. The dotted line in Figure 19 is the region where the first part 40-1 of the insulator 40 was provided, that is, the region where the hole RH is provided. As shown in Figure 19, the multiple holes RH and MH are provided in a position where they partially overlap in the portion provided on the upper part of the semiconductor layer stacking. The multiple holes MH, LBH, and SLH penetrate the multiple insulating layers 21, insulating layer 23, and multiple sacrificial members 50, excluding the bottom insulating layer 21. At the bottom of each hole MH, LBH, and SLH, a portion of the bottom insulating layer 21 is exposed. Subsequently, the hole MH corresponding to the conductive pillar SGP, as well as the holes LBH and SLH, are filled with sacrificial members.

[0075] Next, the sacrificial members 50 are replaced (S106). Specifically, as shown in Figure 20, the sacrificial members 50 around the multiple holes MH are removed by wet etching or the like via the multiple holes MH. The three-dimensional structure of the memory cell array 10 is supported by multiple insulating pillars RP. Then, as shown in Figure 21, semiconductor material is embedded (replaced) in the area where the sacrificial members 50 were removed via the multiple holes MH. For example, CVD (Chemical Vapor Deposition) is used to form the semiconductor layer in this process. After that, the semiconductor material formed inside the holes MH is removed by an etch-back process, and adjacent semiconductor layers 22 in the Z direction are separated.

[0076] Next, as shown in Figure 22, the peripheral portions of the semiconductor layer 22 exposed on the sides of each hole MH are removed by wet etching or the like through the multiple holes MH (S107). As a result, multiple grooves are formed on the sides of each hole MH, in which the semiconductor layer 22 is recessed radially along the XY plane relative to the insulating layers 21 and 23.

[0077] Next, as shown in Figure 23, a functional film 32 is formed in the multiple grooves formed in S107 (S108). Specifically, a tunnel insulating film 37, a charge storage film 36, and a block insulating film 35 are deposited in this order on the side of each hole MH to form the functional film 32. Subsequently, the functional film 32 formed inside the hole MH is removed by an etch-back process. At this time, the functional film 32 formed in the multiple grooves is not removed. The functional film 32 is formed in an arch shape and is in contact with the semiconductor layer 22 on its side.

[0078] Subsequently, as shown in Figures 24 and 25, an insulating film 31 and a conductive film 30 are embedded in each hole MH to form a conductive pillar GP (S109). Specifically, block insulating films 34 and 33 are deposited in this order inside each hole MH to form the insulating film 31. Next, the conductive film 30 is formed to fill each hole MH. The insulating film 31 is in contact with the insulating layer 21 at its bottom surface and with the functional film 32 on a part of its side surface. The conductive film 30 is in contact with the insulating film 31 at its bottom surface and on its side surface. Finally, the conductive film 30 formed on the upper surface of the insulating layer 24 is removed, for example by CMP, exposing the surface corresponding to the upper end of the conductive pillar CGP.

[0079] Furthermore, the conductive pillar SGP is also formed in the same process as S109 after the sacrificial member provided in the hole MH corresponding to the conductive pillar SGP has been removed following the formation of the conductive pillar CGP. However, if the sacrificial member 50 remains in the portion adjacent to the hole MH corresponding to the conductive pillar SGP, the process corresponding to S106 may be inserted before the process of S109.

[0080] Subsequently, a diffusion layer DL2 and multiple source lines SL are formed (S110). Specifically, first, sacrificial members embedded in multiple holes SLH are removed. Then, sacrificial members 50 surrounding the holes SLH are removed via the multiple holes SLH. At this time, multiple semiconductor layers 22 are exposed on the side surfaces of the grooves from which the sacrificial members 50 have been removed. Next, silicon containing, for example, a donor impurity such as phosphorus is embedded (replaced) in the region from which the sacrificial members 50 have been removed, via the multiple holes SLH. Subsequently, the silicon formed inside the holes SLH is removed by an etch-back process, separating adjacent semiconductor layers 22 in the Z direction. This forms a structure corresponding to the diffusion layer DL2. After that, a metal containing, for example, tungsten is embedded in the multiple holes SLH. This forms a structure corresponding to the source lines SL. Before embedding the metal in the multiple holes SLH, the sides of the multiple holes SLH may be coated with, for example, titanium nitride.

[0081] Subsequently, a diffusion layer DL1, a wiring layer LBI, and an insulating pillar LB are formed (S111). Specifically, first, sacrificial members embedded in multiple holes LBH are removed. Then, sacrificial members 50 surrounding the holes LBH are removed via the multiple holes LBH. At this time, multiple semiconductor layers 22 are exposed on the side surfaces of the grooves from which the sacrificial members 50 have been removed. Next, silicon containing, for example, a donor impurity such as phosphorus is embedded (replaced) in the area from which the sacrificial members 50 have been removed, via the multiple holes LBH. Subsequently, the silicon formed inside the holes LBH is removed by an etch-back process, separating adjacent semiconductor layers 22 in the Z direction, and removing silicon provided in the area corresponding to the wiring layer LBI. This forms the structure corresponding to the diffusion layer DL1. Subsequently, a conductor containing, for example, titanium nitride is formed in the area from which the silicon has been removed. Subsequently, the conductor formed inside the holes LBH is removed by an etch-back process, separating adjacent semiconductor layers 22 in the Z direction. This forms the structure corresponding to the wiring layer LBI. Finally, an insulator, such as one containing silicon oxide, is embedded in the hole LBH. This forms a structure corresponding to the insulating pillar LB.

[0082] 3. Effects according to the embodiment According to this embodiment, the integration density of semiconductor memory devices can be improved. This effect will be described in detail below.

[0083] In the memory cell array 10 according to this embodiment, the conductive pillar GP is in contact with two adjacent channels CH in the X direction and functions as a memory cell transistor MT or a selection transistor ST1 or ST2 at each contact point. This structure makes it possible to reduce the spacing between multiple adjacent channels CH in the X direction compared to a configuration in which one conductive pillar corresponds to only one channel, thereby improving the integration density of the semiconductor memory device 3.

[0084] Furthermore, in the memory cell array 10 according to this embodiment, multiple channels CH are separated and insulated in the X direction by multiple pillar rows PL. Each pillar row is composed of multiple insulating pillars RP and multiple conductive pillars GP, which support the structure of the memory cell array 10 during the manufacturing process and suppress deformation of the memory cell array 10 due to stress. In the manufacturing process of the pillar row PL, first multiple holes RH corresponding to multiple insulating pillars RP are formed, and after the multiple holes RH are filled with an insulator 40, multiple holes MH corresponding to multiple conductive pillars GP are formed. Thus, in the memory cell array 10 according to this embodiment, the structure that separates adjacent channels in the X direction is formed in two stages: the formation of a structure corresponding to multiple insulating pillars RP and the formation of a structure corresponding to multiple conductive pillars GP. As a result, compared to a structure in which, for example, a trench that separates channels is formed and then the trench is filled with an insulator after replacement, the deformation of the channel layer CL in the X direction is restricted, and thus deflection of the channel layer CL can be suppressed. Therefore, there is no need to include additional structures to suppress deformation of the memory cell array 10 or bending of the channel layer CL, which reduces the chip area of ​​the additional structures and improves the integration density of the semiconductor memory device 3. Furthermore, since the processing required to form the additional structures can be omitted in the manufacturing process, an increase in manufacturing costs can be suppressed.

[0085] 4. Others The semiconductor memory device 3 according to the embodiment described above can be modified in various ways. Below, the differences between the first and second modifications of the embodiment and this embodiment will be described.

[0086] 4.1 First Variation Figure 26 is a plan view showing an example of a planar layout in the memory cell region of a memory cell array in a semiconductor memory device according to a first modified embodiment.

[0087] As shown in Figure 26, the memory cell array 10 of the semiconductor memory device 3 according to the first modified example is arranged in a grid pattern such that each of the multiple insulating pillars RP and multiple conductive pillars GP included in the multiple pillar rows PL are aligned in the same row in the X direction. For example, the multiple conductive pillars GP aligned in the X direction are connected to the same word line WL or selection gate line SGD or SGS every other time. For example, conductive pillars SGP corresponding to the selection gate line SGD and conductive pillars SGP corresponding to the selection gate line SGS are provided at both ends of each pillar row PL.

[0088] According to the first modified embodiment, the integration density of the semiconductor memory device can be improved, similar to the embodiment.

[0089] 4.2 Second Variation Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to a second modified embodiment. In Figure 27, the Z direction is shown facing downwards in the plane of the paper. Also, in Figure 27, the insulating pillar RP and some components are omitted. Figure 28 is a cross-sectional view showing an example of the cross-sectional structure of a word line switch WLSW provided in the semiconductor memory device according to a second modified embodiment. Figure 29 is a perspective view showing an example of the structure of a word line switch WLSW provided in the semiconductor memory device according to a second modified embodiment. In Figure 29, the insulating layer 70 is partially omitted.

[0090] As shown in Figure 27, the semiconductor memory device 3 according to the second modified embodiment has a bonded structure. The bonded semiconductor memory device 3 has a structure in which a memory chip 100 and a control circuit chip 200 are bonded together in the Z direction. A control circuit including, for example, a CMOS circuit is formed on the control circuit chip 200. For example, a part of the low decoder module 16, a sense amplifier module 17, and a sequencer 14 are formed on the control circuit chip 200.

[0091] The memory chip 100 includes, for example, a memory cell array 10, a plurality of word line switches WLSW, conductive pillars TP and pads PD. Furthermore, the semiconductor memory device 3 according to the second modification of the embodiment shows a structure in which the semiconductor substrate 20 is removed. However, the semiconductor substrate 20 may remain in some or all form without being removed.

[0092] The word line switch WLSW controls whether or not to drive the word line WL included in the corresponding layer unit LU. In other words, when a certain layer unit LU is selected, the corresponding word line switch WLSW is in the ON state, and when it is not selected, the corresponding word line switch WLSW is in the OFF state. The structure of the word line switch WLSW is explained below with reference to Figure 28.

[0093] As shown in Figure 28, the memory chip 100 of the semiconductor memory device 3 according to the second modified embodiment further includes a semiconductor layer 60, conductive layers 61 and 62, wiring layers 63, 64 and 65, contacts 66, 67, 68 and 69, and an insulating layer 70. Of these, the semiconductor layer 60 and the conductive layers 61 and 62 correspond to a part of a transistor that functions as a word line switch (WLSW).

[0094] The semiconductor layer 60 includes, for example, polysilicon. The semiconductor layer 60 extends, for example, in the X direction, with one end connected to the wiring layer 26 via contact 66, and the other end connected to the wiring layer 64, and to the wiring layer 65 via contacts 67 and 68. The semiconductor layer 60 electrically connects both ends when the potential difference between the conductive layers 61 and 62 is large. The semiconductor layer 60 acts as a channel in the transistor. The conductive layer 61 is used as the gate electrode in the transistor. The conductive layer 61 is connected to the wiring layer 63 via contact 69. The conductive layer 62 is used as the back gate electrode in the transistor. The conductive layer 62 may be provided in common within the same layer unit LU, as shown in Figure 29. A voltage controlling the drive of the word line switch WLSW is applied to the wiring layer 63. The conductive layers 61 and 62 include, for example, silicon or metal. The wiring layer 63 may be provided in common within the same layer unit LU, as shown in Figure 29. The wiring layer 64 connects the semiconductor layer 60 and the wiring layer 65. The wiring layer 65 functions as a global word line. The wiring layer 65 is connected to the low decoder module 16 in an area not shown, and the voltage applied to the word line WL is applied to it. The wiring layer 65 is provided in common in the same block BLK. Contact 66 extends in the Z direction through the insulator layer 70 and connects the semiconductor layer 60 and the wiring layer 26. Contact 67 extends in the Z direction through the insulator layer 70 and connects the semiconductor layer 60 and the wiring layer 64. Contact 68 extends in the Z direction through the insulator layer 70 and connects the wiring layers 64 and 65. Contact 69 extends in the Z direction through the insulator layer 70 and connects the conductive layer 61 and the wiring layer 63. The insulator layer 70 insulates each conductive layer, wiring layer, and contact from each other. Furthermore, the portion of the insulating layer 70 provided between the conductive layer 61 and the semiconductor layer 60, and the portion provided between the conductive layer 62 and the semiconductor layer 60, each function as a gate insulating film.

[0095] When the layer unit LU is selected, a high voltage is applied to the wiring layer 63. This causes the semiconductor layer 60 to become conductive, and the conductive pillar GP and the wiring layer 65 in the layer unit LU are connected. As a result, the conductive pillar GP and the row decoder module 16 are electrically connected, and reading or writing of the memory cell transistor MT is performed. On the other hand, when the layer unit LU is not selected, the potential of the wiring layer 63 becomes low. This causes the semiconductor layer 60 to become non-conductive, and the conductive pillar GP and the wiring layer 65 in the layer unit LU are insulated.

[0096] The conductive pillar TP is provided at the same height as the memory cell array 10 and is a pillar that penetrates multiple semiconductor layers 22 in the Z direction. The conductive pillar TP is insulated from each of the stacked semiconductor layers and is connected to a pad PD at its end. The pad PD is exposed to the outside on the surface of the semiconductor memory device 3. The pad PD is used to connect the semiconductor memory device 3 to the memory controller 2, etc. Although Figure 27 shows one conductive pillar TP and one pad PD as representative examples, multiple conductive pillars TP and pads PD may be provided.

[0097] The control circuit chip 200 includes a transistor TR. Although Figure 27 shows one transistor TR as representative, multiple transistors TR are provided. The transistor TR constitutes, for example, a low decoder module 16 or a sense amplifier module 17.

[0098] On the surface where the memory chip 100 and the control circuit chip 200 are bonded, the semiconductor memory device 3 includes a plurality of bonding pads BP1 and BP2. The plurality of bonding pads BP1 are formed on the memory chip 100 and are connected via wiring to one of the conductive pillars CGP, SGP, and CP, and conductive pillar TP, etc. The plurality of bonding pads BP2 are formed on the control circuit chip 200 and are connected via wiring to a plurality of transistors TR. The bonding pads BP1 and BP2 include active pads that are connected to elements (wiring) and dummy pads that are not connected to elements. The bonding pads BP1 and BP2 are in contact with each other in the Z direction. In the active pads, each electrically connects to the elements to which it is connected. The bonding pads BP1 and BP2 include, for example, copper (Cu).

[0099] The above structure illustrates the configuration in which the memory chip 100 and the control circuit chip 200 are bonded together.

[0100] According to the second modification of the embodiment, the integration density of the semiconductor memory device can be improved, similar to the embodiment.

[0101] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0102] 1…Memory system 2…Memory controller 3…Semiconductor memory 10…Memory cell array 11…Input / Output Circuits 12…Logic control circuits 13…Register 14… Sequencer 15…Driver module 16… Raw Decoder Module 17…Sense Amp Module 20… Semiconductor substrates 21, 23, 24, 25, 70... Insulating layer 22, 60… Semiconductor layer 26, 27, 63, 64, 65, LBI… Wiring Layers 30... Conductive film 31…Insulator film 32… Functional membrane 33, 34, 35… Block insulating film 36...Charge storage film 37...Tunnel insulating film 38... Conductor 40. INS...Insulator 50… Sacrificial parts 61, 62... conductive layer 66, 67, 68, 69, CPP, MPP… Contact BL...bit line BLK...block BP1, BP2… Adhesive pads CCR… Contact Area CH...Channel CL...Channel Layer CP, GP, CGP, SGP, TP... Conductive pillars CU... Cell Unit DL1, DL2... Diffusion layer LBH, MH, RH, SLH… Hall LB, RP... Insulating pillar LU... Layer Unit MCR…Memory cell region MT...Memory cell transistor NS...NAND string PD... pad PL... Pillar row SGD, SGS... Selectable gate lines SL…Source Line SLR…Source line region ST1, ST2…Selection transistor SU... String Unit TR...Transistor WL...Word line WLSW... Word wire switch

Claims

1. Two first conductive pillars extending in a first direction intersecting the substrate and aligned in a second direction intersecting the first direction, A first semiconductor layer and a second semiconductor layer are provided in a first plane parallel to the substrate, so as to sandwich the two first conductive pillars in a third direction intersecting the first and second directions, A first insulator is provided between the two first conductive pillars, insulating the two first conductive pillars from each other and insulating the first semiconductor layer and the second semiconductor layer in the first plane, In the first plane, two first charge storage films are provided between the two first conductive pillars and the first semiconductor layer, In the first plane, two second charge storage films are provided between the two first conductive pillars and the second semiconductor layer, Equipped with, The portion of the first insulator that contacts the first semiconductor layer and the second semiconductor layer in the first plane is formed in a concentric circular or concentric elliptical shape with its center between the two first conductive pillars. Semiconductor memory device.

2. A third semiconductor layer and a fourth semiconductor layer are provided between the substrate and the first plane, and in a second plane parallel to the substrate, spaced apart from the first semiconductor layer and the second semiconductor layer in the first direction, and sandwiching the two first conductive pillars in the third direction. In the second plane, two third charge storage films are provided between the two first conductive pillars and the third semiconductor layer, In the second plane, two fourth charge storage films are provided between the two first conductive pillars and the fourth semiconductor layer, Furthermore, The first insulator is It includes a first portion having a columnar structure that extends in the first direction while having a tapered shape that narrows from the first plane to the second plane, and a plurality of second portions having a structure that extends radially from the first portion onto the first and second planes at the portion where it intersects with the first and second planes, In the second plane, the third semiconductor layer and the fourth semiconductor layer are in contact with each of them in the third direction and are insulated from each other. The portions in contact with the third semiconductor layer and the fourth semiconductor layer are formed in a concentric circular or concentric elliptical shape with their centers between the two first conductive pillars. The semiconductor memory device according to claim 1.

3. Each of the two first conductive pillars is in contact with the first and second portions of the first insulator in the first plane, and in contact with the second portion of the first insulator but not with the first portion in the second plane. The semiconductor memory device according to claim 2.

4. Two second conductive pillars extending in the first direction and intersecting the first plane, and arranged in the second direction so as to sandwich the two first conductive pillars and the first semiconductor layer in the third direction, A second insulator is provided between the two second conductive pillars and insulates the two second conductive pillars from each other. Two fifth charge storage films are provided between the two second conductive pillars and the first semiconductor layer in the first plane, Furthermore, The portion of the second insulator that contacts the first semiconductor layer in the first plane is formed in a concentric circular or concentric elliptical shape with its center between the two second conductive pillars. The semiconductor memory device according to claim 1.

5. The two first conductive pillars and the two second conductive pillars are arranged in a staggered pattern when viewed in the first direction, with the first semiconductor layer in between, at alternating positions in the third direction. The semiconductor memory device according to claim 4.

6. The two first conductive pillars and the two second conductive pillars are arranged in a grid pattern in the first direction, at substantially the same positions in the third direction, via the first semiconductor layer. The semiconductor memory device according to claim 4.

7. A plurality of first conductive pillars, including the two first conductive pillars, extending in the first direction, aligned in the second direction, and provided so as to be sandwiched in the third direction by the first semiconductor layer and the second semiconductor layer, A plurality of first insulators, each provided between each of the plurality of first conductive pillars, which insulate adjacent plurality of first conductive pillars from each other and insulate the first semiconductor layer and the second semiconductor layer in the first plane, In the first plane, a plurality of first charge storage films, each including the two first charge storage films, are provided between the plurality of first conductive pillars and the first semiconductor layer, In the first plane, a plurality of second charge storage films, each including the two second charge storage films, are provided between the plurality of first conductive pillars and the second semiconductor layer, Furthermore, Each of the plurality of first insulators is formed such that the portion in contact with the first semiconductor layer and the second semiconductor layer in the first plane is formed in a concentric circular or concentric elliptical shape with its center between two adjacent first conductive pillars in the second direction. The plurality of first conductive pillars and the plurality of first insulators are arranged alternately in the second direction, forming a pillar row. The semiconductor memory device according to claim 1.

8. The two first conductive pillars are arranged in the second direction and sandwich the two first conductive pillars in the second direction, and the third conductive pillar and fourth conductive pillar are provided so as to extend in the first direction and be sandwiched in the third direction by the first semiconductor layer and the second semiconductor layer in the first plane, A third insulator is provided between the third conductive pillar and the two first conductive pillars, insulating them from each other and insulating the first semiconductor layer and the second semiconductor layer in the first plane, A fourth insulator is provided between the third conductive pillar and the two first conductive pillars, insulating them from each other and insulating the first semiconductor layer and the second semiconductor layer in the first plane, The semiconductor memory device according to claim 1, further comprising:

9. The first and second semiconductor layers are sandwiched in the second direction, and the first and second semiconductor layers are further provided in contact with the ends of the first and second semiconductor layers in the second direction, The third conductive pillar is in contact with the first diffusion layer, The fourth conductive pillar is in contact with the second diffusion layer, The semiconductor memory device according to claim 8.

10. The first diffusion layer and the second diffusion layer contain silicon doped with donor impurities. The semiconductor memory device according to claim 9.

11. A third semiconductor layer and a fourth semiconductor layer are provided between the substrate and the first plane, and in a second plane parallel to the substrate, spaced apart in the first direction from the first semiconductor layer and the second semiconductor layer, and sandwiching the two first conductive pillars, the third conductive pillar and the fourth conductive pillar in the third direction. In the second plane, two third charge storage films are provided between the two first conductive pillars and the third semiconductor layer, In the second plane, two fourth charge storage films are provided between the two first conductive pillars and the fourth semiconductor layer, A third diffusion layer and a fourth diffusion layer are provided so as to sandwich the third semiconductor layer and the fourth semiconductor layer in the second direction, and are in contact with the ends of the third semiconductor layer and the fourth semiconductor layer in the second direction. A fifth conductive pillar extending in the first direction, intersecting the second diffusion layer in the first plane, and intersecting the fourth diffusion layer in the second plane, Furthermore, The second and fourth diffusion layers are subjected to substantially the same voltage via the fifth conductive pillar. The semiconductor memory device according to claim 9.

12. In the first plane, a first wiring layer having one end in contact with the first diffusion layer, In the second plane, a second wiring layer having one end in contact with the third diffusion layer, Furthermore, The first wiring layer and the second wiring layer are electrically insulated. The semiconductor memory device according to claim 11.

13. Between the first plane and the second plane, there is further an insulating layer extending in the second and third directions and containing the first film type, The insulating layer insulates the first semiconductor layer from the third semiconductor layer, and the second semiconductor layer from the fourth semiconductor layer, respectively. The two first conductive pillars and the first insulator pass through the insulating layer in the first direction. The first insulator includes a second film type different from the first film type. The semiconductor memory device according to claim 2.

14. The second film type includes silicon oxide doped with impurities, The semiconductor memory device according to claim 13.

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