Gate driver circuit for reducing dead time inefficiency

Abstract

A driver circuit (600) includes a first buffer (415) that receives a control signal (VIN 435) and a first transistor (M2) coupled to the first buffer and an output (495). A second transistor (M5) is coupled to a first current mirror (430) and the output. A third transistor (M6) is coupled to the output and an inverter (440). A fourth transistor (M7) receives an output of the inverter at its control input and is coupled to the output. A fifth transistor (M8) is coupled to the third transistor. The second, third, and fifth transistors receive a supply voltage (Vmotor) at their respective control inputs. A sixth transistor (M9) receives an inversion of the control signal at its control input and is coupled to the fifth transistor and a second current mirror (525). A current source (535) is coupled to the second current mirror and a second buffer (540). A seventh transistor (M12) receives an output of the second buffer at its control input and is coupled to the first buffer. An eighth transistor (M13) is coupled to the first buffer and the seventh transistor.

Description

Background Technology

[0001] An H-bridge driver comprises two high-side transistors and two low-side transistors, configured such that each high-side transistor is connected in series with a corresponding low-side transistor, and a load is coupled to a node between the pairs of high-side and low-side transistors. Each pair of high-side and low-side transistors is called a half-bridge. Gate driver circuitry converts control signals into power signals that can efficiently turn each transistor in the H-bridge driver on and off. To prevent shoot-through conditions within the half-bridge during high-to-low or low-to-high transitions, a dead time is inserted between the off state of one transistor and the on state of the other. The length of the dead time is typically equal to the time required to turn the transistor in the half-bridge driver on or off. However, the dead time limits the operating frequency of the H-bridge driver and allows for power dissipation through the transistors in the H-bridge driver.

[0002] Some gate driver circuits reduce power consumption during dead time by turning transistors on and off faster. This can improve the efficiency of H-bridge drivers, but at the cost of generating electromagnetic interference (EMI) in the integrated circuit (IC), disrupting the operation of other circuitry within the IC. Some gate driver circuits balance the need for fast turn-on and turn-off times with controlled EMI by implementing comparators to detect different operating regions of each transistor during turn-on and turn-off, and only accelerating regions less likely to cause EMI. However, these comparators are often expensive, especially for high-side gate drivers that require floating power supplies. Summary of the Invention

[0003] In some embodiments, the driver circuit regulates the drive current during transistor on and off periods based on the operating region of the transistor. The driver circuit includes: a first buffer configured to receive a first control signal; and a first transistor coupled to the output of the first buffer and the output node of the driver circuit. The driver circuit further includes a first current mirror and a second transistor coupled to the first current mirror and the output node. The control input of the second transistor receives a power supply voltage. A third transistor is coupled to the output node and an inverter. The control input of the third transistor also receives a power supply voltage.

[0004] The fourth transistor is coupled to the output node, and its control input receives the inverter output. The fifth transistor is coupled to the third transistor, and its control input receives the supply voltage. The sixth transistor is coupled to the fifth transistor and the second current mirror. Its control input receives a second control signal, which is the inverted version of the first control signal. A current source is coupled to the second current mirror and the second buffer. The seventh transistor is coupled to the first buffer, and its control input receives the output of the second buffer. The eighth transistor is coupled to both the first buffer and the seventh transistor.

[0005] The first transistor is configured to turn off in response to a voltage at the output node exceeding a threshold voltage of the transistor driven by the driver circuit, thereby preventing current from flowing from the buffer through the first transistor to the output node. The third transistor is configured to turn on in response to a voltage at the output node exceeding a power supply voltage at the control input of the third transistor, thereby causing the fourth transistor to turn on and allowing current to flow through the fourth transistor to the output node.

[0006] The fifth transistor is configured to turn off in response to the voltage at the output node being equal to the supply voltage plus the voltage across the third transistor plus the threshold voltage of the fifth transistor, thereby preventing current from flowing from the output node through the fifth transistor. The second current mirror is configured to stop generating current in response to the fifth transistor remaining in the off state. The seventh transistor is configured to turn on in response to the second current mirror not generating current, thereby allowing additional current to flow from the output node through the buffer and the seventh transistor. Attached Figure Description

[0007] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1 An example H-bridge motor driver is shown.

[0009] Figure 2 The diagram illustrates the change in gate-to-source voltage over time for the high-side and low-side transistors in an example H-bridge motor driver.

[0010] Figures 3A to 3B The diagram illustrates the time-varying gate-to-source voltages of the high-side and low-side transistors in an example H-bridge motor driver, and the time-varying voltage at the motor output node.

[0011] Figure 4 Show Figure 1 Example pull-up gate driver circuit of transistors in example H-bridge motor driver.

[0012] Figure 5 Show Figure 1 Example pull-down gate driver circuit of transistors in an example H-bridge motor driver.

[0013] Figure 6 Show Figure 1 Example gate driver circuit of transistors in an example H-bridge motor driver.

[0014] Figure 7The diagram shows the gate-to-source voltage of the transistor in the example H-bridge motor driver, the impedance seen by the example gate driver circuit due to the charge pump protection circuit, the current mirror input to the example gate driver circuit and the current output by the current mirror, and the time variation of the single pulse signal of the charge pump protection circuit. Detailed Implementation

[0015] As described above, some gate driver circuits cause electromagnetic interference (EMI) in circuits (e.g., integrated circuits (ICs), occupy a large area on the IC, or cause power consumption in the corresponding H-bridge driver circuit. The disclosed example gate driver circuit detects different operating regions of each transistor in the corresponding H-bridge driver circuit during turn-on and turn-off, and only accelerates regions unlikely to cause EMI, thereby reducing power consumption in the H-bridge driver circuit. The disclosed example uses specific portions of the gate driver circuit during multiple operating regions and includes only two high-voltage and area-intensive transistors, thereby reducing the total area occupied by the gate driver circuit. In the event of a short circuit, the two high-voltage transistors also protect the corresponding H-bridge driver circuit by automatically disconnecting the H-bridge driver circuit from the charge pump or boost converter that supplies the increased supply voltage to the gate terminals of the transistors in the H-bridge driver circuit.

[0016] The disclosed example gate driver circuit includes a first buffer configured to receive a control signal for a specific transistor in an associated H-bridge driver circuit. The first transistor is coupled to the output of the first buffer and the output node of the gate driver circuit, and provides drive current to the gate terminal of the specific transistor in the associated H-bridge driver circuit during a first operating region, during which the gate-to-source voltage of the specific transistor increases to a threshold voltage of the specific transistor. Once the gate-to-source voltage of the specific transistor increases to the threshold voltage and reaches a plateau, and the drain-to-source voltage of the specific transistor decreases, the first transistor is turned off and no drive current is provided to the gate terminal of the specific transistor.

[0017] The second transistor is coupled to the first current mirror and the output node, and is configured to receive control signals for a specific transistor in the associated H-bridge driver circuitry. During the second operating region, although the gate-to-source voltage of the specific transistor reaches a plateau and the drain-to-source voltage decreases during conduction, the second transistor and the first current mirror provide a carefully controlled drive current to the gate terminal of the specific transistor. The drive current is selected to change the voltage at the output node in the associated H-bridge driver circuitry at a specific rate so that the voltage change generates EMI below a specific threshold associated with the IC and reduces noise supplied to other circuitry on the IC.

[0018] The third transistor is coupled to the output node and the inverter, and is configured to receive a control signal for a specific transistor in the associated H-bridge driver circuit. The fourth transistor is coupled to the output node and the power supply voltage node, and is configured to receive the output of the inverter. When the voltage at the output node is greater than the voltage of the control signal, the third and fourth transistors turn on, and an additional drive current flows from the power supply voltage node through the fourth transistor to the output node of the gate driver circuit and the gate terminal of the specific transistor in the associated H-bridge driver circuit, thus completing the turn-on.

[0019] The fifth transistor is coupled to the third and sixth transistors and is configured to receive a control signal for a specific transistor in the associated H-bridge driver circuit. During the fourth operating region, and when the control signal indicates that a specific transistor should be turned off, a pull-down current flows from the output node through the third and fifth transistors to the sixth transistor and the second current mirror. The sixth transistor is configured to receive the inverted control signal for the specific transistor. During the fifth operating region, as the voltage at the output node approaches the voltage of the control signal, the pull-down current flowing through the third, fifth, and sixth transistors decreases until it stops when the voltage at the output node equals the voltage of the control signal and the threshold voltage of the third and fifth transistors (which are turned off).

[0020] As the pull-down current flowing through the third, fifth, and sixth transistors decreases and stops, an additional pull-down current flows through the first transistor, the first buffer, and the seventh transistor coupled to the first buffer. This current is carefully controlled to change the voltage at the output node of the associated H-bridge driver circuit at a specific rate during the fifth operating region, generating EMI below a specific threshold associated with the IC. When the pull-down current flowing through the third, fifth, and sixth transistors stops, a current source coupled to the second current mirror provides current to the input of the second buffer. The output of the second buffer is coupled to the gate terminal of the eighth transistor, which is coupled to the seventh transistor and the first buffer. When the current source provides current to the second buffer during the sixth operating region, the eighth transistor turns on and increases the pull-down current flowing through the first transistor and the first buffer, thereby turning off the specific transistor in the associated H-bridge driver circuit.

[0021] Figure 1 An example H-bridge motor driver 100 is shown. Although Figure 1An H-bridge implemented as a motor driver is shown, but the H-bridge and gate driver circuit described herein can be used in a variety of applications, including other types of power electronic devices. An example H-bridge motor driver 100 includes high-side power field-effect transistors (FETs) M_H1 and M_H3, and low-side power FETs M_H2 and M_H4. The source terminal of M_H1 is coupled to the drain terminal of M_H2 at node 115, forming a half-bridge configuration. The source terminal of M_H3 is coupled to the drain terminal of M_H4 at node 135, forming another half-bridge configuration. The drain terminals of M_H1 and M_H3 are coupled at node 105 to receive the supply voltage Vmotor. The source terminals of M_H2 and M_H4 are coupled at node 160 to receive a common-mode voltage. In some examples, the common-mode voltage at node 160 is ground. Nodes 115 and 135 form the output nodes of the H-bridge motor driver 100, and load 150 is coupled to nodes 115 and 135.

[0022] The gate terminal of each of M_H1, M_H2, M_H3, and M_H4 is coupled to its respective gate driver circuit. The gate terminal of M_H1 is coupled to receive gate drive current from gate driver circuit 110. The gate terminal of M_H2 is coupled to receive gate drive current from gate driver circuit 120. The gate terminal of M_H3 is coupled to receive gate drive current from gate driver circuit 130. The gate terminal of M_H4 is coupled to receive gate drive current from gate driver circuit 140.

[0023] The H-bridge motor driver 100 includes metal-oxide-semiconductor field-effect transistors (MOSFETs). In this example, M_H1, M_H2, M_H3, and M_H4 are n-type MOSFETs (NMOS). In other examples, one or more of M_H1, M_H2, M_H3, and M_H4 are p-type MOSFETs (PMOS) or bipolar junction transistors (BJTs). A BJT includes a base corresponding to a gate terminal, and collector and emitter corresponding to drain and source terminals. The base of the BJT and the gate terminal of the MOSFET are also referred to as control inputs. The collector and emitter of the BJT and the drain and source terminals of the MOSFET are also referred to as current terminals.

[0024] Figure 2The diagram illustrates the time-varying gate-to-source voltage Vgs_HS 210 of M_H1 and the gate-to-source voltage Vgs_LS 220 of M_H2 in an example H-bridge motor driver 100. To prevent shoot-through current, the switching scheme controlling M_H1 and M_H2 includes a dead time 250, during which neither the high-side transistor M_H1 nor the low-side transistor M_H2 is turned on. This ensures that M_H1 is completely off before M_H2 turns on. As previously mentioned, the dead time 250 slows down the achievable switching frequency of the H-bridge motor driver 100 and increases the power consumed by the H-bridge motor driver 100. To address this issue, some motor drivers increase the slew rate, i.e., the speed at which transistors turn on and off, thereby reducing propagation delay. An increase in slew rate can also increase EMI and create noise that interferes with the operation of other circuitry within the IC. Because EMI affects the operation of other circuitry, some gate driver circuits prioritize slew rate and the IC's EMI requirements over switching frequency.

[0025] Figure 3A The diagram illustrates the time-varying gate-to-source voltage Vgs_HS360 of the high-side transistor M_H1 and the voltage Vnode115370 at node 115 in an example H-bridge motor driver 100. The description is within the context of M_H1 in the H-bridge motor driver 100. Figure 3A However, the high-side transistors M_H3 or other high-side transistors in other H-bridge drivers will experience similar gate-to-source voltages and voltages at the output node. In regions 305-315, the transistor is turned on. In region 320, M_H1 remains on, while in regions 325-335, the transistor is turned off. Region 305 is the transistor on-state, where the gate-to-source capacitance Cgs of M_H1 is charged to the threshold voltage Vth. When Vgs_HS360 is greater than Vth, the transistor conducts current. The ramp rate in region 305 is similar to... Proportional, where Idrive is the current applied to the gate terminal of the transistor, and Cgd is the gate-to-drain capacitance of the transistor.

[0026] Region 310 is referred to as the Miller region, where Vgs_HS 360 remains constant, and Vnode115 370 increases with the charging of Cgd. The time spent in region 310, tSlew, is related to... Proportional. Because region 310 and the added Vnode115 370 can create EMI and noise in other circuits on the IC, tSlew and the corresponding drive current Idrive are determined based on the IC's requirements and the amount of EMI that other circuits on the IC can withstand. Once Cgd is charged, the conductive channel of M_H1 is fully enhanced by applying a higher gate drive voltage and drive current Idrive to the gate terminal in region 315 (referred to as the RDSON enhancement region). The ramp rate in region 315 is proportional to... Proportional. Once Vgs_HS 360 reaches the transistor's turn-on voltage and enters region 320, M_H1 is in the on state.

[0027] When the transistor is off, Vgs_HS 360 decreases as the gate capacitance Cgs + Cgd of M_H1 discharges to the Miller steady-state level in region 325. The gate current is provided by the gate capacitance, and the ramp rate is... Proportional. Once the gate voltage reaches the Miller steady-state level, Vnode115 370 decreases with further discharge of Cgd. The time spent in region 330, tSlew, is proportional to... Proportional. As in region 310, region 330 and the reduced Vnode115 370 can cause EMI and noise in other circuitry on the IC. TSlew and the corresponding drive current are determined based on the IC's requirements and the amount of EMI that other circuitry on the IC can withstand. In region 335, both Cgs and Cgd are discharged to zero volts, thereby reducing Vgs_HS 360 to zero volts and turning off the transistor. Ramp rate and Proportional.

[0028] To improve switching efficiency and optimize each of the three operating regions (on, off, and back), while keeping the EMI generated during switching within the IC's requirements, the drive current Idrive is varied in each operating region. The varied drive current Idrive accelerates the turn-on of transistors in regions 305 and 315 and accelerates the turn-off of transistors in regions 325 and 335, but the turn-on and turn-off rates in regions 310 and 330 are carefully controlled to keep the generated EMI within acceptable limits for the IC.

[0029] Figure 3B The diagram illustrates the variation of the gate-to-source voltage Vgs_LS380 of the low-side transistor M_H4 and the voltage Vnode135390 at node 135 over time in the example H-bridge motor driver 100. The description is within the context of M_H4 in the H-bridge motor driver 100. Figure 3BHowever, the low-side transistor M_H2 or other low-side transistors in the H-bridge driver will experience similar gate-to-source voltages and voltages at the output node. Just like in... Figure 3A Similar to the previous example, regions 305-315 correspond to transistor conduction. In region 320, M_H4 remains in the conduction state, while in regions 325-335, the transistor is off. Region 305 is the transistor conduction region, where the gate-to-source capacitance Cgs of M_H4 is charged to the threshold voltage Vth. When Vgs_LS 380 is greater than Vth, the transistor conducts current. The ramp rate in region 305 is... Proportional, where Idrive is the current applied to the gate terminal of the transistor, and Cgd is the gate-to-drain capacitance of the transistor.

[0030] Region 310 is called the Miller region, where Vgs_LS 380 remains constant, and Vnode135 390 decreases as Cgd is charged. The time spent in region 310, tSlew, is related to... Proportional. Since region 310 and the reduced Vnode135 390 can create EMI and noise in other circuitry on the IC, tSlew and the corresponding drive current Idrive are determined based on the IC's requirements and the amount of EMI that other circuitry on the IC can withstand. Once Cgd is charged, the conductive channel of M_H4 is fully enhanced by applying a higher gate drive voltage and drive current Idrive to the gate terminal in region 315 (referred to as the RDSON enhancement region). The ramp rate in region 315 is proportional to... Proportional. Once Vgs_LS 380 reaches the transistor's turn-on voltage and enters region 320, M_H4 is in the turn-on state.

[0031] To improve switching efficiency and optimize each of the three operating regions (on, off, and back), while keeping EMI during switching within the IC's requirements, the drive current Idrive varies in each operating region, such as... Figure 3A The same applies to transistor M_H1 in the IC. The varying drive current Idrive accelerates the turn-on of transistors in regions 305 and 315 and accelerates the turn-off of transistors in regions 325 and 335, but the turn-on and turn-off speeds in regions 310 and 330 are carefully controlled to keep the created EMI within acceptable limits for the IC.

[0032] Figure 4 Showing the use of Figure 1Example pull-up gate driver circuit 400 is shown in the example H-bridge motor driver 100. Pull-up gate driver circuit 400 is shown in relation to M_H1 and gate driver circuit 110, but can also be used in gate driver circuits 120, 130, and 140. Pull-up gate driver circuit 400 includes NMOS transistors M1 and M2, PMOS transistors M_A, M3, M4, M5, M6, and M7, and inverters 415 and 440. In other examples, one or more of M1 and M2 are PMOS transistors, and one or more of M_A, M3, M4, M5, M6, and M7 are NMOS transistors. In other examples, one or more of M1, M2, M_A, M3, M4, M5, M6, and M7 are bipolar junction transistors.

[0033] Inverter 415 is configured to receive control signal VIN 435 and is coupled to the gate terminal of M_A. The source terminal of M_A is coupled to receive the supply voltage Vsupply at node 450, and the drain terminal of M_A is coupled to the source terminal of M2. In some examples, Vsupply is equal to Vmotor and equal to 5V. In this example, the gate terminal of M2 is configured to receive a bias voltage equal to twice the threshold voltage Vth of M_H1. The drain terminal of M2 is coupled to the output node 495 of the pull-up gate driver circuit 400. When VIN 435 indicates that M_H1 should be turned on, a logic low signal is applied to the gate terminal of M_A, causing M_A to turn on. M_A acts as a closed switch and allows the drive current Idrive to flow from the supply voltage at node 450 through M2 to the output node 495 during region 305 and through extension to the gate terminal of M_H1. When the voltage at output node 495 is approximately Vth, M2 enters the cutoff region, thus acting as an open switch and disconnecting M_A and current from node 450 from output node 495. This transitions the Vgs_HS 360 of M_H1 from region 305 to region 310.

[0034] The gate terminal of M1 is configured to receive VIN 435. The drain terminal of M1 is connected at node 425 to the drain terminal and gate terminal of M3 and the gate terminal of M4. The source terminal of M1 is connected to a charge pump protection circuit 460, which is configured to prevent the charge pump or boost converter coupled to node 405 from failing in the event of a short circuit at node 115. The source terminals of M3 and M4 are coupled to node 405 and are configured to receive the charge pump or boost converter voltage Vboost. M3 and M4 serve as a current mirror 430. The drain terminal of M4 is coupled to the source terminal of M5. The gate terminal of M5 is configured to receive Vmotor, and the drain terminal of M5 is coupled to the output node 495. During region 310, the current mirror 430 and M5 provide a drive current Idrive from the charge pump or boost converter to the output node 495.

[0035] The gate terminal of M6 is configured to receive Vmotor, and its drain terminal is coupled to output node 495. The source terminal is coupled to the input of inverter 440. Inverter 440 is coupled to the gate terminal of M7. The source terminal of M7 is coupled to node 405 and configured to receive the charge pump or boost converter voltage Vboost. The drain terminal of M7 is coupled to output node 495. During region 310, the voltage at output node 495 of M6's drain terminal is compared with Vmotor applied to its gate terminal. When the voltage at output node 495 exceeds Vmotor, M6 turns on, and the source terminal of M6 has the same voltage as the voltage at output node 495, resulting in a logic high input to inverter 440. Inverter 440 converts the logic high signal to a logic low signal and applies it to the gate terminal of M7, causing M7 to turn on and act as a closed switch. This ends region 310 and transitions Vgs_HS 360 to region 315. M7 allows additional current to flow from Vboost at node 405 to output node 495, thereby increasing the drive current Idrive applied to the gate terminal of M_H1. When Vgs_HS360 reaches the turn-on voltage of M_H1, the pull-up of M_H1 is complete and M_H1 turns on.

[0036] Figure 5 Showing the use of Figure 1Example pull-down gate driver circuit 500 is shown in the example H-bridge motor driver 100. Pull-down gate driver circuit 500 is shown in relation to M_H1 and gate driver circuit 110, but it can also be used in gate driver circuits 120, 130, and 140. Pull-down gate driver circuit 500 includes NMOS transistors M2, M9, M10, M11, M12, and M13, and PMOS transistors M_B, M_C, and M8, as well as diode 505, current source 535, and buffer 540. In other examples, one or more of M2, M9, M10, M11, M12, and M13 are PMOS transistors, and one or more of M_B, M_C, and M8 are NMOS transistors. In other examples, one or more of M2, M_B, M_C, M8, M9, M10, M11, M12, and M13 are bipolar junction transistors.

[0037] M_C is coupled to node 405 and output node 495 and is configured to receive a voltage that biases it to the off state and acts as a disconnect switch, thereby disconnecting Vboost at node 405 from output node 495. Diode 505 is coupled to output node 495 and the source terminal of M8. The gate terminal of M8 is configured to receive Vmotor, and the drain terminal of M8 is coupled at node 510 to the drain terminals of M_B and M9. The gate terminal of M_B is configured to receive the voltage at node 115, and the source terminal of M_B is coupled to output node 495. The gate terminal of M9 is configured to receive... VIN435, and the source terminal of M9 is coupled at node 520 to the gate terminals of M10 and M11, as well as the drain terminal of M10. The source terminals of M10 and M11 are coupled to common-mode node 455. The drain terminal of M11 is coupled at node 530 to the output of current source 535 and the input of buffer 540. M10 and M11 serve as current mirror 525. The output of buffer 540 is coupled to the gate terminal of M12.

[0038] The drain terminal of M2 is connected to the drain terminal of M_C at output node 495, and the source terminal of M2 is connected to the drain terminals of M12 and M13 at node 515. The gate terminal of M2 is configured to receive a bias voltage to keep it on and act as a closed switch, which in this example is twice the threshold voltage of M_H1. The source terminals of M12 and M13 are coupled to common-mode node 455. Charge pump protection circuit 460 biases the gate terminal of M13 as a current source. The gate terminal of M12 is coupled to the output of buffer 540. During off-time, the gate terminal of M13 receives a signal that biases M13 to keep it on and act as a closed switch. This creates a path for the Ipulldown current to flow through M2 and M13 to common-mode node 455.

[0039] When VIN 435 indicates that M_H1 should be turned off, the Ipulldown current flows through M2 and M13 to the common-mode node 455, and the Istrong current flows through diodes 505, M8, M9, and M10 to the common-mode node 455, thereby reducing Vgs_HS 360 during region 325. While the Istrong current flows through M10 in the current mirror 525, M11 acts as a closed switch, causing current to flow from current source 535 through M11 to the common-mode node 455. This results in a logic low voltage input to node 530 of buffer 540. This logic low signal is provided to the gate terminal of M12, keeping it off and acting as an open switch.

[0040] When the voltage at output node 495 approaches Vmotor + Vth + the voltage across diode 505, the Istrong current flowing through M8 approaches zero, and the Ipulldown current remains stable. This provides a substantially constant pull-down current to the gate terminals of output node 495 and M_H1, allowing the voltage at node 115 to decrease at a rate suitable for the IC's EMI requirements, and causing Vgs_HS 360 to transition from region 325 to region 330. When Vgs_HS 360 decreases below Vmotor + Vth + the voltage across diode 505, it has transitioned from region 330 to region 335, and M8 is turned off, acting as an open switch so that no current flows through M9 to current mirror 525. This allows the voltage at node 530 to increase, and allows current source 535 to supply its current to the input of buffer 540. This causes the input to buffer 540 and the output from buffer 540 to become logic high. A logic high signal is provided to the gate terminal of M12, causing it to conduct and act as a closed switch. This creates another path for current flow, thereby increasing the Ipulldown current and accelerating the decrease of Vgs_HS 360 during region 335. When Vgs_HS 360 reaches zero volts, M_H1 is completely turned off.

[0041] Figure 6 Show Figure 1Example gate driver circuit 600 for transistors in example H-bridge motor driver 100 combines features of pull-up gate driver circuit 400 and pull-down gate driver circuit 500. Gate driver circuit 600 is shown in relation to M_H1 and gate driver circuit 110, but can also be used in gate driver circuits 120, 130, and 140. Gate driver circuit 600 includes NMOS transistors M1, M2, M9, M10, M11, M12, and M13, and PMOS transistors M3, M4, M5, M6, M7, and M8, as well as inverter 440, current source 535, and buffers 615 and 540. Only M6 and M7 are high-voltage PMOS transistors with high gate capacitance, occupying a relatively large area on the IC. The remaining transistors are small, low-power FETs. In other examples, one or more of M1, M2, M9, M10, M11, M12, and M13 are PMOS transistors, and one or more of M3, M4, M5, M6, M7, and M8 are NMOS transistors. In other examples, one or more of M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, and M13 are bipolar junction transistors.

[0042] Buffer 615 is configured to receive VIN 435 and is coupled to the source terminal of M2 and the drain terminal of M13. In this example, buffer 615 includes a complementary MOSFET inverter. Inverter 420 is configured to receive VIN 435 and is coupled to the gate terminal of PMOS transistor M_Inv1 and the gate terminal of NMOS transistor M_Inv2. The source terminal of M_Inv1 is coupled to the supply voltage Vsupply, which in some examples is equal to Vmotor and equal to 5V. The drain terminal of M_Inv1 is coupled to the drain terminal of M_Inv2. The source terminal of M_Inv2 is coupled to the drain terminal of M13 at node 515. The source terminal of M2 is coupled to the drain terminals of both M_Inv1 and M_Inv2. In the gate driver circuit 600, M_Inv1 is... Figure 4 In the pull-up gate driver circuit 400, it acts as M_A.

[0043] In this example, the gate terminal of M2 is configured to receive a bias voltage equal to twice the threshold voltage Vth of M_H1, and the drain terminal of M2 is coupled to the output node 495 of the gate driver circuit 600. When VIN 435 indicates that M_H1 should be turned on, the buffer 615 allows the drive current Idrive to flow from the supply voltage through M_Inv1 and M2 to the output node 495 during region 305, and then through an extension to the gate terminal of M_H1. When the voltage at the output node 495 is approximately Vth, M2 is turned off, thus acting as an open switch and disconnecting the buffer 615 and the current from its supply from the output node 495. This transitions the Vgs_HS 360 of M_H1 from region 305 to region 310.

[0044] The gate terminal of M1 is configured to receive VIN435. The drain terminal of M1 is connected at node 425 to the drain terminal and gate terminal of M3 and the gate terminal of M4. The source terminal of M1 is connected to a charge pump protection circuit 460, which is configured to prevent the charge pump or boost converter coupled to node 405 from failing in the event of a short circuit at node 115. The source terminals of M3 and M4 are coupled to node 405 and configured to receive the charge pump or boost converter voltage Vboost. M3 and M4 serve as a current mirror 430. The drain terminal of M4 is coupled to the source terminal of M5. The gate terminal of M5 is configured to receive Vmotor, and the drain terminal of M5 is coupled to the output node 495. During region 310, the current mirror 430 and M5 provide a drive current Idrive to the output node 495.

[0045] The gate terminal of M6 is configured to receive Vmotor, and the drain terminal of M6 is coupled to output node 495. The source terminal is coupled to the input of inverter 440 at node 605. Inverter 440 is coupled to the gate terminal of M7. The source terminal of M7 is coupled to node 405 and configured to receive the charge pump or boost converter voltage Vboost. The drain terminal of M7 is coupled to output node 495. During region 310, the voltage at the output node 495 of M6's drain terminal is compared with Vmotor applied to its gate terminal.

[0046] When the voltage at output node 495 exceeds Vmotor, M6 turns on, and the current from the source terminal input of M6 to inverter 440 becomes logic high. Inverter 440 converts the logic high signal to a logic low signal and applies a logic low signal to the gate terminal of M7, causing M7 to turn on and act as a closed switch. This ends region 310 and transitions Vgs_HS360 to region 315. M7 allows additional current to flow from Vboost at node 405 to output node 495, thereby increasing the drive current Idrive applied to the gate terminal of M_H1 and accelerating the increase of Vgs_HS360 during region 315. When Vgs_HS360 reaches the turn-on voltage of M_H1, the pull-up of M_H1 is complete, and M_H1 turns on.

[0047] M_H1 is kept on by M7 during region 320, and M7 maintains Vboost at output node 495. In the event of a short circuit at node 115, the voltage at the drain terminals of output node 495 and M6 will decrease rapidly, causing M6 to turn off and the input to inverter 440 to be logic low. Inverter 440 converts the logic low signal to a logic high signal and applies it to the gate terminal of M7, causing M7 to turn off. This causes M7 to act as a disconnect switch and disconnects the charge pump from output node 495 and the short circuit. Any short-circuit current from the charge pump before M7 disconnects it from output node 495 is absorbed by Zener diode 165 in the H-bridge motor driver circuit 100, which is connected to the gate and source terminals of M_H1. M_H2, M_H3, and M_H4 each have Zener diode 165 coupled to their respective gate and source terminals.

[0048] At node 605, the source terminal of M8 is coupled to the source terminal of M6 and also to the input of inverter 440. In gate driver circuit 600, M6 acts as diode 505 in pull-down gate driver circuit 500. The gate terminal of M8 is configured to receive Vmotor, and the drain terminal of M8 is coupled to the drain terminal of M9 at node 510. The gate terminal of M9 is configured to receive Vmotor. VIN 435, and the source terminal of M9 is coupled at node 520 to the gate terminals of M10 and M11, as well as the drain terminal of M10. The source terminals of M10 and M11 are coupled to common-mode node 455. The drain terminal of M11 is coupled at node 530 to the output of current source 535 and the input of buffer 540. M10 and M11 serve as current mirror 525.

[0049] The drain terminals of M12 and M13 are coupled to the source terminal of M_Inv2 at node 515, and the source terminals of M12 and M13 are coupled to the common-mode node 455. The gate terminal of M13 is coupled to the shoot-through protection circuit 460. The gate terminal of M12 is coupled to the output of buffer 540. During the off period, the gate terminal of M13 receives a signal that biases it to conduct and acts as a closed switch. This creates a path for the Ipulldown current from the output node 495 to the common-mode node 455.

[0050] When VIN 435 indicates that M_H1 should be turned off, the Ipulldown current flows through M2, M_Inv2, and M13 to the common-mode node 455, and the Istrong current flows through M6, M8, M9, and M10 to the common-mode node 455, thereby reducing Vgs_HS 360 during region 325. In the gate driver circuit 600, M_Inv2 acts as M_B in the pull-down gate driver circuit 500, and M6 acts as diode 505 in the pull-down gate driver circuit 500. When the Istrong current flows through M10 in the current mirror 525, M11 acts as a closed switch and causes current from the current source 535 to flow through M11 to the common-mode node 455. This causes the voltage input to node 530 of the buffer 540 to become a logic low signal. This logic low signal is provided to the gate terminal of M12, thereby keeping it in the off state and acting as an open switch.

[0051] When the voltage at output node 495 approaches Vmotor plus Vth, the Istrong current flowing through M8 approaches zero, while the Ipulldown current remains stable. This provides a substantially constant drive current to the gate terminals of output node 495 and M_H1, allowing the voltage at node 115 to decrease at a rate suitable for the IC's EMI requirements, and causing Vgs_HS 360 to transition from region 325 to region 330. When Vgs_HS 360 decreases below Vmotor plus Vth, it has transitioned from region 330 to region 335, and M8 transitions to the cutoff region, acting as an open switch, resulting in zero Istrong current and no current flowing through M9 to current mirror 525. This allows current source 535 to supply current to the input of buffer 540, resulting in a logic high signal at the input to buffer 540 and the output from buffer 540. The logic high signal is provided to the gate terminal of M12, causing it to conduct and act as a closed switch. This provides an alternative path for current flow, thereby increasing the Ipulldown current and accelerating the decrease of Vgs_HS 360 during region 335. When Vgs_HS 360 reaches zero volts, M_H1 is completely cut off.

[0052] The gate driver circuit 600 is area-efficient because it comprises only two large-area high-voltage transistors, M6 and M7. The reuse of M2 in pull-up regions 305 and pull-down regions 325-335, and the reuse of M6 as a comparator in regions 315 and 325, reduce the area requirement of the gate driver circuit 600 while allowing it to detect the operating region and increase or decrease the drive current Idrive accordingly. With M_H1 on and off and the corresponding dead time, the varying drive current Idrive reduces propagation delay without generating problematic EMI or interrupting the operation of other circuitry in the IC.

[0053] As previously discussed, the gate driver circuit 600 receives two inputs from the charge pump protection circuit 460. One input is supplied to the source terminal of M1 during region 310 and increases the current supplied by the current mirror 430. The other input is supplied to the gate terminal of M13 during the off period and biases M13 to conduct and act as a closed switch. Figure 7 The diagram shows Vgs_HS 360 as a function of time, the impedance 710 seen from the charge pump protection circuit 460 at the source terminal of M1, the current 720 input to and output from the current mirror 430, and the single pulse signal 730 from the charge pump protection circuit 460 applied to the gate terminal of M13.

[0054] During regions 305 and 315, the impedance 710 from the charge pump protection circuit 460 is greater than the impedance during region 310. The reduced impedance 710 in region 310 increases the current 720 input to the current mirror 430 and output by the current mirror 430. This increased current 720 is solely responsible for the drive current supplied to the output node 495 during region 310 and is selected such that its slew rate meets the IC's EMI requirements. Increasing and maintaining the increased impedance 710 before and after region 310 reduces the current drawn from the charge pump. As previously stated, in the event of a short circuit at node 115, M6 and M8 automatically disconnect the charge pump from the output node 495, while the increased impedance from the charge pump protection circuit 460 carefully controls the current 720 drawn from the charge pump via the current mirror 430, thereby preventing charge pump failure.

[0055] In some charge pump protection circuits, a single-pulse signal 730 is applied to the gate terminals of one or more transistors within the charge pump protection circuit. During region 310, the single-pulse signal 730 is logic high, causing one or more transistors within the charge pump protection circuit to turn on and act as closed switches, thereby reducing the impedance 710 from the charge pump protection circuit 460. This also causes M13 to act as a closed switch, as M_Inv2 is off and acts as an open switch, thus disconnecting M13 from the output node 495. During regions 325-335, the single-pulse signal 730 is logic high, biasing M13 to turn on and act as a closed switch. M_Inv2 is also on and acts as a closed switch. This creates a path for the Ipulldown current. Although this also reduces the impedance 710 from the charge pump protection circuit 460, M1 is off and acts as an open switch, so no additional current 720 is drawn from the charge pump.

[0056] In this specification, the term "coupled" refers to an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connections. The statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0057] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are also possible.

Claims

1. A pull-up driver circuit, comprising: A first sub-circuit, configured to control the drive current output by the pull-up driver circuit through the output node during a first operating region, includes: The first inverter, and A first transistor, which is coupled to the first inverter and the output node; A second sub-circuit, configured to control the drive current during a second operating region, includes: The second transistor, coupled to the current mirror, and A third transistor, coupled to the current mirror and the output node; and A third sub-circuit, configured to control the drive current during a third operating region, includes: The fourth transistor, coupled to the second inverter and the output node, and The fifth transistor is coupled to the second inverter and the output node. The second sub-circuit further includes a sixth transistor coupled between the first inverter and the first transistor.

2. The pull-up driver circuit according to claim 1, wherein, The first transistor is configured to turn off in response to a voltage at the output node that is greater than a threshold voltage of the transistor driven by the pull-up driver circuit.

3. The pull-up driver circuit according to claim 1, wherein, The second sub-circuit is configured to control the drive current such that electromagnetic interference caused by the transistor driven by the pull-up driver circuit is less than a threshold.

4. The pull-up driver circuit according to claim 1, wherein, The fourth transistor is configured to receive a power supply voltage and is further configured to turn on in response to a voltage at the output node being greater than the power supply voltage.

5. A pull-down driver circuit, comprising: A first sub-circuit, configured to generate the drive current output by the pull-down driver circuit through the output node during a first operating region and a second operating region, includes: A diode, coupled to the output node and the first transistor, and A second transistor is coupled to the first transistor and the current mirror; A second sub-circuit, configured to generate the drive current during the first, second, and third operating regions, includes: A third transistor, coupled to the output node and a fourth transistor; and A third sub-circuit, configured to generate the drive current during the third operating region, includes: A current source, coupled to the current mirror and the buffer, and A fifth transistor, coupled to the third and fourth transistors, is configured to receive the output of the buffer.

6. The pull-down driver circuit according to claim 5, wherein, The first sub-circuit is configured to reduce the generated drive current in response to the voltage at the output node being within a specified range of the power supply voltage plus the voltage across the diode plus the threshold voltage of the first transistor.

7. The pull-down driver circuit according to claim 5, wherein, The first sub-circuit is configured to stop generating drive current in response to the voltage at the output node being equal to the power supply voltage plus the voltage across the diode plus the threshold voltage of the first transistor.

8. The pull-down driver circuit according to claim 7, wherein, The first transistor is configured to receive the power supply voltage, and is further configured to turn off in response to the voltage at the output node being equal to the power supply voltage plus the voltage across the diode plus the threshold voltage of the first transistor.

9. The pull-down driver circuit according to claim 5, wherein, The current mirror is configured to stop generating current in response to the first sub-circuit not generating drive current.

10. The pull-down driver circuit according to claim 9, wherein, The fifth transistor is configured to turn on in response to the current mirror not generating current.

11. A driver circuit comprising: A first buffer, configured to receive a first control signal; A first transistor coupled to the output node of the driver circuit, wherein the current terminal of the first transistor is configured to receive the output of the first buffer; First current mirror; A second transistor is coupled to the first current mirror and the output node, wherein the control input of the second transistor is configured to receive a power supply voltage; A third transistor, coupled to the output node and the inverter, wherein the control input of the third transistor is configured to receive the power supply voltage; A fourth transistor coupled to the output node, wherein the control input of the fourth transistor is configured to receive the output of the inverter; A fifth transistor coupled to the third transistor, wherein the control input of the fifth transistor is configured to receive the power supply voltage; A sixth transistor coupled to the fifth transistor and the second current mirror, wherein the control input of the sixth transistor is configured to receive a second control signal, and wherein the second control signal is the inverse of the first control signal; A current source, which is coupled to the second current mirror and the second buffer; A seventh transistor, coupled to the first buffer, wherein the control input of the seventh transistor is configured to receive the output of the second buffer; and The eighth transistor is coupled to the first buffer and the seventh transistor.

12. The driver circuit according to claim 11, wherein, The first transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-type metal-oxide-semiconductor field-effect transistors, and the second transistor, the third transistor, the fourth transistor, and the fifth transistor are p-type metal-oxide-semiconductor field-effect transistors.

13. The driver circuit according to claim 11, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are bipolar junction transistors.

14. The driver circuit according to claim 11, wherein, The control input of the eighth transistor is configured to receive a third control signal from a charge pump protection circuit configured to prevent charge pump failure.

15. The driver circuit according to claim 11, wherein, The first current mirror includes a ninth transistor and a tenth transistor coupled to the ninth transistor.

16. The driver circuit according to claim 15, wherein, The current terminals of the ninth transistor and the tenth transistor are coupled to the power supply voltage node.

17. The driver circuit according to claim 15, wherein, The ninth transistor and the tenth transistor are bipolar junction transistors.

18. The driver circuit according to claim 15, wherein, The ninth transistor and the tenth transistor are p-type metal-oxide-semiconductor field-effect transistors.

19. The driver circuit of claim 15, further comprising an eleventh transistor coupled to the first current mirror and charge pump protection circuit, wherein, The control input of the eleventh transistor is configured to receive the first control signal, and wherein the current terminal of the eleventh transistor is coupled to the control input of the ninth transistor and the control input of the tenth transistor.

20. The driver circuit according to claim 19, wherein, The current output by the first current mirror varies based on the impedance from the charge pump protection circuit.

21. The driver circuit according to claim 11, wherein, The second current mirror includes a twelfth transistor and a thirteenth transistor coupled to the twelfth transistor.

22. The driver circuit according to claim 21, wherein, The twelfth and thirteenth transistors are bipolar junction transistors.

23. The driver circuit according to claim 21, wherein, The twelfth and thirteenth transistors are n-type metal-oxide-semiconductor field-effect transistors.

24. The driver circuit according to claim 11, wherein, The current terminal of the fourth transistor is coupled to the power supply voltage node.

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