Semiconductor equipment

Abstract

This aims to suppress the increase in the planar size of semiconductor devices while improving their reliability. [Solution] The semiconductor device 100 comprises an n-type semiconductor substrate, a seal ring wiring SL1 formed in an annular shape to surround regions 1A and 3A of the semiconductor substrate in a plan view, and a p-type impurity region PA formed in the semiconductor substrate. The impurity region PA is provided between region 1A and region 3A so as to extend to a position that overlaps with the seal ring wiring SL1 in a plan view. Ground potential is supplied to the impurity region PA.

Description

[Technical Field] 【0001】 This invention relates to a semiconductor device. [Background technology] 【0002】 A semiconductor device has been developed that integrates two output power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and a control circuit for controlling the operation of each of the two output power MOSFETs. For example, Patent Document 1 discloses an IPD (Intelligent Power Device) as such a semiconductor device. 【0003】 The semiconductor device described in Patent Document 1 comprises a first region where one output power MOSFET is formed, a second region where the other output power MOSFET is formed, and a third region where a MOSFET for the control circuit is formed. 【0004】 Furthermore, Patent Document 1 also discloses the following problems: A high potential higher than the drain potential may be applied to the source electrode constituting the output terminal of the power MOSFET in the first region as electrical noise from outside the semiconductor device. In this case, a parasitic current flows from the p-type body region of the first region to the n-type semiconductor substrate. At this time, a leakage current flows from the p-type body region of the first region to the p-type body region of the second region as part of the parasitic current. In addition, a leakage current also flows from the p-type body region of the first region to the p-type well region of the third region. 【0005】 Such leakage currents can cause malfunctions in the power MOSFETs in the second region and the MOSFETs in the third region. [Prior art documents] [Patent Documents] 【0006】 [Patent Document 1] Japanese Patent Publication No. 2015-88617 [Overview of the Initiative] [Problems that the invention aims to solve] 【0007】 Patent Document 1 describes how p-type impurity regions are formed in a semiconductor substrate to absorb the leakage current described above. These p-type impurity regions are located between the first and second regions, between the first and third regions, and between the second and third regions. By connecting the battery potential (drain potential) to the p-type impurity regions, the leakage current is absorbed into the p-type impurity regions. This suppresses malfunctions in the power MOSFETs of the second region and the MOSFETs of the third region. 【0008】 In recent IPDs (Integrated Processing Units), the miniaturization of semiconductor devices has been accelerated, and the requirements for suppressing leakage current have become stricter. To further suppress leakage current and improve the reliability of semiconductor devices, for example, it is conceivable to create p-type impurity regions surrounding the first, second, and third regions in a plan view. However, in that case, the planar area required to create the p-type impurity regions increases, increasing the planar size of the semiconductor device, which makes it difficult to promote miniaturization of the semiconductor device. Therefore, there is a need for a technology that can suppress the increase in the planar size of the semiconductor device while suppressing leakage current and improving the reliability of the semiconductor device. 【0009】 Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem] 【0010】 A brief overview of some of the representative embodiments disclosed in this application is as follows: 【0011】 In one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a seal ring wiring formed in an annular shape so as to surround a first region and a second region of the semiconductor substrate in a plan view, and an impurity region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type. The impurity region is provided between the first region and the second region so as to extend to a position overlapping with the seal ring wiring in a plan view. A ground potential is supplied to the impurity region. 【0012】 In one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a seal ring wiring formed in an annular shape so as to surround a first region and a second region of the semiconductor substrate in a plan view, and an impurity region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type. The impurity region is provided between the first region and the second region and between the seal ring wiring and a part of the second region. A ground potential is supplied to the impurity region. 【Effects of the Invention】 【0013】 According to one embodiment, an increase in the planar size of the semiconductor device can be suppressed, and the reliability of the semiconductor device can be improved. 【Brief Description of the Drawings】 【0014】 [Figure 1] FIG. 1 is a plan view showing a semiconductor device in Embodiment 1. [Figure 2] FIG. 2 is a plan view showing a semiconductor device in Embodiment 1. [Figure 3] FIG. 3 is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 4] FIG. 4 is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 5] FIG. 5 is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 6] FIG. 6 is a cross-sectional view showing parasitic current and leakage current generated in Embodiment 1. [Figure 7] Figure 7 is a plan view showing the semiconductor device in the modified example 1. [Figure 8] Figure 8 is a plan view showing the semiconductor device in the modified example 2. [Figure 9] Figure 9 is a plan view showing the semiconductor device in modified example 3. [Figure 10] Figure 10 is a plan view showing the semiconductor device in modified example 4. [Figure 11] Figure 11 is a plan view showing the semiconductor device in the modified example 5. [Figure 12] Figure 12 is a cross-sectional view showing a semiconductor device in modified example 5. [Figure 13] Figure 13 is a plan view showing the semiconductor device in Embodiment 2. [Figure 14] Figure 14 is a plan view showing the semiconductor device in the example under consideration. [Modes for carrying out the invention] 【0015】 The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary. 【0016】 Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, depth direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction. 【0017】 (Embodiment 1) <Structure of a semiconductor device> The structure of the semiconductor device (semiconductor chip) 100 in Embodiment 1 will be described below with reference to Figures 1 to 5. Figure 1 is a plan view showing the semiconductor device 100. Figure 2 is a plan view showing the wiring layer above that shown in Figure 1. Figure 3 shows a cross-sectional view along line AA shown in Figures 1 and 2. Figure 4 shows a cross-sectional view along line BB shown in Figures 1 and 2. Figure 5 shows a cross-sectional view along line CC shown in Figures 1 and 2. 【0018】 As shown in Figure 1, the semiconductor device 100 comprises region 1A, region 2A located next to region 1A, and region 3A located next to both region 1A and region 2A. Furthermore, as shown in Figures 3, 4, and 5, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. As shown in Figures 3 and 4, a plurality of n-type power MOSFETs 1Q are formed in the region of the semiconductor substrate SUB corresponding to region 1A (first region). As shown in Figure 3, a plurality of n-type power MOSFETs 2Q are formed in the region of the semiconductor substrate SUB corresponding to region 2A (second region). In addition, the semiconductor device 100 includes a control circuit for controlling the operation of each of the plurality of power MOSFETs 1Q and the plurality of power MOSFETs 2Q. As shown in Figure 4, a plurality of p-type MOSFETs 3Q and a plurality of n-type MOSFETs 4Q, which constitute part of the control circuit, are formed in the region of the semiconductor substrate SUB corresponding to region 3A (third region). 【0019】 As shown in Figures 3, 4, and 5, the semiconductor device 100 comprises a plurality of wirings M1 formed on top of the semiconductor substrate SUB, a plurality of wirings M2 formed on top of the plurality of wirings M1, and a plurality of wirings M3 formed on top of the plurality of wirings M2. 【0020】 Multiple wirings M1 include absorption wirings AW1 and seal ring wirings SL1. Figure 1 shows the absorption wirings AW1 and seal ring wirings SL1. In a plan view, the seal ring wirings SL1 are formed in an annular shape so as to surround region 1A (i.e., the first region of the semiconductor substrate SUB), region 2A (i.e., the second region of the semiconductor substrate SUB), and region 3A (i.e., the third region of the semiconductor substrate SUB). Although not shown here, seal ring wirings SL2 and SL3, which are electrically connected to the seal ring wirings SL1, are also formed in annular shapes so as to surround regions 1A, 2A, and 3A in a plan view. 【0021】 Absorption regions PA are formed in the semiconductor substrate SUB as p-type impurity regions. Absorption regions PA are provided between region 1A and region 2A, between region 1A and region 3A, and between region 2A and region 3A. Furthermore, absorption regions PA extend to a position where they overlap with the seal ring wiring SL1 in a plan view. In addition, in Embodiment 1, absorption regions PA also overlap with the portion of the seal ring wiring SL1 that surrounds regions 1A and 2A in a plan view. 【0022】 Although not shown in the diagram here, the absorption region PA extends to a position where it overlaps with the seal ring wirings SL2 and SL3, which are located above the seal ring wiring SL1. Furthermore, in a plan view, the absorption region PA also overlaps with the portions of the seal ring wirings SL2 and SL3 that surround regions 1A and 2A. 【0023】 The absorption wiring AW1 is formed on the absorption region PA and is electrically connected to the absorption region PA. In a plan view, the absorption wiring AW1 is provided between region 1A and region 2A, between region 1A and region 3A, and between region 2A and region 3A, so as to cover a portion of the absorption region PA. The absorption wiring AW1 is separate from the seal ring wiring SL1. 【0024】 The absorption region PA is supplied with ground potential via the absorption wiring AW1. As will be described later, the seal ring wiring SL1 is electrically connected to the drain electrode DE via the semiconductor substrate SUB. Therefore, the drain potential is supplied to the seal ring wiring SL1. The absorption region PA and the absorption wiring AW1 are electrically isolated from the seal ring wiring SL1. 【0025】 Figure 2 shows several wirings M3, including the seal ring wiring SL3, source electrode SE1, source electrode SE2, multiple pads PAD, and multiple absorption wirings AW3. Source electrode SE1 is electrically connected to the source region NS and body region PB of power MOSFET 1Q. Source electrode SE2 is electrically connected to the source region NS and body region PB of power MOSFET 2Q. The multiple pads PAD are electrically connected to MOSFETs 3Q and 4Q. 【0026】 External connection members are connected to the upper surfaces of each of the seal ring wiring SL3, source electrode SE1, source electrode SE2, multiple pads PAD, and multiple absorption wiring AW3, thereby electrically connecting the semiconductor device 100 to other semiconductor chips, lead frames, or wiring boards. The external connection members are, for example, wires made of aluminum, gold, or copper, or clips made of copper plates. 【0027】 Absorption wiring AW3 is electrically connected to the absorption region PA via absorption wiring AW2 and absorption wiring AW1. By connecting the ground potential terminal provided outside the semiconductor device 100 to the absorption wiring AW3 using an external connection member, the ground potential is supplied to the absorption region PA. 【0028】 The cross-sectional structure of the semiconductor device 100 will be described below with reference to Figures 3 to 5. 【0029】 As shown in Figures 3 to 5, the semiconductor device 100 comprises an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND. The impurity concentration in the drain region ND is higher than the impurity concentration in the drift region NV. 【0030】 The semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by an epitaxial growth method while introducing n-type impurities. In this case, the silicon layer constitutes the drift region NV, and the silicon substrate constitutes the drain region ND. Furthermore, the resistivity of the silicon substrate is 1.0 Ω·cm or more and 2.5 Ω·cm or less, and the resistivity of the silicon layer is 0.158 Ω·cm or more and 0.160 Ω·cm or less. 【0031】 A drain electrode DE is formed on the underside BS of the semiconductor substrate SUB. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain electrode DE is formed over the entire underside BS of the semiconductor substrate SUB. Drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE. 【0032】 The cross-sectional structures of region 1A and region 2A are described below with reference to Figure 3. Note that the cross-sectional structure of power MOSFET 2Q in region 2A is substantially the same as that of power MOSFET 1Q in region 1A; therefore, the cross-sectional structure of power MOSFET 1Q will be described as representative here. 【0033】 As shown in Figure 3, a trench TR is formed in the semiconductor substrate SUB to a predetermined depth from the upper surface TS of the semiconductor substrate SUB. Inside the trench TR, a gate electrode GE1 is formed via a gate insulating film GI1. The gate insulating film GI1 is, for example, a silicon oxide film. The gate electrode GE1 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced. 【0034】 A p-type body region PB is formed in the semiconductor substrate SUB such that its depth from the top surface TS is shallower than the depth of the trench TR. An n-type source region NS is formed in the body region PB. The impurity concentration in the source region NS is higher than that of the drift region NV. The portion of the body region PB that is adjacent to the gate electrode GE1 via the gate insulating film GI1 and located between the source region NS and the drift region NV constitutes the channel region of the power MOSFET 1Q. In other words, the power MOSFET 1Q in this embodiment is a so-called vertical field-effect transistor (power semiconductor) in which current flows in the thickness direction of the semiconductor substrate SUB. 【0035】 An interlayer insulating film IL0 is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL0 is made of, for example, a silicon oxide film. Holes are formed in the interlayer insulating film IL0 that penetrate the source region NS and reach the body region PB. At the bottom of the holes, a diffusion region PR is formed in the body region PB. The diffusion region PR has a higher impurity concentration than the body region PB. The diffusion region PR is mainly provided to lower the contact resistance with the plug PG and to prevent latch-up. 【0036】 A plug PG is formed inside the above-mentioned hole. The plug PG is electrically connected to the source region NS, the body region PB, and the diffusion region PR. The plug PG includes, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film. 【0037】 A wiring M1 is formed on the interlayer insulating film IL0. The wiring M1 is electrically connected to the plug PG. The wiring M1 includes, for example, a second barrier metal film, a second conductive film formed on the second barrier metal film, and a third barrier metal film formed on the second conductive film. The second and third barrier metal films are, for example, laminated films of titanium film and titanium nitride film, respectively. The second conductive film is, for example, an aluminum alloy film with copper or silicon added. 【0038】 An interlayer insulating film IL1 is formed on the interlayer insulating film IL0 so as to cover the wiring M1. The interlayer insulating film IL1 is made of, for example, a silicon oxide film. A hole is formed in the interlayer insulating film IL1 that reaches the wiring M1. A via V1 is formed inside the hole. The via V1 is electrically connected to the wiring M1. A wiring M2 is formed on the interlayer insulating film IL1. The wiring M2 is electrically connected to the via V1. 【0039】 An interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the wiring M2. The interlayer insulating film IL2 is made of, for example, a silicon oxide film. A hole is formed in the interlayer insulating film IL2 that reaches the wiring M2. A via V2 is formed inside the above hole. The via V2 is electrically connected to the wiring M2. A wiring M3 is formed on the interlayer insulating film IL2. The wiring M3 is electrically connected to the via V2. 【0040】 The structure of via V2 and via V1 is similar to that of plug PG, and includes a first barrier metal film and a first conductive film. The structure of wiring M3 and wiring M2 is similar to that of wiring M1, and includes a second barrier metal film, a second conductive film, and a third barrier metal film. The thickness of wiring M3 is greater than the thickness of wiring M2 and wiring M1, respectively. 【0041】 Source potential is supplied to the source region NS, body region PB, and diffusion region PR of power MOSFET1Q from source electrode SE1 (wiring M3). Source potential is supplied to the source region NS, body region PB, and diffusion region PR of power MOSFET2Q from source electrode SE2 (wiring M3). 【0042】 As shown in Figures 3 and 4, a field insulating film IF0 and an absorption region PA are formed in the semiconductor substrate SUB between region 1A and region 2A, between region 1A and region 3A, and between region 2A and region 3A. The field insulating film IF0 is, for example, a silicon oxide film. The absorption region PA is provided in the semiconductor substrate SUB where the field insulating film IF0 is not formed, and is electrically connected to the absorption wiring AW1 via a plug PG. 【0043】 In Embodiment 1, the absorption region PA includes a p-type well region HPW, a p-type well region PW, and a p-type diffusion region PM as p-type impurity regions constituting the absorption region PA. The well region HPW is formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The well region PW is formed within the well region HPW. The diffusion region PM is formed within the well region PW. The impurity concentration in the well region PW is higher than that of the well region HPW. The impurity concentration in the diffusion region PM is higher than that of the well region PW. 【0044】 The well region HPW, well region PW, and diffusion region PM that constitute the absorption region PA are formed by the same manufacturing process as the well region HPW, well region PW, and diffusion region PM formed in region 3A described later. Note that the p-type impurity region that constitutes the absorption region PA is just one example; the absorption region PA may be composed of other p-type impurity regions or of just one p-type impurity region. 【0045】 The cross-sectional structure of region 3A will be described below with reference to Figure 4. The semiconductor device 100 includes a control circuit for controlling the operation of each of the multiple power MOSFETs 1Q and 2Q, but may also include other circuits such as a charge pump circuit, a temperature sensing circuit, or a current sensing circuit. The multiple p-type MOSFETs 3Q and n-type MOSFETs 4Q formed in region 3A are used not only as part of the control circuit but also as part of other circuits. 【0046】 As shown in Figure 4, a p-type well region (HPW) is formed in the semiconductor substrate (SUB). Within the HPW, n-type well regions (NW) and p-type well regions (PW) are formed. 【0047】 A gate electrode GE2 is formed on the well region NW via a gate insulating film GI2. The gate insulating film GI2 is, for example, a silicon oxide film. The gate electrode GE2 is, for example, a polycrystalline silicon film into which p-type impurities have been introduced. A pair of p-type diffusion regions PM are formed in the well region NW. The pair of diffusion regions PM constitute the source region or drain region of MOSFET3Q. The portion of the well region NW located below the gate electrode GE2 and sandwiched between the pair of diffusion regions PM constitutes the channel region of MOSFET3Q. In other words, MOSFET3Q in this embodiment is a so-called lateral field-effect transistor in which current flows along the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the well region NW is higher than the impurity concentration in the drift region NV. 【0048】 A gate electrode GE3 is formed on the well region PW via a gate insulating film GI3. The gate insulating film GI3 is, for example, a silicon oxide film. The gate electrode GE3 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced. A pair of n-type diffusion regions NM are formed in the well region PW. The pair of diffusion regions NM constitute the source region or drain region of MOSFET4Q. The portion of the well region PW located below the gate electrode GE3 and sandwiched between the pair of diffusion regions NM constitutes the channel region of MOSFET4Q. In other words, MOSFET4Q in this embodiment is a so-called lateral field-effect transistor in which current flows along the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the diffusion region NM is higher than the impurity concentration in the drift region NV. 【0049】 The gate electrode GE2, diffusion region PM, gate electrode GE3, and diffusion region NM are electrically connected to wiring M1 via plug PG. By appropriately connecting multiple MOSFET3Q and multiple MOSFET4Q using plug PG, wiring M1, via V1, wiring M2, via V2, and wiring M3, the above-mentioned control circuit and other circuits are configured. 【0050】 Furthermore, the connection between the control circuit and the gate electrodes GE1 of each of the multiple power MOSFETs 1Q and 2Q can be made, for example, by routing wire M1 or wire M2 from region 3A to regions 1A and 2A. 【0051】 The cross-sectional structure around the seal ring wiring SL1, SL2, and SL3 will be explained below using Figure 5. 【0052】 As shown in Figure 5, an n-type diffusion region NM is formed in the semiconductor substrate SUB. The seal ring wiring SL1 is electrically connected to the diffusion region NM via plug PG. The seal ring wiring SL2 is electrically connected to the seal ring wiring SL1 via via V1. The seal ring wiring SL3 is electrically connected to the seal ring wiring SL2 via via V2. The semiconductor substrate SUB (diffusion region NM, drift region NV, drain region ND) is electrically connected to the drain electrode DE. Therefore, the drain potential is supplied to the seal ring wirings SL1, SL2, and SL3 from the drain electrode DE via the semiconductor substrate SUB. 【0053】 Absorption wiring AW1 is electrically connected to absorption region PA via plug PG. Absorption wiring AW2 is electrically connected to absorption wiring AW1 via via V1. Absorption wiring AW3 is electrically connected to absorption wiring AW2 via via V2. Absorption wirings AW1, AW2, and AW3 are separate from and electrically isolated from sealing ring wirings SL1, SL2, and SL3. 【0054】 In this example, the absorption region PA overlaps with each of the seal ring wirings SL1, SL2, and SL3 in a plan view. However, it is sufficient for the absorption region PA to overlap with at least one of the seal ring wirings SL1, SL2, and SL3 in a plan view. In the following explanation, the case where the absorption region PA overlaps with the seal ring wiring SL1 in a plan view will be used as a representative example. 【0055】 <Regarding the effects of PA in the absorption region> The effects of providing the absorption region PA will be explained below using Figure 6. 【0056】 In some cases, a high potential higher than the drain potential may be applied as electrical noise from outside the semiconductor device 100 to the source electrode SE1 that constitutes the output terminal of power MOSFET 1Q. In this case, the body region PB of power MOSFET 1Q is forward-biased. As a result, as shown in Figure 6, a parasitic current I flows from the body region PB of power MOSFET 1Q to the semiconductor substrate SUB. B It plays. 【0057】 In this case, a parasitic PNP transistor 10 is formed with the body region PB of power MOSFET 1Q as the emitter, the semiconductor substrate SUB as the base, and the body region PB of power MOSFET 2Q as the collector. Therefore, the parasitic current I B Simultaneously, parasitic current I flows from the body region PB of power MOSFET1Q to the body region PB of power MOSFET2Q. B Leakage current I as part of the C It plays. 【0058】 Furthermore, a p-type well region HPW is formed in the semiconductor substrate SUB in region 3A. Therefore, a parasitic PNP transistor 10 is also formed, with the body region PB of power MOSFET 1Q as the emitter, the semiconductor substrate SUB as the base, and the well region HPW in region 3A as the collector. Consequently, leakage current I also flows from the body region PB of power MOSFET 1Q to the well region HPW in region 3A. C It plays. 【0059】 In some cases, a high potential may be applied as electrical noise to the source electrode SE2 that constitutes the output terminal of power MOSFET2Q. In that case, a leakage current I may flow from the body region PB of power MOSFET2Q to the body region PB of power MOSFET1Q. C As a result, leakage current I flows from the body region PB of power MOSFET 2Q to the well region HPW of region 3A. C It plays. 【0060】 Such leakage current I CIn the power MOSFET 1Q, power MOSFET 2Q, MOSFET 3Q, and MOSFET 4Q, it becomes a factor causing malfunction. 【0061】 The absorption region PA is provided to absorb such leakage current I C The absorption region PA is provided between the region 1A and the region 2A, between the region 1A and the region 3A, and between the region 2A and the region 3A. Also, a ground potential is connected to the absorption region PA. Then, before the leakage current I C reaches the body region PB or the well region HPW of the region 3A, the leakage current I C is absorbed by the absorption region PA. Therefore, malfunction in the power MOSFET 1Q, power MOSFET 2Q, MOSFET 3Q, and MOSFET 4Q can be suppressed. 【0062】 <Regarding the main features of Embodiment 1> The main features of Embodiment 1 will be described below. Before that, a study example will be described. FIG. 14 is a semiconductor device of a study example studied by the inventors of the present application, and shows a plan layout of the absorption region PA in the study example. 【0063】 As can be seen by comparing FIGS. 1 and 14, in Embodiment 1 and the study example, the absorption region PA surrounds the regions 1A and 2A in plan view. However, in the study example, the absorption wiring AW1 also surrounds the regions 1A and 2A in plan view, and the absorption region PA does not overlap with the seal ring wiring SL1 in plan view. Although not shown here, the absorption region PA also does not overlap with the seal ring wirings SL2 and SL3 in plan view. 【0064】 The absorption region PA and the absorption wirings AW1, AW2, AW3 need to be electrically insulated from the seal ring wirings SL1, SL2, SL3. Therefore, in the study example, the seal ring wirings SL1, SL2, SL3 are expanded toward the outer peripheral end of the semiconductor device. As a result, in the study example, the planar size of the semiconductor device increases. 【0065】 In contrast, in Embodiment 1, as shown in Figure 5, the plug PG for connecting the semiconductor substrate SUB and the seal ring wiring SL1 is positioned closer to the outer ring of the seal ring wiring SL1 than to the inner ring of the seal ring wiring SL1. Therefore, as shown in Figures 1 and 5, it is easier to extend the absorption region PA to a position that overlaps with the seal ring wirings SL1, SL2, and SL3 in a plan view. 【0066】 Furthermore, the absorption wiring AW1 is provided between region 1A and region 2A, between region 1A and region 3A, and between region 2A and region 3A. However, the absorption wiring AW1 is separate from the seal ring wiring SL1 and is not provided between the seal ring wiring SL1 and regions 1A, 2A, and 3A. 【0067】 Thus, the absorption region PA of Embodiment 1 suppresses the increase in the planar size of the semiconductor device 100, and also reduces the leakage current I C This suppresses the noise and improves the reliability of the semiconductor device 100. 【0068】 Furthermore, the potential supplied to the absorption region PA is the ground potential. Compared to the case where the drain potential is supplied to the absorption region PA, the potential difference between the high potential supplied as noise to the source electrode SE1 and the potential supplied to the absorption region PA becomes larger. Therefore, the leakage current I C It becomes easier to attract the current to the absorption region PA, and in the absorption region PA, leakage current I C The absorption capacity can be improved. When the ground potential is supplied to the absorption region PA, the leakage current I is improved compared to when the drain potential is supplied to the absorption region PA. C Its absorption capacity improves by approximately 20%. 【0069】 Furthermore, the depth of the absorption region PA is greater than the depth of the body region PB of power MOSFET1Q and the body region PB of power MOSFET2Q. Leakage current I C By providing a relatively deep absorption region PA at the point where the path is formed, the leakage current I C It becomes easier to absorb. 【0070】 (Variation 1) The semiconductor device 100 in Modification 1 of Embodiment 1 will be described below with reference to Figure 7. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained. 【0071】 In Embodiment 1, the absorption region PA completely surrounded both region 1A and region 2A in a plan view. 【0072】 As shown in Figure 7, in Modification 1, the absorption region PA partially surrounds the outer periphery of each of regions 1A, 2A, and 3A in a plan view. That is, in a plan view, the absorption region PA overlaps with the adjacent portions of each of regions 1A, 2A, and 3A of the seal ring wiring SL1. 【0073】 In other words, the portion of the absorption region PA located between region 1A and region 2A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of each region 1A and region 2A in a plan view. Similarly, the portion of the absorption region PA located between region 1A and region 3A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of each region 1A and region 3A in a plan view. Furthermore, the portion of the absorption region PA located between region 2A and region 3A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of each region 2A and region 3A in a plan view. 【0074】 By increasing the area of ​​the absorption region PA, the leakage current I C This improves the absorption capacity. On the other hand, increasing the area of ​​the absorption region PA increases the junction leakage between the absorption region PA and the semiconductor substrate SUB. Increased junction leakage increases the overall power consumption of the semiconductor device 100. 【0075】 In Embodiment 1, since the absorption region PA completely encloses each of region 1A and region 2A in a plan view, the leakage current I from region 1A to region 2A or region 3A C The current path and the leakage current I from region 2A to region 1A or region 3A C The current path is blocked. On the other hand, in Embodiment 1, the area of ​​the absorption region PA tends to increase. 【0076】 Therefore, in Modification 1, the leakage current I C The current path is partially blocked. Leakage current I C By rerouting the current path, the leakage current I C The absorption capacity can be maintained to some extent. By reducing the area of ​​the absorption region PA, junction leakage can be reduced. Therefore, in modified example 1, the overall power consumption of the semiconductor device 100 can be reduced compared to embodiment 1. 【0077】 (Modification 2) The semiconductor device 100 in Modification 2 of Embodiment 1 will be described below with reference to Figure 8. In the following description, the differences from Modification 1 will be mainly explained, and points that overlap with Modification 1 will not be explained. 【0078】 As shown in Figure 8, in Modification 2, the absorption region PA partially surrounds the outer periphery of each of regions 1A and 2A in a plan view. That is, in a plan view, the absorption region PA overlaps with the parts of the seal ring wiring SL1 adjacent to each of regions 1A and 2A. 【0079】 Modification 2 differs from Modification 1 in the following respects: The portion of the absorption region PA located between region 1A and region 3A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of region 1A in a plan view, but does not surround the outer periphery of region 3A. Also, the portion of the absorption region PA located between region 2A and region 3A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of region 2A in a plan view, but does not surround the outer periphery of region 3A. 【0080】 In Modification 2, compared to Modification 1, the leakage current I C Because the distance over which the current path is rerouted is short, the leakage current I C Regarding absorption capacity, Modification 1 is superior to Modification 2. However, in Modification 2, the overall power consumption of the semiconductor device 100 can be further reduced compared to Modification 1. 【0081】 (Variation 3) The semiconductor device 100 in Modification 3 of Embodiment 1 will be described below with reference to Figure 9. In the following description, the differences from Modification 1 will be mainly explained, and points that overlap with Modification 1 will not be explained. 【0082】 As shown in Figure 9, in Modification 3, the absorption region PA partially surrounds the outer periphery of each of regions 1A, 2A, and 3A in a plan view. That is, in a plan view, the absorption region PA overlaps with the adjacent portions of each of regions 1A, 2A, and 3A of the seal ring wiring SL1. 【0083】 Modification 3 differs from Modification 1 in the following respects: The portion of the absorption region PA located between region 1A and region 3A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of region 3A in a plan view, but does not surround the outer periphery of region 1A. Also, the portion of the absorption region PA located between region 2A and region 3A extends to a position where it overlaps with the seal ring wiring SL1 in a plan view, and partially surrounds the outer periphery of region 3A in a plan view, but does not surround the outer periphery of region 1A. 【0084】 In Modification 3, compared to Modification 1, the leakage current I C Because the distance over which the current path is rerouted is short, the leakage current I C Regarding absorption capacity, Modification 1 is superior to Modification 3. However, in Modification 3, the overall power consumption of the semiconductor device 100 can be further reduced compared to Modification 1. 【0085】 (Modification 4) The semiconductor device 100 in Modification 4 of Embodiment 1 will be described below with reference to Figure 10. In the following description, the differences from Modification 1 will be mainly explained, and points that overlap with Modification 1 will be omitted. 【0086】 As shown in Figure 9, in Modification 4, the absorption region PA extends to a position that overlaps with the seal ring wiring SL1 in a plan view. However, in Modification 4, the absorption region PA does not extend to partially surround the outer periphery of each of regions 1A, 2A, and 3A in a plan view. 【0087】 In Modification 4, the leakage current I is compared to Modification 1, Modification 2, and Modification 3. C Because the distance over which the current path is rerouted is short, the leakage current I C Regarding absorption capacity, Modifications 1, 2, and 3 are superior to Modification 4. However, Modification 4 can further reduce the overall power consumption of the semiconductor device 100 compared to Modifications 1, 2, and 3. 【0088】 (Variation 5) The semiconductor device 100 in Modification 5 of Embodiment 1 will be described below with reference to Figures 11 and 12. In the following description, the differences from Modification 4 will be mainly explained, and points that overlap with Modification 4 will be omitted. 【0089】 As shown in Figure 11, in Modification 5, similar to Modification 4, the absorption region PA does not extend to partially surround the outer periphery of each of regions 1A, 2A, and 3A in a plan view. In Modification 5, the absorption region PA extends across the seal ring wiring SL1 in a plan view. 【0090】 In Modification 5, compared to Modification 4, the leakage current I C Because the distance required to bypass the current path is long, the leakage current I CRegarding absorption capacity, Modification 5 is superior to Modification 4. However, in Modification 5, the overall power consumption of the semiconductor device 100 is higher compared to Modification 4. 【0091】 Furthermore, as shown in Figure 12, the plug PG for connecting the semiconductor substrate SUB and the seal ring wiring SL1 is not formed on the absorption region PA so that the absorption region PA is not electrically connected to the seal ring wiring SL1. 【0092】 (Embodiment 2) The semiconductor device 100 in Embodiment 2 will be described below with reference to Figure 13. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1. 【0093】 As shown in Figure 13, in Embodiment 2, as in Embodiment 1, the absorption region PA is provided between region 1A and region 2A, between region 1A and region 3A, and between region 2A and region 3A. However, in Embodiment 2, the absorption region PA does not overlap with the seal ring wiring SL1 in a plan view, but is provided between the seal ring wiring SL1 and a part of region 3A. The absorption wiring AW1 covers the absorption region PA in a plan view. 【0094】 In Embodiment 2, the leakage current I C The current path is partially blocked. Leakage current I C By rerouting the current path, the leakage current I C The absorption capacity can be maintained to a certain extent. By reducing the area of ​​the absorption region PA, junction leakage can be reduced. Therefore, in Embodiment 2, the overall power consumption of the semiconductor device 100 can be reduced compared to Embodiment 1. 【0095】 The technology of Embodiment 2 can be suitably used when it is difficult to extend the absorption region PA to a position where it overlaps with the seal ring wiring SL1, SL2, and SL3 in a plan view, or when there is a small number of MOSFETs 3Q and MOSFETs 4Q in region 3A, and there is room to arrange the absorption region PA. 【0096】 Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention. 【0097】 For example, the number of wiring layers is not limited to three layers, such as wiring M1, M2, and M3; it could be two layers, or four or more layers. 【0098】 Furthermore, although it has been explained that the semiconductor device 100 (i.e., the semiconductor substrate SUB) has three regions, the number of regions that the semiconductor device 100 has may be two. In this case, for example, an n-type power MOSFET is formed in the first region, and a p-type MOSFET and an n-type MOSFET are formed in the second region as a control circuit for controlling the operation of the power MOSFET formed in the first region. 【0099】 Furthermore, while trench-gate type power MOSFETs were described as vertical field-effect transistors (i.e., power semiconductors) formed in region 1A (i.e., the first region of the semiconductor substrate SUB) and region 2A (i.e., the second region of the semiconductor substrate SUB) of the semiconductor device 100 (i.e., the semiconductor substrate SUB), they are not limited to power MOSFETs; IGBTs (Insulated Gate Bipolar Transistors) may also be used. 【0100】 Furthermore, the power MOSFET is not limited to n-type but may also be p-type. In that case, the conductivity types of the semiconductor substrate SUB and each impurity region are composed of the conductivity type and reverse conductivity type described in the above embodiment. [Explanation of Symbols] 【0101】 100 Semiconductor Devices 10 Parasitic PNP Transistors 1A, 2A, 3A area 1Q, 2Q n-type power MOSFETs 3Q p-type MOSFET 4Q n-type MOSFET AW1, AW2, AW3 absorption wiring BS semiconductor substrate bottom surface DE drain electrode GE1, GE2, GE3 GE1 GI1, GI2, GI3 gate dielectric film HPW well area IF0 Field Insulation Film IL0, IL1, IL2 interlayer insulating film M1, M2, M3 wiring ND Drain region (impurity region) NM diffusion region (impurity region) NS source area (impurity area) NV drift region (impurity region) NW well region (impurity region) PA absorption region (impurity region) PAD PB body region (impurity region) PG Plug PM diffusion region (impurity region) PR diffusion region (impurity region) PW well region (impurity region) SE1, SE2 source electrodes SL1, SL2, SL3 sealing ring wiring SUB Semiconductor Substrate TR Trench Top surface of TS semiconductor substrate V1, V2 Via

Claims

[Claim 1] A first-type conductive semiconductor substrate having an upper surface and a lower surface, A vertical first field-effect transistor, which is a power semiconductor, is formed in the first region of the semiconductor substrate, A second field-effect transistor is formed in a second region of the semiconductor substrate located adjacent to the first region, and controls the operation of the first field-effect transistor. A sealing ring wiring formed in a ring shape in a plan view, surrounding the first and second regions, and formed on the upper surface of the semiconductor substrate, An impurity region is formed in the semiconductor substrate so as to extend to a predetermined depth from the upper surface of the semiconductor substrate, and is a second conductivity type opposite to the first conductivity type. Equipped with, The impurity region is provided between the first region and the second region so as to extend to a position that overlaps with the seal ring wiring in a plan view. A semiconductor device in which the impurity region is supplied with ground potential. [Claim 2] In the semiconductor device described in claim 1, A vertical third field-effect transistor, which is a power semiconductor, is formed in a third region of the semiconductor substrate that is located adjacent to the first region and adjacent to the second region. The seal ring wiring formed on the upper surface of the semiconductor substrate is formed in an annular shape so as to surround the first region, the second region and the third region in a plan view. A semiconductor device in which the impurity regions are provided between the first region and the second region, between the first region and the third region, and between the second region and the third region, so as to extend to a position that overlaps with the seal ring wiring in a plan view. [Claim 3] In the semiconductor device described in claim 2, A semiconductor device in which the first field-effect transistor and the second field-effect transistor are each power MOSFETs. [Claim 4] In the semiconductor device described in claim 3, The semiconductor substrate further comprises a first wiring formed on the upper surface and electrically connected to the impurity region, A semiconductor device wherein the first wiring is provided between the first region and the second region, between the first region and the third region, and between the second region and the third region, so as to cover a portion of the impurity region in a plan view, and is separated from the seal ring wiring. [Claim 5] In the semiconductor device according to claim 4, The semiconductor substrate further comprises a drain electrode formed on the lower surface, The sealing ring wiring is electrically connected to the drain electrode via the semiconductor substrate. A semiconductor device in which the impurity region and the first wiring are electrically insulated from the seal ring wiring. [Claim 6] In the semiconductor device described in claim 3, The first field-effect transistor is, In the first region, a first trench is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A first gate electrode formed inside the first trench via a first gate insulating film, In the first region, the first body region of the second conductivity type formed in the semiconductor substrate such that the depth from the upper surface of the semiconductor substrate is shallower than the depth of the first trench, A first source region of the first conductivity type formed in the first body region, It has, The aforementioned third field-effect transistor is In the third region, a second trench is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A second gate electrode formed inside the second trench via a second gate insulating film, In the third region, the second body region of the second conductivity type formed in the semiconductor substrate is such that the depth from the upper surface of the semiconductor substrate is shallower than the depth of the second trench, The second source region of the first conductivity type formed in the second body region, It has, The aforementioned second field-effect transistor is In the second region, the first well region of the second conductivity type is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A diffusion region of the first conductivity type formed in the first well region and constituting the source region or drain region of the second field-effect transistor, A third gate electrode formed on the first well region via a third gate insulating film, A semiconductor device having [Claim 7] In the semiconductor device described in claim 6, A semiconductor device wherein the depth of the impurity region is greater than the depth of the first body region and the depth of the second body region. [Claim 8] In the semiconductor device described in claim 3, The aforementioned impurity region extends across the seal ring wiring in a plan view, wherein the semiconductor device. [Claim 9] In the semiconductor device described in claim 3, A semiconductor device in which the impurity region overlaps, in a plan view, with the portion of the seal ring wiring that surrounds the first region and the third region. [Claim 10] In the semiconductor device described in claim 3, A semiconductor device in which the impurity region overlaps, in a plan view, with adjacent portions of the seal ring wiring, specifically parts of the first region and the third region. [Claim 11] In the semiconductor device according to claim 10, A semiconductor device in which the impurity region overlaps, in a plan view, with a portion of the sealing ring wiring adjacent to a part of the second region. [Claim 12] A first-type conductive semiconductor substrate having an upper surface and a lower surface, A vertical first field-effect transistor, which is a power semiconductor, is formed in the first region of the semiconductor substrate, A second field-effect transistor is formed in a second region of the semiconductor substrate located adjacent to the first region, and controls the operation of the first field-effect transistor. A sealing ring wiring formed in a ring shape in a plan view, surrounding the first and second regions, and formed on the upper surface of the semiconductor substrate, An impurity region is formed in the semiconductor substrate so as to extend to a predetermined depth from the upper surface of the semiconductor substrate, and is a second conductivity type opposite to the first conductivity type. Equipped with, The impurity region is provided between the first region and the second region, and between the seal ring wiring and a part of the second region. A semiconductor device in which the impurity region is supplied with ground potential. [Claim 13] In the semiconductor device according to claim 12, A vertical third field-effect transistor, which is a power semiconductor, is formed in a third region of the semiconductor substrate that is located adjacent to the first region and adjacent to the second region. The seal ring wiring formed on the upper surface of the semiconductor substrate is formed in an annular shape so as to surround the first region, the second region and the third region in a plan view. A semiconductor device wherein the impurity regions are provided between the first region and the second region, between the first region and the third region, between the second region and the third region, and between the seal ring wiring and the portion of the second region. [Claim 14] In the semiconductor device according to claim 13, A semiconductor device in which the first field-effect transistor and the second field-effect transistor are each power MOSFETs. [Claim 15] In the semiconductor device according to claim 14, A first wiring is formed on the upper surface of the semiconductor substrate so as to cover the impurity region in a plan view, and is electrically connected to the impurity region. A drain electrode formed on the lower surface of the semiconductor substrate, Furthermore, The sealing ring wiring is electrically connected to the drain electrode via the semiconductor substrate. A semiconductor device in which the impurity region and the first wiring are electrically insulated from the seal ring wiring. [Claim 16] In the semiconductor device according to claim 14, The first field-effect transistor is, In the first region, a first trench is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A first gate electrode formed inside the first trench via a first gate insulating film, In the first region, the first body region of the second conductivity type formed in the semiconductor substrate such that the depth from the upper surface of the semiconductor substrate is shallower than the depth of the first trench, A first source region of the first conductivity type formed in the first body region, It has, The aforementioned third field-effect transistor is In the third region, a second trench is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A second gate electrode formed inside the second trench via a second gate insulating film, In the third region, the second body region of the second conductivity type formed in the semiconductor substrate is such that the depth from the upper surface of the semiconductor substrate is shallower than the depth of the second trench, The second source region of the first conductivity type formed in the second body region, It has, The aforementioned second field-effect transistor is In the second region, the first well region of the second conductivity type is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A diffusion region of the first conductivity type formed in the first well region and constituting the source region or drain region of the second field-effect transistor, A third gate electrode formed on the first well region via a third gate insulating film, A semiconductor device having [Claim 17] In the semiconductor device according to claim 16, A semiconductor device wherein the depth of the impurity region is greater than the depth of the first body region and the depth of the second body region. [Claim 18] In the semiconductor device according to claim 14, The aforementioned impurity region does not overlap with the seal ring wiring in a plan view in the semiconductor device.

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