Semiconductor equipment

Abstract

The objective is to provide a semiconductor device with excellent electrical characteristics. [Solution] A semiconductor device comprising a semiconductor layer having a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer containing a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistivity film along the inner surface of the trench with a higher resistivity compared to the semiconductor layer, and a second electrode located in the trench and electrically connected to the first electrode, wherein the thickness of the high-resistivity film is greater on the bottom side of the trench than on the side side.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a trench MOS type Schottky diode. The Schottky diode has a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer and having a trench, a cathode electrode formed in the first semiconductor layer, an insulating film along the inner surface of the trench, and a trench MOS gate embedded in the trench so as to cover the insulating film and contacting an anode electrode. Note that it is not simply recognized as the prior art just because it is described in the background art.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this disclosure is to provide a semiconductor device having excellent electrical characteristics.

Means for Solving the Problems

[0005] To solve the above problems, in one aspect of this disclosure, a semiconductor device has a plurality of trenches and mesa portions between adjacent trenches, and includes a semiconductor layer containing a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistance film along the inner surface of the trench and having a resistivity higher than that of the semiconductor layer, and a second electrode located in the trench and electrically connected to the first electrode, and the film thickness of the high-resistance film is larger on the bottom side than on the side surface side of the trench.

[0006] In another aspect of the present disclosure, a semiconductor device includes a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer including a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistance film having a resistivity higher than that of the semiconductor layer along the inner surface of the trench, and a second electrode located in the trench and electrically connected to the first electrode. The high-resistance film has a larger film thickness on the bottom side than on the side surface side of the trench, and has the same dielectric constant on the side surface side and the bottom side of the trench.

[0007] In still another aspect of the present disclosure, a semiconductor device includes a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer including a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistance film having a resistivity higher than that of the semiconductor layer along the inner surface of the trench, and a second electrode located in the trench and electrically connected to the first electrode. The dielectric constant of the high-resistance film is larger on the bottom side than on the side surface side of the trench.

[0008] In still another aspect of the present disclosure, a semiconductor device includes a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer including a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistance film having a resistivity higher than that of the semiconductor layer along the inner surface of the trench, and a second electrode located in the trench and electrically connected to the first electrode. The high-resistance film has a first portion and a second portion having a larger dielectric constant than the first portion, and the lower end of the second portion is located below the lower end of the first portion.

[0009] In another embodiment of the present disclosure, the semiconductor device comprises a semiconductor layer having a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer having a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portions, a high-resistivity film along the inner surface of the trenches having a higher resistivity than the semiconductor layer, and a second electrode located within the trenches and electrically connected to the first electrode, wherein the semiconductor layer has crystalline defect regions located below the bottom surface of the trenches and extending linearly in cross-section.

[0010] In yet another embodiment of the present disclosure, the semiconductor device comprises a plurality of trenches and mesa portions between adjacent trenches, an n-type semiconductor layer comprising a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portions, a high-resistivity film along the inner surface of the trenches having a higher resistivity than the semiconductor layer, and a second electrode located within the trenches and electrically connected to the first electrode, wherein a p-type region is formed in the semiconductor layer located below the bottom surface of the trenches.

[0011] In yet another embodiment of the present disclosure, the semiconductor device comprises a semiconductor layer having a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer having a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portions, a high-resistivity film along the inner surface of the trenches having a higher resistivity than the semiconductor layer, and a second electrode located within the trenches and electrically connected to the first electrode, wherein at least the upper end of the mesa portions has a lower carrier density than the rest of the semiconductor layer, and the high-resistivity film has a greater thickness on the bottom side of the trenches than on the side side. [Effects of the Invention]

[0012] According to this disclosure, it is possible to provide a semiconductor device with excellent electrical characteristics. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a magnified view of a portion of Figure 1. [Figure 3] Figure 3 is a flowchart showing a method for manufacturing a semiconductor device. [Figure 4] Figure 4 is a schematic cross-sectional view showing a stacked structure including a first substrate, a first semiconductor layer, and a second semiconductor layer. [Figure 5] Figure 5 is a schematic cross-sectional view of a stacked structure including a first substrate, a first semiconductor layer, a second semiconductor layer, and a third electrode. [Figure 6] Figure 6 is a schematic cross-sectional view of a laminated structure including a first substrate, a first semiconductor layer, a second semiconductor layer, a third electrode, and a second substrate. [Figure 7] Figure 7 is a schematic cross-sectional view of a laminated structure including a first semiconductor layer, a second semiconductor layer, a third electrode, and a second substrate. [Figure 8] Figure 8 is a schematic cross-sectional view of a laminated structure including a first semiconductor layer having a trench, a second semiconductor layer, a third electrode, and a second substrate. [Figure 9] Figure 9 is a schematic cross-sectional view of a multilayer structure including a first semiconductor layer, a second semiconductor layer, a high-resistivity film, a third electrode, and a second substrate. [Figure 10] Figure 10 is a schematic cross-sectional view of a laminated structure including a first semiconductor layer, a second semiconductor layer, a high-resistivity film, a first electrode, a second electrode, a third electrode, and a second substrate. [Figure 11] This is a schematic cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 12] This is a schematic cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 13] This is a schematic cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 14] This is a schematic cross-sectional view showing a semiconductor device of a modified example of the fourth embodiment. [Figure 15] This is a schematic cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 16]This is a schematic cross-sectional view showing a semiconductor device of a modified example of the fifth embodiment. [Figure 17] This is a schematic cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 18] This is a schematic cross-sectional view showing a semiconductor device according to the seventh embodiment. [Modes for carrying out the invention]

[0014] The embodiments of the semiconductor device described herein will be explained below with reference to the drawings, but the invention covered by the claims is not limited to these embodiments. Furthermore, not all combinations of configurations described in the embodiments are considered essential for solving the problem. In addition, each configuration of the disclosure is described to the extent that it does not hinder the solving of the problem of the disclosure. The same reference numerals are used for identical components to omit redundant explanations.

[0015] Furthermore, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily depicted to a constant scale, even if not explicitly stated herein. Also, note that a feature in one embodiment may be used in another. Descriptions of well-known elements and manufacturing techniques may be omitted so as not to unnecessarily obscure the embodiments of this disclosure. The examples used herein are solely for the purpose of aiding understanding of this disclosure and enabling those skilled in the art to implement the embodiments. Therefore, the embodiments and examples herein are not to be construed as being limited to the scope of this disclosure, but are determined solely by the claims and applicable law.

[0016] The terms "first," "second," etc., are used to describe various elements used herein, but the elements are not limited by these terms. The terms "first," "second," etc., are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and the second element may be referred to as the first element. As used herein, the term "and / or" encompasses one or more, or any combination of, the listed items.

[0017] In this disclosure, terms such as “equipment,” “possess,” and “include” indicate the existence of the described element, and do not exclude the existence of one or more other elements. Where the expression “connected” or “combined” an element is used in this disclosure, it should be understood that the element may be directly connected to or combined with another element, or there may be an intervening element.

[0018] The semiconductor device described herein is useful for various semiconductor elements, and is particularly useful for power devices. The semiconductor device may be a lateral device in which electrodes are formed only on one side of the semiconductor layer, or a vertical device in which electrodes are formed on both the front and back sides of the semiconductor layer. Examples of semiconductor devices include application to a part of the element structure of diodes, transistors (e.g., MOSFETs), or semiconductor light-emitting elements.

[0019] (First Embodiment) Figure 1 is a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment. The semiconductor device 100 is a Schottky barrier diode, and more specifically, a vertical trench MOS type Schottky barrier diode.

[0020] The semiconductor device 100 comprises a semiconductor layer 4, a high-resistivity film 6, a first electrode 1, and a second electrode 2. In this disclosure, the direction parallel to the thickness direction of the semiconductor layer 4 is defined as the "up and down direction." One direction parallel to the thickness direction of the semiconductor layer 4 is defined as "upward," and the direction opposite to upward is defined as "downward." These directions do not limit the direction of gravity or the direction of mounting the semiconductor device to a substrate or the like during mounting. In this disclosure, of a layer, substrate, or other component, the surface facing upward is described as the top surface, and the surface facing downward is described as the bottom surface. When expressions such as a layer, region, or substrate exist "on top of" or "below" another element are used, it should be understood that it may exist directly on top of or below another element, or the element may exist between other elements. In this disclosure, a cross section perpendicular to the top surface of the semiconductor layer 4, that is, a cross section parallel to the up and down direction, is referred to as the "vertical cross section." The semiconductor device 100 may further comprise a semiconductor layer 5 and a third electrode 3, separate from the semiconductor layer 4. Hereafter, semiconductor layer 4 will be referred to as the first semiconductor layer 4, and another semiconductor layer 5 will be referred to as the second semiconductor layer 5. The first semiconductor layer 4 is an example of a semiconductor layer.

[0021] The first semiconductor layer 4 is an n-type semiconductor. The first semiconductor layer 4 contains a crystalline oxide semiconductor. Preferably, the first semiconductor layer 4 contains a crystalline oxide semiconductor as its main component. In this disclosure, "contains as a main component" means containing 50 atomic percent or more of the total. Preferably, the first semiconductor layer 4 contains 70 atomic percent or more of the crystalline oxide semiconductor, and more preferably 90 atomic percent or more. The first semiconductor layer 4 may contain 100 atomic percent of the crystalline oxide semiconductor. In this case as well, it is included in containing a crystalline oxide semiconductor as its main component.

[0022] The second semiconductor layer 5 is in contact with the lower surface of the first semiconductor layer 4. The second semiconductor layer 5 is an n-type semiconductor having a carrier density greater than that of the first semiconductor layer 4. That is, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 5 is an n+-type semiconductor layer. Note that each of the first semiconductor layer 4 and the second semiconductor layer 5 may be a p-type semiconductor.

[0023] The second semiconductor layer 5 preferably contains a crystalline oxide semiconductor. The main components of the first semiconductor layer 4 and the second semiconductor layer 5 are preferably the same. However, the main components of the first semiconductor layer 4 and the second semiconductor layer 5 may be different. Each of the first semiconductor layer 4 and the second semiconductor layer 5 preferably contains a crystalline oxide semiconductor as its main component. Hereinafter, unless otherwise specified, the crystalline oxide semiconductors of the first semiconductor layer 4 and the second semiconductor layer 5 will simply be referred to as "crystalline oxide semiconductors."

[0024] Crystalline oxide semiconductors are, for example, metal oxides. The metals included in the metal oxide are, for example, one or more metals selected from gallium (Ga), aluminum (Al), indium (In), iron (Fe), chromium (Cr), vanadium (V), titanium (Ti), rhodium (Rh), nickel (Ni), cobalt (Co), and iridium (Ir). It is preferable that the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium. It is particularly preferable that the crystalline oxide semiconductor is a metal oxide containing gallium. The crystalline oxide semiconductor may also be an InAlGaO-based semiconductor containing indium and / or aluminum in addition to gallium. In this disclosure, InAlGaO-based semiconductor means In X Al Y Ga Z O3 means (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5).

[0025] Crystalline oxide semiconductors are, for example, single crystals. However, crystalline oxide semiconductors may also be polycrystalline. Crystalline oxide semiconductors have a corundum structure as their crystal structure. However, the crystal structure of crystalline oxide semiconductors is not limited to a corundum structure. The crystal structure of crystalline oxide semiconductors may be, for example, a β-Gallia structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), or a cubic structure (e.g., a γ-type or δ-type structure).

[0026] The crystalline oxide semiconductor is preferably gallium oxide (Ga2O3) or a mixed crystal containing gallium oxide and other metal oxides. More preferably, the crystalline oxide semiconductor is α-Ga2O3 or a mixed crystal containing α-Ga2O3 and other metal oxides. Examples of other metal oxides include aluminum oxide (Al2O3), indium oxide (In2O3), iridium oxide (IrO2), rhodium oxide (Rh2O3), chromium oxide (Cr2O3), or iron oxide (Fe2O3). The crystalline oxide semiconductor preferably contains 1 atomic percent or more of the other metal oxide. More preferably, the crystalline oxide semiconductor contains 5 atomic percent or more of the other metal oxide, and even more preferably, 10 atomic percent or more. The crystalline oxide semiconductor may contain less than 1 atomic percent of the other metal oxide. In this example, the crystalline oxide semiconductor is gallium oxide (Ga2O3).

[0027] Each of the first semiconductor layer 4 and the second semiconductor layer 5 may contain a dopant. In this disclosure, a dopant means an element that is donated or accepted. The dopant may be a known dopant. Each of the first semiconductor layer 4 and the second semiconductor layer 5 contains an n-type dopant such as tin (Sn), germanium (Ge), silicon (Si), titanium, zirconium (Zr), vanadium, or niobium (Nb). The dopant is preferably tin, germanium, or silicon. The dopant content of each of the first semiconductor layer 4 and the second semiconductor layer 5 is preferably 0.000001 atomic percent or more. The dopant content of each of the first semiconductor layer 4 and the second semiconductor layer 5 is more preferably 0.000001 atomic percent or more and 20 atomic percent or less, and most preferably 0.00001 atomic percent or more and 10 atomic percent or less.

[0028] The carrier density of each of the first semiconductor layer 4 and the second semiconductor layer 5 can be appropriately set, for example, by adjusting the doping amount. The carrier density in each of the first semiconductor layer 4 and the second semiconductor layer 5 is uniform. In the present disclosure, "uniform" includes not only the case of being completely uniform but also the case of being slightly different. That is, it is sufficient that it is substantially uniform. The carrier density of each of the first semiconductor layer 4 and the second semiconductor layer 5 may be non-uniform. Considering both the forward loss and the breakdown voltage of the semiconductor device 100, the carrier density of the first semiconductor layer 4 is preferably 1×10 15 / cm 3 or more and 1×10 17 / cm 3 or less. The carrier density of the first semiconductor layer 4 may exceed 1×10 17 / cm 3 or may be less than 1×10 15 / cm 3 . Considering the forward loss of the semiconductor device 100, the carrier density of the second semiconductor layer 5 is preferably 1×10 17 / cm 3 or more and 1×10 22 / cm 3 or less. The carrier density of the second semiconductor layer 5 may exceed 1×10 22 / cm 3 or may be less than 1×10 17 / cm 3 .

[0029] Each of the first semiconductor layer 4 and the second semiconductor layer 5 has a thickness. Hereinafter, the thickness of the first semiconductor layer 4 is referred to as "thickness t1". The thickness of the second semiconductor layer 5 is referred to as "thickness t2". In order to increase the breakdown voltage of the semiconductor device 100, each of the thickness t1 and the thickness t2 is preferably 1 μm or more and preferably 15 μm or less. Note that each of the thickness t1 and the thickness t2 may be less than 1 μm or may exceed 15 μm. The thickness t1 may be equal to or greater than the thickness t2 or may be less than the thickness t2.

[0030] Figure 2 is a partially enlarged view of Figure 1. The first semiconductor layer 4 has a plurality of trenches 43 and mesa portions 44 between adjacent trenches 43. The plurality of trenches 43 are formed on one surface in the thickness direction of the first semiconductor layer 4. In this example, the plurality of trenches 43 are formed on the upper surface of the first semiconductor layer 4.

[0031] The trench 43 extends in a direction perpendicular to the vertical cross-section. The trench 43 opens upward. The trench 43 has a bottom surface located at the lower end of the trench 43, sides located on both sides in the width direction of the trench 43, and corners located on both sides in the width direction of the trench 43. The corners are the connection points between the bottom surface and the sides of the trench 43. The shape of the vertical cross-section of the corners is arc-shaped. The bottom surface and the sides of the trench 43 are connected via corners so as not to form sharp angles. However, the bottom surface and each side of the trench 43 may be connected via corners that do have sharp angles.

[0032] The trench 43 has a depth D and a width W1. The depth D of the trench 43 is the vertical dimension from the upper surface of the first semiconductor layer 4 to the lower end of the trench 43. The width W1 of the trench 43 is the distance between the two sides of the trench 43. The depth D of the trench 43 is preferably 3 μm or less, and more preferably 1.5 μm or less. The depth of the trench 43 is preferably 1 μm or more, and more preferably 1 μm or more and 1.5 μm or less. However, the depth D of the trench 43 is not limited. The depth D of the trench 43 may be less than 1 μm or greater than 3 μm. The width W1 of the trench 43 is preferably 0.5 μm or more and 2 μm or less. The width W1 of the trench 43 may be less than 0.5 μm or greater than 2 μm.

[0033] The mesa portion 44 is a part of the first semiconductor layer 4 that protrudes above the bottom surface of the trench 43. The width W1 of the trench 43 is greater than the width W2 of the mesa portion 44. However, the width W1 of the trench 43 may be smaller than the width W2 of the mesa portion 44. The width W2 of the mesa portion 44 is, for example, 0.5 μm or more and 2 μm or less. However, the width W2 of the mesa portion 44 is not limited.

[0034] The mesa portion 44 is formed from the same material as the portion of the first semiconductor layer 4 other than the mesa portion 44. In this disclosure, "same" includes not only being exactly the same, but also being substantially the same. That is, the mesa portion 44 may be formed from substantially the same material as the portion of the first semiconductor layer 4 other than the mesa portion 44. For example, even if the mesa portion 44 contains trace amounts of substances such as impurities that are not present in the portion of the first semiconductor layer 4 other than the mesa portion 44, it is still included in the statement "the mesa portion 44 is formed from the same material as the portion of the first semiconductor layer 4 other than the mesa portion 44." The carrier density of the mesa portion 44 is the same as the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44. The carrier density at least at the upper end of the mesa portion 44 is 1.0 × 10⁻¹⁴ 16 / cm 3 It may be greater than or equal to 1.0 × 10 16 / cm 3 It is acceptable to be less than [a certain value].

[0035] The high-resistivity film 6 is provided individually in each of the multiple trenches 43. The resistivity of the high-resistivity film 6 is greater than the resistivity of the first semiconductor layer 4. The high-resistivity film 6 is preferably semi-insulating or insulating. The resistivity of the high-resistivity film 6 is 1 × 10⁻⁶ 6 It is preferable that it be Ω·cm or more, 1 × 10 10 It is even more preferable that the resistivity is Ω·cm or greater. The resistivity of the high-resistivity film 6 is 1 × 10⁻⁶. 6 The resistance may be less than Ω·cm. In this example, the high-resistance film 6 is an insulating film. The insulating film may also be called a dielectric film. The high-resistance film 6 may be, for example, a semiconductor film or an undoped film having a carrier density lower than that of the first semiconductor layer 4.

[0036] High-resistivity films 6 include, for example, Ga2O3, (AlGa)2O3, InAlGaO, AlInZnGaO4, AlN, HfO2, and HfSi. x O y It includes ZrO2, SiN, SiON, Al2O3, MgO, GdO, SiO2, or Si3N4. The resistivity of the high-resistivity film 6 can be adjusted to a predetermined value depending, for example, on impurities contained in the high-resistivity film 6 and the manufacturing process of the semiconductor device 100. By using such a high-resistivity film 6, the semiconductor properties of the semiconductor device 100 can be made to appear in good condition. To increase the dielectric constant of the high-resistivity film 6, the high-resistivity film 6 contains HfO 2、 HfSi x O y It is preferable that the layer contains ZrO2, Al2O3, or SiO2. The high-resistivity film 6 is particularly preferably HfO2 or Al2O3, and in this example, it is HfO2. The lifetime field of the high-resistivity film 6 is lower than the breakdown field of the first semiconductor layer 4. However, the lifetime field of the high-resistivity film 6 may be higher than or equal to the breakdown field of the first semiconductor layer 4.

[0037] The high-resistance film 6 is along the inner surface of the trench 43. The high-resistance film 6 covers the inner surface of the trench 43. In a vertical cross-section, the shape of the high-resistance film 6 is U-shaped. In this example, the high-resistance film 6 is formed only within the trench 43 and not on the upper surface of the mesa portion 44. The high-resistance film 6 does not have to be formed on the upper part of the side surface of the trench 43. That is, the high-resistance film 6 may be formed only on the lower part of the side surface of the trench 43. The high-resistance film 6 has two first parts 61 located on both sides of the trench 43 (i.e., one side and the other side of the trench 43) and a second part 62 located on the bottom surface side of the trench 43. The first part 61 and the second part 62 are formed integrally. The first part 61 and the second part 62 may be formed separately.

[0038] The first part 61 and the second part 62 are formed from the same material. Therefore, the dielectric constant of the high-resistivity film 6 is the same on the side and bottom sides of the trench 43. That is, the dielectric constant of the first part 61 and the dielectric constant of the second part 62 are the same. However, the first part 61 and the second part 62 may be formed from different materials. The dielectric constant of the high-resistivity film 6 may differ on the side and bottom sides of the trench 43.

[0039] The two first parts 61 are spaced apart from each other in the width direction of the trench 43. The first parts 61 extend along the corresponding sides of the trench 43. The first parts 61 cover the corresponding sides of the trench 43.

[0040] The second portion 62 extends along the bottom surface of the trench 43. The ends of the second portion 62 in the width direction of the trench 43 are connected to the lower ends of the two first portions 61, respectively. The portion of the high-resistance film 6 that protrudes upward from the second portion 62 is the first portion 61. The lower end of the first portion 61 is the base of the first portion 61 that protrudes upward from the second portion 62. The lower end of the second portion 62 is the bottom surface of the second portion 62. The lower end of the second portion 62 is located below the lower end of the first portion 61. The second portion 62 covers the bottom surface of the trench 43.

[0041] The connection between the first part 61 and the second part 62 is preferably formed in an arc shape along the corner of the trench 43. That is, the first part and the second part 62 are preferably connected via an arc-shaped connection so as to have no corners. In this case, the electric field strength of the connection can be reduced.

[0042] The first part 61 and the second part 62 each have a thickness. Hereinafter, the thickness of the first part 61 will be referred to as "film thickness t3". The thickness of the second part 62 will be referred to as "film thickness t4". Film thickness t3 is the dimension of the first part 61 in the width direction of the trench 43. Film thickness t4 is the dimension of the second part 62 in the vertical direction. The high-resistance film 6 has a greater film thickness on the bottom side of the trench 43 than on the side side. That is, film thickness t4 is greater than film thickness t3. Note that film thickness t4 may be the same as film thickness t3, or it may be less than film thickness t3.

[0043] The thickness of the high-resistance film 6 on the bottom side of the trench 43, i.e., the film thickness t4, is preferably 40% or more of the depth D of the trench 53. The film thickness t4 may be 50% or more of the depth of the trench 53, or 60% or more. However, the film thickness t4 may be less than 40% of the depth of the trench 53.

[0044] The first electrode 1 is formed on the upper surface of the mesa portion 44, that is, on the upper surface of the first semiconductor layer 4, excluding the portion where the multiple trenches 43 are formed. The first electrode 1 is Schottky bonded to the upper surface of the mesa portion 44. As a result, a Schottky barrier is formed between the first electrode 1 and the mesa portion 44.

[0045] The thickness t5 of the first electrode 1 is preferably 0.1 nm or more and 10 μm or less. More preferably the thickness t5 of the first electrode 1 is 5 nm or more and 500 nm or less, and even more preferably 10 nm or more and 200 nm or less. The thickness t5 of the first electrode 1 may be less than 0.1 nm or greater than 10 μm.

[0046] The second electrode 2 is provided individually in each of the multiple trenches 43. The first electrode 1 and the second electrode 2 are electrically connected. The second electrode 2 is formed integrally with the first electrode 1. In this example, the first electrode 1 and the second electrode 2 form a Schottky electrode. In Figures 1 and 2, for convenience, the boundary between the first electrode 1 and the second electrode 2 is shown with a dashed line, but the boundary between the first electrode 1 and the second electrode 2 does not need to be clearly visible externally. Also, the first electrode 1 and the second electrode 2 may be formed as separate components.

[0047] Preferably, the first electrode 1 and the second electrode 2 are formed from the same material. However, the first electrode 1 and the second electrode 2 may be formed from different materials. The materials of the first electrode 1 and the second electrode 2 may be conductive inorganic materials or conductive organic materials. Preferably, each of the first electrode 1 and the second electrode 2 is a metal or contains a metal. The metal is, for example, at least one metal selected from groups 4 to 12 of the periodic table. The "periodic table" refers to the periodic table defined by the International Union of Pure and Applied Chemistry (IUPAC). Examples of metals in group 4 of the periodic table are titanium (Ti), zirconium (Zr), or hafnium (Hf). Examples of metals in group 5 of the periodic table are vanadium (V), niobium (Nb), or tantalum (Ta). Metals in Group 6 of the periodic table include, for example, chromium (Cr), molybdenum (Mo), or tungsten (W). Metals in Group 7 of the periodic table include, for example, manganese (Mn), technetium (Tc), or rhenium (Re). Metals in Group 8 of the periodic table include, for example, iron (Fe), ruthenium (Ru), or osmium (Os). Metals in Group 9 of the periodic table include, for example, cobalt (Co), rhodium (Rh), or iridium (Ir). Metals in Group 10 of the periodic table include, for example, nickel (Ni), palladium (Pd), or platinum (Pt). Metals in Group 11 of the periodic table include, for example, copper (Cu), silver (Ag), or gold (Au). Metals in Group 12 of the periodic table include, for example, zinc (Zn), cadmium (Cu), or mercury (Hg). The work function of the metal is preferably 4.0 eV to 5.0 eV. The materials of the first electrode 1 and the second electrode 2 are not limited and may be silicides, other compounds, etc.

[0048] The second electrode 2 is located within the trench 43. In this disclosure, "located within the trench 43" means that at least a portion of the second electrode 2 is located within the trench 43. In this example, the second electrode 2 has a portion located within the trench 43 and a portion that extends above the trench 43. The second electrode 2 may also have only a portion located within the trench 43. The portion of the second electrode 2 located within the trench 43 is in contact with the first portion 61 and the second portion 62 of the high-resistivity film 6.

[0049] As shown in Figure 1, the third electrode 3 is formed on the lower surface of the second semiconductor layer 5. In this example, the third electrode 3 is ohmic junctioned with the second semiconductor layer 5. That is, the third electrode 3 is an ohmic electrode.

[0050] The material of the third electrode 3 may be a conductive inorganic material or a conductive organic material. In particular, it is preferable that the third electrode 3 be a metal. The metal of the third electrode 3 may be the same as or different from the metal of the first electrode 1 or the metal of the second electrode 2. The metal of the third electrode 3 may be, for example, at least one metal selected from groups 4 to 12 of the periodic table.

[0051] Next, an example of a method for manufacturing the semiconductor device 100 will be described. Figure 3 is a flowchart showing the method for manufacturing the semiconductor device 100. Figures 4 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device 100 in order. Note that Figures 4 to 6 show the stacked structure inverted.

[0052] A method for manufacturing a semiconductor device 100 includes a semiconductor layer formation step of forming a first semiconductor layer 4 and a second semiconductor layer 5 on a first substrate 8, a third electrode formation step of forming a third electrode 3 on the second semiconductor layer 5, a bonding step of bonding a second substrate 9 to the third electrode 3, a first removal step of removing the first substrate 8, a trench formation step of forming a trench 43 in the semiconductor layer 4, a high-resistance film formation step of forming a high-resistance film 6 in the trench 43 of the first semiconductor layer 4, and a first electrode / second electrode formation step of forming a first electrode 1 and a second electrode 2 on the first semiconductor layer 4. The method for manufacturing a semiconductor device 100 may further include a second removal step of removing the second substrate 9 from the third electrode 3.

[0053] The first substrate 8 (see Figure 4) is, for example, a base substrate. The first substrate 8 may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate.

[0054] The first substrate 8 is, for example, a sapphire substrate, a gallium oxide substrate, a SiC substrate, a ZnO substrate, or a GaN substrate, or a substrate containing gallium oxide and aluminum oxide. Preferably, the first substrate 8 is mainly composed of a material having a corundum structure, a β-gallia structure, or a hexagonal crystal structure. A material having a corundum structure is, for example, α-Al2O3 or α-Ga2O3. A first substrate 8 formed from a material having a corundum structure is, for example, an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, or an α-type gallium oxide substrate (a-plane, m-plane, r-plane, or c-plane). A first substrate 8 formed from a material having a β-gallia structure is, for example, a β-Ga2O3 substrate. The first substrate 8 may also be a mixed crystal substrate containing Ga2O3 and Al2O3, with Al2O3 being more than 0 wt% and 60 wt% or less. The first substrate 8, formed from a substrate material having a hexagonal crystal structure, is, for example, a SiC substrate, a ZnO substrate, or a GaN substrate. The material and crystal structure of the first substrate 8 are not limited and may be known materials.

[0055] The semiconductor layer formation process includes a first semiconductor layer formation process for forming a first semiconductor layer 4 on a first substrate 8, and a second semiconductor layer formation process for forming a second semiconductor layer 5 on the first semiconductor layer 4.

[0056] In the first semiconductor layer formation process, a first semiconductor layer 4 is formed on one surface of the first substrate 8 in the thickness direction. In the first semiconductor layer formation process, the first semiconductor layer 4 is formed by, for example, CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MOVPE (Metal Organic Vapor Phase Epitaxy), mist CVD, mist epitaxy, MBE (Molecular Beam Epitxy), HVPE (Hydride Vapor Phase Epitaxy), PLD (Pulsed Laser Deposition), or ALD (Atomic Layer Deposition), or other known methods. Preferably, the first semiconductor layer 4 is formed by mist CVD or mist epitaxy. In the mist CVD method or mist epitaxy method, for example, the raw material solution is atomized, causing droplets to float. These atomized droplets are then transported to the first substrate 8 by a carrier gas, and a thermal reaction occurs near the first substrate 8, forming a first semiconductor layer 4 on the first substrate 8.

[0057] In the second semiconductor layer formation process, the second semiconductor layer 5 is formed on the side of the first semiconductor layer 4 opposite to the first substrate 8. In the second semiconductor layer formation process, the second semiconductor layer 5 is formed by, for example, CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, PLD, or ALD, or by other known methods. The second semiconductor layer 5 may be formed by the same method as the first semiconductor layer 4. Preferably, the second semiconductor layer 5 is formed by the mist CVD method or the mist epitaxy method. In the mist CVD method or the mist epitaxy method, for example, the raw material solution is atomized, causing droplets to float. These atomized droplets are then transported onto the first semiconductor layer 4 by a carrier gas, and the atomized droplets undergo a thermal reaction near the first semiconductor layer 4 to form the second semiconductor layer 5.

[0058] In the third electrode formation step, as shown in Figure 5, the third electrode 3 is formed on the side of the second semiconductor layer 5 opposite to the first semiconductor layer 4. The third electrode 3 is formed by, for example, a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, or CVD. Wet methods include, for example, screen printing or die coating. The third electrode 3 may also be formed by other known methods.

[0059] In the bonding process, as shown in Figure 6, the second substrate 9 is bonded to the side of the third electrode 3 opposite to the second semiconductor layer 5. The second substrate 9 is, for example, a metal support substrate. However, the second substrate 9 may be a support substrate other than a metal support substrate. For bonding the second substrate 9 and the third electrode 3, for example, a known conductive adhesive layer is used. The conductive adhesive layer is, for example, an Ag sintered layer. The bonding method is not limited to Ag sintering bonding; other known bonding methods such as room temperature bonding may also be used.

[0060] In the first removal step, the first substrate 8 is removed from the first semiconductor layer 4 by known means such as peeling, as shown in Figure 7. The side of the first semiconductor layer 4 opposite to the second semiconductor layer 5, that is, the side from which the first substrate 8 has been removed, is preferably planarized by CMP (Chemical Mechanical Polishing) or the like before the trench formation step described later.

[0061] In the trench formation process, as shown in Figure 8, a trench 43 is formed on the surface of the first semiconductor layer 4 from which the first substrate 8 has been removed. In the trench formation process, the trench 43 is formed by, for example, the RIE (Reactive Ion Etching) method. More specifically, the trench formation process includes at least etching the first semiconductor layer 4 using a plasma-generated etching gas. In this case, the pressure of the etching gas is preferably, for example, 0.5 Pa or more and 1.5 Pa or less, and more preferably 0.8 Pa or more and 1.2 Pa or less. Furthermore, the etching gas preferably contains at least halogen. Furthermore, it is preferable that the plasma-generated etching gas contains at least oxygen. It is also preferable that the etching is performed in a halogen gas atmosphere. Furthermore, it is preferable that the plasma bias of the etching gas be 25 W or more and 75 W or less. By using such a preferred RIE method, trenches can be easily formed. Note that the method for forming the trench 43 is not limited to the RIE method, and may be formed by other known methods.

[0062] In the high-resistance film formation process, a high-resistance film 6 is formed on the inner surface of the trench 43, as shown in Figure 9. In the high-resistance film formation process, the high-resistance film 6 is formed by, for example, sputtering, vacuum deposition, CVD, ALD, or other known methods.

[0063] In the first electrode and second electrode formation step, as shown in Figure 10, the first electrode 1 and the second electrode 2 are formed on the first semiconductor layer 4 and the high-resistivity film 6. The means for forming the first electrode 1 and the second electrode 2 are, for example, a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, or CVD. Wet methods include, for example, screen printing or die coating. The first electrode 1 and the second electrode 2 may also be formed by other known methods. When the first semiconductor layer 4 contains a metastable phase crystalline oxide semiconductor (e.g., α-Ga2O3), the first electrode 1 and the second electrode 2 are preferably formed at a temperature below 800°C, and more preferably at a temperature below 600°C. The method for manufacturing the semiconductor device 100 is not limited to the method described above.

[0064] In the second removal step, the second substrate 9 is removed from the third electrode 3 by known means, such as peeling. This forms the semiconductor device 100 shown in Figure 1.

[0065] In the semiconductor device 100, when a forward voltage is applied between the Schottky electrode formed by the first electrode 1 and the second electrode 2 and the ohmic electrode, which is the third electrode 3, the energy barrier at the interface between the first electrode 1 and the first semiconductor layer 4 decreases, and current flows from the Schottky electrode to the ohmic electrode. On the other hand, when a reverse voltage is applied between the Schottky electrode and the ohmic electrode, the Schottky barrier makes it difficult for current to flow through the semiconductor device 100. At this time, the depletion layer formed at the interface between the first semiconductor layer 4 and the high-resistivity film 6 expands in the direction away from the second electrode 2 in the first semiconductor layer 4. As a result, the electric field at the interface between the first semiconductor layer 4 and the first electrode 1 is relaxed, and the leakage current is reduced.

[0066] In the semiconductor device 100 of this embodiment described above, the thickness of the high-resistance film 6 is greater on the bottom side of the trench 43 than on the side side. For example, if the thickness of the high-resistance film 6 is the same on the side and bottom sides of the trench 43, the electric field strength at the bottom of the high-resistance film 6 in the first semiconductor layer 4, especially the electric field strength near the corner formed by the bottom and side of the trench 43, tends to be large. However, in this embodiment, the thickness of the high-resistance film 6 is greater on the bottom side of the trench 43. Therefore, the electric field strength at the bottom of the high-resistance film 6 can be reduced, and malfunctions in the high-resistance film 6 are less likely to occur. Also, because the thickness of the high-resistance film 6 on the side side of the trench 43 is small, when a forward voltage is applied to the semiconductor device 100, the electrical resistance in the mesa portion 44 decreases due to the accumulation effect. Therefore, the forward loss of the semiconductor device 100 can be reduced.

[0067] Furthermore, the width W1 of the trench 43 is greater than the width W2 of the mesa portion 44. That is, the width W2 of the mesa portion 44 is smaller than the width W1 of the trench 43. Therefore, when a reverse voltage is applied to the semiconductor device 100 and the depletion layer spreads from the trench 43 to the mesa portion 44, it becomes difficult for current to flow into the mesa portion 44. Thus, the breakdown voltage of the semiconductor device 100 can be improved.

[0068] Furthermore, if the film thickness of the high-resistivity film 6 on the bottom side of the trench 43 is 40% or more of the trench depth, the electric field strength at the bottom of the high-resistivity film 6 can be further reduced.

[0069] In addition, if the dielectric constant is the same on the side and bottom sides of the trench 43 within the high-resistivity film 6, the high-resistivity film 6 can be formed using the same material.

[0070] Furthermore, the carrier density at least at the upper end of the mesa portion 44 is 1.0 × 10⁻⁶ 16 / cm 3 As a result, the electrical resistance of the mesa portion 44 when a forward voltage is applied can be reduced, and forward losses can be further reduced.

[0071] Furthermore, if the depth D of the trench 43 is less than 1.5 μm, the electrical resistance of the mesa portion 44 can be reduced, thereby reducing forward losses. Similarly, if the depth D of the trench 43 is less than or equal to the width of the trench 43, forward losses can also be reduced.

[0072] Furthermore, if the high-resistivity film 6 contains HfO2 or Al2O3, the dielectric constant of the high-resistivity film 6 increases, and the electric field strength of the high-resistivity film 6 can be further reduced when a voltage is applied in the reverse direction.

[0073] Therefore, in this embodiment, it is possible to provide a semiconductor device with excellent electrical characteristics, such as a low rise voltage and high withstand voltage.

[0074] (Other embodiments) Next, an embodiment different from the first embodiment described above will be explained. In the following descriptions of each embodiment, elements common to the first embodiment will be denoted by the same reference numerals, and explanations of matters that overlap with those explained in the first embodiment will be omitted.

[0075] (Second Embodiment) Figure 11 is a schematic cross-sectional view of the semiconductor device 200 according to the second embodiment, and corresponds to Figure 2. In this embodiment, the dielectric constant of the high-resistivity film 6 is greater on the bottom side of the trench 43 than on the side side.

[0076] More specifically, the second part 62 is formed from a material with a higher dielectric constant than the first part 61. For example, the first part 61 is formed from SiO2, and the second part 62 is formed from HfO2. The thickness t3 of the first part 61 and the thickness t4 of the second part 62 are the same. However, the thickness t4 of the second part 62 may be greater than the thickness t3 of the first part 61, or less than the thickness t3 of the first part 61.

[0077] In the semiconductor device 200 of this embodiment, the dielectric constant of the high-resistivity film 6 is greater on the bottom side of the trench 43 than on the side side. Therefore, the electric field at the bottom of the high-resistivity film 6, where the electric field tends to concentrate, can be mitigated, making it less likely for problems to occur in the high-resistivity film 6.

[0078] (Third embodiment) Figure 12 is a schematic cross-sectional view of a semiconductor device 300 according to the third embodiment, and corresponds to Figure 2. The first semiconductor layer 4 of this embodiment includes a crystal defect region 45. The crystal defect region 45 contains crystal defects at a higher density than other parts of the first semiconductor layer 4. Because the crystal defect region 45 contains crystal defects at a higher density, its resistivity is higher than that of other parts of the first semiconductor layer 4. In other words, the crystal defect region 45 can also be called a high-resistivity region. Crystal defects can be observed, for example, by a cross-sectional TEM (transmission electron microscope) image or a cross-sectional SEM (scanning electron microscope) image.

[0079] The crystal defect region 45 is located below the bottom surface of the trench 43, that is, below the bottom of the high-resistance film 6 (i.e., the second portion 62). The crystal defect region 45 may be separate from the high-resistance film 6 or in contact with the high-resistance film 6. The crystal defect region 45 extends linearly in a vertical cross-section. In this disclosure, “linear” includes broad linear shapes, i.e., rod-shaped and strip-shaped shapes. Also, “linear” includes simply elongated shapes and curved shapes. The crystal defect region 45 is formed in a straight line along the bottom of the high-resistance film 6 in a vertical cross-section. The crystal defect region 45 may be formed in a linear shape extending in cross-sections other than the vertical cross-section.

[0080] The density of crystal defects in crystal defect region 45 is 1.0 × 10⁻⁶. 18 / cm 3 Preferably, the above is true. The density of crystal defects in the crystal defect region 45 is 1.0 × 10⁻⁶. 19 / cm 3 The above is 1.0 × 10 20 / cm 3 or more, or 1.0 × 10 21 / cm 3 The above is also acceptable. Furthermore, the density of crystal defects in the crystal defect region 45 is not limited to 1.0 × 10⁻⁶. 18 / cm 3 It is acceptable to be less than [a certain value].

[0081] The crystal defect region 45 contains impurities at a higher density than other parts of the first semiconductor layer 4. The impurities contain elements different from the main elements contained in the first semiconductor layer 4. The impurities may contain only one element or multiple elements. Hereinafter, the elements contained in the impurities will be referred to as "impurity elements" as needed. In this example, the impurities are individual elements. However, the impurities may also be compounds. It is preferable that the impurity elements are elements that do not function as donors or acceptors for the first semiconductor layer 4. In this case, the crystal defect region 45 may contain only impurities among the dopants and impurities, or it may contain both dopants and impurities. All elements in the crystal defect region 45, excluding the impurity elements, may be the same as all elements contained in the first semiconductor layer 4. It is preferable that the impurity elements are metallic elements with a mass number greater than magnesium (Mg). For example, the impurity element is aluminum (Al). However, the impurity elements may also be elements other than aluminum. The concentration of impurity elements in the crystal defect region 45 is, for example, 1.0 × 10⁻⁶ 15 / cm 3 The above 1.0 × 10 22 / cm 3 The following applies. Furthermore, the concentration of impurities within the crystal defect region 45 is not limited.

[0082] Regions of the first semiconductor layer 4 other than the crystal defect region 45 may contain the same impurity elements as those contained in the crystal defect region 45. In this case, the concentration of impurity elements in the crystal defect region 45 is greater than the concentration of impurity elements in the regions of the first semiconductor layer 4 other than the crystal defect region 45. The concentration of impurity elements is measured, for example, using secondary ion mass spectrometry (SIMS). Alternatively, the concentration of impurity elements may be measured by other known methods such as secondary ion mass spectrometry (e.g., NanoSIMS), transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (TEM-EDX), or calculation using a numerical calculation code (SRIM / TRIM). The concentration of impurity elements in the crystal defect region 45 may be greater than the concentration of dopant in the crystal defect region 45. The concentration of impurity elements in the crystal defect region 45 is, for example, 1.0 × 10⁻⁶.17 / cm 3 That's all.

[0083] The crystal defect region 45 is formed, for example, after the trench formation process and before the high-resistance film formation process. The crystal defect region 45 is formed, for example, by ion implantation of impurities into the first semiconductor layer 4. That is, the crystal defect region 45 is formed by ion implantation into the first semiconductor layer 4 of the stacked structure shown in Figure 8. When impurities are implanted into the first semiconductor layer 4, damage is inflicted on the region of the first semiconductor layer 4 through which the impurities pass. The region damaged in this way by ion implantation becomes the crystal defect region 45. The ion implantation may be a box profile or a single profile. The crystal defect region 45 may also be formed by means other than ion implantation. For example, the crystal defect region 45 may be formed by irradiating the first semiconductor layer 4 with protons or helium.

[0084] In this embodiment, by forming a crystal defect region 45 below the bottom surface of the trench 43, the electric field strength at the bottom of the high-resistance film 6 can be further reduced, making it less likely for defects to occur in the high-resistance film 6. The semiconductor device 200 of the second embodiment may also include a crystal defect region similar to the crystal defect region 45 of this embodiment. Furthermore, the semiconductor device 200 of the second embodiment may have a film thickness of the high-resistance film 6 that is greater on the bottom surface of the trench 43 than on the side surface, similar to the first embodiment, and may also include a crystal defect region similar to the crystal defect region 45 of this embodiment.

[0085] (Fourth Embodiment) Figure 13 is a schematic cross-sectional view of a semiconductor device 400 according to the fourth embodiment. The semiconductor device 400 of this embodiment includes a p-type region 46 formed in the first semiconductor layer 4.

[0086] The main component of the p-type region 46 may be the same as or different from the main component of the first semiconductor layer 4. The p-type region 46 is, for example, an oxide semiconductor. It is preferable that the p-type region 46 is crystalline. In this case, the p-type region 46 may be a single crystal, a polycrystalline material, or the like. It is preferable that the p-type region 46 contains an oxide of a first metal. The first metal is, for example, a D-block metal or a Group 13 metal of the periodic table. "D-block" refers to an element that has electrons that fill the 3d, 4d, 5d, and 6d orbitals. Examples of block metals include scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), and lutetium (Lu). These include hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lawrencium (Lr), rutherfordium (Rf), dubnium (Db), seaborgium (Sg), bohrium (Bh), hassium (Hs), meitnerium (Mt), dermstadtium (Ds), roentgenium (Rg), or copernicium (Cn). Group 13 metals include, for example, aluminum, gallium, or indium. The p-type region 46 preferably has a corundum structure or a β-gallia structure, and more preferably has a corundum structure.

[0087] The p-type region 46 may contain an oxide of a first metal and an oxide of a second metal. The second metal is preferably a metal selected from Group 6 and Group 9 of the periodic table. Examples of Group 6 metals include chromium (Cr), molybdenum (Mo), or tungsten (W). Examples of Group 9 metals include cobalt (Co), rhodium (Rh), or iridium (Ir). The p-type region 46 preferably contains a mixed crystal of the oxide of the first metal and the oxide of the second metal, and more preferably the mixed crystal of the oxide of the first metal and the oxide of the second metal is the main component.

[0088] Furthermore, the p-type region 46 may contain a p-type dopant. The p-type dopant is not particularly limited, but examples include magnesium (Mg), zinc (Zn), calcium (Ca), hydrogen (H), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), francium (Fr), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), copper (Cu), silver (Ag), gold (Au), cadmium (Cd), mercury (Hg), thallium (Tl), lead (Pb), nitrogen (N), or phosphorus (P), or two or more of these elements. In addition, the material of the p-type region 46 is not limited and may be a semiconductor other than an oxide semiconductor.

[0089] The p-type region 46 is located below the bottom surface of the trench 43. The p-type region 46 is along the bottom of the high-resistivity film 6 and is in contact with the bottom of the high-resistivity film 6. However, the p-type region 46 may be separated from the high-resistivity film 6.

[0090] In this embodiment, by forming a p-type region 46 below the bottom surface of the trench 43, the electric field strength at the bottom of the high-resistivity film 6 can be further reduced, making it less likely for the high-resistivity film 6 to malfunction. The semiconductor device 200 of the second embodiment may also include a p-type region similar to the p-type region 46 of this embodiment. Furthermore, the semiconductor device 200 of the second embodiment may have a film thickness of the high-resistivity film 6 that is greater on the bottom surface of the trench 43 than on the side surface, similar to the first embodiment, and may also include a p-type region similar to the p-type region 46 of this embodiment.

[0091] Figure 14 is a schematic cross-sectional view showing a modified example of this embodiment. The first semiconductor layer 4 may include a high carrier density region 42a located below the bottom surface of the trench 43 and outside the p-type region 46 in the width direction of the trench 43. The high carrier density region 42a is an n-type region in which the carrier density is greater than that of the other parts of the first semiconductor layer 4. The carrier density of the high carrier density region 42a may be greater than or equal to that of the second semiconductor layer 5. In the example shown in Figure 14, the first semiconductor layer 4 includes high carrier density regions 42a located on both sides of the p-type region 46 in the width direction of the trench 43. The p-type region 46 is located between the two high carrier density regions 42a. Each high carrier density region 42a is in contact with the p-type region 46.

[0092] In this example, the depletion layer can be suppressed from extending from the p-type region 46 to the mesa region 44, and the electrical resistance of the high-carrier-density region 42a becomes smaller than the electrical resistance of other parts of the first semiconductor layer 4. Therefore, the forward characteristics of the semiconductor device 400 can be improved.

[0093] (Fifth embodiment) Figure 15 is a schematic cross-sectional view of a semiconductor device 500 according to the fifth embodiment, and corresponds to Figure 2. In this embodiment, at least the upper end portion 44a of the mesa portion 44 has a lower carrier density compared to other portions of the first semiconductor layer 4. Specifically, the carrier density of the upper end portion 44a is lower than the carrier density of all other portions of the first semiconductor layer 4 except the upper end portion 44a. Also, the carrier density of the upper end portion 44a is 1.0 × 10⁻¹⁰ 16 / cm 3 It is less than . Furthermore, the carrier density at the upper end portion 44a is not limited to 1.0 × 10 16 / cm 3 That's fine too.

[0094] In this embodiment, the carrier density at the upper end portion 44a of the mesa portion 44 is low, and the width of the depletion layer extending over the mesa portion 44 can be increased. As a result, the breakdown voltage of the semiconductor device 400 can be improved.

[0095] Figure 16 is a schematic cross-sectional view showing a modified example of this embodiment. In the example shown in Figure 16, the overall carrier density of the mesa portion 44 is smaller than the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44. In this case as well, "at least the upper portion 44a of the mesa portion 44 has a lower carrier density compared to the rest of the first semiconductor layer 4" is included.

[0096] The carrier density of the mesa portion 44 may decrease gradually or stepwise towards the top. In this case, the carrier density at the upper end 44a of the mesa portion 44 will be lower than the carrier density of the portion of the mesa portion 44 other than the upper end 44a. This case is also included in the statement "at least the upper end 44a of the mesa portion 44 has a lower carrier density compared to the rest of the first semiconductor layer 4". In this case, for example, the carrier density at the upper end 44a of the mesa portion 44 may be lower than the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44, or it may be higher than or equal to the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44. Also, the carrier density at the lower end of the mesa portion 44 may be higher than the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44, or it may be lower than or equal to the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44.

[0097] Furthermore, in each of the semiconductor devices 200 of the second embodiment, 300 of the third embodiment, and 400 of the fourth embodiment, similar to this embodiment and its modifications, the carrier density at least at the upper end 44a of the mesa portion 44 may be lower compared to other parts of the first semiconductor layer 4. Moreover, in each of the semiconductor devices 200 of the second embodiment, 300 of the third embodiment, and 400 of the fourth embodiment, similar to the first embodiment, the thickness of the high-resistivity film 6 is greater on the bottom side of the trench 43 than on the side side, and similar to this embodiment, the carrier density at least at the upper end 44a of the mesa portion 44 may be lower compared to other parts of the first semiconductor layer 4.

[0098] (Sixth Embodiment) Figure 17 is a schematic cross-sectional view of a semiconductor device 600 according to the sixth embodiment. In this embodiment, at least the upper end of the mesa portion 44 has a higher carrier density compared to other parts of the first semiconductor layer 4. Specifically, the overall carrier density of the mesa portion 44 is greater than the carrier density of other parts of the first semiconductor layer 4 other than the mesa portion 44. Furthermore, the carrier density of the mesa portion 44 is 1.0 × 10⁻¹⁴. 16 / cm 3 That concludes the explanation. Furthermore, the carrier density of the mesa portion 44 is not limited to 1.0 × 10⁻⁶. 16 / cm 3 It is acceptable to be less than [a certain value].

[0099] In this embodiment, the carrier density of the mesa portion 44 is high, which reduces the electrical resistance of the mesa portion 44 and improves the forward characteristics of the semiconductor device 400.

[0100] Furthermore, the carrier density of the mesa portion 44 may increase gradually or stepwise towards the top. In this case, the carrier density at the upper end of the mesa portion 44 will be greater than the carrier density of the portion of the mesa portion 44 other than the upper end. This case is also included in the statement "at least the upper end 44a of the mesa portion 44 has a higher carrier density compared to the rest of the first semiconductor layer 4". In this case, for example, the carrier density at the upper end of the mesa portion 44 may be less than the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44, or it may be greater than or equal to the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44. Also, the carrier density at the lower end of the mesa portion 44 may be greater than the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44, or it may be less than or equal to the carrier density of the portion of the first semiconductor layer 4 other than the mesa portion 44. Furthermore, the carrier density at the upper end of the mesa portion 44 may be greater than the carrier density of all other portions of the first semiconductor layer 4 except the upper end of the mesa portion 44.

[0101] Furthermore, in each of the semiconductor devices 200 of the second embodiment, 300 of the third embodiment, and 400 of the fourth embodiment, similar to this embodiment, the carrier density at least at the upper end of the mesa portion 44 may be higher compared to other parts of the first semiconductor layer 4.

[0102] (Seventh Embodiment) Figure 18 is a schematic cross-sectional view of a semiconductor device 700 according to the seventh embodiment. In this embodiment, the depth D of the trench 43 is less than or equal to the width W1 of the trench. Specifically, the depth D of the trench 43 is smaller than the width W1 of the trench. However, the depth D of the trench 43 may be the same as the width W1 of the trench. The width W1 of the trench 43 is, for example, 0.5 μm or more and 2 μm or less. However, the depth D and width W1 of the trench 43 are not limited. The width W2 of the mesa portion 44 is, for example, 0.5 μm or more and 2 μm or less. However, the width W2 of the mesa portion 44 is not limited.

[0103] In this embodiment, the trench width W1 can be increased and the width of the mesa portion 44 can be decreased. Therefore, when a reverse voltage is applied to the semiconductor device 700 and the depletion layer formed at the interface between the mesa portion 44 and the high-resistance film 6 expands towards the mesa portion 44, it becomes even more difficult for current to flow through the mesa portion 44. Thus, the breakdown voltage of the semiconductor device 700 can be further improved. In addition, the depth D of the trench 43 can be decreased and the vertical length of the mesa portion 44 can be shortened. Therefore, the electrical resistance of the mesa portion 44 when a forward voltage is applied to the semiconductor device 700 can be decreased, and the forward loss of the semiconductor device 700 can be reduced. Note that, in each of the semiconductor device 200 of the second embodiment, the semiconductor device 300 of the third embodiment, the semiconductor device 400 of the fourth embodiment, the semiconductor device 500 of the fifth embodiment, and the semiconductor device 600 of the sixth embodiment, the depth D of the trench 43 may be less than or equal to the trench width W1, similar to this embodiment. Furthermore, in each of the semiconductor devices 200 of the second embodiment, 300 of the third embodiment, 400 of the fourth embodiment, 500 of the fifth embodiment, and 600 of the sixth embodiment, the thickness of the high-resistance film 6 is greater on the bottom side of the trench 43 than on the side side, similar to the first embodiment, and the depth D of the trench 43 may be less than or equal to the width W1 of the trench, similar to this embodiment.

[0104] The following is an addendum to this disclosure.

[0105] (Note 1) A semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor containing gallium, having a plurality of trenches and mesa portions between adjacent trenches; a first electrode electrically connected to the mesa portions; a high-resistivity film having a higher resistivity than the semiconductor layer along the inner surface of the trenches; and a second electrode located within the trenches and electrically connected to the first electrode, wherein the thickness of the high-resistivity film is greater on the bottom side of the trenches than on the side side.

[0106] (Note 2) The semiconductor device according to Appendix 1, wherein the width of the trench is greater than the width of the mesa portion.

[0107] (Note 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the high-resistance film has the same dielectric constant on the side and bottom sides of the trench.

[0108] (Note 4) The semiconductor device according to Appendix 1 or Appendix 2, wherein the dielectric constant of the high-resistivity film is greater on the bottom side than on the side side of the trench.

[0109] (Note 5) The semiconductor device according to any one of the appendices 1 to 4, wherein the semiconductor layer is located below the bottom surface of the trench and has a linearly extending crystal defect region in cross-section.

[0110] (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein a p-type region located below the bottom surface of the trench is formed in the semiconductor layer.

[0111] (Note 7) The semiconductor device according to any one of the appendices 1 to 6, wherein at least the upper end of the mesa portion has a carrier density lower than that of the other portion of the semiconductor layer.

[0112] (Note 8) The carrier density at least at the upper end of the mesa portion is 1.0 × 10⁻⁶ 16 / cm 3 A semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is less than [amount missing].

[0113] (Note 9) The semiconductor device according to any one of the appendices 1 to 6, wherein at least the upper end of the mesa portion has a carrier density greater than that of other parts of the semiconductor layer.

[0114] (Note 10) The semiconductor device according to any one of the appendices 1 to 9, wherein the thickness of the high-resistance film on the bottom surface side of the trench is 40% or more of the depth of the trench.

[0115] (Note 11) The semiconductor device according to any one of the appendices 1 to 10, wherein the depth of the trench is less than 1.5 μm.

[0116] (Note 12) The semiconductor device according to any one of the appendices 1 to 11, wherein the depth of the trench is less than or equal to the width of the trench.

[0117] (Note 13) The high-resistance film is a semiconductor device according to any one of the appendices 1 to 12, comprising HfO2 or Al2O3.

[0118] (Note 14) A semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor containing gallium, having a plurality of trenches and mesa portions between adjacent trenches; a first electrode electrically connected to the mesa portions; a high-resistivity film along the inner surface of the trenches, having a higher resistivity than the semiconductor layer; and a second electrode located within the trenches and electrically connected to the first electrode, wherein the dielectric constant of the high-resistivity film is higher on the bottom side of the trenches than on the side side.

[0119] (Note 15) A semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor containing gallium, having a plurality of trenches and mesa portions between adjacent trenches; a first electrode electrically connected to the mesa portions; a high-resistance film along the inner surface of the trenches; and a second electrode located within the trenches and electrically connected to the first electrode, wherein the high-resistance film has a first portion and a second portion having a greater dielectric constant than the first portion, and the lower end of the second portion is located below the lower end of the first portion.

[0120] (Note 16) A semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor containing gallium, having a plurality of trenches and mesa portions between adjacent trenches; a first electrode electrically connected to the mesa portions; a high-resistance film along the inner surface of the trenches; and a second electrode located within the trenches and electrically connected to the first electrode, wherein the semiconductor layer has a crystalline defect region located below the bottom surface of the trenches and extending linearly in cross-section.

[0121] (Note 17) A semiconductor device comprising a plurality of trenches and mesa portions between adjacent trenches, an n-type semiconductor layer containing a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portions, a high-resistance film along the inner surface of the trenches, and a second electrode located within the trenches and electrically connected to the first electrode, wherein a p-type region is formed in the semiconductor layer located below the bottom surface of the trenches. [Explanation of Symbols]

[0122] D Depth W1 width W2 width t2 thickness t1 Thickness t3 film thickness t4 film thickness t5 thickness 1 1st electrode 2 2nd electrode 3 Third electrode 4. First semiconductor layer (semiconductor layer) 42a: High carrier density region 43: Trench 44: Mesa Club 44a: Upper end 45: Crystal defect region 46 :p-type region 5. Second Semiconductor Layer 6 High resistance film 61 :1st part 62:Second part 8. First substrate 9. Second circuit board 100: Semiconductor Device 200: Semiconductor equipment 300: Semiconductor equipment 400: Semiconductor Equipment 500: Semiconductor equipment 600: Semiconductor Device 700: Semiconductor Equipment

Claims

1. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity compared to the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, The semiconductor device wherein the thickness of the high-resistance film is greater on the bottom side of the trench than on the side side.

2. The semiconductor device according to claim 1, wherein the width of the trench is greater than the width of the mesa portion.

3. The semiconductor device according to claim 2, wherein the dielectric constant of the high-resistance film is the same on the side and bottom sides of the trench.

4. The semiconductor device according to claim 2, wherein the dielectric constant of the high-resistivity film is greater on the bottom side of the trench than on the side side.

5. The semiconductor device according to any one of claims 2 to 4, wherein the semiconductor layer is located below the bottom surface of the trench and has a linearly extending crystal defect region in cross-section.

6. The semiconductor device according to any one of claims 2 to 4, wherein a p-type region located below the bottom surface of the trench is formed in the semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 4, wherein at least the upper end of the mesa portion has a lower carrier density compared to other parts of the semiconductor layer.

8. The carrier density at least at the upper end of the mesa portion is 1.0 × 10⁻⁶ １６ / cm ３ The semiconductor device according to claim 7, which is less than [amount missing].

9. The semiconductor device according to any one of claims 1 to 4, wherein at least the upper end of the mesa portion has a carrier density greater than other parts of the semiconductor layer.

10. The semiconductor device according to any one of claims 1 to 4, wherein the thickness of the high-resistivity film on the bottom surface side of the trench is 40% or more of the depth of the trench.

11. The semiconductor device according to any one of claims 1 to 4, wherein the depth of the trench is 1.5 μm or less.

12. The semiconductor device according to any one of claims 1 to 4, wherein the depth of the trench is less than or equal to the width of the trench.

13. The aforementioned high-resistivity film is HfO ２ or Al ２ O ３ A semiconductor device according to any one of claims 1 to 4, including the following:

14. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity than the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, The semiconductor device wherein the high-resistance film has a greater film thickness on the bottom side of the trench than on the side side, and the dielectric constant is the same on the side and bottom sides of the trench.

15. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity than the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, The dielectric constant of the high-resistivity film is greater on the bottom side of the trench than on the side side of the trench.

16. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity than the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, The high-resistance film has a first portion and a second portion having a greater dielectric constant than the first portion. The lower end of the second portion is a semiconductor device located below the lower end of the first portion.

17. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity than the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, The semiconductor layer is a semiconductor device having a linear crystal defect region located below the bottom surface of the trench.

18. The n-type semiconductor layer comprises a crystalline oxide semiconductor containing gallium, having a plurality of trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity than the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, A semiconductor device having a p-type region formed in the semiconductor layer, located below the bottom surface of the trench.

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