Semiconductor equipment

Abstract

The objective is to provide semiconductor devices that are less prone to malfunctions. [Solution] A semiconductor device comprising a semiconductor layer having a plurality of trenches and mesa portions between adjacent trenches, and containing a crystalline oxide semiconductor containing gallium; a first electrode electrically connected to the mesa portion; a high-resistance film along the inner surface of the trenches; a second electrode located within the trenches and electrically connected to the first electrode; and a carrier discharge portion in contact with the second electrode and the bottom surface of the trenches, for discharging carriers to the second electrode.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a trench MOS type Schottky diode. The Schottky diode comprises a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer and having a trench, a cathode electrode formed on the first semiconductor layer, an insulating film covering the inner surface of the trench, and a trench MOS gate embedded in the trench so as to cover the insulating film and in contact with the anode electrode. It should be noted that mere mention in the background art does not automatically mean that it is prior art. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-087348 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this disclosure aims to solve is to provide a semiconductor device that is less prone to malfunctions. [Means for solving the problem]

[0005] To solve the above problems, in one embodiment of the present disclosure, a semiconductor device comprises a semiconductor layer having a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer containing a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistivity film along the inner surface of the trench and having a higher resistivity than the semiconductor layer, a second electrode located in the trench and electrically connected to the first electrode, and a carrier discharge portion in contact with the second electrode and the bottom surface of the trench and discharging carriers to the second electrode.

[0006] In another aspect of the present disclosure, a semiconductor device includes a plurality of trenches and mesa portions between adjacent trenches, a semiconductor layer including a crystalline oxide semiconductor containing gallium, a first electrode electrically connected to the mesa portion, a high-resistance film along the inner surface of the trench and having a higher resistivity than the semiconductor layer, and a second electrode located in the trench and electrically connected to the first electrode. The semiconductor layer is located below the bottom surface of the trench and has a crystal defect region linearly extending in a cross section.

Advantages of the Invention

[0007] According to the present disclosure, a semiconductor device that is less likely to have problems can be provided.

Brief Description of the Drawings

[0008] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a partially enlarged view of FIG. 1. [Figure 3] FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device. [Figure 4] FIG. 4 is a cross-sectional view schematically showing a laminated structure including a first semiconductor layer, a second semiconductor layer, and a first substrate. [Figure 5] FIG. 5 is a cross-sectional view schematically showing a laminated structure including a first semiconductor layer, a second semiconductor layer, a third electrode, and a first substrate. [Figure 6] FIG. 6 is a cross-sectional view schematically showing a laminated structure including a first semiconductor layer, a second semiconductor layer, a third electrode, a first substrate, and a second substrate. [Figure 7] FIG. 7 is a cross-sectional view schematically showing a laminated structure including a first semiconductor layer, a second semiconductor layer, a third electrode, and a second substrate. [Figure 8] FIG. 8 is a cross-sectional view schematically showing a laminated structure including a first semiconductor layer, a second semiconductor layer, a second substrate, and a third electrode in which trenches are formed. [Figure 9]Figure 9 is a schematic cross-sectional view showing a multilayer structure including a first semiconductor layer, a second semiconductor layer, a second substrate, a third electrode, and a high-resistivity film. [Figure 10] Figure 10 is a schematic cross-sectional view showing a multilayer structure including a semiconductor layer, a third electrode, a second substrate, a high-resistivity film, and a carrier discharge section. [Figure 11] Figure 11 is a schematic cross-sectional view of a laminated structure including a semiconductor layer, a first electrode, a second electrode, a third electrode, a second substrate, a high-resistivity film, and a carrier discharge section. [Figure 12] Figure 12 is a schematic cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 14] Figure 14 is a schematic cross-sectional view showing a modified semiconductor device. [Figure 15] Figure 15 is a schematic cross-sectional view showing another modified semiconductor device. [Modes for carrying out the invention]

[0009] Embodiments of the semiconductor device described herein will be explained below with reference to the drawings. However, the invention claimed is not limited to these embodiments. Furthermore, not all combinations of configurations described in the embodiments are considered essential for solving the problem. Each configuration in this disclosure is described to the extent that it does not hinder the solution of the problem of this disclosure. Additionally, identical components are denoted by the same reference numerals to avoid redundant explanations.

[0010] Furthermore, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily depicted to a constant scale, even if not explicitly stated herein. Also, note that a feature in one embodiment may be used in another. Descriptions of well-known elements and manufacturing techniques may be omitted so as not to unnecessarily obscure the embodiments of this disclosure. The examples used herein are solely for the purpose of aiding understanding of this disclosure and enabling those skilled in the art to implement the embodiments. Therefore, the embodiments and examples herein are not to be construed as being limited to the scope of this disclosure, but are determined solely by the claims and applicable law.

[0011] The terms "first," "second," etc., are used to describe various elements used herein, but the elements are not limited by these terms. The terms "first," "second," etc., are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and the second element may be referred to as the first element. As used herein, the term "and / or" encompasses one or more, or any combination of, the listed items.

[0012] In this disclosure, each of the terms “equipment,” “possess,” and “includes” indicates the presence of the described element, and does not exclude the presence of one or more other elements. Where the expression “connected” or “combined” an element is used in this disclosure, it should be understood that the element may be directly connected to or combined with another element, or there may be an intervening element.

[0013] The semiconductor device described herein is useful for various semiconductor elements, and is particularly useful for power devices. The semiconductor device may be a lateral device in which electrodes are formed only on one side of the semiconductor layer, or a vertical device in which electrodes are formed on both the front and back sides of the semiconductor layer. Examples of semiconductor devices include their application to a part of the element structure of diodes, transistors (e.g., MOSFETs), or semiconductor light-emitting elements.

[0014] (First Embodiment) Figure 1 is a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment. The semiconductor device 100 is a Schottky barrier diode, and more specifically, a vertical trench MOS type Schottky barrier diode.

[0015] The semiconductor device 100 comprises a semiconductor layer 4, a high-resistivity film 6, a carrier discharge section 7, a first electrode 1, and a second electrode 2. In this disclosure, the direction parallel to the thickness direction of the semiconductor layer 4 is defined as the "upper direction." One direction parallel to the thickness direction of the semiconductor layer 4 is defined as "upward," and the direction opposite to upward is defined as "downward." These directions do not limit the direction of gravity or the direction of mounting the semiconductor device to a substrate during mounting. In this disclosure, the surface of a layer, substrate, or other component facing upward is described as the upper surface, and the surface facing downward is described as the lower surface. When expressions such as a layer, region, or substrate exist "on top of" or "below" another element are used, it should be understood that it may exist directly on top of or below another element, or the element may exist between other elements. In this disclosure, a cross section perpendicular to the upper surface of the semiconductor layer 4, that is, a cross section parallel to the up-down direction, is referred to as the "vertical cross section."

[0016] The semiconductor device 100 may further include a semiconductor layer 5 separate from the semiconductor layer 4 and a third electrode 3. Hereinafter, the semiconductor layer 4 will be referred to as the first semiconductor layer 4, and the other semiconductor layer 5 will be referred to as the second semiconductor layer 5. The first semiconductor layer 4 is an example of a semiconductor layer. The first semiconductor layer 4 is formed on the second semiconductor layer 5. The conductivity type of the first semiconductor layer 4 and the conductivity type of the second semiconductor layer 5 are the same. In this example, each of the first semiconductor layer 4 and the second semiconductor layer 5 is an n-type semiconductor. The second semiconductor layer 5 has a carrier density greater than that of the first semiconductor layer 4. That is, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 5 is an n+-type semiconductor layer. Note that the first semiconductor layer 4 may be a p-type semiconductor. That is, the first semiconductor layer 4 may be a p-type semiconductor layer, and the second semiconductor layer 5 may be a p+-type semiconductor.

[0017] The first semiconductor layer 4 contains a crystalline oxide semiconductor. Preferably, the first semiconductor layer 4 contains a crystalline oxide semiconductor as its main component. In this disclosure, "contains as a main component" means containing 50 atomic percent or more of the total. Preferably, the first semiconductor layer 4 contains 70 atomic percent or more of the crystalline oxide semiconductor, and more preferably 90 atomic percent or more. The first semiconductor layer 4 may contain 100 atomic percent of the crystalline oxide semiconductor. In this case as well, it is included in containing a crystalline oxide semiconductor as its main component.

[0018] The second semiconductor layer 5 is in contact with the lower surface of the first semiconductor layer 4. The second semiconductor layer 5 preferably contains a crystalline oxide semiconductor. The main components of the first semiconductor layer 4 and the second semiconductor layer 5 are preferably the same. However, the main components of the first semiconductor layer 4 and the second semiconductor layer 5 may be different.

[0019] Preferably, each of the first semiconductor layer 4 and the second semiconductor layer 5 contains a crystalline oxide semiconductor as its main component. Hereinafter, unless otherwise specified, the crystalline oxide semiconductor of each of the first semiconductor layer 4 and the second semiconductor layer 5 will simply be referred to as "crystalline oxide semiconductor".

[0020] Crystalline oxide semiconductors are, for example, metal oxides. The metals included in the metal oxide are, for example, one or more metals selected from gallium (Ga), aluminum (Al), indium (In), iron (Fe), chromium (Cr), vanadium (V), titanium (Ti), rhodium (Rh), nickel (Ni), cobalt (Co), and iridium (Ir). It is preferable that the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium. It is particularly preferable that the crystalline oxide semiconductor is a metal oxide containing gallium. The crystalline oxide semiconductor may also be an InAlGaO-based semiconductor containing indium and / or aluminum in addition to gallium. In this disclosure, InAlGaO-based semiconductor means In X Al Y Ga Z O3 means (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5).

[0021] Crystalline oxide semiconductors are, for example, single crystals. However, crystalline oxide semiconductors may also be polycrystalline. Crystalline oxide semiconductors have a corundum structure as their crystal structure. However, the crystal structure of crystalline oxide semiconductors is not limited to a corundum structure. The crystal structure of crystalline oxide semiconductors may be, for example, a β-Gallia structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), or a cubic structure (e.g., a γ-type or δ-type structure).

[0022] The crystalline oxide semiconductor is preferably gallium oxide (Ga2O3) or a mixed crystal containing gallium oxide and other metal oxides. More preferably, the crystalline oxide semiconductor is α-Ga2O3 or a mixed crystal containing α-Ga2O3 and other metal oxides. Examples of other metal oxides include aluminum oxide (Al2O3), indium oxide (In2O3), iridium oxide (IrO2), rhodium oxide (Rh2O3), chromium oxide (Cr2O3), or iron oxide (Fe2O3). The crystalline oxide semiconductor preferably contains 1 atomic percent or more of the other metal oxide. More preferably, the crystalline oxide semiconductor contains 5 atomic percent or more of the other metal oxide, and even more preferably, 10 atomic percent or more. In this example, the crystalline oxide semiconductor is gallium oxide (Ga2O3).

[0023] Each of the first semiconductor layer 4 and the second semiconductor layer 5 may contain a dopant. In this disclosure, a dopant means an element that is donored or acceptored. The dopant may be a known dopant. If each of the first semiconductor layer 4 and the second semiconductor layer 5 is an n-type semiconductor, each of the first semiconductor layer 4 and the second semiconductor layer 5 contains, as an n-type dopant, for example, tin (Sn), germanium (Ge), silicon (Si), titanium, zirconium (Zr), vanadium or niobium (Nb), or two or more of these elements. The n-type dopant is preferably tin, germanium or silicon. If each of the first semiconductor layer 4 and the second semiconductor layer 5 is a p-type semiconductor, each of the first semiconductor layer 4 and the second semiconductor layer 5 contains, for example, magnesium (Mg), zinc (Zn), calcium (Ca), hydrogen (H), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), francium (Fr), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), copper (Cu), silver (Ag), gold (Au), cadmium (Cd), mercury (Hg), thallium (Tl), lead (Pb), nitrogen (N), or phosphorus (P), or two or more of these elements as a p-type dopant. The dopant content of each of the first semiconductor layer 4 and the second semiconductor layer 5 is preferably 0.000001 atomic percent or more. More preferably, the dopant content of each of the first semiconductor layer 4 and the second semiconductor layer 5 is 0.000001 atomic percent or more and 20 atomic percent or less, and most preferably 0.00001 atomic percent or more and 10 atomic percent or less.

[0024] The carrier density of each of the first semiconductor layer 4 and the second semiconductor layer 5 can be appropriately set, for example, by adjusting the doping amount. The carrier density in each of the first semiconductor layer 4 and the second semiconductor layer 5 is uniform. In the present disclosure, "uniform" includes not only the case of being completely uniform but also the case of being slightly different. That is, it is sufficient that it is substantially uniform. The carrier density of each of the first semiconductor layer 4 and the second semiconductor layer 5 may be non-uniform. Considering both the forward loss and the breakdown voltage of the semiconductor device 100, the carrier density of the first semiconductor layer 4 is preferably 1×10 15 / cm 3 or more and 1×10 17 / cm 3 or less. The carrier density of the first semiconductor layer 4 may exceed 1×10 17 / cm 3 or may be less than 1×10 15 / cm 3 . Considering the forward loss of the semiconductor device 100, the carrier density of the second semiconductor layer 5 is preferably 1×10 17 / cm 3 or more and 1×10 22 / cm 3 or less. The carrier density of the second semiconductor layer 5 may exceed 1×10 22 / cm 3 or may be less than 1×10 17 / cm 3 .

[0025] FIG. 2 is a partial enlarged view of FIG. 1. The first semiconductor layer 4 has a plurality of trenches 43 and mesa portions 44 between adjacent trenches 43. The plurality of trenches 43 are formed on one surface in the thickness direction of the first semiconductor layer 4. In this example, the plurality of trenches 43 are formed on the upper surface of the first semiconductor layer 4. The trench 43 extends in a direction orthogonal to the vertical cross section. The trench 43 opens upward.

[0026] The trench 43 has a bottom surface located at the lower end of the trench 43, sides located on both sides in the width direction of the trench 43, and corners located on both sides in the width direction of the trench 43. The corners are the connection points between the bottom surface and the sides of the trench 43. The corners have an arc shape in their vertical cross-section. The bottom surface and the sides of the trench 43 are connected via corners so as not to form sharp angles. However, the bottom surface and each side of the trench 43 may be connected via corners that do have sharp angles.

[0027] The mesa portion 44 is a part of the first semiconductor layer 4 that protrudes above the bottom surface of the trench 43. The width of the trench 43 may be the same as the width of the mesa portion 44, or it may be greater than the width of the mesa portion 44, or it may be less than the width of the mesa portion 44.

[0028] The high-resistivity film 6 is provided individually in each of the multiple trenches 43. The resistivity of the high-resistivity film 6 is greater than the resistivity of the first semiconductor layer 4. The resistivity of the high-resistivity film 6 is 1 × 10⁻⁶ 6 It is preferable that it be Ω·cm or more, 1 × 10 10 It is even more preferable that the resistivity is Ω·cm or greater. The resistivity of the high-resistivity film 6 is 1 × 10⁻⁶. 6 The resistance may be less than Ω·cm. The high-resistance film 6 is preferably semi-insulating or insulating. In this example, the high-resistance film 6 is an insulating film. The insulating film may also be called a dielectric film. The high-resistance film 6 may be, for example, a semiconductor film or an undoped film having a carrier density lower than that of the first semiconductor layer 4.

[0029] High-resistivity films 6 include, for example, Ga2O3, (AlGa)2O3, InAlGaO, AlInZnGaO4, AlN, HfO2, and HfSi. x O yIt includes ZrO2, SiN, SiON, Al2O3, MgO, GdO, SiO2, or Si3N4. The resistivity of the high-resistivity film 6 can be adjusted to a predetermined value depending, for example, on impurities contained in the high-resistivity film 6 and the manufacturing process of the high-resistivity film 6. By using such a high-resistivity film 6, the semiconductor properties of the semiconductor device 100 can be made to appear in good condition. To increase the dielectric constant of the high-resistivity film 6, the high-resistivity film 6 contains HfO 2、 HfSi x O y It is preferable that the layer contains ZrO2, Al2O3, or SiO2. The high-resistivity film 6 is particularly preferably HfO2 or Al2O3, and in this example, it is HfO2. The lifetime field of the high-resistivity film 6 is lower than the breakdown field of the first semiconductor layer 4. However, the lifetime field of the high-resistivity film 6 may be higher than or equal to the breakdown field of the first semiconductor layer 4.

[0030] The high-resistivity film 6 follows the inner surface of the trench 43 and covers a portion of its inner surface. Specifically, the high-resistivity film 6 has two first portions 61 located on both sides of the trench 43 (i.e., one side and the other side of the trench 43) and a second portion 62 located on the bottom side of the trench 43. The first portions 61 and the second portions 62 are formed integrally. The high-resistivity film 6 does not have to be formed on the upper part of the side surface of the trench 43. That is, the high-resistivity film 6 may be formed only on the lower part of the side surface of the trench 43. Also, the first portions 61 and the second portions 62 may be formed separately. In that case, the resistivity of the high-resistivity film 6 may be formed differently for the first portion 61 and the second portion 62. The resistivity of the first portion 61 may be lower or higher than that of the second portion 62.

[0031] The two first parts 61 are spaced apart from each other in the width direction of the trench 43. The first parts 61 extend along the corresponding sides of the trench 43. The first parts 61 cover the corresponding sides of the trench 43.

[0032] The second portion 62 extends along the bottom surface of the trench 43. The second portion 62 covers a portion of the bottom surface of the trench 43. The ends of the second portion 62 in the width direction of the trench 43 are connected to the lower ends of the two first portions 61, respectively. The portion of the high-resistivity film 6 that protrudes upward from the second portion 62 is the first portion 61. Each of the first portion 61 and the second portion 62 has a thickness. The thickness of the first portion 61 and the thickness of the second portion 62 may be the same. The thickness of the first portion 61 may be less than or greater than the thickness of the second portion 62. Forming the second portion 62 thicker can suppress the reduction in reliability at high electric field strengths applied to the corners of the trench 43.

[0033] The connection between the first portion 61 and the second portion 62 is preferably formed in an arc shape along the corner of the trench 43. That is, the first portion 61 and the second portion 62 are preferably connected via an arc-shaped connection so that no corner is formed. In this case, the electric field strength of the connection can be reduced.

[0034] The second portion 62 has an opening 63 that penetrates vertically. In this example, the second portion 62 is divided into two parts: one located on one side of the trench 43 and the other located on the other side of the trench 43, with the opening 63 formed between these two parts. The opening 63 may also be a hole, in which case the second portion 62 is not divided by the opening 63. The opening 63 is located in the middle of the width direction of the bottom surface of the trench 43. In this disclosure, "middle" means the position between the two ends. That is, the opening 63 may be formed at the center of the width direction of the bottom surface of the trench 43, or at a position offset from the center. The portion of the bottom surface of the trench 43 other than the portion corresponding to the opening 63, i.e., both ends of the bottom surface of the trench 43 in the width direction, is covered by the two portions of the second portion 62.

[0035] The first electrode 1 is formed on the upper surface of the mesa portion 44, that is, on the upper surface of the first semiconductor layer 4, excluding the portion where the multiple trenches 43 are formed. The first electrode 1 is Schottky bonded to the upper surface of the mesa portion 44. As a result, a Schottky barrier is formed between the first electrode 1 and the mesa portion 44.

[0036] The second electrode 2 is provided individually in each of the multiple trenches 43. The first electrode 1 and the second electrode 2 are electrically connected. In this example, the first electrode 1 and the second electrode 2 form a Schottky electrode. The second electrode 2 is formed integrally with the first electrode 1. In Figures 1 and 2, for convenience, the boundary between the first electrode 1 and the second electrode 2 is shown with a dashed line, but the boundary between the first electrode 1 and the second electrode 2 does not need to be clearly visible externally. Also, the first electrode 1 and the second electrode 2 may be formed as separate components.

[0037] It is preferable that the first electrode 1 and the second electrode 2 are formed from the same material. However, the first electrode 1 and the second electrode 2 may be formed from different materials. The materials of the first electrode 1 and the second electrode 2 may be conductive inorganic materials or conductive organic materials. It is preferable that each of the first electrode 1 and the second electrode 2 is a metal or contains a metal. The metal is, for example, at least one metal selected from groups 4 to 12 of the periodic table. The "periodic table" refers to the periodic table defined by the International Union of Pure and Applied Chemistry (IUPAC). Examples of metals in group 4 of the periodic table are titanium (Ti), zirconium (Zr), or hafnium (Hf). Examples of metals in group 5 of the periodic table are vanadium (V), niobium (Nb), or tantalum (Ta). Metals in Group 6 of the periodic table include, for example, chromium (Cr), molybdenum (Mo), or tungsten (W). Metals in Group 7 of the periodic table include, for example, manganese (Mn), technetium (Tc), or rhenium (Re). Metals in Group 8 of the periodic table include, for example, iron (Fe), ruthenium (Ru), or osmium (Os). Metals in Group 9 of the periodic table include, for example, cobalt (Co), rhodium (Rh), or iridium (Ir). Metals in Group 10 of the periodic table include, for example, nickel (Ni), palladium (Pd), or platinum (Pt). Metals in Group 11 of the periodic table include, for example, copper (Cu), silver (Ag), or gold (Au). Metals in Group 12 of the periodic table include, for example, zinc (Zn), cadmium (Cd), or mercury (Hg). The work function of the metal is preferably 4.0 eV to 5.0 eV. The materials of the first electrode 1 and the second electrode 2 are not limited and may be silicides or other compounds.

[0038] The second electrode 2 is located within the trench 43. In this disclosure, "located within the trench 43" means that at least a portion of the second electrode 2 is located within the trench 43. In this example, the second electrode 2 has a portion located within the trench 43 and a portion that extends above the trench 43. The second electrode 2 may have only a portion located within the trench 43. The portion of the second electrode 2 located within the trench 43 is in contact with the first portion 61 and the second portion 62 of the high-resistivity film 6.

[0039] The carrier discharge section 7 is provided in the second portion 62 of the high-resistivity film 6. Specifically, the carrier discharge section 7 is formed in the opening 63 of the high-resistivity film 6. The carrier discharge section 7 discharges carriers to the second electrode 2. That is, the carrier discharge section 7 discharges holes to the second electrode 2. The carrier discharge section 7 is located between the second electrode 2 and the bottom surface of the trench 43.

[0040] In this example, the carrier discharge section 7 is a semiconductor with a conductivity type different from that of the first semiconductor layer 4. That is, the carrier discharge section 7 is a p-type semiconductor. However, if the first semiconductor layer 4 is a p-type semiconductor, the carrier discharge section 7 may be an n-type semiconductor. In this case, the carrier discharge section 7 discharges electrons as carriers to the second electrode 2.

[0041] The carrier discharge section 7 is preferably crystalline. The carrier discharge section 7 may be a single crystal, a polycrystalline material, or the like. However, the carrier discharge section 7 does not have to be crystalline. The main component of the carrier discharge section 7 may be the same as or different from the main component of the first semiconductor layer 4.

[0042] The carrier discharge section 7 is preferably an oxide semiconductor. It is even more preferable that the carrier discharge section 7 is a crystalline oxide semiconductor. However, the carrier discharge section 7 is not limited to an oxide semiconductor.

[0043] The carrier discharge section 7 preferably contains an oxide of a first metal. The first metal is, for example, a D-block metal or a Group 13 metal of the periodic table. "D-block" refers to an element that has electrons filling the 3d, 4d, 5d, and 6d orbitals. Examples of d-block metals include scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), and lutetium (Lu). Examples of Group 13 metals include hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lawrencium (Lr), rutherfordium (Rf), dubnium (Db), seaborgium (Sg), bohrium (Bh), hassium (Hs), meitnerium (Mt), dermstadtium (Ds), roentgenium (Rg), or copernicium (Cn). Group 13 metals include, for example, aluminum, gallium, or indium. The first metal preferably has a corundum structure or a β-gallia structure, and more preferably a corundum structure.

[0044] The carrier discharge section 7 may contain an oxide of a second metal in addition to the oxide of the first metal. The second metal is preferably a metal selected from Group 6 and Group 9 metals of the periodic table. Examples of Group 6 metals include chromium (Cr), molybdenum (Mo), or tungsten (W). Examples of Group 9 metals include cobalt (Co), rhodium (Rh), or iridium (Ir). The carrier discharge section 7 preferably contains a mixed crystal of the oxide of the first metal and the oxide of the second metal, and more preferably has a mixed crystal of the oxide of the first metal and the oxide of the second metal as its main component.

[0045] The carrier discharge section 7 may contain a dopant. That is, if the carrier discharge section 7 is a p-type semiconductor, it may contain a p-type dopant, and if the carrier discharge section 7 is an n-type semiconductor, it may contain an n-type dopant. Examples of the p-type and n-type dopants contained in the carrier discharge section 7 include the dopants contained in the first semiconductor layer 4 and the second semiconductor layer 5, respectively.

[0046] The lower surface of the carrier discharge section 7 is substantially flush with the lower surface of the second portion 62 of the high-resistivity film 6. The upper surface of the carrier discharge section 7 is substantially flush with the upper surface of the second portion 62 of the high-resistivity film 6. The carrier discharge section 7 is in contact with the first semiconductor layer 4 and the second electrode 2. More specifically, the lower surface of the carrier discharge section 7 is in contact with the bottom surface of the trench 43. The upper surface of the carrier discharge section 7 is in contact with the lower surface of the second electrode 2.

[0047] As shown in Figure 1, the third electrode 3 is formed on the lower surface of the second semiconductor layer 5. In this example, the third electrode 3 is ohmic junctioned with the second semiconductor layer 5. That is, the third electrode 3 is an ohmic electrode.

[0048] The material of the third electrode 3 may be a conductive inorganic material or a conductive organic material. Preferably, the third electrode 3 is a metal. The metal of the third electrode 3 may be the same as or different from the metal of the first electrode 1 or the second electrode 2. For example, the metal of the third electrode 3 is at least one metal selected from groups 4 to 12 of the periodic table.

[0049] Next, an example of a method for manufacturing the semiconductor device 100 will be described. Figure 3 is a flowchart showing the method for manufacturing the semiconductor device 100. Figures 4 to 11 are cross-sectional views showing the method for manufacturing the semiconductor device 100 in order. Note that Figures 4 to 6 show the stacked structure inverted.

[0050] A method for manufacturing a semiconductor device 100 includes a semiconductor layer formation step of forming a first semiconductor layer 4 and a second semiconductor layer 5 on a first substrate 8, a third electrode formation step of forming a third electrode 3 on the second semiconductor layer 5, a bonding step of bonding a second substrate 9 to the third electrode 3, a first removal step of removing the first substrate 8, a trench formation step of forming a trench 43 in the first semiconductor layer 4, a high-resistance film formation step of forming a high-resistance film 6 in the trench 43 of the first semiconductor layer 4, a carrier discharge section formation step of forming a carrier discharge section 7, and a first electrode / second electrode formation step of forming a first electrode 1 and a second electrode 2 on the first semiconductor layer 4. The method for manufacturing a semiconductor device 100 may further include a second removal step of removing the second substrate 9 from the third electrode 3.

[0051] The first substrate 8 (see Figure 4) is, for example, a base substrate. The first substrate 8 may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate.

[0052] The first substrate 8 is, for example, a sapphire substrate, a gallium oxide substrate, a SiC substrate, a ZnO substrate, or a GaN substrate, or a substrate containing gallium oxide and aluminum oxide. Preferably, the first substrate 8 is mainly composed of a material having a corundum structure, a β-gallia structure, or a hexagonal crystal structure. A material having a corundum structure is, for example, α-Al2O3 or α-Ga2O3. A first substrate 8 formed from a material having a corundum structure is, for example, an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, or an α-type gallium oxide substrate (a-plane, m-plane, r-plane, or c-plane). A first substrate 8 formed from a material having a β-gallia structure is, for example, a β-Ga2O3 substrate. The first substrate 8 may also be a mixed crystal substrate containing Ga2O3 and Al2O3, with Al2O3 being more than 0 wt% and 60 wt% or less. The first substrate 8, formed from a substrate material having a hexagonal crystal structure, is, for example, a SiC substrate, a ZnO substrate, or a GaN substrate. The material and crystal structure of the first substrate 8 are not limited and may be known materials.

[0053] The semiconductor layer formation process includes a first semiconductor layer formation step of forming a first semiconductor layer 4 on a first substrate 8, and a step of forming a second semiconductor layer 5 on the first semiconductor layer 4.

[0054] In the first semiconductor layer formation process, a first semiconductor layer 4 is formed on one surface of the first substrate 8 in the thickness direction. In the first semiconductor layer formation process, the first semiconductor layer 4 is formed by, for example, CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MOVPE (Metal Organic Vapor Phase Epitaxy), mist CVD, mist epitaxy, MBE (Molecular Beam Epitxy), HVPE (Hydride Vapor Phase Epitaxy), PLD (Pulsed Laser Deposition), or ALD (Atomic Layer Deposition), or other known methods. Preferably, the first semiconductor layer 4 is formed by mist CVD or mist epitaxy. In the mist CVD method or mist epitaxy method, for example, the raw material solution is atomized, causing droplets to float. These atomized droplets are then transported to the first substrate 8 by a carrier gas, and a thermal reaction occurs near the first substrate 8, forming a first semiconductor layer 4 on the first substrate 8.

[0055] In the second semiconductor layer formation process, the second semiconductor layer 5 is formed on the side of the first semiconductor layer 4 opposite to the first substrate 8. In the second semiconductor layer formation process, the second semiconductor layer 5 is formed by, for example, CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, PLD, or ALD, or by other known methods. The second semiconductor layer 5 may be formed by the same method as the first semiconductor layer 4. Preferably, the second semiconductor layer 5 is formed by the mist CVD method or the mist epitaxy method. In the mist CVD method or the mist epitaxy method, for example, the raw material solution is atomized, causing droplets to float. These atomized droplets are then transported onto the first semiconductor layer 4 by a carrier gas, and the atomized droplets undergo a thermal reaction near the first semiconductor layer 4 to form the second semiconductor layer 5.

[0056] In the third electrode formation step, as shown in Figure 5, the third electrode 3 is formed on the side of the second semiconductor layer 5 opposite to the first semiconductor layer 4. The third electrode 3 is formed by, for example, a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, or CVD. Wet methods include, for example, screen printing or die coating. The third electrode 3 may also be formed by other known methods.

[0057] In the bonding process, as shown in Figure 6, the second substrate 9 is bonded to the side of the third electrode 3 opposite to the second semiconductor layer 5. The second substrate 9 is, for example, a metal support substrate. However, the second substrate 9 may be a support substrate other than a metal support substrate. For bonding the second substrate 9 and the third electrode 3, for example, a known conductive adhesive layer is used. The conductive adhesive layer is, for example, an Ag sintered layer. The bonding method is not limited to Ag sintering bonding; other known bonding methods such as room temperature bonding may also be used.

[0058] In the first removal step, the first substrate 8 is removed from the first semiconductor layer 4 by known means such as peeling, as shown in Figure 7. The side of the first semiconductor layer 4 opposite to the second semiconductor layer 5, that is, the side from which the first substrate 8 has been removed, is preferably planarized by CMP (Chemical Mechanical Polishing) or the like before the trench formation step described later.

[0059] In the trench formation process, as shown in Figure 8, a trench 43 is formed on the surface of the first semiconductor layer 4 from which the first substrate 8 has been removed. In the trench formation process, the trench 43 is formed by, for example, the RIE (Reactive Ion Etching) method. Specifically, the trench formation process includes at least etching the first semiconductor layer 4 using a plasma-generated etching gas. In this case, the pressure of the etching gas is preferably, for example, 0.5 Pa or more and 1.5 Pa or less, and more preferably 0.8 Pa or more and 1.2 Pa or less. Furthermore, the etching gas preferably contains at least halogen. Furthermore, it is preferable that the plasma-generated etching gas contains at least oxygen. It is also preferable that the etching is performed in a halogen gas atmosphere. Furthermore, it is also preferable that the plasma bias of the etching gas is 25 W or more and 75 W or less. By using such a preferred RIE method, trenches can be easily formed. Note that the method for forming the trench 43 is not limited to the RIE method, and may be formed by other known methods.

[0060] In the high-resistance film formation process, a high-resistance film 6 is formed on the inner surface of the trench 43, as shown in Figure 9. In the high-resistance film formation process, the high-resistance film 6 is formed by, for example, sputtering, vacuum deposition, CVD, ALD, or other known methods. In the high-resistance film formation process, an opening 63 is formed in a part of the high-resistance film 6.

[0061] In the carrier discharge section formation process, as shown in Figure 10, a carrier discharge section 7 is formed in the opening 63 of the high-resistivity film 6. The carrier discharge section 7 is formed, for example, by the same method as the first semiconductor layer 4 or the second semiconductor layer 5.

[0062] In the first electrode and second electrode formation step, as shown in Figure 11, the first electrode 1 and the second electrode 2 are formed on the first semiconductor layer 4 and the high-resistivity film 6. The means for forming the first electrode 1 and the second electrode 2 are, for example, a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, or CVD. Wet methods include, for example, screen printing or die coating. The first electrode 1 and the second electrode 2 may also be formed by other known methods. When the first semiconductor layer 4 contains a metastable phase crystalline oxide semiconductor (for example, α-Ga2O3), the first electrode 1 and the second electrode 2 are preferably formed at a temperature below 800°C, and more preferably at a temperature below 600°C. The method for manufacturing the semiconductor device 100 is not limited to the method described above.

[0063] In the second removal step, the second substrate 9 is removed from the third electrode 3 by known means, such as peeling. This forms the semiconductor device 100 shown in Figure 1.

[0064] To turn on the semiconductor device 100, a forward voltage is applied between the Schottky electrode formed by the first electrode 1 and the second electrode 2, and the ohmic electrode, which is the third electrode 3. When a forward voltage is applied to the semiconductor device 100 in this way, the energy barrier at the interface between the first electrode 1 and the first semiconductor layer 4 is reduced, and current flows from the Schottky electrode to the ohmic electrode. On the other hand, when a reverse voltage is applied between the Schottky electrode and the ohmic electrode, the Schottky barrier makes it difficult for current to flow through the semiconductor device 100. At this time, the depletion layer formed at the interface between the first semiconductor layer 4 and the high-resistivity film 6 expands in the direction away from the second electrode 2 in the first semiconductor layer 4. As a result, the electric field at the interface between the first semiconductor layer 4 and the first electrode 1 is relaxed, and the leakage current is reduced.

[0065] Incidentally, when a reverse voltage is applied to the semiconductor device 100, the electric field at the bottom of the trench 43 strengthens, causing interband tunneling and the generation of carriers, which may accumulate at the bottom of the trench 43. For example, if the conductivity type of the first semiconductor layer 4 is n-type, holes may accumulate at the bottom of the trench 43. On the other hand, if the conductivity type of the first semiconductor layer 4 is p-type, electrons may accumulate at the bottom of the trench 43. Such carrier accumulation strengthens the electric field in the high-resistivity film 6, which can cause malfunctions in the high-resistivity film 6. In contrast, the semiconductor device 100 of this embodiment is provided with a carrier discharge section 7 that is in contact with the second electrode 2 and the bottom surface of the trench 43. Therefore, carriers generated at the bottom of the trench 43 are discharged from the carrier discharge section 7 through the second electrode 2 to the outside of the semiconductor device 100. Consequently, even if a high voltage is applied to the semiconductor device 100, malfunctions are less likely to occur in the high-resistivity film 6, and the breakdown voltage of the semiconductor device 100 is improved.

[0066] Furthermore, in this embodiment, the high-resistance film 6 includes a first portion 61 along the side surface of the trench 43 and a second portion 62 along the bottom surface of the trench 43, and the carrier discharge portion 7 is located in an opening 63 formed in the second portion 62. Therefore, carriers generated at the bottom of the trench 43 can be efficiently discharged from the carrier discharge portion 7. For example, if the high-resistance film 6 extends over the entire bottom of the trench 43, the middle portion in the width direction of the bottom of the trench 43 is less prone to electric field concentration and has a lower voltage compared to both ends, making it easier for carriers to accumulate. However, since the carrier discharge portion 7 is provided in the opening 63 of the second portion 62 along the bottom surface of the trench 43, carriers can be efficiently discharged. Therefore, the withstand voltage of the semiconductor device 100 can be further improved.

[0067] Furthermore, if a material with a high dielectric constant, such as HfO2, is used as the high-resistivity film 6, the electric field on the first semiconductor layer 4 side becomes higher, and carriers generated by interband tunneling accumulate at the bottom of the trench 43, causing the film electric field to rise and the dielectric breakdown voltage to decrease. In this disclosure, the decrease in dielectric breakdown voltage can be further suppressed by deliberately lowering the resistivity of the high-resistivity film 6 in order to discharge the accumulated carriers.

[0068] Furthermore, by making the resistivity of the first portion 61 as high as that of an insulating film and the resistivity of the second portion 62 as low as that of a semi-insulating film, carriers accumulated at the bottom of the trench 43 can be discharged more effectively.

[0069] (modified version) Next, a modified example of the first embodiment will be described. In the following descriptions of each modified example, elements common to the first embodiment will be denoted by the same reference numerals, and explanations of matters that overlap with those described in the third embodiment will be omitted.

[0070] In this modified example, the carrier discharge layer 7 is a high-resistivity layer with a higher resistivity compared to the first semiconductor layer 4. However, the resistivity of the carrier discharge layer 7 is lower than that of the high-resistivity film 6. As the material for the carrier discharge layer 7, for example, the material exemplified as the material for the high-resistivity film 6 in the first embodiment is used. The resistivity of the carrier discharge layer 7 can be adjusted to a predetermined value depending, for example, on impurities contained in the carrier discharge layer 7 and the manufacturing process of the carrier discharge layer 7.

[0071] The resistivity of the carrier discharge section 7 is 10 6 It may be Ω·cm or more, or 10 10 It may be greater than Ω·cm. The resistivity of the carrier discharge section 7 is 10 6 The density may be less than Ω·cm. The carrier discharge section 7 is preferably semi-insulating. In this example, the carrier discharge section 7 is a semi-insulating film. The carrier discharge section 7 may be, for example, a semiconductor film or an undoped film having a carrier density lower than that of the first semiconductor layer 4.

[0072] In this modified example, the carrier discharge section 7 is formed in the opening 63 of the high-resistance film 6 by the same method as the high-resistance film 6 during the carrier discharge section formation process.

[0073] In this modified example as well, the carrier discharge section 7, which is a high-resistance layer, can discharge carriers generated at the bottom of the trench 43 to the second electrode 2.

[0074] (Other embodiments) Next, an embodiment different from the first embodiment described above will be explained. In the following descriptions of each embodiment, elements common to the first embodiment will be denoted by the same reference numerals, and explanations of matters that overlap with those explained in the first embodiment will be omitted.

[0075] (Second Embodiment)

[0076] Figure 12 is a schematic cross-sectional view of a semiconductor device 200 according to the second embodiment, and corresponds to Figure 2. In this embodiment, the carrier discharge section 7 is formed integrally with the second electrode 2 and is a part of the second electrode 2.

[0077] Specifically, the second electrode 2 is formed from a material that has a higher barrier height relative to the first semiconductor layer 4 compared to the first electrode 1. As the material for the first electrode 1, for example, the material exemplified as the material for the first electrode 1 in the first embodiment is used, and as the material for the second electrode 2, for example, a material with a larger work function compared to the material for the first electrode 1 is used from among the materials exemplified as the material for the second electrode 2 in the first embodiment. The second electrode 2 preferably contains Pt, Ir, Ni, Pd, or Au. Furthermore, the second electrode 2 is preferably a metal with a work function of 5.0 eV or higher. The material for the second electrode 2 is not limited and may be a silicide or other compound. The material for the second electrode 2 may be the same as the material for the first electrode 1. The second electrode 2 may be formed from a material that has a lower barrier height relative to the first semiconductor layer 4 compared to the first electrode.

[0078] The lower end of the second electrode 2 is located at the opening 63 of the high-resistivity film 6, and this lower end forms a carrier discharge section 7. In other words, the carrier discharge section 7 is part of the second electrode 2. The lower surface of the lower end of the second electrode 2, i.e., the lower surface of the carrier discharge section 7, is Schottky bonded to the bottom surface of the trench 43 of the first semiconductor layer 4. As a result, a Schottky barrier with a barrier height higher than the barrier height of the mesa section 44 of the first electrode 1 is formed between the carrier discharge section 7 and the bottom surface of the trench 43.

[0079] In the semiconductor device 200 of this embodiment, carriers generated at the bottom of the trench 43 are discharged to the outside of the semiconductor device 200 from the carrier discharge section 7, which is part of the second electrode 2. The semiconductor device 200 of this embodiment may further include the carrier discharge section 7 of the first embodiment. That is, the semiconductor device 200 may further include a p-type semiconductor in contact with the second electrode and the bottom surface of the trench 43.

[0080] (Third embodiment) Figure 13 is a schematic cross-sectional view of a semiconductor device 300 according to the third embodiment, and corresponds to Figure 2. The semiconductor device 300 of this embodiment further includes a crystal defect region 45.

[0081] The first semiconductor layer 4 includes a crystal defect region 45. The crystal defect region 45 contains impurities at a higher density than other parts of the first semiconductor layer 4. Because the crystal defect region 45 contains crystal defects at a high density, its resistivity is higher compared to other parts of the first semiconductor layer 4. In other words, the crystal defect region 45 can also be called a high-resistivity region. Crystal defects can be observed, for example, by cross-sectional TEM (transmission electron microscope) images or cross-sectional SEM (scanning electron microscope) images.

[0082] The crystal defect region 45 is located below the high-resistance film 6, more specifically, below the bottom of the high-resistance film 6 (i.e., the second portion 62). The crystal defect region 45 is also located below the carrier discharge portion 7. The crystal defect region 45 may be separate from the high-resistance film 6 or in contact with it. The crystal defect region 45 extends linearly in a vertical cross-section. In this disclosure, "linear" includes broad linear shapes, i.e., rod-shaped and strip-shaped shapes. "Linear" also includes simply elongated shapes and curved shapes. The crystal defect region 45 is formed linearly along the bottom of the high-resistance film 6 in a vertical cross-section. The crystal defect region 45 may also be formed linearly in cross-sections other than the vertical cross-section.

[0083] The density of crystal defects in crystal defect region 45 is 1.0 × 10⁻⁶. 18 / cm 3 Preferably, the above is true. The density of crystal defects in the crystal defect region 45 is 1.0 × 10⁻⁶. 19 / cm 3 The above is 1.0 × 10 20 / cm 3 or more, or 1.0 × 10 21 / cm 3 The above is also acceptable. Furthermore, the density of crystal defects in the crystal defect region 45 is not limited to 1.0 × 10⁻⁶. 18 / cm 3 It is acceptable to be less than [a certain value].

[0084] The crystal defect region 45 contains crystal defects at a higher density than other parts of the first semiconductor layer 4. The impurities contained in the crystal defect region 45 contain elements different from the elements contained in the main components of the first semiconductor layer 4. The impurities may contain only one element or multiple elements. Hereinafter, the elements contained in the impurities will be referred to as "impurity elements" as needed. In this example, the impurities are individual elements. However, the impurities may also be compounds. It is preferable that the impurity elements are elements that do not function as donors or acceptors for the first semiconductor layer 4. In this case, the crystal defect region 45 may contain only impurities among the dopants and impurities, or it may contain both dopants and impurities. All elements in the crystal defect region 45, excluding the impurity elements, may be the same as all elements contained in the first semiconductor layer 4. It is preferable that the impurity elements are metallic elements with a mass number greater than magnesium (Mg). For example, the impurity element is aluminum (Al). However, the impurity elements may also be elements other than aluminum. The concentration of impurity elements in the crystal defect region 45 is, for example, 1.0 × 10⁻⁶ 15 / cm 3 The above 1.0 × 10 22 / cm 3 The following applies. Furthermore, the concentration of impurities within the crystal defect region 45 is not limited.

[0085] Regions of the first semiconductor layer 4 other than the crystal defect region 45 may contain the same impurity elements as those contained in the crystal defect region 45. In this case, the concentration of impurity elements in the crystal defect region 45 is greater than the concentration of impurity elements in the regions of the first semiconductor layer 4 other than the crystal defect region 45. The concentration of impurity elements is measured, for example, using secondary ion mass spectrometry (SIMS). Alternatively, the concentration of impurity elements may be measured by other known methods such as secondary ion mass spectrometry (e.g., NanoSIMS), transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (TEM-EDX), or calculation using a numerical calculation code (SRIM / TRIM). The concentration of impurity elements in the crystal defect region 45 may be greater than the concentration of dopant in the crystal defect region 45. The concentration of impurity elements in the crystal defect region 45 is, for example, 1.0 × 10⁻⁶. 17 / cm 3 That's all.

[0086] The crystal defect region 45 is formed, for example, after the trench formation process and before the high-resistance film formation process. The crystal defect region 45 is formed, for example, by ion implantation of impurities into the first semiconductor layer 4. That is, the crystal defect region 45 is formed by ion implantation into the first semiconductor layer 4 of the stacked structure shown in Figure 8. When impurities are implanted into the first semiconductor layer 4, damage is inflicted on the region of the first semiconductor layer 4 through which the impurities pass. The region damaged in this way by ion implantation becomes the crystal defect region 45. The ion implantation may be a box profile or a single profile. The crystal defect region 45 may also be formed by means other than ion implantation. For example, the crystal defect region 45 may be formed by irradiating the first semiconductor layer 4 with protons or helium.

[0087] In this embodiment, the formation of a crystal defect region 45 below the high-resistivity film 6 reduces the electric field strength at the bottom of the high-resistivity film 6, making it less likely for defects to occur in the high-resistivity film 6.

[0088] (modified version) Next, a modified example of the third embodiment will be described. In the following descriptions of each modified example, elements common to the third embodiment will be denoted by the same reference numerals, and explanations of matters that overlap with those described in the third embodiment will be omitted.

[0089] (Variation 1) Figure 14 is a schematic cross-sectional view of the semiconductor device 300A of the first modified example, and corresponds to Figure 13. In this modified example, the carrier discharge section 7 is formed integrally with the second electrode 2 and is part of the second electrode 2. That is, the semiconductor device 300A of this modified example is a device in which a crystal defect region 45 is provided on the semiconductor device 200 of the second embodiment.

[0090] (Modification 2) Figure 15 is a schematic cross-sectional view of the semiconductor device 300B of the modified example 2, and corresponds to Figure 13. The semiconductor device 300B of this modified example does not have a carrier discharge unit 7.

[0091] Specifically, the second portion 62 of the high-resistance film 6 is formed over the entire bottom surface of the trench 43, and no opening 63 is formed in the high-resistance film 6. That is, the high-resistance film 6 extends over the entire inner surface of the trench 43. Below the second portion 62 of the high-resistance film 6, a crystal defect region 45 is located.

[0092] The following is an addendum to this disclosure.

[0093] (Note 1) A semiconductor device comprising: a semiconductor layer having a plurality of trenches and mesa portions between adjacent trenches, and containing a crystalline oxide semiconductor containing gallium; a first electrode electrically connected to the mesa portion; a high-resistivity film along the inner surface of the trenches, having a higher resistivity than the semiconductor layer; a second electrode located within the trenches and electrically connected to the first electrode; and a carrier discharge portion in contact with the second electrode and the bottom surface of the trenches, for discharging carriers to the second electrode.

[0094] (Note 2) The semiconductor device described in Appendix 1, wherein the carrier discharge section is a semiconductor with a conductivity type different from that of the semiconductor layer.

[0095] (Note 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the carrier discharge section is a high-resistivity layer with a higher resistivity compared to the semiconductor layer.

[0096] (Note 4) The carrier discharge section is a part of the second electrode, and is a semiconductor device according to any one of the appendices 1 to 3.

[0097] (Note 5) The semiconductor device according to Appendix 4, wherein the first electrode forms a Schottky barrier between itself and the mesa portion, and the carrier discharge portion forms a Schottky barrier between itself and the bottom surface of the trench, having a barrier height higher than the barrier height of the first electrode relative to the mesa portion.

[0098] (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein the high-resistance film includes a first portion along the side surface of the trench and a second portion connected to the first portion and along the bottom surface of the trench, and the carrier discharge portion is provided in the second portion.

[0099] (Note 7) The semiconductor device according to Appendix 6, wherein the second portion has an opening that penetrates in the thickness direction of the semiconductor layer, and the carrier discharge portion is located in the opening.

[0100] (Note 8) A semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor containing gallium, having a plurality of trenches and mesa portions between adjacent trenches; a first electrode electrically connected to the mesa portions; a high-resistivity film along the inner surface of the trenches with a higher resistivity compared to the semiconductor layer; and a second electrode located within the trenches and electrically connected to the first electrode, wherein the semiconductor layer is located below the bottom surface of the trenches and has linearly extending crystal defect regions in cross-section.

[0101] [Explanation of symbols]

[0102] 100 Semiconductor Equipment 200 Semiconductor Equipment 300 semiconductor equipment 300A Semiconductor Equipment 300B Semiconductor Equipment 1 1st electrode 2 2nd electrode 3 Third electrode 4. First semiconductor layer (n-type semiconductor layer) 43 Trench 44 Mesa 45 Crystal defect regions 5. Second semiconductor layer (n+ type semiconductor layer) 6 High resistance film 61 Part 1 62 Part 2 63 Aperture 7. Carrier discharge section 8. First substrate 9. Second circuit board

Claims

1. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity compared to the semiconductor layer, is provided along the inner surface of the trench. A second electrode located within the trench and electrically connected to the first electrode, A semiconductor device comprising a carrier discharge section that contacts the second electrode and the bottom surface of the trench and discharges carriers to the second electrode.

2. The semiconductor device according to claim 1, wherein the carrier discharge section is a semiconductor with a conductivity type different from that of the semiconductor layer.

3. The semiconductor device according to claim 1, wherein the carrier discharge section is a high-resistivity layer with a higher resistivity compared to the semiconductor layer.

4. The semiconductor device according to claim 1, wherein the carrier discharge portion is part of the second electrode.

5. The first electrode forms a Schottky barrier between itself and the mesa portion. The semiconductor device according to claim 4, wherein the carrier discharge portion forms a Schottky barrier between itself and the bottom surface of the trench, the barrier height being higher than the barrier height of the first electrode with respect to the mesa portion.

6. The high-resistance film includes a first portion along the side surface of the trench and a second portion connected to the first portion and along the bottom surface of the trench. The semiconductor device according to any one of claims 1 to 5, wherein the carrier discharge section is provided in the second portion.

7. The second portion has an opening that penetrates in the thickness direction of the semiconductor layer, The carrier discharge section is located in the opening, as described in claim 6.

8. A semiconductor layer comprising a crystalline oxide semiconductor containing gallium, having multiple trenches and mesa portions between adjacent trenches, A first electrode electrically connected to the mesa portion, A high-resistivity film, which has a higher resistivity compared to the semiconductor layer, is provided along the inner surface of the trench. The trench contains a second electrode that is electrically connected to the first electrode, The semiconductor layer is located below the bottom surface of the trench and has a linearly extending crystal defect region in cross-section.

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