Memory circuit and information processing device

Abstract

This system enables word-line underdrive read assist with low power consumption and minimal power drop. [Solution] The system includes a word line driver 12 that sets the potential of the word line signal input to the selected memory cell 11 to a second value that is a certain amount lower than the first value until stable operation of the memory cell 11 is ensured; a timing adjustment circuit 15 that determines the time for setting the potential of the word line signal to the second value; and a pull-up circuit 14 that boosts the potential of the word line signal from the second value to the first value according to the determined time.

Description

Technical Field

[0001] The present invention relates to a memory circuit and an information processing apparatus.

Background Art

[0002] With the miniaturization of semiconductor technology, manufacturing variations have increased, and variations in transistor characteristics, wiring resistance, and capacitance have also increased. In recent years, the industrial use of AI (Artificial Intelligence) and big data has advanced, and computing power for processing a large amount of data is required. To reduce the power consumption of LSI (Large Scale Integrated circuit), a strong demand for lower operating voltages has emerged. With large variations and at low voltages, the stability (SNM: Static Noise Margin) of memory cells during SRAM (Static Random Access Memory) readout decreases, and data retention within the memory cells becomes impossible.

[0003] FIG. 1 is a diagram showing a circuit 6 including a memory cell (MC61) and a WL (Word Line) driver 62 in a first conventional example. FIG. 2 is a diagram showing the WL signal and the node operation waveforms in the circuit 6 shown in FIG. 1.

[0004] MC61 is composed of six transistors (PU0 / 1, PG0 / 1, PD0 / 1), and access to MC data is performed by a WL signal. Here, assume that in the initial state of the read operation, the C node is at a low potential (LO) and the CX node is at a high potential (HI). At the beginning of the read operation, the bit lines (BL, BLB) are precharged to HI by a precharge circuit not shown.

[0005] Next, as shown by reference numeral A1 in FIG. 2, access to MC61 is performed by setting the WL signal to HI. Since BL is HI and C is LO, current I flows from BL through PG0 and PD0 CELLThis occurs when the quality of the MC61 transistors after manufacturing varies, and the driving force ratio between PD0 and PG0 (PD driving force / PG driving force) becomes small. As shown by symbol A2 in Figure 2, the potential rise of C increases, PD1, to which C is connected, reacts, CX begins to fall, and eventually C and CX reverse, causing data corruption.

[0006] Various read assist circuits have been proposed to ensure stable operation. The most common is the Word Line Under Drive (WLUD) method, which improves the stability of the memory cell by lowering the WL level during memory cell access below the power supply voltage.

[0007] Figure 3 shows circuit 6a in the second conventional example. Figure 4 shows the WL signal and node operation waveforms within MC61 in circuit 6a shown in Figure 3.

[0008] The circuit 6a shown in Figure 3 includes a step-down circuit 63 in addition to the MC61 and WL driver 62 in the circuit 6 shown in Figure 1.

[0009] The basic operation is the same as in the first conventional example without assistance shown in Figure 1. Assume that in the initial state of the read operation, the C node is at a low potential (LO) and the CX node is at a high potential (HI). At the beginning of the read operation, the bit lines (BL, BLB) are pre-charged to HI by a pre-charge circuit (not shown).

[0010] As shown by the symbol B1 in Figure 4, the MC61 is accessed by setting the WL signal to HI. During access, the potential of the WL signal is limited to VDD-α, which is lower than the power supply voltage VDD, due to the step-down circuit added as an assist circuit. Because the WL signal does not rise to VDD, the gate-source potential of PG0 V GS The voltage decreases, and the driving force of PG0 decreases. Therefore, the ratio of the driving forces of PD0 and PG0 increases, and the rise in C is suppressed (solid line labeled B2 in Figure 4). A problem with this method is that the WL signal is not raised to VDD, so the V of PG0 GSBecause it is small I CELL The size decreases, and the read speed slows down.

[0011] Therefore, a circuit has been proposed that improves the readout speed, which decreases by raising the WL signal to VDD after a certain period of time.

[0012] Figure 5 shows circuit 6b in the third conventional example. Figure 6 shows the WL signal and node operation waveforms within MC61 in circuit 6b shown in Figure 5.

[0013] As shown in Figure 5, circuit 6b comprises multiple MC61 (MC[0],...,MC[n-1],MC[n]), a WL driver 62a, a pull-down circuit 63a, and a pull-down circuit control signal driver 64. The WL driver 62a has multiple inverters (INV[0],...,INV[n-1],INV[n]). The pull-down circuit 63a has multiple transistors (P[0],...,P[n-1],P[n]). n is a natural number.

[0014] The pull-down circuit 63a is connected to WL to prevent the WL signal from rising to VDD.

[0015] Figure 6 describes the WL driver INV[n], WL signal WL[n], pull-down circuit P1[n], and memory cell MC[n], all controlled by the word line selection signal / WL[n].

[0016] As shown by the symbol D1 in Figure 6, the WL driver 62a raises the WL[n] potential, and as shown by the symbol D2, the control signal / WUEN potential of the pull-down circuit 63a is lowered before the timing (T1) when access to MC[n] begins. The pull-down circuit 63a keeps the WL signal at VDD-α.

[0017] At the timing (T2) after the stability of MC[n] is ensured, the / WUEN potential is increased, and the pull-down circuit is turned OFF as shown in symbol D3, causing the WL signal to rise to VDD. Then, as shown in symbol D4, as the WL signal rises to VDD, the driving force of PG0 of MC[n] increases, and I CELL This increases the drive force reduction period, shortening the duration of the reduction and improving the read speed. [Prior art documents] [Patent Documents]

[0018] [Patent Document 1] Japanese Patent Publication No. 2009-070474 [Overview of the project] [Problems that the invention aims to solve]

[0019] Since the control signal for the pull-down circuit 63a is connected to all pull-down circuits 63a of the WL signal, the pull-down circuit control signal driver 64 that drives the pull-down circuit control signal has a very large driving force and consumes a lot of power. Also, because the control signal is common to all WL signals, it operates every cycle, resulting in a high operating rate. As a result, a large current flows through the power supply of this pull-down circuit control signal driver 64 at a high operating rate. If the power supply wiring connected to the pull-down circuit control signal driver 64 is insufficient and the current supply is insufficient, the necessary potential for the power supply cannot be maintained (in other words, power drop). Power drop can cause problems such as malfunctions and reduced speed.

[0020] One aspect of this approach is to achieve word-line underdrive read assist with low power consumption and minimal power drop. [Means for solving the problem]

[0021] On one side, the memory circuit includes a word line driver that sets the potential of the word line signal input to the selected memory cell to a second value that is a certain amount lower than the first value until the stable operation of the memory cell is ensured, a timing adjustment circuit that determines the time to set the potential of the word line signal to the second value, and a pull-up circuit that boosts the potential of the word line signal from the second value to the first value according to the determined time.

Advantages of the Invention

[0022] On one side, it is possible to realize read assist in a word line underdrive method with low power consumption and low power supply drop.

Brief Description of the Drawings

[0023] [Figure 1] It is a diagram showing a circuit including an MC and a WL driver in a first conventional example. [Figure 2] It is a diagram showing the operation waveforms of the WL signal and the nodes in the MC in the circuit shown in FIG. 1. [Figure 3] It is a diagram showing a circuit in a second conventional example. [Figure 4] It is a diagram showing the operation waveforms of the WL signal and the nodes in the MC in the circuit shown in FIG. 3. [Figure 5] It is a diagram showing a circuit in a third conventional example. [Figure 6] It is a diagram showing the operation waveforms of the WL signal and the nodes in the MC in the circuit shown in FIG. 5. [Figure 7] It is a diagram illustrating the memory circuit in an embodiment. [Figure 8] It is a diagram showing the operation waveforms of the nodes in the memory circuit shown in FIG. 7. [Figure 9] It is a diagram showing the details of the memory circuit shown in FIG. 7. [Figure 10] It is a diagram showing the operation waveforms of the nodes in the memory circuit shown in FIG. 8. [Figure 11] It is a diagram showing the memory circuit in a first modification. [Figure 12] This figure shows the node operation waveform in the memory circuit shown in Figure 11. [Figure 13] This figure shows the memory circuit in the second modified example. [Figure 14] This figure shows the node operation waveform in the memory circuit shown in Figure 13. [Figure 15] This is a schematic block diagram showing an example of the hardware configuration of the information processing device in the embodiment. [Modes for carrying out the invention]

[0024] [A] Embodiment An embodiment will be described below with reference to the drawings. However, the embodiment shown below is merely illustrative, and there is no intention to exclude various modifications or applications of techniques not explicitly shown in the embodiment. In other words, this embodiment can be implemented in various ways without departing from its spirit. Furthermore, each figure is not intended to represent only the components shown in the figure, but may include other functions, etc.

[0025] In the following diagrams, the same symbols indicate the same parts, so their explanations are omitted.

[0026] [A-1] Example of an embodiment Figure 7 is a diagram illustrating the memory circuit 1 in the embodiment. Figure 8 is a diagram showing the node operation waveform in the memory circuit 1 shown in Figure 7.

[0027] As shown in Figure 7, the memory circuit 1 includes an MC11, a WL driver 12, a step-down circuit 13, a pull-up circuit 14, and a timing adjustment circuit 15.

[0028] A WL driver 12 is connected to MC11, and a step-down circuit 13 is connected to the WL driver 12 to limit the rise of the WL signal to VDD-α. The word line selection signal / WL is also input to the timing adjustment circuit 15. The output of the timing adjustment circuit 15 / WL_D is connected to a pull-up circuit 14 that raises the WL signal to VDD.

[0029] As shown by the symbol E1 in Figure 8, at time T1, / WL transitions from VDD to VSS, and WL is raised by the WL driver 12. Here, as shown by the symbol E2, the step-down circuit 13 prevents the WL signal potential from rising to VDD, keeping it at a certain amount lower, VDD-α. With the WL potential at VDD-α, the MC11 performs readout operations in a stable state.

[0030] On the other hand, as shown in symbol E3, / WL is also input to the timing adjustment circuit 15, and a delayed / WL_D is output for a time sufficient to ensure the stability of MC11. / WL_D is input to the pull-up circuit 14. As shown in symbol E4, the pull-up circuit 14 raises the potential of the WL signal to the power supply voltage VDD as the / WL_D potential transitions from VDD to VSS. The readout speed of MC11 is improved as the potential of the WL signal rises to VDD.

[0031] Figure 9 shows the details of the memory circuit 1 shown in Figure 7. Figure 10 shows the node operation waveform in the memory circuit 1 shown in Figure 8.

[0032] The MC11 consists of six transistors (PU0 / 1, PG0 / 1, PD0 / 1), and access to the MC data is performed by the WL signal.

[0033] The WL driver 12 drives the access signal WL to the MC11. Until stable operation of the MC11 is ensured, the WL driver 12 sets the potential of the WL signal input to the selected MC11 to a second value (e.g., VDD-α) which is a certain amount lower than a first value (e.g., VDD).

[0034] The step-down circuit 13 lowers the word line selection signal WL by a certain amount compared to the power supply voltage VDD.

[0035] The pull-up circuit 14 is provided between the timing adjustment circuit 15 and the signal line of the WL signal, and raises the WL signal to the power supply voltage VDD. The pull-up circuit 14 increases the potential of the WL signal from a second value (e.g., VDD-α) to a first value (e.g., VDD) according to the time determined by the timing adjustment circuit 15.

[0036] The timing adjustment circuit 15 adjusts the operating timing of the pull-up circuit 14 from / WL. The timing adjustment circuit 15 determines the time to set the potential of the WL signal to a second value (for example, VDD-α).

[0037] Here, the data holding nodes C and CX of MC11 are assumed to be C at a low potential (LO) and CX at a high potential (HI), respectively, and both bit lines (BL, BLB) are precharged to HI by a precharge circuit not shown.

[0038] First, as shown by the symbol F1 in Figure 10, the / WL signal transitions from VDD to VSS at time T1.

[0039] Here, as shown by symbol F2, the step-down circuit 13 keeps the potential of the WL signal at VDD-α, which is a certain amount lower than VDD. With the potential of the WL signal at VDD-α, the MC11 performs readout operations in a stable state.

[0040] After the read operation progresses and the potential of BL drops by a certain amount, ensuring stable operation of MC11, a timing (T2) that has been delayed by a certain time by the timing adjustment circuit 15 arrives, as shown in symbol F3.

[0041] By adjusting the input of pull-up circuit 14 / WL_D to LO by timing adjustment circuit 15, the potential of the WL signal rises from VDD-α to VDD, as shown in symbol F4.

[0042] As shown in symbol F5, when the potential of the WL signal rises to VDD, the driving force of PG0 of MC11 increases. CELL This increases, improving the BL read speed.

[0043] At this time, the time it takes for the potential of the WL signal to rise from VDD-α to VDD is determined by the delay time of the timing adjustment circuit 15. The appropriate delay time must be long enough so that data corruption of C and CX does not occur even when the read operation is performed assuming the worst possible stability of MC11. Conversely, a shorter delay time will increase the read speed.

[0044] [A-2] First variation In the embodiment shown in Figure 9, a through-current flows from P2 through N0 during the period from when / WL becomes HI and N0 turns ON until when / WL_D becomes HI and P2 turns OFF (between T3 and T4 in Figure 10).

[0045] Figure 11 shows the memory circuit 1a in the first modified example. Figure 12 shows the node operation waveform in the memory circuit 1a shown in Figure 11.

[0046] The memory circuit 1a shown in Figure 11 has the function of suppressing the shoot-through current that occurs in the memory circuit 1 shown in Figure 9. In addition to the MC11, WL driver 12, step-down circuit 13, and pull-up circuit 14 shown in Figure 9, the memory circuit 1a includes two inverters 16. Furthermore, the memory circuit 1a includes a timing adjustment circuit 15a instead of the timing adjustment circuit 15 shown in Figure 9.

[0047] The timing adjustment circuit 15a adjusts the operating timing of the pull-up circuit 14 from / WL0 and outputs the timing-adjusted signal / WL_D. The timing adjustment circuit 15a also includes a selection circuit 151 that selects either the timing-adjusted signal / WL0_D or / WL0 as is.

[0048] The selection circuit 151 is controlled by / WL. Here, the selection circuit 151 controls the signal so that / WL0_D is selected when / WL0 transitions from VDD to VSS, and / WL0 is selected when the / WL0 signal transitions from VSS to VDD. In other words, the selection circuit 151 adjusts the timing by selecting and outputting either the timing-adjusted signal or the unadjusted signal.

[0049] Here, the data holding nodes C and CX of MC11 are assumed to be C at a low potential (LO) and CX at a high potential (HI), respectively, and both bit lines (BL, BLB) are pre-charged to HI by a pre-charge circuit (not shown).

[0050] First, before time T1, the / WL signal transitions from VDD to VSS, and / WL0 transitions from VDD to VSS. At this point, the step-down circuit 13 keeps the potential of the WL signal at VDD-α, which is a certain amount lower than VDD. With the potential of the WL signal at VDD-α, the MC11 performs read operations in a stable state.

[0051] On the other hand, the / WL0 input to the timing adjustment circuit 15a at time T1 is selected by the selection circuit 151 (XTG) of the timing adjustment circuit 15a. Therefore, as shown by the symbol G1 in Figure 12, the input is delayed until the timing (T2) after the read operation has progressed, the potential of BL has dropped by a certain amount, and the stable operation of MC11 has been ensured.

[0052] As shown in symbol G2, at timing (T2), the / WL0_D signal propagates to the input signal / WL_D of the pull-up circuit 14.

[0053] As shown in code G3, setting / WL_D to LO turns on the pull-up circuit 14, raising the potential of the WL signal from VDD-α to VDD.

[0054] As shown in code G4, the potential of the WL signal rises to VDD, increasing the driving force of PG0 of MC11 and improving the readout speed. Next, at time T3, / WL0 transitions from VSS to VDD, and the WL signal transitions from VDD to VSS.

[0055] On the other hand, as shown in code G5, / WL0 input to the timing adjustment circuit 15a at time T3 has TG selected in the selection circuit 151 of the timing adjustment circuit 15a. Therefore, with a delay added for passing through the selection circuit 151 from / WL0, it propagates to / WL_D at time T4, setting / WL_D to HI, which turns off the pull-up circuit 14.

[0056] As shown in symbol G6, by matching the timing at which N0 of the WL driver 12 turns ON with the timing at which the pull-up circuit 14 (P2) turns OFF (i.e., T3 = T4), it is possible to prevent shoot-through current from flowing.

[0057] [A-3] Second variation Figure 13 shows the memory circuit 1b in the second modified example. Figure 14 shows the node operation waveform in the memory circuit 1b shown in Figure 13.

[0058] The memory circuit 1b shown in Figure 13, like the memory circuit 1a shown in Figure 11, has the function of suppressing the shoot-through current that occurs in the memory circuit 1 shown in Figure 9. The memory circuit 1b shown in Figure 13, like the memory circuit 1a shown in Figure 9, includes an MC11, a WL driver 12, a step-down circuit 13, a pull-up circuit 14, and a timing adjustment circuit 15. In Figure 13, the pull-up circuit 14 is connected not to the WL signal, but to the connection net VDDWL between the WL driver 12 and the step-down circuit 13.

[0059] The data holding nodes C and CX of MC11 are assumed to be pre-charged to low potential (LO) for C and high potential (HI) for CX, respectively, and both bit lines (BL, BLB) are pre-charged to HI by a pre-charge circuit (not shown).

[0060] First, as shown by the symbol H1 in Figure 14, at time T1, the / WL signal transitions from VDD to VSS, and the WL signal is raised by the WL driver 12.

[0061] Here, as indicated by the symbol H2, the step-down circuit 13 keeps the potential of the WL signal at VDD-α, which is a certain amount lower than VDD. With the potential of the WL signal at VDD-α, the MC11 performs the read operation in a stable state.

[0062] As indicated by symbol H3, the timing adjustment circuit 15 advances the read operation, causing the potential of BL to drop by a certain amount, and delays the timing (T2) until stable operation of MC11 is ensured.

[0063] As shown in symbol H4, at timing (T2), the input / WL_D of the pull-up circuit 14 is set to LO by the timing adjustment circuit 15, which raises the potential of the WL signal from VDD-α to VDD.

[0064] As shown in symbol H5, when the potential of the WL signal rises to VDD, the driving force of PG0 of MC11 increases. CELL This increases, improving read speed.

[0065] As indicated by symbol H6, at time T3, / WL transitions from VSS to VDD, and the WL signal transitions from VDD to VSS. At time T3, the input / WL_D of the pull-up circuit 14 is still LO, and the pull-up circuit 14 is ON. However, since / WL is HI, P0 of the WL driver 12 is OFF, and regardless of the timing at T4, the through-current that occurs from P2 to N0 in the embodiment shown in Figure 9 does not occur.

[0066] [A-4] Hardware Configuration Example Figure 15 is a schematic block diagram showing an example of the hardware configuration of the information processing device 2 in the embodiment.

[0067] The information processing device 2 may be, for example, a server, and as shown in Figure 15, it includes a CPU 21, memory 22, display control device 23, storage device 24, input interface (IF) 25, external recording medium processing device 26, and communication IF 27.

[0068] Memory 22 is an example of a storage unit, and is exemplified by Read Only Memory (ROM) and Random Access Memory (RAM). A program such as a Basic Input / Output System (BIOS) may be written to the ROM of memory 22. The software program in memory 22 may be read and executed by the CPU 21 as appropriate. The RAM of memory 22 may be used as temporary storage memory or working memory. Memory 22 includes memory circuits 1, 1a, and 1b.

[0069] The display control device 23 is connected to the display device 131 and controls the display device 131. The display device 131 is a liquid crystal display, an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), an electronic paper display, etc., and displays various information to the operator of the information processing device 2. The display device 131 may be combined with an input device, for example, a touch panel. The display device 131 displays various information to the user of the information processing device 2.

[0070] The storage device 24 is a storage device with high I / O performance, and may include, for example, Dynamic Random Access Memory (DRAM), Solid State Drive (SSD), Storage Class Memory (SCM), or Hard Disk Drive (HDD).

[0071] Input IF25 is connected to an input device such as a mouse 251 or a keyboard 252, and may control such an input device. The mouse 251 and keyboard 252 are examples of input devices, and the operator performs various input operations through these input devices.

[0072] The external recording medium processing device 26 is configured to accommodate the recording medium 160. The external recording medium processing device 26 is configured to read the information recorded on the recording medium 160 when the recording medium 160 is mounted. In this example, the recording medium 160 is portable. For example, the recording medium 160 is a non-temporary recording medium such as a flexible disk, optical disk, magnetic disk, magneto-optical disk, or semiconductor memory.

[0073] Communication IF27 is an interface that enables communication with external devices.

[0074] The CPU 21 is an example of a processor, and is a processing unit that performs various control and calculations. The CPU 21 realizes various functions by executing the Operating System (OS) and programs loaded into memory 22. The CPU 21 may be a multiprocessor containing multiple CPUs, a multicore processor having multiple CPU cores, or a configuration having multiple multicore processors.

[0075] The device for controlling the overall operation of the information processing device 2 is not limited to the CPU 21, but may be, for example, one of the following: MPU, DSP, ASIC, PLD, or FPGA. Furthermore, the device for controlling the overall operation of the information processing device 2 may be a combination of two or more types of CPU, MPU, DSP, ASIC, PLD, and FPGA. Note that MPU is an abbreviation for Micro Processing Unit, DSP is an abbreviation for Digital Signal Processor, and ASIC is an abbreviation for Application Specific Integrated Circuit. Also, PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

[0076] [B] effect According to the memory circuits 1, 1a, 1b and the information processing device 2 in the above-described embodiment, the following effects can be achieved, for example.

[0077] The WL driver 12 sets the potential of the WL signal input to the selected MC11 to a second value that is a certain amount lower than the first value, until stable operation of the MC11 is ensured. The timing adjustment circuit 15 determines the time for setting the potential of the WL signal to the second value. The pull-up circuit 14 boosts the potential of the WL signal from the second value to the first value according to the determined time.

[0078] This eliminates the need for pull-down circuit control signals with high driving force and operating efficiency required to control numerous WL pull-down circuits, as in conventional technology. Although the added timing adjustment circuit 15 needs to be added for each WL, it only needs to control the pull-up circuit 14 for each WL signal, resulting in a very small driving force. Furthermore, since only the timing adjustment circuit 15 corresponding to the WL that needs to be operated operates, and the others do not, it is possible to achieve equivalent WL underdrive lead assist with lower power consumption and power supply drop than conventional technology.

[0079] The pull-up circuit 14 is provided between the timing adjustment circuit 15 and the signal line of the WL signal.

[0080] This allows the potential of the WL signal to be increased after a predetermined time has elapsed.

[0081] The timing adjustment circuit 15 includes a selection circuit 151 that selects and outputs either the signal after timing adjustment or the signal without timing adjustment to adjust the timing.

[0082] This prevents the generation of through-current from flowing from the pull-up circuit 14 to the WL driver 12.

[0083] The step-down circuit 13 steps down the potential of the WL signal from a first value to a second value. The pull-up circuit 14 is connected to the timing adjustment circuit 15 and also between the WL driver 12 and the step-down circuit 13.

[0084] This makes it possible to prevent through-current from flowing from the pull-up circuit 14 to the WL driver 12 by the simple timing adjustment circuit 15.

[0085] [C] Others The disclosed technology is not limited to the embodiments described above and can be implemented in various modified forms without departing from the spirit of this embodiment. Each configuration and process of this embodiment can be selected or combined as needed.

[0086] [D] Note The following additional information is disclosed regarding the embodiments described above.

[0087] (Note 1) A word line driver sets the potential of the word line signal input to the selected memory cell to a second value that is a certain amount lower than the first value, until the stable operation of the memory cell is ensured. A timing adjustment circuit that determines the time to set the potential of the word line signal to the second value, A pull-up circuit that increases the potential of the word line signal from the second value to the first value according to the determined time, A memory circuit equipped with this.

[0088] (Note 2) The pull-up circuit is provided between the timing adjustment circuit and the signal line of the word line signal. The memory circuit described in Appendix 1.

[0089] (Note 3) The timing adjustment circuit includes a selection circuit that selects and outputs either the signal after timing adjustment or the signal without timing adjustment to adjust the time. The memory circuit described in Appendix 1 or 2.

[0090] (Note 4) The system further includes a step-down circuit that reduces the potential of the word line signal from the first value to the second value, The pull-up circuit is connected to the timing adjustment circuit and also connected between the word line driver and the step-down circuit. The memory circuit described in Appendix 1.

[0091] (Note 5) An information processing device comprising a processor and a memory having a memory circuit, The aforementioned memory circuit is A word line driver sets the potential of the word line signal input to the selected memory cell to a second value that is a certain amount lower than the first value, until the stable operation of the memory cell is ensured. A timing adjustment circuit that determines the time to set the potential of the word line signal to the second value, A pull-up circuit that increases the potential of the word line signal from the second value to the first value according to the determined time, An information processing device equipped with the following features.

[0092] (Note 6) The pull-up circuit is provided between the timing adjustment circuit and the signal line of the word line signal. The information processing device described in Appendix 5.

[0093] (Note 7) The timing adjustment circuit includes a selection circuit that selects and outputs either the signal after timing adjustment or the signal without timing adjustment to adjust the time. The information processing device described in Appendix 5 or 6.

[0094] (Note 8) The system further includes a step-down circuit that reduces the potential of the word line signal from the first value to the second value, The pull-up circuit is connected to the timing adjustment circuit and also connected between the word line driver and the step-down circuit. The information processing device described in Appendix 5. [Explanation of symbols]

[0095] 1,1a,1b: Memory circuit 6,6a,6b:Circuit 11,61 :MC 12,62,62a:WL driver 13,63: Step-down circuit 14: Pull-up circuit 15,15a: Timing adjustment circuit 151: Selection Circuit 16: Inverter 2: Information Processing Device 21: CPU 22: Memory 23: Display control device 24:Storage device 25: Input IF 26: External recording medium processing device 27: Communication Interface 63a: Pull-down circuit 64: Pull-down circuit control signal driver 131:Display device 251: Mouse 252: Keyboard 160: Recording media

Claims

1. A word line driver sets the potential of the word line signal input to the selected memory cell to a second value that is a certain amount lower than the first value, until the stable operation of the memory cell is ensured. A timing adjustment circuit that determines the time to set the potential of the word line signal to the second value, A pull-up circuit that increases the potential of the word line signal from the second value to the first value according to the determined time, A memory circuit equipped with this.

2. The pull-up circuit is provided between the timing adjustment circuit and the signal line of the word line signal. The memory circuit according to claim 1.

3. The timing adjustment circuit includes a selection circuit that selects and outputs either the signal after timing adjustment or the signal without timing adjustment to adjust the time. The memory circuit according to claim 1 or 2.

4. The system further includes a step-down circuit that reduces the potential of the word line signal from the first value to the second value. The pull-up circuit is connected to the timing adjustment circuit and also connected between the word line driver and the step-down circuit. The memory circuit according to claim 1.

5. An information processing device comprising a processor and a memory having a memory circuit, The aforementioned memory circuit is A word line driver sets the potential of the word line signal input to the selected memory cell to a second value that is a certain amount lower than the first value, until the stable operation of the memory cell is ensured. A timing adjustment circuit that determines the time to set the potential of the word line signal to the second value, A pull-up circuit that increases the potential of the word line signal from the second value to the first value according to the determined time, An information processing device equipped with the following features.

Images