Methods for manufacturing semiconductor wafers and semiconductor devices

Abstract

This system accurately detects piping defects at an early stage in the manufacturing process of semiconductor devices. [Solution] The semiconductor wafer comprises a semiconductor substrate, a plurality of chip regions, scribe regions that demarcate the plurality of chip regions, and an interlayer insulating film formed on the semiconductor substrate. A TEG is formed within the scribe region. The TEG comprises an active region OD1 formed in the semiconductor substrate, an active region OD2 formed in the semiconductor substrate and adjacent to the active region OD1 in the X direction, a gate electrode G formed on the active region OD1 and the active region OD2 and extending in the X direction, an insulating region IR formed in the semiconductor substrate adjacent to the active region OD2 in the Y direction perpendicular to the X direction and not overlapping with the gate electrode G in a plan view, a plug PLG formed in the interlayer insulating film and connected to the active region OD1, and a dummy plug DG formed in the interlayer insulating film and connected to the insulating region IR.

Description

Technical Field

[0001] The present invention relates to a manufacturing technique of semiconductor wafers and semiconductor devices, and more particularly to a technique effective when applied to a semiconductor wafer including a TEG (Test Element Group).

Background Art

[0002] Japanese Patent Application Laid-Open No. 2007-19342 (Patent Document 1) describes a technique related to a TEG for detecting a piping defect occurring between contact plugs.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, in order to advance the miniaturization of semiconductor devices, reducing the interval between adjacent cells has been considered. In the manufacturing process of semiconductor devices, an interlayer insulating film is formed so as to cover a plurality of cells. When the interval between adjacent cells becomes narrow, the aspect ratio between the gate electrodes of the cells becomes high. As a result, it becomes difficult to sufficiently embed the interlayer insulating film between the gate electrodes of the cells. Thereby, voids may occur in the interlayer insulating film embedded between the gate electrodes of the cells.

[0005] In the interlayer insulating film, a plurality of plugs are formed. When voids occur in the interlayer insulating film, the conductive material of the plurality of plugs may be embedded in the voids. There is a risk of occurrence of a "piping defect" in which adjacent plugs are electrically connected through the conductive material embedded in the voids.

[0006] In this regard, there is a method to detect piping defects by performing wafer testing after forming cells and wiring on the wafer. However, to detect piping defects based on wafer testing, it is necessary to perform physical analysis to identify the piping defects after detecting anomalies in the wafer testing. In this case, it takes time to detect the piping defects.

[0007] Therefore, there is a need to be able to accurately detect piping defects at an early stage in the manufacturing process of semiconductor devices.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0009] In one embodiment, the semiconductor wafer includes a semiconductor substrate, a plurality of chip regions, scribe regions that demarcate the plurality of chip regions, and an interlayer insulating film formed on the semiconductor substrate. A TEG is formed within the scribe region. The TEG includes a first active region formed in the semiconductor substrate, a second active region formed in the semiconductor substrate and adjacent to the first active region in a first direction, a first gate electrode formed on the first and second active regions and extending in a first direction, an insulating region formed in the semiconductor substrate adjacent to the second active region in a second direction orthogonal to the first direction and not overlapping with the first gate electrode in a plan view, a first plug formed in the interlayer insulating film and connected to the first active region, and a second plug formed in the interlayer insulating film and connected to the insulating region.

[0010] In one embodiment, a method for manufacturing a semiconductor device includes (a) a step of preparing a semiconductor wafer having a semiconductor substrate, a plurality of chip regions, scribe regions that demarcate the plurality of chip regions, an interlayer insulating film formed on the semiconductor substrate, and a TEG formed within the scribe region; and (b) a step of detecting a piping defect between a first plug and a second plug. The TEG has a first active region formed in the semiconductor substrate, a second active region formed in the semiconductor substrate and adjacent to the first active region in a first direction, a first gate electrode formed on the first and second active regions and extending in a first direction, an insulating region formed in the semiconductor substrate adjacent to the second active region in a second direction orthogonal to the first direction and not overlapping with the first gate electrode in a plan view, a first plug formed in the interlayer insulating film and connected to the first active region, and a second plug formed in the interlayer insulating film and connected to the insulating region. [Effects of the Invention]

[0011] According to one embodiment, piping defects can be accurately detected at an early stage in the manufacturing process of semiconductor devices. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows the layout of the non-volatile memory formed in the chip area. [Figure 2] This is a cross-sectional view of the non-volatile memory along line AA in Figure 1. [Figure 3] This figure shows the layout of the TEG in the first related technology. [Figure 4] This figure shows the layout of the TEG in the second related technology. [Figure 5] This is a diagram that explains the basic concept. [Figure 6] This figure shows the layout of the TEG in Embodiment 1. [Figure 7] This is a cross-sectional view of the TEG along line AA in Figure 6. [Figure 8]This is a diagram showing the layout of a TEG in a state where no piping defect occurs in Embodiment 1. [Figure 9] This is a diagram showing the layout of a TEG in a state where a piping defect occurs in Embodiment 1. [Figure 10] This is a diagram showing the layout of a TEG in a state where no piping defect occurs in Embodiment 2. [Figure 11] This is a diagram showing the layout of a TEG in a state where a piping defect occurs in Embodiment 2. [Figure 12] This is a diagram showing a continuity check in an examination example. [Figure 13] This is a diagram showing a continuity check in Embodiment 2. [Figure 14] This is a diagram showing the layout of a TEG in a state where no piping defect occurs in Embodiment 3. [Figure 15] This is a diagram showing the layout of a TEG in a state where a piping defect occurs in Embodiment 3. [Figure 16] This is a diagram showing the layout of a TEG in an examination example. [Figure 17] This is a diagram showing the layout of a TEG in Embodiment 4.

Best Mode for Carrying Out the Invention

[0013] In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated explanations thereof are omitted. Note that, for the sake of clarity of the drawings, hatching may be added even in a plan view.

[0014] <Examination of Improvement> A semiconductor wafer has a plurality of chip regions and scribe regions that partition the plurality of chip regions. A semiconductor device used as a product is formed in each of the plurality of chip regions. On the other hand, the scribe regions are cut by a dicing saw in a dicing process for singulating the semiconductor wafer into a plurality of semiconductor chips.

[0015] Generally, TEGs are often formed in the scribed area. A TEG is a test pattern formed within the scribed area of ​​a semiconductor wafer to evaluate semiconductor processes and devices. TEGs are used to characterize circuit patterns and to evaluate or analyze defects that occur during the manufacturing of semiconductor devices.

[0016] For example, the use of a TEG (Technical Emission Generator) is being considered to detect piping defects. The following describes related techniques for detecting piping defects using a TEG.

[0017] In this specification, "related technology" refers to technology that is not publicly known but has a problem identified by the present inventor, and is a technology that forms the basis of this disclosure.

[0018] Figure 1 shows the layout of the non-volatile memory formed on the chip area.

[0019] In Figure 1, the non-volatile memory includes control gate electrodes CG1A, CG2A, CG3A, CG4A, memory gate electrodes MG1A, MG2A, MG3A, MG4A, active regions OD1A, OD2A, OD3A, OD4A, OD5A, OD6A, insulating region STI1A, STI2A, STI3A, STI4A, plugs PLG1A, PLG2A, PLG3A, PLG4A, PLG5A, and PLG6A.

[0020] The control gate electrode CG1A and the memory gate electrode MG1A extend parallel to each other in the X direction. The control gate electrode CG2A and the memory gate electrode MG2A extend parallel to each other in the X direction. The control gate electrode CG3A and the memory gate electrode MG3A extend parallel to each other in the X direction. The control gate electrode CG4A and the memory gate electrode MG4A extend parallel to each other in the X direction.

[0021] The active region OD1A has a portion that overlaps planarly with the control gate electrodes CG1A and CG2A. The active region OD2A has a portion that overlaps planarly with the control gate electrodes CG1A and CG2A. The active region OD3A has a portion that overlaps planarly with the control gate electrodes CG1A and CG2A.

[0022] The active region OD4A has a portion that overlaps planarly with the control gate electrodes CG3A and CG4A. The active region OD5A has a portion that overlaps planarly with the control gate electrodes CG3A and CG4A. The active region OD6A has a portion that overlaps planarly with the control gate electrodes CG3A and CG4A.

[0023] The insulating region STI1A extends in the Y direction. The insulating region STI1A is located planar between the active region OD1A and the active region OD2A. The insulating region STI1A includes portions that overlap planar with the control gate electrode CG1A and the memory gate electrode MG1A. The insulating region STI1A includes portions that overlap planar with the control gate electrode CG2A and the memory gate electrode MG2A.

[0024] The insulating region STI2A extends in the Y direction. The insulating region STI2A is located planar between the active regions OD2A and OD3A. The insulating region STI2A includes portions that overlap planar with the control gate electrode CG1A and the memory gate electrode MG1A. The insulating region STI2A includes portions that overlap planar with the control gate electrode CG2A and the memory gate electrode MG2A.

[0025] The insulating region STI3A extends in the Y direction. The insulating region STI3A is located planar between the active regions OD1A and OD2A. The insulating region STI3A includes portions that overlap planar with the control gate electrode CG3A and the memory gate electrode MG3A. The insulating region STI3A also includes portions that overlap planar with the control gate electrode CG4A and the memory gate electrode MG4A.

[0026] The insulating region STI4A extends in the Y direction. The insulating region STI4A is located planar between the active regions OD2A and OD3A. The insulating region STI4A includes portions that overlap planar with the control gate electrode CG3A and the memory gate electrode MG3A. The insulating region STI4A includes portions that overlap planar with the control gate electrode CG4A and the memory gate electrode MG4A.

[0027] Plug PLG1A is positioned planarly between the control gate electrode CG1A and the control gate electrode CG2A. Plug PLG1A is formed on the active region OD1A. Plug PLG1A is electrically connected to the active region OD1A.

[0028] Plug PLG2A is positioned planarly between the control gate electrode CG1A and the control gate electrode CG2A. Plug PLG2A is formed on the active region OD2A. Plug PLG2A is electrically connected to the active region OD2A.

[0029] Plug PLG3A is positioned planarly between the control gate electrode CG1A and the control gate electrode CG2A. Plug PLG3A is formed on the active region OD3A. Plug PLG3A is electrically connected to the active region OD3A.

[0030] Plug PLG4A is positioned planarly between the control gate electrode CG3A and the control gate electrode CG4A. Plug PLG4A is formed on the active region OD4A. Plug PLG4A is electrically connected to the active region OD4A.

[0031] Plug PLG5A is positioned planarly between the control gate electrode CG3A and the control gate electrode CG4A. Plug PLG5A is formed on the active region OD5A. Plug PLG5A is electrically connected to the active region OD5A.

[0032] Plug PLG6A is positioned planarly between the control gate electrode CG3A and the control gate electrode CG4A. Plug PLG6A is formed on the active region OD6A. Plug PLG6A is electrically connected to the active region OD6A.

[0033] Figure 2 is a cross-sectional view of the non-volatile memory along line AA in Figure 1.

[0034] In Figure 2, an active region OD2A is formed within the semiconductor substrate SUB. A control gate electrode CG1A is formed on the active region OD2A via a gate insulating film. In the Y direction, the control gate electrode CG1A and the control gate electrode CG2A are separated from each other.

[0035] A memory gate electrode MG1A is formed on one side wall of the control gate electrode CG1A via a multilayer insulating film (ONO film). A memory gate electrode MG2A is formed on one side wall of the control gate electrode CG2A via a multilayer insulating film (ONO film). An interlayer insulating film IL is formed on the active region OD2A so as to cover the control gate electrode CG1A, memory gate electrode MG1A, control gate electrode CG2A, and memory gate electrode MG2A. A plug PLG2A is formed within the interlayer insulating film IL. The plug PLG2A is connected to the drain region. In the Y direction, the plug PLG2A is located between the control gate electrode CG1A and the control gate electrode CG2A.

[0036] In a non-volatile memory configured in this way, a piping failure may occur, for example, between plug PLG1A and plug PLG2A. To detect this piping failure, a first related technique can be considered that uses a TEG to detect the piping failure.

[0037] Figure 3 shows the layout of the TEG in the first related technology.

[0038] In Figure 3, the TEG has control gate electrode CG1B, control gate electrode CG2B, control gate electrode CG3B, control gate electrode CG4B, memory gate electrode MG1B, memory gate electrode MG2B, memory gate electrode MG3B, memory gate electrode MG4B, active region OD1B, active region OD2B, active region OD3B, active region OD4B, active region OD5B, active region OD6B, insulating region STI1B, insulating region STI2B, insulating region STI3B, insulating region STI4B, plug PLG1B, plug PLG2B, plug PLG3B, plug PLG4B, plug PLG5B, plug PLG6B, dummy plug DG1B, dummy plug DG2B, dummy plug DG3B, and dummy plug DG4B.

[0039] The control gate electrode CG1B and the memory gate electrode MG1B extend parallel to each other in the X direction. The control gate electrode CG2B and the memory gate electrode MG2B extend parallel to each other in the X direction. The control gate electrode CG3B and the memory gate electrode MG3B extend parallel to each other in the X direction. The control gate electrode CG4B and the memory gate electrode MG4B extend parallel to each other in the X direction.

[0040] The active region OD1B has a portion that overlaps planarly with the control gate electrodes CG1B and CG2B. The active region OD2B has a portion that overlaps planarly with the control gate electrodes CG1B and CG2B. The active region OD3B has a portion that overlaps planarly with the control gate electrodes CG1B and CG2B.

[0041] The active region OD4B has a portion that overlaps planarly with the control gate electrodes CG3B and CG4B. The active region OD5B has a portion that overlaps planarly with the control gate electrodes CG3B and CG4B. The active region OD6B has a portion that overlaps planarly with the control gate electrodes CG3B and CG4B.

[0042] The insulating region STI1B extends in the Y direction. The insulating region STI1B is located planar between the active regions OD1B and OD2B. The insulating region STI1B includes portions that overlap planar with the control gate electrode CG1B and the memory gate electrode MG1B. The insulating region STI1B also includes portions that overlap planar with the control gate electrode CG2B and the memory gate electrode MG2B.

[0043] The insulating region STI2B extends in the Y direction. The insulating region STI2B is located planar between the active regions OD2B and OD3B. The insulating region STI2B includes portions that overlap planar with the control gate electrode CG1B and the memory gate electrode MG1B. The insulating region STI2B includes portions that overlap planar with the control gate electrode CG2B and the memory gate electrode MG2B.

[0044] The insulating region STI3B extends in the Y direction. The insulating region STI3B is located planar between the active regions OD1B and OD2B. The insulating region STI3B includes portions that overlap planar with the control gate electrode CG3B and the memory gate electrode MG3B. The insulating region STI3B also includes portions that overlap planar with the control gate electrode CG4B and the memory gate electrode MG4B.

[0045] The insulating region STI4B extends in the Y direction. The insulating region STI4B is located planar between the active regions OD2B and OD3B. The insulating region STI4B includes portions that overlap planar with the control gate electrode CG3B and the memory gate electrode MG3B. The insulating region STI4B includes portions that overlap planar with the control gate electrode CG4B and the memory gate electrode MG4B.

[0046] Plug PLG1B is positioned planarly between the control gate electrode CG1B and the control gate electrode CG2B. Plug PLG1B is formed on the active region OD1B. Plug PLG1B is electrically connected to the active region OD1B.

[0047] Plug PLG2B is positioned planarly between the control gate electrode CG1B and the control gate electrode CG2B. Plug PLG2B is formed on the active region OD2B. Plug PLG2B is electrically connected to the active region OD2B.

[0048] Plug PLG3B is positioned planarly between the control gate electrode CG1B and the control gate electrode CG2B. Plug PLG3B is formed on the active region OD3B. Plug PLG3B is electrically connected to the active region OD3B.

[0049] Plug PLG4B is positioned planarly between the control gate electrode CG3B and the control gate electrode CG4B. Plug PLG4B is formed on the active region OD4B. Plug PLG4B is electrically connected to the active region OD4B.

[0050] Plug PLG5B is positioned planarly between the control gate electrode CG3B and the control gate electrode CG4B. Plug PLG5B is formed on the active region OD5B. Plug PLG5B is electrically connected to the active region OD5B.

[0051] Plug PLG6B is positioned planarly between the control gate electrode CG3B and the control gate electrode CG4B. Plug PLG6B is formed on the active region OD6B. Plug PLG6B is electrically connected to the active region OD6B.

[0052] The dummy plug DG1B is located in a planar manner between the control gate electrode CG1B and the control gate electrode CG2B. The dummy plug DG1B is located in a planar manner between the active region OD1B and the active region OD2B. The dummy plug DG1B is located in a planar manner between the plug PLG1B and the plug PLG2B. The dummy plug DG1B is formed on the insulating region STI1B.

[0053] The dummy plug DG2B is located in a planar manner between the control gate electrode CG1B and the control gate electrode CG2B. The dummy plug DG2B is located in a planar manner between the active region OD2B and the active region OD3B. The dummy plug DG2B is located in a planar manner between the plug PLG2B and the plug PLG3B. The dummy plug DG2B is formed on the insulating region STI2B.

[0054] The dummy plug DG3B is located in a planar manner between the control gate electrode CG3B and the control gate electrode CG4B. The dummy plug DG3B is located in a planar manner between the active region OD1B and the active region OD2B. The dummy plug DG3B is located in a planar manner between the plug PLG4B and the plug PLG5B. The dummy plug DG3B is formed on the insulating region STI3B.

[0055] The dummy plug DG4B is located in a planar manner between the control gate electrode CG3B and the control gate electrode CG4B. The dummy plug DG4B is located in a planar manner between the active region OD2B and the active region OD3B. The dummy plug DG4B is located in a planar manner between the plug PLG5B and the plug PLG6B. The dummy plug DG4B is formed on the insulating region STI4B.

[0056] In a TEG configured in this way, for example, if a piping failure occurs between plug PLG1B and plug PLG2B in Figure 3, the dummy plug DG1B, located between plug PLG1B and plug PLG2B, will also be electrically connected to plug PLG1B and plug PLG2B.

[0057] On the other hand, if there is no piping fault between plug PLG1B and plug PLG2B, the dummy plug DG1B, located between plug PLG1B and plug PLG2B, is electrically insulated from plug PLG1B and plug PLG2B.

[0058] Therefore, for example, piping failures can be detected by checking for continuity or noncontinuity between plug PLG1B and dummy plug DG1B. Continuity or noncontinuity between plug PLG1B and dummy plug DG1B can be detected using the potential contrast method described later. If a piping failure is detected in the TEG formed in the scribe region, there is a high probability that a piping failure also occurs in the non-volatile memory formed in the chip region. For this reason, piping failures in non-volatile memory can be detected by using the TEG.

[0059] Thus, the TEG in the first related technology can detect piping defects. However, in recent years, semiconductor devices have become smaller, and for example, the layout of the non-volatile memory shown in Figure 1 is reduced. In this case, even in the TEG shown in Figure 3, for example, the width L1 in the X direction of the insulating region STI1B shown in Figure 3 is reduced. As a result, it becomes difficult to form a dummy plug DG1B on the insulating region STI1B. Therefore, as semiconductor devices become smaller, it becomes difficult to use the TEG shown in Figure 3.

[0060] In this regard, TEG in the second related technology is being considered.

[0061] Figure 4 shows the layout of the TEG in the second related technology.

[0062] In Figure 4, the active regions OD2B and OD5B shown in Figure 3 are not formed. In the second related technology shown in Figure 4, the insulating regions 10A and 10B, indicated by the dotted lines, are formed. A dummy plug DG1 is formed on the insulating region 10A.

[0063] Dummy plug DG1 is located in a planar manner between control gate electrode CG1 and control gate electrode CG2. Dummy plug DG1 is located in a planar manner between active region OD1B and active region OD3B. Dummy plug DG1 is located in a planar manner between plug PLG1B and plug PLG3B.

[0064] A dummy plug DG2 is formed on the insulating region 10B. The dummy plug DG2 is located in a planar manner between the control gate electrode CG3 and the control gate electrode CG4. The dummy plug DG2 is located in a planar manner between the active region OD1B and the active region OD3B. The dummy plug DG2 is located between the plug PLG4B and the plug PLG6B.

[0065] In a TEG configured in this way, for example, in Figure 4, if a piping failure occurs between plug PLG1B and dummy plug DG1, plug PLG1B and dummy plug DG1 are electrically connected. Conversely, if no piping failure occurs between plug PLG1B and dummy plug DG1, plug PLG1B and dummy plug DG1 are electrically insulated. Therefore, for example, a piping failure can be detected by checking for continuity or non-continuity between plug PLG1B and dummy plug DG1. In other words, if a piping failure is detected in a TEG formed in the scribe region, there is a high probability that a piping failure has also occurred in the non-volatile memory formed in the chip region. For this reason, by using the TEG in the second related technology, a piping failure in the non-volatile memory can be detected. In particular, according to the second related technology, even if the width L1 in the X direction of the insulating region STI1B shown in Figure 4 is reduced, the dummy plug DG1 can still be placed.

[0066] However, the inventors have newly discovered that there is room for improvement in the second related technology. The inventors' newly discovered findings will be explained below.

[0067] As shown in Figure 4, the TEG in the second related technology forms insulating regions IR1 and IR2 without forming active regions OD2B and OD5B.

[0068] Therefore, the TEG in the second related technology has a larger insulating region area than the non-volatile memory shown in Figure 1.

[0069] For example, not only insulating regions STI1B, STI2B, STI3B, and STI4B, but also insulating regions 10A and 10B are formed by embedding insulating films in the trenches. Etching is used to form the trenches. The shape of the trench formed by etching is influenced by the area etched (first factor).

[0070] The insulating region 10A includes portions that overlap planarly with the control gate electrode CG1 and the memory gate electrode MG1. The insulating region 10A includes portions that overlap planarly with the control gate electrode CG2 and the memory gate electrode MG2. The insulating region 10B includes portions that overlap planarly with the control gate electrode CG3 and the memory gate electrode MG3. The insulating region 10B includes portions that overlap planarly with the control gate electrode CG4 and the memory gate electrode MG4. As a result, steps are created between the upper surface of insulating region 10A and the upper surface of the semiconductor substrate, and between the upper surface of insulating region 10B and the upper surface of the semiconductor substrate. These steps affect the processing shapes of the control gate electrode CG1, control gate electrode CG2, control gate electrode CG3 and control gate electrode CG4, as well as the heights of insulating region 10A and insulating region 10B (second factor).

[0071] For example, in Figure 1, an active region OD2A is formed between insulating region STI1A and insulating region STI2A, while in Figure 4, an insulating region 10A is formed between insulating region STI1B and insulating region STI2B. Therefore, the processing shape of the portion of the control gate electrode CG1A located on the active region OD2A in Figure 1 is different from the processing shape of the portion of the control gate electrode CG1B located on the insulating region 10A in Figure 4. As a result, the shape of the interlayer insulating film formed next to the control gate electrode CG1A is also different from the shape of the interlayer insulating film formed next to the control gate electrode CG1B. Consequently, the probability of voids occurring in the interlayer insulating film differs between the non-volatile memory shown in Figure 1 and the TEG shown in Figure 4. In other words, the probability of piping defects occurring differs between the non-volatile memory shown in Figure 1 and the TEG shown in Figure 4.

[0072] As a result, the first and second factors influence how piping failures occur. Specifically, the way piping failures occur in the TEG under the second related technology may differ from how they occur in the non-volatile memory shown in Figure 1. For example, piping failures may occur in the TEG under the second related technology, while they may not occur in the non-volatile memory shown in Figure 1. Conversely, piping failures may not occur in the TEG under the second related technology, while they may occur in the non-volatile memory shown in Figure 1. Thus, the second related technology may not be able to detect piping failures with high accuracy.

[0073] Therefore, the technical concept of this disclosure will be explained below.

[0074] <Basic philosophy> Figure 5 is a diagram that explains the basic concept.

[0075] In Figure 5, the TEG has a gate electrode G, active region OD1, active region OD2, insulating region STI, insulating region IR, plug PLG, and dummy plug DG.

[0076] Active regions OD1 and OD2 have portions that are separated from each other in the X direction. An insulating region IR is formed so as to be in contact with active region OD2. The insulating region IR is planarly separated from the gate electrode G. A plug PLG is formed on active region OD1. A dummy plug DG is formed on insulating region IR. The dummy plug DG is positioned adjacent to the plug PLG.

[0077] In this configuration of the TEG, plug PLG is electrically connected to the active region OD1. If there is no piping fault between plug PLG and dummy plug DG, dummy plug DG is electrically floating. If there is a piping fault between plug PLG and dummy plug DG, dummy plug DG is electrically connected to plug PLG.

[0078] Therefore, piping defects can be detected by checking for continuity or nonconductivity between the plug PLG and the dummy plug DG. In other words, if a piping defect is detected in the TEG formed in the scribe region, there is a high probability that a piping defect is also occurring in the semiconductor device formed in the chip region. For this reason, by using the TEG in the basic concept, piping defects in semiconductor devices can be detected.

[0079] As shown in Figure 5, in the basic concept, the insulating region IR is planarly separated from the gate electrode G, unlike the insulating region IR1 of the second related technology shown in Figure 4. In other words, in the basic concept, the insulating region IR does not have a planarly overlapping portion with the gate electrode G1.

[0080] Therefore, even if the insulating region IR is formed, the processed shape of the gate electrode G and the like are not affected. That is, even if the insulating region IR is formed, it does not affect the manner in which piping defects occur. That is, it is possible to suppress the manner in which piping defects occur in the TEG in the basic idea from being different from the manner in which piping defects occur in the semiconductor device formed in the chip region. Therefore, according to the basic idea, piping defects can be detected accurately.

[0081] Hereinafter, embodiments embodying the basic idea will be described.

[0082] <Embodiment 1> The semiconductor wafer in Embodiment 1 has a plurality of chip regions and scribe regions partitioning the plurality of chip regions. A non-volatile memory is formed in each of the plurality of chip regions. The TEG formed in the scribe region is a pattern for detecting piping defects of the non-volatile memory.

[0083] <<Configuration of TEG>> FIG. 6 is a diagram showing the layout of the TEG in Embodiment 1.

[0084] In FIG. 6, the TEG has a control gate electrode CG1B, a control gate electrode CG2B, a control gate electrode CG3B, a control gate electrode CG4B, a memory gate electrode MG1B, a memory gate electrode MG2B, a memory gate electrode MG3B, a memory gate electrode MG4B, an active region OD1B, an active region OD2B, an active region OD3B, an active region OD4B, an active region OD5B, an active region OD6B, an insulating region STI1B, an insulating region STI2B, an insulating region STI3B, an insulating region STI4B, a plug PLG1B, a plug PLG3B, a plug PLG4B, a plug PLG6B, a dummy plug DG1, and a dummy plug DG2.

[0085] The active region OD2B is adjacent to the active region OD1B in the X direction. The insulating region IRA is adjacent to the active region OD2B in the Y direction, which is perpendicular to the X direction. The insulating region IRA is formed so as not to overlap with the control gate electrode CG1B in a plan view. The insulating region IRA is formed so as not to overlap with the control gate electrode CG2B in a plan view.

[0086] The insulating region IRA is planarly separated from the control gate electrode CG1B. The insulating region IRA is planarly separated from the control gate electrode CG2B. The insulating region IRA consists of a trench and an insulating film embedded within the trench.

[0087] The insulating region IRB is planarly separated from the control gate electrode CG3B. The insulating region IRB is planarly separated from the control gate electrode CG4B. The insulating region IRB consists of a trench and an insulating film embedded within the trench. The insulating regions STI1B, STI2B, STI3B, and STI4B each consist of a trench and an insulating film embedded within the trench.

[0088] Plug PLG1B is connected to the active region OD1B. Dummy plug DG1 is connected to the insulated region IRA.

[0089] The dummy plug DG1 is located in a planar manner between the control gate electrode CG1B and the control gate electrode CG2B. The dummy plug DG1 is located in a planar manner between the insulating region STI1B and the insulating region STI2B. The dummy plug DG1 is located in a planar manner between the plug PLG1B and the plug PLG3B. The dummy plug DG1 is formed on the insulating region IRA.

[0090] The dummy plug DG2 is located in a planar manner between the control gate electrode CG3B and the control gate electrode CG4B. The dummy plug DG2 is located in a planar manner between the insulating region STI3B and the insulating region STI4B. The dummy plug DG2 is located in a planar manner between the plug PLG4B and the plug PLG6B. The dummy plug DG2 is formed on the insulating region IRB.

[0091] As shown in Figure 6, in Embodiment 1, the insulating region IRA is planarly separated from the control gate electrode CG1B and the control gate electrode CG2B. The insulating region IRA does not have any planar overlapping portion with the control gate electrode CG1B and the control gate electrode CG2B.

[0092] The insulating region IRB is planarly separated from the control gate electrodes CG3B and CG4B. The insulating region IRB does not have any planar overlap with the control gate electrodes CG3B and CG4B.

[0093] Figure 7 is a cross-sectional view of the TEG along line AA in Figure 6.

[0094] In Figure 7, an active region OD2B is formed within the semiconductor substrate SUB. A control gate electrode CG1B is formed on the active region OD2B via a gate insulating film. In the Y direction, the control gate electrode CG1B and the control gate electrode CG2B are separated from each other. A memory gate electrode MG1B is formed on one sidewall of the control gate electrode CG1B via a multilayer insulating film (ONO film). A memory gate electrode MG2B is formed on one sidewall of the control gate electrode CG2B via a multilayer insulating film (ONO film).

[0095] An interlayer insulating film IL is formed on the active region OD2B so as to cover the control gate electrode CG1B, memory gate electrode MG1B, control gate electrode CG2B, and memory gate electrode MG2B. A dummy plug DG1 is formed within the interlayer insulating film IL. An insulating region IRA is formed within the active region OD2B. The dummy plug DG1 is connected to the insulating region IRA. In the Y direction, the dummy plug DG1 is located between the control gate electrode CG1B and the control gate electrode CG2B. In Figure 7, the control gate electrode CG1B and the control gate electrode CG2B are not formed on the insulating region IRA.

[0096] Therefore, as can be seen by referring to Figures 2 and 7, the cross-sectional shape of the portion of the control gate electrode CG1B located on the active region OD2B is the same as the cross-sectional shape of the portion of the control gate electrode CG1A located on the active region OD2A. The cross-sectional shape of the portion of the control gate electrode CG2B located on the active region OD2B is the same as the cross-sectional shape of the portion of the control gate electrode CG2A located on the active region OD2A.

[0097] In other words, even if an insulating region IRA is formed, the processing shape of the control gate electrode CG and memory gate electrode MG is not affected. Even if an insulating region IRB is formed, the processing shape of the control gate electrode CG and memory gate electrode MG is not affected.

[0098] According to Embodiment 1, forming an insulating region (IRA) does not affect how piping defects occur. Forming an insulating region (IRB) also does not affect how piping defects occur. In other words, it is possible to suppress the difference between how piping defects occur in the TEG in Embodiment 1 and how piping defects occur in semiconductor devices formed in the chip region. For this reason, according to Embodiment 1, piping defects can be detected with high accuracy.

[0099] In the TEG of Embodiment 1, for example, in Figure 6, if a piping defect occurs between adjacent plugs PLG1B and dummy plug DG1, plug PLG1B and dummy plug DG1 are electrically connected. Conversely, if no piping defect occurs between adjacent plugs PLG1B and dummy plug DG1, dummy plug DG1 is electrically insulated from plug PLG1B.

[0100] Therefore, for example, piping failures can be detected by checking for continuity or noncontinuity between plug PLG1B and dummy plug DG1. In other words, if a piping failure is detected in the TEG formed in the scribe area, there is a high probability that a piping failure has also occurred in the non-volatile memory formed in the chip area. For this reason, piping failures in non-volatile memory can be detected by using the TEG.

[0101] In this regard, Embodiment 1 uses the potential contrast method to detect piping defects. The method for detecting piping defects in Embodiment 1 will be described below.

[0102] <<Method for detecting piping defects>> Figure 8 shows the layout of the TEG in Embodiment 1 when no piping defects have occurred. The observation results when the TEG without piping defects is inspected using the potential contrast method are explained below. In Figure 8, brightness and darkness can be observed in the plugs by the potential contrast method. For example, plug PLG1B, which is electrically connected to the active region OD1B, is observed to be bright. Plug PLG3B, which is electrically connected to the active region OD3B, is observed to be bright. Plug PLG4B, which is electrically connected to the active region OD4B, is observed to be bright. Plug PLG6B, which is electrically connected to the active region OD6B, is observed to be bright.

[0103] In contrast, for example, dummy plug DG1, formed on the insulating region IRA, is not electrically connected to the active region OD2B. In other words, the potential of dummy plug DG1 is a floating potential. As a result, dummy plug DG1 is observed as dark. Dummy plug DG2, formed on the insulating region IRB, is not electrically connected to the active region OD5B. In other words, the potential of dummy plug DG2 is a floating potential. As a result, dummy plug DG2 is observed as dark.

[0104] Figure 9 shows the layout of the TEG in the state where a piping defect has occurred in Embodiment 1. The observation results when the TEG with the piping defect was inspected using the potential contrast method will be explained.

[0105] As shown in Figure 9, a piping defect has occurred between plug PLG1B and dummy plug DG1. In Figure 9, for example, plug PLG1B, which is electrically connected to active region OD1B, is observed to be bright. Plug PLG3B, which is electrically connected to active region OD3B, is observed to be bright. Plug PLG4B, which is electrically connected to active region OD4B, is observed to be bright. Plug PLG6B, which is electrically connected to active region OD6B, is observed to be bright.

[0106] In contrast, for example, dummy plug DG2, formed on the insulating region IRB, is not electrically connected to the active region OD5B. In other words, the potential of dummy plug DG2 is at a floating potential. As a result, dummy plug DG2 is observed as dark. On the other hand, due to poor piping, dummy plug DG1, formed on the insulating region IRA, is electrically connected to plug PLG1B, formed on the active region OD1B. As a result, dummy plug DG1 is observed as bright.

[0107] Therefore, comparing Figure 8 and Figure 9, the contrast of the dummy plug DG1 is observed to be bright rather than dark due to the piping defect. As a result, according to Embodiment 1, the piping defect can be detected.

[0108] Next, a method for manufacturing a semiconductor device having the piping defect detection method described above will be explained.

[0109] <<Manufacturing Method for Semiconductor Devices>> The manufacturing process for semiconductor devices includes a wafer process. The wafer process includes a substrate process and a wiring process. First, a semiconductor wafer having multiple chip regions and scribe regions that demarcate the multiple chip regions is prepared. After performing the substrate process on the semiconductor wafer, the interlayer insulating film formation process and the contact plug formation process, which are part of the wiring process, are performed. The semiconductor wafer after the contact plug formation process has the following configuration.

[0110] A TEG is formed within the scribe region. The TEG has a first active region, a second active region, a first gate electrode, an insulating region, a first plug, and a second plug. The first active region is formed within the semiconductor substrate. The second active region is formed within the semiconductor substrate. The second active region is adjacent to the first active region in a first direction. The first gate electrode is formed on the first active region and on the second active region. The first gate electrode extends in a first direction. The insulating region is adjacent to the second active region in a second direction perpendicular to the first direction. The insulating region is formed within the semiconductor substrate so as not to overlap with the first gate electrode in a plan view. The first plug is formed within the interlayer insulating film. The first plug is connected to the first active region. The second plug is formed within the interlayer insulating film. The second plug is connected to the insulating region.

[0111] Subsequently, the semiconductor device manufacturing method in Embodiment 1 includes a step of detecting a piping defect between the first plug and the second plug. Here, the step of detecting a piping defect between the first plug and the second plug uses a potential contrast method.

[0112] Subsequently, the process of forming the first and second wiring is carried out. The process of forming the first and second wiring is included in the wiring process. The first and second wiring are formed on the interlayer insulating film. The first wiring is in contact with the first plug. The second wiring is in contact with the second plug.

[0113] In Embodiment 1, as described above, a process for detecting piping defects is performed after carrying out part of the substrate process and wiring process (up to the contact plug formation process). Therefore, according to Embodiment 1, piping defects can be accurately detected at an early stage before the wafer process is completed. In other words, according to Embodiment 1, the manufacturing of products with piping defects can be suppressed. Specifically, piping defects can be detected at an early stage before carrying out the process of forming the first and second wiring after the contact plug formation process.

[0114] <Embodiment 2> Embodiment 2 describes an example in which a continuity check using wiring is used as a method for detecting piping defects. In Embodiment 2, wiring is used. For this reason, the TEG has wiring WL1A, wiring WL1B, and wiring WL1C in addition to the TEG configuration shown in Figure 6. Wiring WL1A is in contact with plugs PLG1B and PLG4B. Wiring WL1B is in contact with dummy plugs DG1 and DG2. Wiring WL1C is in contact with plugs PLG3B and PLG6B (see Figure 10).

[0115] Figure 10 shows the layout of the TEG in the second embodiment when no piping defects have occurred.

[0116] A continuity check between wiring WL1A and wiring WL1B reveals, for example, that there are no piping defects between plug PLG1B and dummy plug DG1, and there are no piping defects between plug PLG4B and dummy plug DG2. Therefore, it is determined that wiring WL1A and wiring WL1B are not electrically connected.

[0117] Figure 11 shows the layout of the TEG in the state where a piping defect has occurred in Embodiment 2. Specifically, as shown in Figure 11, a piping defect has occurred between plug PLG1B and dummy plug DG1.

[0118] A continuity check between wiring WL1A and wiring WL1B reveals, for example, a piping defect between plug PLG1B and dummy plug DG1, leading to the conclusion that wiring WL1A is electrically connected to wiring WL1B.

[0119] Therefore, comparing Figure 10 and Figure 11, the continuity check result between wiring WL1A and wiring WL1B will be "electrically connected" rather than "electrically disconnected" due to the piping fault. From this, it can be determined that the piping fault can be detected by detecting the state in which wiring WL1A and wiring WL1B are electrically connected to each other.

[0120] Next, a method for manufacturing a semiconductor device having the piping defect detection method described above will be explained.

[0121] Similar to Embodiment 1, after performing the substrate process on the semiconductor wafer, the interlayer insulating film formation process and the contact plug formation process, which are part of the wiring process, are performed. Furthermore, in Embodiment 2, wiring WL1A that contacts plug PLG1B and wiring WL1B that contacts dummy plug DG1 are formed.

[0122] Subsequently, in Embodiment 2, a piping defect is detected by detecting the electrical connection between wiring WL1A and wiring WL1B through a continuity check.

[0123] In Embodiment 2, as described above, a step to detect piping defects is performed after carrying out part of the substrate process and wiring process. Specifically, the step to detect piping defects is performed after carrying out the process of forming wiring WL1A, wiring WL1B, and wiring WL1C. Therefore, according to Embodiment 2, piping defects can be detected accurately at an early stage before the wafer process is completed. Piping defects can be detected before carrying out the process of forming wiring located above wiring WL1A, wiring WL1B, and wiring WL1C.

[0124] In Embodiment 2, instead of the potential contrast method, a continuity check using wiring is used as the method for detecting piping defects. In this regard, the continuity check using wiring has a shorter measurement time compared to the potential contrast method. Therefore, according to Embodiment 2, the piping defect detection process can be carried out without significantly affecting the throughput in the semiconductor device manufacturing process.

[0125] The advantages of Embodiment 2 will be described below.

[0126] Figure 12 shows a diagram illustrating the continuity check in the example.

[0127] In Figure 12, a plug PLG1B is formed on the active region OD1B. A wiring WL1A is formed on the plug PLG1B. The wiring WL1A is electrically connected to the active region OD1B via the plug PLG1B.

[0128] A plug PLG2B is formed on the active region OD2B. A wiring WL1B is formed on the plug PLG2B. The wiring WL1B is electrically connected to the active region OD2B via the plug PLG2B.

[0129] A continuity check is performed between wiring WL1A and wiring WL1B. Specifically, a 0V voltage is applied to wiring WL1A while a positive voltage is applied to wiring WL1B to perform the continuity check between wiring WL1A and wiring WL1B.

[0130] For example, if there is a piping fault between plug PLG1B and plug PLG2B, a leakage current I1 will flow between plug PLG1B and plug PLG2B. Therefore, if there is a piping fault between plug PLG1B and plug PLG2B, a continuity check will detect that wiring WL1A and wiring WL1B are electrically connected to each other.

[0131] However, in the example considered, even if there is no piping fault between plug PLG1B and plug PLG2B, a leakage current I2 flows due to the pn junction included in the active region OD2B. Therefore, even if there is no piping fault between plug PLG1B and plug PLG2B, a leakage current I2 is detected in the continuity check between wiring WL1A and wiring WL1B.

[0132] In the example considered, if the short circuit due to piping failure is minute, i.e., if the leakage current I1 due to piping failure is minute, even if the continuity check detects that wiring WL1A and wiring WL1B are electrically connected, the difference between leakage current I2 and leakage current I1 may be small, making it impossible to identify the piping failure. In other words, in the example considered, it is difficult to accurately detect piping failures.

[0133] Figure 13 shows the continuity check in Embodiment 2.

[0134] In Figure 13, a plug PLG1B is formed on the active region OD1B. Wiring WL1A is formed on plug PLG1B. Wiring WL1A is electrically connected to the active region OD1B via plug PLG1B. On the other hand, a dummy plug DG1 is formed on the insulating region IRA. Wiring WL1B is formed on the dummy plug DG1.

[0135] A continuity check is performed between wiring WL1A and wiring WL1B. Specifically, a 0V voltage is applied to wiring WL1A while a positive voltage is applied to wiring WL1B to perform the continuity check between wiring WL1A and wiring WL1B.

[0136] For example, if there is a piping fault between plug PLG1B and dummy plug DG1, a leakage current I1 will flow between plug PLG1B and dummy plug DG1. Therefore, if there is a piping fault between plug PLG1B and dummy plug DG1, the continuity check will detect that wiring WL1A and wiring WL1B are electrically connected.

[0137] In this embodiment 2, as shown in Figure 13, an insulating region IRA is formed, so the leakage current I2 shown in Figure 12 does not flow. Therefore, if there is no piping fault between plug PLG1B and dummy plug DG1, the continuity check will detect that wiring WL1A is not electrically connected to wiring WL1B.

[0138] Therefore, in Embodiment 2, if the continuity check detects that wiring WL1A and wiring WL1B are electrically connected to each other, it can be determined that a piping defect has occurred. In other words, in Embodiment 2, piping defects can be detected with high accuracy.

[0139] <Embodiment 3> The semiconductor wafer in Embodiment 3 has multiple chip regions and scribe regions that demarcate the multiple chip regions. A DRAM is formed in each of the multiple chip regions. The TEG formed in the scribe region is a pattern for detecting piping defects in the DRAM.

[0140] Figure 14 shows the layout of the TEG in Embodiment 3 when no piping defects have occurred. In Figure 14, the TEG has gate electrodes G1, G2, G3, G4, and G5. Gate electrodes G1, G2, G3, G4, and G5 are arranged at predetermined intervals from each other in the X direction. Each of gate electrodes G1, G2, G3, G4, and G5 extends in the Y direction.

[0141] Multiple plugs are arranged between gate electrode G1 and gate electrode G2. The row of plugs between gate electrode G1 and gate electrode G2 is denoted as row R1. Multiple plugs are arranged between gate electrode G2 and gate electrode G3. The row of plugs between gate electrode G2 and gate electrode G3 is denoted as row R2. Multiple plugs are arranged between gate electrode G3 and gate electrode G4. The row of plugs between gate electrode G3 and gate electrode G4 is denoted as row R3. Multiple plugs are arranged between gate electrode G4 and gate electrode G5. The row of plugs between gate electrode G4 and gate electrode G5 is denoted as row R4. In Embodiment 3, one example of a TEG is shown in row R1, and another example of a TEG is shown in row R4. Note that the illustration of the TEG is omitted in rows R2 and R3.

[0142] Let's focus on column R1. From bottom to top, column R1 contains bit plug BPLG1, dummy plug DG1, capacitive plug CPLG2, dummy plug DG2, capacitive plug CPLG3, and dummy plug DG3. Bit plug BPLG1, capacitive plug CPLG2, and capacitive plug CPLG3 are formed on the active region. Dummy plug DG1 is formed on the insulating region IR1. Dummy plug DG2 is formed on the insulating region IR2. Dummy plug DG3 is formed on the insulating region IR3.

[0143] In Figure 14, light and dark areas can be observed in the plug using the potential contrast method.

[0144] For example, bit plug BPLG1 is observed to be bright. Dummy plug DG1 is observed to be dark. Capacitive plug CPLG2 is observed to be bright. Dummy plug DG2 is observed to be dark. Capacitive plug CPLG3 is observed to be bright. Dummy plug DG3 is observed to be dark.

[0145] Let's focus on column R4. In column R4, from bottom to top, capacitive plugs CPLG5, CPLG6, dummy plug DG4, CPLG7, CPLG8, and dummy plug DG5 are arranged. Capacitive plugs CPLG5, CPLG6, CPLG7, and CPLG8 are formed on the active region. Dummy plug DG4 is formed on the insulating region IR4. Dummy plug DG5 is formed on the insulating region IR5.

[0146] In Figure 14, light and dark areas can be observed in the plug using the potential contrast method.

[0147] For example, capacitive plug CPLG5 is observed to be bright. Capacitive plug CPLG6 is observed to be bright. Dummy plug DG4 is observed to be dark. Capacitive plug CPLG7 is observed to be bright. Capacitive plug CPLG8 is observed to be bright. Dummy plug DG5 is observed to be dark.

[0148] Figure 15 shows the layout of the TEG in the state where piping defects occur in Embodiment 3. Specifically, as shown in Figure 15, piping defects occur between dummy plug DG1 and capacitive plug CPLG2. Also, piping defects occur between capacitive plug CPLG6 and dummy plug DG4.

[0149] In Figure 15, light and dark areas can be observed in the plug using the potential contrast method.

[0150] Focusing on column R1, bit plug BPLG1 is observed to be bright. Dummy plug DG1 is observed to be bright. Capacitive plug CPLG2 is observed to be bright. Dummy plug DG2 is observed to be dark. Capacitive plug CPLG3 is observed to be bright. Dummy plug DG3 is observed to be dark.

[0151] Focusing on row R4, capacitive plug CPLG5 is observed to be bright. Capacitive plug CPLG6 is observed to be bright. Dummy plug DG4 is observed to be bright. Capacitive plug CPLG7 is observed to be bright. Capacitive plug CPLG8 is observed to be bright. Dummy plug DG5 is observed to be dim.

[0152] Therefore, comparing Figure 14 and Figure 15, focusing on column R1, the dummy plug DG1 is observed brightly rather than darkly due to the piping defect. As a result, as shown in Figure 15, the bit plug BPLG1, dummy plug DG1, and capacitance plug CPLG2 are all observed brightly. By detecting this condition, according to Embodiment 3, a piping defect occurring between the dummy plug DG1 and the capacitance plug CPLG2 can be detected.

[0153] Comparing Figures 14 and 15, focusing on column R4, we see that due to the piping defect, dummy plug DG4 is observed brightly rather than darkly. As a result, as shown in Figure 15, capacitive plugs CPLG5 and CPLG6, and dummy plug DG4 are all observed brightly. By detecting this condition, a piping defect occurring between capacitive plug CPLG6 and dummy plug DG4 can be detected.

[0154] The TEGs listed in column R1 form dummy plugs every other plug, regardless of whether they are bit plugs or capacitive plugs, and also form an insulating area beneath the dummy plugs. In this case, piping defects between adjacent plugs can be detected, regardless of whether they are bit plugs or capacitive plugs.

[0155] On the other hand, the TEG described in column R4, for example, uses dummy plugs for only the bit plug (or only the capacitance plug) and forms an insulating region below the dummy plug. In this case, the layout of the insulating region and dummy plug becomes easier. That is, the TEG can be easily formed.

[0156] <Embodiment 4> The semiconductor wafer in Embodiment 4 has multiple chip regions and scribe regions that partition the multiple chip regions. SRAM is formed in each of the multiple chip regions. The TEG formed in the scribe region is a pattern for detecting piping defects in the SRAM.

[0157] Figure 16 shows the layout of the TEG in the example under consideration.

[0158] The TEG shown in Figure 16 has a pattern similar to, for example, the layout of an SRAM formed in a chip region. In Figure 16, the TEG has an n-type well NW, a p-type well PW1, and a p-type well PW2.

[0159] Multiple load transistors constituting the SRAM are formed in the n-type well NW. The load transistors are made of p-type MOSFETs. Multiple drive transistors constituting the SRAM are formed in the p-type well PW1. The drive transistors are made of n-type MOSFETs. Multiple drive transistors constituting the SRAM are formed in the p-type well PW2. The drive transistors are made of n-type MOSFETs.

[0160] In Figure 16, we focus on plugs PLG1 and PLG2.

[0161] The brightness of plugs PLG1 and PLG2 is observed using the potential contrast method. When potential conditions are used in which plug PLG1 is observed brightly within the region of the n-type well NW, plug PLG2 is observed darkly within the region of the p-type well PW1.

[0162] Therefore, if there is no piping fault between plug PLG1 and plug PLG2, plug PLG1 will appear brighter, while plug PLG2 will appear darker.

[0163] In contrast, if a piping defect A1 occurs between plug PLG1 and plug PLG2, plug PLG1 and plug PLG2 become electrically connected through the piping defect A1. As a result, plug PLG2 is observed to be bright.

[0164] Therefore, due to the piping defect A1, plug PLG2 will be observed as bright rather than dark. By detecting this condition, when using the TEG shown in Figure 16, the piping defect A1 occurring between plug PLG1 and plug PLG2 can be detected.

[0165] In Figure 16, we focus on shared plugs SPLG1 and SPLG2. Both shared plugs SPLG1 and SPLG2 are located within the n-type well NW in a plan view. Therefore, if there is no piping defect between shared plugs SPLG1 and SPLG2, shared plug SPLG1 will be observed as bright, and shared plug SPLG2 will also be observed as bright.

[0166] If a piping defect A2 occurs between shared plug SPLG1 and shared plug SPLG2, shared plug SPLG1 and shared plug SPLG2 become electrically connected to each other via the piping defect A2. As a result, shared plug SPLG2 is observed to be bright. That is, when using the TEG shown in Figure 16, regardless of whether or not a piping defect A2 occurs between shared plug SPLG1 and shared plug SPLG2, in all conditions, shared plug SPLG1 is observed to be bright, and shared plug SPLG2 is also observed to be bright.

[0167] In the SRAM cell, the distance between shared plug SPLG1 and shared plug SPLG2 is smaller than the distance between plug PLG1 and plug PLG2, making it prone to short circuits due to poor piping.

[0168] However, the TEG shown in Figure 16 cannot detect piping defects A2 that occur between shared plug SPLG1 and shared plug SPLG2.

[0169] Therefore, we use the TEG of Embodiment 4 shown in Figure 17.

[0170] Figure 17 shows the layout of the TEG in Embodiment 4.

[0171] The TEG shown in Figure 17 has a dummy plug DG1 formed on the insulating region IR1. In Figure 17, if there is no piping defect A2 between the shared plug SPLG1 and the dummy plug DG1, the shared plug SPLG1 is observed to be bright. On the other hand, although the dummy plug DG1 is formed in the n-type well NW, the dummy plug DG1 is observed to be dark because it is formed on the insulating region IR1.

[0172] In contrast, if a piping defect A2 occurs between the shared plug SPLG1 and the dummy plug DG1, the shared plug SPLG1 and the dummy plug DG1 become electrically connected to each other via the piping defect A2. As a result, the dummy plug DG1 is observed to be bright. Therefore, due to the piping defect A2, the dummy plug DG1 is observed to be bright, not dark. By detecting this condition, the piping defect A2 occurring between the shared plug SPLG1 and the dummy plug DG1 can be detected when using the TEG shown in Figure 17.

[0173] Based on the above, by using the TEG of Embodiment 4 shown in Figure 17, it is possible to detect the piping defect A2 between the shared plug SPLG1 and the dummy plug DG1.

[0174] In other words, if a piping defect A2 is detected in the TEG formed in the scribe region, there is a high probability that a piping defect has also occurred between shared plug SPLG1 and shared plug SPLG2 in the SRAM formed in the chip region.

[0175] Therefore, by using the TEG of Embodiment 4 shown in Figure 17, piping defects in the SRAM can be detected. In particular, the distance between shared plug SPLG1 and shared plug SPLG2 is smaller than the distance between plug PLG1 and plug PLG2, making it more prone to piping defects. In this regard, by adopting the method of detecting piping defects using the TEG of Embodiment 4, piping defects occurring between shared plug SPLG1 and shared plug SPLG2 can be detected with high accuracy.

[0176] The present inventors have described the invention in detail based on its embodiments, but it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0177] 10A Insulation Area 10B Insulation Area A1 Piping defect A2 Piping defect BPLG1 Bitplug CG1A Control gate electrode CG1B Control Grid Circuit CG2A Control gate electrode CG2B Control gate electrode CG3A Control Trigger Plate CG3B Control gate CG4A Control gate electrode CG4B Control gate CPLG2 Capacity Plug CPLG3 Capacity Plug CPLG5 Capacity Plug CPLG6 Capacity Plug CPLG7 Capacity Plug CPLG8 Capacity Plug DG Dummy Plug DG1 Dummy Plug DG1B Dummy Plug DG2 Dummy Plug DG2B Dummy Plug DG3 Dummy Plug DG3B Dummy Plug DG4 Dummy Plug DG4B Dummy Plug DG5 Dummy Plug G Post Office IR isolation region IRA Insulation Area IRB (Insulation Zone) IR1 Insulation Area IR2 Insulation Region IR3 Insulation Area IR4 Insulation Region IR5 isolation region MG1A Memory Gridgate MG1B Memory Grid MG2A Memory Gridgate MG2B memory gate MG3A Memory Shut-off Circuit MG3B memory gate MG4A Memory Guard Signal MG4B memory gate NW n-type well OD1 active region OD1A active region OD1B active region OD2 active region OD2A active region OD2B active region OD3A active region OD3B active region OD4A active region OD4B active region OD5A active region OD5B active region OD6A active region OD6B active region PLG Plug PLG1 Plug PLG1A Plug PLG1B Plug PLG2 Plug PLG2A plug PLG2B Plug PLG3A Plug PLG3B Plug PLG4A plug PLG4B Plug PLG5A plug PLG5B Plug PLG6A plug PLG6B Plug PW1 p-type well PW2 p-type well SPLG1 Shared Plug SPLG2 Shared Plug STI isolation area STI1A Insulation Area STI2A Insulation Area STI3A Insulation Area STI4A Insulation Area SUB Semiconductor Substrate WL1A Wiring WL1B Wiring WL1C Wiring

Claims

1. Semiconductor substrate and Multiple chip regions, A scribe region that partitions the aforementioned multiple chip regions, The semiconductor substrate has an interlayer insulating film formed on it, Within the scribe region, a TEG is formed. The aforementioned TEG is, A first active region formed within the semiconductor substrate, A second active region is formed within the semiconductor substrate and is adjacent to the first active region in the first direction, A first gate electrode formed on the first active region and the second active region and extending in the first direction, An insulating region formed within the semiconductor substrate such that it is adjacent to the second active region in a second direction perpendicular to the first direction and does not overlap with the first gate electrode in a plan view, A first plug formed within the interlayer insulating film and connected to the first active region, A second plug formed within the interlayer insulating film and connected to the insulating region, A semiconductor wafer having the following characteristics.

2. In the semiconductor wafer according to claim 1, If there is no piping defect between the first plug and the second plug, the second plug is electrically floating. If a piping defect exists between the first plug and the second plug, the second plug is electrically connected to the first plug.

3. In the semiconductor wafer according to claim 1, The first plug and the first wiring which is electrically connected, The second wiring is electrically connected to the second plug, It has.

4. In the semiconductor wafer according to claim 3, The first wiring is formed on the interlayer insulating film and is in contact with the first plug. The second wiring is formed on the interlayer insulating film and is in contact with the second plug.

5. In the semiconductor wafer according to claim 1, The aforementioned insulating region is A trench formed in the semiconductor substrate, An insulating film embedded in the trench, It has.

6. In the semiconductor wafer according to claim 1, Non-volatile memory is formed in each of the aforementioned plurality of chip regions. The TEG is configured to detect whether or not there is a piping defect in the non-volatile memory.

7. In the semiconductor wafer according to claim 6, The TEG has a second gate electrode that extends in the first direction, separate from the first gate electrode, The first active region includes a portion that overlaps in a planar manner with the first gate electrode and the second gate electrode. The second active region includes a portion that overlaps planarly with the first gate electrode and the second gate electrode. The insulating region is formed so as not to overlap the first gate electrode and the second gate electrode in a planar manner.

8. In the semiconductor wafer according to claim 1, A DRAM is formed in each of the aforementioned plurality of chip regions. The TEG is configured to detect whether or not there is a piping defect in the DRAM.

9. In the semiconductor wafer according to claim 1, SRAM is formed in each of the aforementioned plurality of chip regions. The TEG is configured to detect whether or not there is a piping defect in the SRAM.

10. In the semiconductor wafer according to claim 6, The aforementioned non-volatile memory is A third active region formed within the semiconductor substrate, A third gate electrode formed on the third active region and extending in the first direction, It has.

11. In the semiconductor wafer according to claim 10, The cross-sectional shape of the portion of the first gate electrode located on the second active region is the same as the cross-sectional shape of the portion of the third gate electrode located on the third active region.

12. (a) A step of preparing a semiconductor wafer having a semiconductor substrate, a plurality of chip regions, scribe regions that demarcate the plurality of chip regions, an interlayer insulating film formed on the semiconductor substrate, and a TEG formed within the scribe region. (b) A step of detecting a piping defect between the first plug and the second plug, Equipped with, The aforementioned TEG is, A first active region formed within the semiconductor substrate, A second active region is formed within the semiconductor substrate and is adjacent to the first active region in the first direction, A first gate electrode formed on the first active region and the second active region and extending in the first direction, An insulating region formed within the semiconductor substrate such that it is adjacent to the second active region in a second direction perpendicular to the first direction and does not overlap with the first gate electrode in a plan view, A first plug formed within the interlayer insulating film and connected to the first active region, A method for manufacturing a semiconductor device, comprising: a second plug formed in the interlayer insulating film and connected to the insulating region.

13. In the method for manufacturing a semiconductor device according to claim 12, In step (b) above, the piping defect is detected by the potential contrast method.

14. In the method for manufacturing a semiconductor device according to claim 13, The process is followed by a step of forming wiring after step (b).

15. In the method for manufacturing a semiconductor device according to claim 12, After step (a) and before step (b), A step of forming a first wiring that contacts the first plug on the interlayer insulating film, A step of forming a second wiring that contacts the second plug on the interlayer insulating film, It has, In step (b) above, the piping defect is detected by detecting the electrical connection between the first wiring and the second wiring through a continuity check.

16. In the method for manufacturing a semiconductor device according to claim 12, The aforementioned insulating region is A trench formed in the semiconductor substrate, An insulating film embedded in the trench, It has.

17. In the method for manufacturing a semiconductor device according to claim 12, A non-volatile memory is formed in each of the plurality of chip regions of the semiconductor wafer prepared in step (a) above. The TEG is configured to detect whether or not there is a piping defect in the non-volatile memory.

18. In the method for manufacturing a semiconductor device according to claim 17, The TEG has a second gate electrode that extends in the first direction, separate from the first gate electrode, The first active region includes a portion that overlaps in a planar manner with the first gate electrode and the second gate electrode. The second active region includes a portion that overlaps planarly with the first gate electrode and the second gate electrode. The insulating region is formed so as not to overlap the first gate electrode and the second gate electrode in a planar manner.

19. In the method for manufacturing a semiconductor device according to claim 17, The aforementioned non-volatile memory is A third active region formed within the semiconductor substrate, A third gate electrode formed on the third active region and extending in the first direction, It has.

20. In the method for manufacturing a semiconductor device according to claim 19, The cross-sectional shape of the portion of the first gate electrode located on the second active region is the same as the cross-sectional shape of the portion of the third gate electrode located on the third active region.

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