Chip optimization method and apparatus for intelligent chip factory, and controller and medium

Abstract

The present disclosure relates to the technical field of chips. Provided are a chip optimization method and apparatus for an intelligent chip factory, and a controller and a medium. The method comprises: acquiring defect monitoring data of a chip (S110); on the basis of the defect monitoring data of the chip and a preset defect diagnosis model, determining a target-type defect (S120); on the basis of digital defect map data corresponding to the target-type defect, an integrated layout and mask pattern information of the chip, and a preset yield prediction model, determining yield information of the target-type defect (S130); and on the basis of the yield information of the target-type defect, adjusting the integrated layout and / or the mask pattern information of the chip (S140).

Description

Chip optimization methods, devices, controllers, and media in smart chip factories

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202411791042.1, filed on December 5, 2024, entitled “Chip Optimization Method, Apparatus, Controller and Medium for Smart Chip Factory”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of chip technology, and in particular to a chip optimization method for a smart chip factory, a chip optimization apparatus for a smart chip factory, a computer-readable storage medium, and a controller. Background Technology

[0004] In related technologies, digital defect map data is not used when training yield prediction models, and there is a lack of full data digitization capability for defect scanning. This causes distortion of training data for artificial intelligence computing systems, resulting in poor prediction performance of yield prediction models, which in turn affects the yield of smart chip factories.

[0005] Public content

[0006] This disclosure aims to at least partially address one of the technical problems in related technologies. To this end, the first objective of this disclosure is to propose a chip optimization method for a smart chip factory. The method includes: acquiring chip defect monitoring data; determining target defect types based on the chip defect monitoring data and a preset defect diagnosis model; determining yield information for the target defect types based on digital defect map data corresponding to the target defect types, chip integration layout and mask pattern information, and a preset yield prediction model; and adjusting the chip integration layout and / or mask pattern information based on the yield information of the target defect types. This improves the chip yield in the smart chip factory.

[0007] The second objective of this disclosure is to propose a chip optimization device for a smart chip factory.

[0008] A third objective of this disclosure is to provide a computer-readable storage medium.

[0009] The fourth objective of this disclosure is to propose a controller.

[0010] To achieve the above objectives, the first aspect of this disclosure proposes a chip optimization method for a smart chip factory. The method includes: acquiring chip defect monitoring data; determining a target type defect based on the chip defect monitoring data and a preset defect diagnosis model; determining the yield information of the target type defect based on the digital defect map data corresponding to the target type defect, the chip's integrated layout and mask pattern information, and a preset yield prediction model; and adjusting the chip's integrated layout and / or mask pattern information based on the yield information of the target type defect.

[0011] According to one embodiment of this disclosure, the yield information of the target type defect includes the layout line yield value, wherein adjusting the chip integration layout based on the yield information of the target type defect includes: adjusting the chip integration layout when the layout line yield value is less than a first preset yield threshold.

[0012] According to one embodiment of this disclosure, the yield information of the target type defect includes a mask design yield value, wherein adjusting the mask pattern information of the chip based on the yield information of the target type defect includes: adjusting the mask pattern information of the chip when the mask design yield value is less than a second preset yield threshold.

[0013] According to one embodiment of this disclosure, the method further includes modifying the simulated digital twins of the process equipment and reactor cavity to test the adjusted chip integration layout and / or mask pattern information.

[0014] According to one embodiment of this disclosure, the method further includes: acquiring offline defect monitoring data and online defect monitoring data of the chip; training a preset defect diagnosis model based on the offline defect monitoring data and online defect monitoring data, wherein the offline defect monitoring data includes the defect type, defect information, digital defect map data of the control wafer, and the corresponding process equipment and reactor cavity, and the online defect monitoring data includes the defect type, defect information, digital defect map data of the product wafer, and the corresponding process equipment and reactor cavity.

[0015] According to one embodiment of this disclosure, the method further includes: acquiring wafer acceptance test data, wafer capability test data, lithography exposure pattern data, integrated circuit layout data, and integrated circuit mask pattern data; and training a preset yield prediction model based on the wafer acceptance test data, wafer capability test data, lithography exposure pattern data, integrated circuit layout data, and integrated circuit mask pattern data.

[0016] According to one embodiment of this disclosure, the method further includes: maintaining the target type defect according to the maintenance technology corresponding to the target type defect, so as to reduce the degree of defect.

[0017] To achieve the above objectives, a second aspect of this disclosure provides a chip optimization apparatus for a smart chip factory. The apparatus includes: an acquisition module for acquiring chip defect monitoring data; a first determination module for determining a target type defect based on the chip defect monitoring data and a preset defect diagnosis model; a second determination module for determining the yield information of the target type defect based on digital defect map data corresponding to the target type defect, chip integration layout and mask pattern information, and a preset yield prediction model; and an adjustment module for adjusting the chip integration layout and / or mask pattern information based on the yield information of the target type defect.

[0018] To achieve the above objectives, a third aspect of this disclosure provides a computer-readable storage medium storing a chip optimization program for a smart chip factory, which, when executed by a processor, implements the aforementioned chip optimization method for a smart chip factory.

[0019] To achieve the above objectives, a fourth aspect of this disclosure provides a controller, including a memory, a processor, and a chip optimization program for a smart chip factory stored in the memory and executable on the processor. When the processor executes the chip optimization program for the smart chip factory, it implements the aforementioned control method for the smart chip factory.

[0020] According to embodiments of the present disclosure, a chip optimization method, apparatus, controller, and medium for a smart chip factory include: acquiring chip defect monitoring data; determining a target type of defect based on the chip defect monitoring data and a preset defect diagnosis model; determining yield information of the target type of defect based on digital defect map data corresponding to the target type of defect, chip integration layout and mask pattern information, and a preset yield prediction model; and adjusting the chip integration layout and / or mask pattern information based on the yield information of the target type of defect. This improves the chip yield of the smart chip factory. Attached Figure Description

[0021] Figure 1 is a flowchart of a chip optimization method for a smart chip factory according to some embodiments of the present disclosure;

[0022] Figure 2 is an analytical diagram of a chip optimization method for a smart chip factory according to some embodiments of the present disclosure;

[0023] Figure 3 is a block diagram of a chip optimization apparatus for a smart chip factory according to some embodiments of the present disclosure;

[0024] Figure 4 is a block diagram of a controller according to some embodiments of the present disclosure. Detailed Implementation

[0025] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0026] The following describes in detail, with reference to the accompanying drawings, the chip optimization method, apparatus, controller, and medium of the smart chip factory according to embodiments of the present disclosure.

[0027] Figure 1 is a flowchart of a chip optimization method for a smart chip factory according to some embodiments of the present disclosure. Referring to Figure 1, the chip optimization method for a smart chip factory according to embodiments of the present disclosure may include the following steps:

[0028] S110 acquires defect monitoring data for the chip.

[0029] Specifically, chip defect monitoring data can be acquired through high-speed industrial cameras, and the specific acquisition method is not limited here.

[0030] S120 determines the target type of defect based on the chip's defect monitoring data and a preset defect diagnosis model.

[0031] Specifically, chip defects can be categorized into those that affect chip yield and those that do not. Target type defects refer to those that affect chip yield. By inputting chip defect monitoring data into a preset defect diagnosis model, target type defects can be identified within the chip's defects.

[0032] S130, determine the yield information of the target type defect based on the digital defect map data corresponding to the target type defect, the chip integration layout and mask pattern information, and the preset yield prediction model.

[0033] Specifically, after identifying the target type of defect affecting yield, it is necessary to further determine the reason why the target type of defect affects yield. For example, it may be determined that the low chip yield is due to the chip's integration layout or mask pattern. Therefore, it is necessary to input the digital defect map data corresponding to the target type of defect, the chip's integration layout, and the mask pattern information into a preset yield prediction model to predict the yield information of the target type of defect, such as the predicted layout circuit yield value and the mask design yield value.

[0034] S140, adjust the chip integration layout and / or mask pattern information based on the yield information of the target type defect.

[0035] Specifically, after determining the yield information of the target type of defect, such as the yield value of the layout circuit and the yield value of the mask design, the yield value of the layout circuit and the yield value of the mask design are compared with the preset yield value. Based on the comparison result, it is determined that the target type of defect affects the chip yield due to the integrated layout, mask pattern information or integrated layout and mask pattern information. Based on the comparison result, the integrated layout, mask pattern information or integrated layout and mask pattern information are adjusted to improve the yield.

[0036] For example, if the layout line yield value is relatively low, it indicates that the chip yield is affected by target type defects caused by the integrated layout, so the integrated layout is adjusted; if the mask design yield value is relatively low, it indicates that the chip yield is affected by target type defects caused by the mask design, so the mask pattern information is adjusted; if both the layout line yield value and the mask design yield value are relatively low, it indicates that the chip yield is affected by target type defects caused by the integrated layout and grinding design, so the integrated layout and mask pattern information are adjusted.

[0037] This improves the chip yield rate of smart chip factories.

[0038] In some embodiments, the yield information of the target type defect includes the layout circuit yield value. Adjusting the chip's integrated layout based on the target type defect yield information includes: adjusting the chip's integrated layout when the layout circuit yield value is less than a first preset yield threshold. The first preset yield threshold can be determined based on actual conditions and is not specifically limited here.

[0039] Specifically, the layout yield value is compared with the first preset yield threshold. Based on the comparison result, it is determined whether the chip yield is affected by the target type defect caused by the integrated layout. If it is determined that the chip yield is low due to the integrated layout, the chip's integrated layout is adjusted to improve the chip yield.

[0040] For example, if the layout line yield value is greater than or equal to the first preset yield threshold, it means that the integrated layout is not the cause of the target type defect affecting the chip yield, and there is no need to adjust the chip's integrated layout; if the layout line yield value is less than the first preset yield threshold, it means that the integrated layout is the cause of the target type defect affecting the chip yield, and there is a need to adjust the chip's integrated layout to improve the chip yield.

[0041] In some embodiments, the yield information of the target type defect includes a mask design yield value. Adjusting the mask pattern information of the chip based on the yield information of the target type defect includes: adjusting the mask pattern information of the chip when the mask design yield value is less than a second preset yield threshold. The second preset yield threshold can be determined according to actual conditions and is not specifically limited here.

[0042] Specifically, the mask design yield value is compared with a second preset yield threshold. Based on the comparison result, it is determined whether the target type defect caused by the mask design affects the chip yield. If it is determined that the chip yield is low due to the mask design, the mask pattern information of the chip is adjusted to improve the chip yield.

[0043] For example, if the mask design yield value is greater than or equal to the second preset yield threshold, it means that the mask design is not the cause of the target type defect affecting the chip yield, and there is no need to adjust the mask pattern information of the chip; if the mask design yield value is less than the second preset yield threshold, it means that the mask design is the cause of the target type defect affecting the chip yield, and there is a need to adjust the mask pattern information of the chip to improve the chip yield.

[0044] In some embodiments, the method further includes modifying the simulated digital twins of the process equipment and reactor chamber to test the adjusted chip integration layout and / or mask pattern information.

[0045] Specifically, after adjusting the chip's integrated layout, mask pattern information, or both integrated layout and mask pattern information, the simulated digital twins of the process equipment and reactor cavity also need to be modified accordingly. This is to test the adjusted chip's integrated layout, mask pattern information, or both integrated layout and mask pattern information, and determine whether to modify the process equipment and reactor cavity based on the test results.

[0046] For example, if the test results show that the chip yield is improved after modifying the integrated layout, mask pattern information, or both integrated layout and mask pattern information of the chip, then the process equipment and reactor cavity are modified accordingly; if the test results show that the chip yield is not improved after modifying the integrated layout, mask pattern information, or both integrated layout and mask pattern information of the chip, then the process equipment and reactor cavity are not modified accordingly.

[0047] In some embodiments, the method further includes: acquiring offline defect monitoring data and online defect monitoring data of the chip; training a preset defect diagnosis model based on the offline defect monitoring data and online defect monitoring data, wherein the offline defect monitoring data includes the defect type, defect information, digital defect map data of the control wafer, and the corresponding process equipment and reactor cavity, and the online defect monitoring data includes the defect type, defect information, digital defect map data of the product wafer, and the corresponding process equipment and reactor cavity.

[0048] For example, high-precision industrial cameras and optical systems are used to scan and capture images of the control wafer surface. Image processing techniques are used to extract defect features, labeling defect types (e.g., particles, scratches, contact defects, voids, bubbles, and contamination) and defect information (e.g., defect length, location, and shape). This defect information is then digitized into corresponding digital defect map data. Combined with the corresponding process equipment and reactor chamber, this constitutes the chip's offline defect monitoring data (control wafer defect data). The acquisition method for the chip's online defect monitoring data (product wafer defect data) is the same as that for offline defect monitoring data, and will not be elaborated here. The offline and online monitoring data are integrated to form a unified dataset, and the data is preprocessed, such as through standardization and normalization. Then, a suitable defect diagnosis model is selected, such as a deep learning-based convolutional neural network or a YOLOv8 model, training parameters are set, and the model is trained using the integrated dataset to obtain a preset defect diagnosis model.

[0049] It should be noted that no specific restrictions are placed on the training methods for the defect diagnosis model here.

[0050] In some embodiments, the method further includes: acquiring wafer acceptance test data, wafer capability test data, lithography exposure pattern data, integrated circuit layout data, and integrated circuit mask pattern data; and training a preset yield prediction model based on the wafer acceptance test data, wafer capability test data, lithography exposure pattern data, integrated circuit layout data, and integrated circuit mask pattern data.

[0051] For example, wafer acceptance test data includes test results at each location on the wafer (e.g., whether the wafer's pattern routing signal is powered on), which can be obtained through the wafer fab's yield management system. Wafer capability test data includes capability test results at each location on the wafer (e.g., whether the response speed of the wafer's pattern routing CPU is qualified), which can be obtained through the wafer fab's statistical process control system. Lithography exposure pattern data refers to the exposure status during the lithography process, which can be obtained through the lithography machine's control system. Integrated circuit layout data refers to the design layout of integrated circuits, which can be exported from integrated circuit design software. Integrated circuit mask pattern data contains the mask patterns used to manufacture integrated circuits, usually provided by the mask fabrication system. The above data are integrated to form a unified dataset, and the data is preprocessed, such as normalization, noise reduction, and missing value handling. Then, a suitable yield prediction model is selected, such as support vector machine, K-nearest neighbor, random forest, etc., training parameters are set, and the model is trained using the integrated dataset to obtain the yield prediction model.

[0052] It should be noted that no specific restrictions are placed on the training method for the yield prediction model here.

[0053] In some embodiments, the method further includes: maintaining the target type defect according to the maintenance technology corresponding to the target type defect, so as to reduce the degree of defect.

[0054] Specifically, the digital defect map data corresponding to the target type of defect is transmitted to the PMS (Periodical Maintenance System). The PMS then performs maintenance on the target type of defect based on the corresponding maintenance techniques to reduce the defect severity. Furthermore, digital defect map data corresponding to defects other than the target type can also be transmitted to the PMS. The PMS then performs maintenance on these other defects based on the corresponding maintenance techniques to further reduce their severity. In this way, the PMS can dynamically adjust machine warranties, guiding the direction of machine warranty maintenance and promptly reducing defects and failure rates.

[0055] It should be noted that during the production process of product wafers, virtual metrology technology may be used. For example, the operating parameters of the process tools are input into a preset virtual metrology AI model to predict product parameters. If the prediction results are inaccurate, it may also affect the chip yield. Therefore, if the chip yield still cannot be improved after determining the yield information of the target type of defect and adjusting the chip integration layout and / or mask pattern information according to the yield information of the target type of defect, it is necessary to adjust the preset virtual metrology AI model in order to improve the chip yield.

[0056] As a specific example, referring to Figure 2, a preset defect diagnosis model is trained based on the defect type, defect information, digital defect map data of the control wafer, and the corresponding process equipment and reactor chamber, as well as the defect type, defect information, digital defect map data of the product wafer, and the corresponding process equipment and reactor chamber. The chip defect monitoring data is input into the preset defect diagnosis model for defect diagnosis, and the target type of defect in the chip defect is diagnosed, that is, the defect affecting the chip yield is determined.

[0057] A preset yield prediction model is trained based on wafer acceptance test data, wafer capability test data, lithography exposure data, integrated circuit layout data, and integrated circuit mask pattern data. Digital defect map data corresponding to the target type of defect, chip integration layout, and mask pattern information are input into the preset yield prediction model to predict the layout circuit yield value and mask design yield value for the target type of defect. Based on the layout circuit yield value and mask design yield value, the chip integration layout and / or mask pattern information is adjusted to improve chip yield. After adjusting the chip integration layout and / or mask pattern information, the simulated digital twins of the process equipment and reactor chamber are also modified to test the adjusted chip integration layout and / or mask pattern information. Furthermore, the preset defect diagnosis model transmits the digital defect map data corresponding to the target type of defect and the digital defect map data corresponding to defects other than the target type of defect to the PMS (Process Management System). The PMS maintains the defects according to the corresponding maintenance techniques to reduce the defect severity.

[0058] In summary, the optimization method disclosed herein digitizes all defect information scanning, collecting data and information such as defect location, defect characteristics, defect quantity, defect composition and classification, and defect causes. This data is then used to train a pre-defined defect diagnosis model and a pre-defined yield prediction model. The pre-defined defect diagnosis model is used to determine the defect types affecting yield, and the pre-defined yield prediction model is used to determine the reasons why defects affect yield. Based on these reasons, corresponding adjustments are made, thereby improving chip yield. Furthermore, it can, to some extent, avoid damage to products caused by electron beam scanning ions, reduce or replace the frequency or sampling quantity and scanning frequency area of ​​defect scanning on the machine or product, dynamically support PMS adjustments to machine warranty, guide machine warranty direction to promptly reduce defects and failure rates, provide real-time feedback on machine or chip anomalies and faults, search for poorly performing or outlier machines in machine groups, assist in machine rating and dynamic optimization of process machine systems, and assist in digital twin simulation of process machines and reactor chambers to optimize process machines.

[0059] Corresponding to the above embodiments, this disclosure also proposes a chip optimization device for a smart chip factory.

[0060] Referring to Figure 3, the chip optimization device 300 of the smart chip factory includes: an acquisition module 310, a first determination module 320, a second determination module 330, and an adjustment module 340.

[0061] The acquisition module 310 is used to acquire defect monitoring data of the chip. The first determination module 320 is used to determine the target type of defect based on the chip's defect monitoring data and a preset defect diagnosis model. The second determination module 330 is used to determine the yield information of the target type of defect based on the digital defect map data corresponding to the target type of defect, the chip's integrated layout and mask pattern information, and a preset yield prediction model. The adjustment module 340 is used to adjust the chip's integrated layout and / or mask pattern information based on the yield information of the target type of defect.

[0062] According to one embodiment of this disclosure, the yield information of the target type defect includes the layout line yield value, and the adjustment module 340 is specifically used to adjust the integrated layout of the chip when the layout line yield value is less than a first preset yield threshold.

[0063] According to one embodiment of this disclosure, the yield information of the target type defect includes the mask design yield value. The adjustment module 340 is specifically used to adjust the mask pattern information of the chip when the mask design yield value is less than a second preset yield threshold.

[0064] According to one embodiment of this disclosure, the simulated digital twins of the process equipment and reactor cavity are modified to test the adjusted chip integration layout and / or mask pattern information.

[0065] According to one embodiment of this disclosure, offline defect monitoring data and online defect monitoring data of a chip are acquired; a preset defect diagnosis model is trained based on the offline defect monitoring data and online defect monitoring data, wherein the offline defect monitoring data includes the defect type, defect information, digital defect map data of the control wafer, and the corresponding process equipment and reactor cavity, and the online defect monitoring data includes the defect type, defect information, digital defect map data of the product wafer, and the corresponding process equipment and reactor cavity.

[0066] According to one embodiment of this disclosure, wafer acceptance test data, wafer capability test data, lithography exposure pattern data, integrated circuit layout data, and integrated circuit mask pattern data are obtained; a preset yield prediction model is trained based on the wafer acceptance test data, wafer capability test data, lithography exposure pattern data, integrated circuit layout data, and integrated circuit mask pattern data.

[0067] According to one embodiment of this disclosure, the target type defect is maintained according to the maintenance technology corresponding to the target type defect in order to reduce the degree of defect.

[0068] It should be noted that the above explanation of the embodiments and beneficial effects of the chip optimization method for smart chip factories also applies to the chip optimization apparatus for smart chip factories in the embodiments of this disclosure. To avoid redundancy, it will not be elaborated in detail here.

[0069] Corresponding to the above embodiments, this disclosure also proposes a computer-readable storage medium.

[0070] The present disclosure discloses a computer-readable storage medium storing a chip optimization program for a smart chip factory, which, when executed by a processor, implements the aforementioned chip optimization method for a smart chip factory.

[0071] It should be noted that the above explanation of the embodiments and beneficial effects of the chip optimization method for smart chip factories also applies to the computer-readable storage medium of the embodiments of this disclosure. To avoid redundancy, it will not be elaborated in detail here.

[0072] Corresponding to the above embodiments, this disclosure also proposes a controller.

[0073] Referring to Figure 4, the controller 400 of this disclosure includes a memory 410, a processor 420, and a chip optimization program for a smart chip factory stored in the memory 410 and executable on the processor 420. When the processor 420 executes the chip optimization program for the smart chip factory, it implements the aforementioned control method for the smart chip factory.

[0074] It should be noted that the above explanation of the embodiments and beneficial effects of the control method for intelligent chip factories also applies to the controllers of the embodiments of this disclosure. To avoid redundancy, they will not be elaborated in detail here.

[0075] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0076] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0077] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0079] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0080] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A chip optimization method for a smart chip factory, the method comprising: Acquire defect monitoring data for the chip; The target type of defect is determined based on the defect monitoring data of the chip and the preset defect diagnosis model; The yield information of the target type defect is determined based on the digital defect map data corresponding to the target type defect, the chip integration layout and mask pattern information, and the preset yield prediction model. The chip's integration layout and / or mask pattern information are adjusted based on the yield information of the target type of defect.

2. The chip optimization method for a smart chip factory according to claim 1, wherein, The yield information for the target type of defect includes the layout circuit yield value, wherein adjusting the integrated layout of the chip based on the yield information for the target type of defect includes: If the yield value of the layout circuit is less than the first preset yield threshold, the integrated layout of the chip is adjusted.

3. The chip optimization method for a smart chip factory according to claim 1 or 2, wherein, The yield information for the target type of defect includes a mask design yield value, wherein adjusting the mask pattern information of the chip based on the yield information for the target type of defect includes: If the mask design yield value is less than the second preset yield threshold, the mask pattern information of the chip is adjusted.

4. The chip optimization method for a smart chip factory according to claim 3, wherein, The method further includes: The simulated digital twins of the process equipment and reactor chamber are modified to test the adjusted integrated layout and / or mask pattern information of the chip.

5. The chip optimization method for a smart chip factory according to claim 1, wherein, The method further includes: Acquire offline and online defect monitoring data for the chip; The preset defect diagnosis model is trained based on the offline defect monitoring data and the online defect monitoring data. The offline defect monitoring data includes the defect type, defect information, digital defect map data of the control wafer, and the corresponding process equipment and reactor cavity. The online defect monitoring data includes the defect type, defect information, digital defect map data of the product wafer, and the corresponding process equipment and reactor cavity.

6. The chip optimization method for a smart chip factory according to claim 1, wherein, The method further includes: Acquire wafer acceptance test data, wafer capability test data, lithography exposure data, integrated circuit layout data, and integrated circuit mask pattern data; The preset yield prediction model is trained based on the wafer acceptance test data, the wafer capability test data, the photolithography exposure data, the integrated circuit layout data, and the integrated circuit mask pattern data.

7. The chip optimization method for a smart chip factory according to claim 1, wherein, The method further includes: Based on the maintenance techniques corresponding to the target type of defect, the target type of defect is maintained to reduce the degree of defect.

8. A chip optimization apparatus for a smart chip factory, the apparatus comprising: The acquisition module is used to acquire defect monitoring data of the chip; The first determining module is used to determine the target type defect based on the defect monitoring data of the chip and the preset defect diagnosis model; The second determining module is used to determine the yield information of the target type defect based on the digital defect map data corresponding to the target type defect, the chip's integrated layout and mask pattern information, and a preset yield prediction model; An adjustment module is used to adjust the integrated layout and / or mask pattern information of the chip based on the yield information of the target type of defect.

9. A computer-readable storage medium storing a chip optimization program for a smart chip factory, wherein the chip optimization program for a smart chip factory, when executed by a processor, implements the chip optimization method for a smart chip factory according to claims 1-7.

10. A controller comprising a memory, a processor, and a chip optimization program for a smart chip factory stored in the memory and executable on the processor, wherein when the processor executes the chip optimization program for the smart chip factory, it implements the control method for the smart chip factory according to claims 1-7.

Images