Semiconductor and display devices

JP2026102800APending Publication Date: 2026-06-23SEMICON ENERGY LAB CO LTD

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Patent Information

Authority / Receiving Office: JP · JP
Patent Type: Applications
Current Assignee / Owner: SEMICON ENERGY LAB CO LTD
Filing Date: 2026-03-18
Publication Date: 2026-06-23

Application Information

Patent Timeline

18 Mar 2026

Application

23 Jun 2026

Publication

JP2026102800A

IPC: G09G3/20; G09G3/3225; G09F9/00; G09F9/30; H10D30/67; H10D86/40; H10K59/12

CPC: G09G3/3659; G09G2300/0439; G09G2300/0814; G09G3/3611

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Static indicating devices Identification means

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【0021】 本発明の一形態によれば、表示装置の駆動回路の構成において、配線を含めた回路の構成を簡略化することが可能となる。すなわち、アクティブ状態(選択信号が出力される状態)と非アクティブ状態(選択信号が出力されない状態、又は非選択信号が出力され続ける状態)を制御する信号が入力される配線(クロック信号線など)を設けることで、部分駆動可能な表示装置を提供することができる。

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Figure 2026102800000001_ABST

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Abstract

To provide a display device that simplifies the circuit configuration, including wiring, while also enabling partial drive. The challenge is to address the following issues. [Solution] Multiple signal processing circuits are provided in stages corresponding to the gate signal lines of the pixel region, and the signal processing In the circuit, the first transistor controls the potential of the gate signal line, and the gate signal line's active Active state (a selection signal is output), Inactive state (a selection signal is not output) A signal is input to control the state (or the state in which a non-selection signal is continuously output), and the next stage is started. The clock signal is input to the second transistor, which outputs a reset signal and a reset signal to the previous stage. By configuring it in this way, the number of wires required for the device to operate is reduced.

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Claims

1. It has first to eleventh transistors, Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor, the other of which is always in contact with the first gate signal line, Either the source or the drain of the second transistor is always in contact with the power line. The source or drain of the second transistor, the other of which, is always in contact with the first gate signal line. Either the source or the drain of the third transistor is always in contact with the second clock signal line. The source or drain of the third transistor, the other of which is always in contact with the second gate signal line, Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor, the other of which is always in contact with the second gate signal line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The gate of the fifth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the sixth transistor is always in contact with the gate of the second transistor. Either the source or the drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in contact with the first signal line. Either the source or drain of the eighth transistor is always in contact with the gate of the sixth transistor. The source or drain of the eighth transistor is always in electrical contact with the source or drain of the sixth transistor. The gate of the eighth transistor is always in contact with the other of the source or drain of the eighth transistor. Either the source or the drain of the ninth transistor is always in electrical contact with the power line. The source or drain of the ninth transistor is always in contact with the gate of the sixth transistor. The gate of the ninth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the 10th transistor is always in contact with the gate of the 1st transistor. The gate of the 10th transistor is always in contact with the second signal line. Either the source or drain of the 11th transistor is always in contact with the third gate signal line. The gate of the 11th transistor is always in contact with the third gate signal line. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor, at least through the channel formation region of the fifth transistor, the fifth transistor is ON. When the power line is in a conductive state with the gate of the second transistor, the gate of the fourth transistor and the gate of the fifth transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is ON. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the tenth transistor, the tenth transistor is ON. When the third gate signal line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the eleventh transistor, the eleventh transistor is ON. At least one of the first to eleventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

2. It has first to eleventh transistors, Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor, the other of which is always in contact with the first gate signal line, Either the source or the drain of the second transistor is always in contact with the power line. The source or drain of the second transistor, the other of which, is always in contact with the first gate signal line. Either the source or the drain of the third transistor is always in contact with the second clock signal line. The source or drain of the third transistor, the other of which is always in contact with the second gate signal line, Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor, the other of which is always in contact with the second gate signal line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fifth transistor is always in electrical contact with the power line. The gate of the fifth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the sixth transistor is always in contact with the gate of the second transistor. Either the source or the drain of the seventh transistor is always in electrical contact with the power line. The gate of the seventh transistor is always in contact with the first signal line. Either the source or drain of the eighth transistor is always in contact with the gate of the sixth transistor. The source or drain of the eighth transistor is always in electrical contact with the source or drain of the sixth transistor. The gate of the eighth transistor is always in contact with the other of the source or drain of the eighth transistor. Either the source or the drain of the ninth transistor is always in electrical contact with the power line. The source or drain of the ninth transistor is always in contact with the gate of the sixth transistor. The gate of the ninth transistor is always in electrical contact with the gate of the first transistor. The source or drain of the 10th transistor is always in electrical contact with the power line. The gate of the 10th transistor is always in contact with the second signal line. Either the source or drain of the 11th transistor is always in contact with the gate of the first transistor. The gate of the 11th transistor is always in contact with the third gate signal line. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor, at least through the channel formation region of the fifth transistor, the fifth transistor is ON. When the power line is in a conductive state with the gate of the second transistor, the gate of the fourth transistor and the gate of the fifth transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is ON. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the tenth transistor, the tenth transistor is ON. When the third gate signal line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the eleventh transistor, the eleventh transistor is ON. At least one of the first to eleventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

3. It has a gate driver and a pixel, The gate driver has first to eleventh transistors, Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor, the other of which is always in contact with the first gate signal line, Either the source or the drain of the second transistor is always in contact with the power line. The source or drain of the second transistor, the other of which, is always in contact with the first gate signal line. Either the source or the drain of the third transistor is always in contact with the second clock signal line. The source or drain of the third transistor, the other of which is always in contact with the second gate signal line, Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor, the other of which is always in contact with the second gate signal line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The gate of the fifth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the sixth transistor is always in contact with the gate of the second transistor. Either the source or the drain of the seventh transistor is always in contact with the gate of the second transistor. The gate of the seventh transistor is always in contact with the first signal line. Either the source or drain of the eighth transistor is always in contact with the gate of the sixth transistor. The source or drain of the eighth transistor is always in electrical contact with the source or drain of the sixth transistor. The gate of the eighth transistor is always in contact with the other of the source or drain of the eighth transistor. Either the source or the drain of the ninth transistor is always in electrical contact with the power line. The source or drain of the ninth transistor is always in contact with the gate of the sixth transistor. The gate of the ninth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the 10th transistor is always in contact with the gate of the 1st transistor. The gate of the 10th transistor is always in contact with the second signal line. Either the source or drain of the 11th transistor is always in contact with the third gate signal line. The gate of the 11th transistor is always in contact with the third gate signal line. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor, at least through the channel formation region of the fifth transistor, the fifth transistor is ON. When the power line is in a conductive state with the gate of the second transistor, the gate of the fourth transistor and the gate of the fifth transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is ON. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the tenth transistor, the tenth transistor is ON. When the third gate signal line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the eleventh transistor, the eleventh transistor is ON. At least one of the first to eleventh transistors has an oxide semiconductor in its channel formation region. The pixel is connected to the first gate signal line, The aforementioned pixel is a display device having a light-emitting element.

4. It has a gate driver and a pixel, The gate driver has first to eleventh transistors, Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor, the other of which is always in contact with the first gate signal line, Either the source or the drain of the second transistor is always in contact with the power line. The source or drain of the second transistor, the other of which, is always in contact with the first gate signal line. Either the source or the drain of the third transistor is always in contact with the second clock signal line. The source or drain of the third transistor, the other of which is always in contact with the second gate signal line, Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor, the other of which is always in contact with the second gate signal line, The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fifth transistor is always in electrical contact with the power line. The gate of the fifth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the sixth transistor is always in contact with the gate of the second transistor. Either the source or the drain of the seventh transistor is always in electrical contact with the power line. The gate of the seventh transistor is always in contact with the first signal line. Either the source or drain of the eighth transistor is always in contact with the gate of the sixth transistor. The source or drain of the eighth transistor is always in electrical contact with the source or drain of the sixth transistor. The gate of the eighth transistor is always in contact with the other of the source or drain of the eighth transistor. Either the source or the drain of the ninth transistor is always in electrical contact with the power line. The source or drain of the ninth transistor is always in contact with the gate of the sixth transistor. The gate of the ninth transistor is always in electrical contact with the gate of the first transistor. The source or drain of the 10th transistor is always in electrical contact with the power line. The gate of the 10th transistor is always in contact with the second signal line. Either the source or drain of the 11th transistor is always in contact with the gate of the first transistor. The gate of the 11th transistor is always in contact with the third gate signal line. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor, at least through the channel formation region of the fifth transistor, the fifth transistor is ON. When the power line is in a conductive state with the gate of the second transistor, the gate of the fourth transistor and the gate of the fifth transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is ON. When the power line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the tenth transistor, the tenth transistor is ON. When the third gate signal line is in a conductive state with the gate of the first transistor, the gate of the third transistor and the gate of the ninth transistor via at least the channel formation region of the eleventh transistor, the eleventh transistor is ON. At least one of the first to eleventh transistors has an oxide semiconductor in its channel formation region. The pixel is connected to the first gate signal line, The aforementioned pixel is a display device having a light-emitting element.