Information processing system

Abstract

This information processing system is configured to notify the status of the inference circuit during its formation, and to recover the logic data even if a power outage occurs while the logic data for the inference circuit is being rewritten. [Solution] The information processing system 1 is configured to include a first programmable logic device 10 that forms a communication circuit 13 for communication, and a second programmable logic device 20 that forms an inference circuit 23 that performs inference processing according to a learning model. For example, when the information processing system 1 is started up, the first programmable logic device 10 is configured to form the communication circuit 13 before the second programmable logic device 20.

Description

Technical Field

[0001] The present invention relates to an information processing system.

Background Art

[0002] Conventionally, a technique for performing inference processing based on a learning model using a programmable logic device (PLD) has been proposed (for example, Patent Document 1). In this conventional technique, when a new learning model is created, inference processing based on the new learning model can be performed by rewriting an inference circuit based on the logic data of the new learning model.

[0003] Also, conventionally, a technique for forming a communication circuit in a programmable logic device has been proposed (for example, Patent Documents 2 and 3). By forming a communication circuit in a programmable logic device, for example, when the communication protocol is changed, the communication circuit can be rewritten to support the new communication protocol.

[0004] By the way, when an inference circuit is formed in a programmable logic device, as the learning model increases, the inference circuit becomes large-scale. Therefore, a programmable logic device that executes inference processing based on a learning model assumes a large-scale circuit in the future, and a large-capacity one is selected in advance. On the other hand, the circuit scale of the communication circuit is small compared to the inference circuit. Therefore, a configuration in which the inference circuit and the communication circuit are formed in the same programmable logic device can be easily considered.

[0005] Figure 7 shows an example configuration of a system 200 in which an inference circuit 222 and a communication circuit 221 are formed on the same programmable logic device 203. This system 200 comprises a processor 201, a bus 202, and a circuit board 205. The circuit board 205 mounts the programmable logic device 203 and a storage unit 204. The processor 201 is connected to the bus 202 and, via the bus 202, to the programmable logic device 203. The programmable logic device 203 is connected to the bus 202 and also to an external device 252 via a network 251. The programmable logic device 203 is also connected to the storage unit 204.

[0006] The memory unit 204 is comprised of a non-volatile memory device whose data can be rewritten. The memory unit 204 stores logic data 233 that is applied to the programmable logic device 203. This logic data 233 includes logic data 231 for the communication circuit and logic data 232 for the inference circuit.

[0007] The programmable logic device 203 includes a configuration circuit 210 and a circuit formation region 220. The configuration circuit 210 is formed as a fixed circuit whose configuration cannot be changed. On the other hand, the circuit formation region 220 is a region in which the circuit configuration can be changed.

[0008] When power is supplied to the programmable logic device 203, the configuration circuit 210 forms a circuit in the circuit formation area 220 during startup. At this time, the configuration circuit 210 reads logic data 233 from the storage unit 204 and forms a circuit in the circuit formation area 220 based on the logic data 233. The configuration circuit 210 forms a communication circuit 221 in the circuit formation area 220 based on logic data 231 for the communication circuit. The configuration circuit 210 also forms an inference circuit 222 in the circuit formation area 220 based on logic data 232 for the inference circuit.

[0009] If the inference circuit 222 is large in scale, the configuration circuit 210 will take a considerable amount of time to form the inference circuit 222. Even if the communication circuit 221 is small in scale, the communication circuit 221 will not operate until all circuit formation in the circuit formation area 220 is complete. Therefore, if the inference circuit 222 is large in scale, it will take a long time to form the circuit, and the communication circuit 221 will be unusable until the circuit formation is complete. Consequently, the system 200 on which the programmable logic device 203 is implemented will be unable to communicate with the outside world until the circuit formation by the configuration circuit 210 is complete. Therefore, users of the system 200 will not be able to understand the status of the system 200 after power-on, resulting in a problem of poor usability.

[0010] Furthermore, since the learning model is updated daily, the logic data 232 for the inference circuit is also frequently updated. As shown in Figure 7, when the inference circuit 222 and the communication circuit 221 are formed on the same programmable logic device 203, the logic data 232 for the inference circuit in the memory unit 204 is rewritten via the communication circuit 221. However, as the amount of data in the logic data 232 for the inference circuit increases, rewriting the data also takes a long time. Therefore, there is a possibility that the power supply to the system 200 may be cut off while the logic data 232 is being rewritten via the communication circuit 221. If the power supply to the system 200 is cut off while the logic data 232 is being rewritten, the logic data 232 in the memory unit 204 may be corrupted. In that case, the programmable logic device 203 will not be able to properly form the inference circuit 222 at startup, and will also be unable to use the communication circuit 221. Consequently, the system 200 will not be able to properly restore the programmable logic device 203, and will be forced to replace the board 205. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Publication No. 2022-32179 [Patent Document 2] Japanese Patent Publication No. 2004-326143 [Patent Document 3] Japanese Patent Publication No. 2008-90582 [Overview of the Initiative] [Problems that the invention aims to solve]

[0012] This invention was made to solve the above problems. Specifically, the present invention aims to provide an information processing system that makes it easier for the user to understand the state of the system even while an inference circuit is being formed, and that enables the logic data to be restored normally even if a power outage occurs while the logic data for the inference circuit is being rewritten. [Means for solving the problem]

[0013] To achieve the above objective, the invention according to claim 1 is an information processing system characterized by comprising: a first programmable logic device that forms a communication circuit for performing communication; and a second programmable logic device that forms an inference circuit that performs inference processing according to a learning model.

[0014] The invention according to claim 2 is characterized in that, in the information processing system of claim 1, at startup, the first programmable logic device forms the communication circuit before the second programmable logic device.

[0015] The invention according to claim 3 is characterized in that, in the information processing system of claim 2, the second programmable logic device starts forming the inference circuit after the communication circuit has been formed in the first programmable logic device.

[0016] The invention according to claim 4 is characterized in that, in the information processing system of claim 1, the system further comprises a storage unit that stores first logic data for forming the communication circuit and second logic data for forming the inference circuit, wherein the first programmable logic device forms the communication circuit by reading the first logic data from the storage unit and expanding it, and the second programmable logic device forms the inference circuit by reading the second logic data from the storage unit and expanding it.

[0017] The invention according to claim 5 is characterized in that, in the information processing system of claim 4, the second logic data is rewritten in accordance with the update of the learning model.

[0018] The invention according to claim 6 is characterized in that, in the information processing system of claim 5, the communication circuit is capable of rewriting the second logic data stored in the storage unit.

[0019] The invention according to claim 7 is an information processing system according to claim 2, further comprising a first programmable logic device and a processor connected to the second programmable logic device, wherein the processor is capable of communicating with the outside via the communication circuit after the communication circuit is formed in the first programmable logic device.

[0020] The invention according to claim 8 is characterized in that, in the information processing system of claim 7, the first programmable logic device has a first configuration circuit that forms the communication circuit, and the first configuration circuit notifies the processor of the formation state of the communication circuit.

[0021] The invention according to claim 9 is the information processing system according to claim 8, wherein the second programmable logic device has a second configuration circuit that forms the inference circuit, and the second configuration circuit is configured to notify the processor of the formation state of the inference circuit.

[0022] The invention according to claim 10 is the information processing system according to claim 9, wherein the processor is configured to notify externally, via the communication circuit, of the formation state of the inference circuit.

[0023] The invention according to claim 11 is the information processing system according to claim 10, wherein the processor is configured to send an error notification via the communication circuit when the inference circuit is not formed in the second programmable logic device.

[0024] The invention according to claim 12 is the information processing system according to claim 10, wherein the processor is configured to notify, via the communication circuit, the completion of startup when the formation of the inference circuit is completed in the second programmable logic device.

[0025] The invention according to claim 13 is the information processing system according to any one of claims 1 to 12, further comprising an acquisition unit that acquires the physical property information of the paper, and the inference circuit outputs image formation parameters for the paper by performing the inference process based on the physical property information acquired by the acquisition unit.

[0026] [[ID=十九]] The invention according to claim 14 is the information processing system according to claim 13, wherein the learning model is a learning model that has learned teacher data in which the physical property information of the paper, the image formation parameters applied when forming an image on the paper, and the evaluation information indicating the evaluation result of the image formed on the paper are mutually associated. [[ID=二十二]]

[0027] It should be noted that there is an error in the line "[[ID=十九]] " where the Chinese character "十九" is used instead of a correct ID. It should be something like a proper number or alphanumeric combination as in other cases. Also, "[[ID=二十二]]

[0027] " has a similar incorrect Chinese character usage. These might be input errors and should be corrected for a more accurate and proper translation.The invention according to claim 15 is characterized in that, in the information processing system of claim 14, the system further comprises: a paper feeder for feeding paper; an image forming unit for forming an image on the paper fed from the paper feeder; and a physical property detection unit disposed between the paper feeder and the image forming unit in the paper transport path, which detects the physical properties of the paper and generates physical property information, wherein the acquisition unit acquires the physical property information from the physical property detection unit.

[0028] The invention according to claim 16 is characterized in that, in the information processing system of claim 15, the system further comprises an image inspection unit provided downstream of the image forming unit in the paper transport path, which inspects the image formed on the paper in the image forming unit and generates the evaluation information. [Effects of the Invention]

[0029] According to the present invention, a communication circuit for communication and an inference circuit for executing inference processing according to a learning model are formed in separate programmable logic devices. Therefore, the present invention makes it possible to notify the outside via the communication circuit of the status of the inference circuit during its formation. Furthermore, even if a power outage occurs while the logic data for the inference circuit is being rewritten, the present invention makes it possible to recover the logic data via the communication circuit. [Brief explanation of the drawing]

[0030] [Figure 1] This is a diagram showing the information processing system in the first embodiment. [Figure 2] This diagram illustrates the circuit formation procedure for a programmable logic device. [Figure 3] This figure shows the information processing system in the second embodiment. [Figure 4] This figure shows an example of the configuration of the information processing system and external devices in the third embodiment. [Figure 5] This is a diagram showing the schematic configuration of the information processing system, which is the fourth embodiment. [Figure 6] This is a block diagram showing an example of the configuration of the control unit. [Figure 7] This figure shows an example configuration in which the inference circuit and communication circuit are formed on the same programmable logic device. [Modes for carrying out the invention]

[0031] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. In the embodiments described below, elements common to all are denoted by the same reference numerals, and redundant explanations of these elements will be omitted.

[0032] (First Embodiment) First, a first embodiment of the present invention will be described. Figure 1 is a diagram showing an information processing system 1 according to the first embodiment of the present invention. This information processing system 1 comprises a processor 2, a bus 3, an acquisition unit 4, a first programmable logic device 10, a second programmable logic device 20, and a storage unit 30. The first programmable logic device 10 and the second programmable logic device 20 are composed of, for example, field-programmable gate arrays (FPGAs). The processor 2 is an arithmetic processing unit that performs various processes by executing a computer-readable program.

[0033] The processor 2, the first programmable logic device 10, and the second programmable logic device 20 are connected to the bus 3 and can input and output data to each other. The first programmable logic device 10, the second programmable logic device 20, and the storage unit 30 are mounted on a single board 5. The acquisition unit 4 is connected to the second programmable logic device 20 and supplies inference data to the second programmable logic device 20.

[0034] The first programmable logic device 10 is a device that forms a communication circuit 13. The first programmable logic device 10 includes a configuration circuit 11 formed in a fixed area where the circuit configuration cannot be changed, and a circuit formation area 12 where the circuit configuration can be changed. When the first programmable logic device 10 is started up, the configuration circuit 11 reads logic data 31 for the communication circuit from the storage unit 30 and expands the logic data 31 in the circuit formation area 12, thereby forming the communication circuit 13 in the circuit formation area 12. The logic data 31 for the communication circuit is first logic data.

[0035] The second programmable logic device 20 is a device that forms an inference circuit 23. The second programmable logic device 20 includes a configuration circuit 21 formed in a fixed area where the circuit configuration cannot be changed, and a circuit formation area 22 where the circuit configuration can be changed. When the second programmable logic device 20 is started up, the configuration circuit 21 reads logic data 32 for the inference circuit from the storage unit 30 and expands the logic data 32 into the circuit formation area 22, thereby forming the inference circuit 23 in the circuit formation area 22. The logic data 32 for the inference circuit is the second logic data.

[0036] The storage unit 30 is composed of a non-volatile storage device that allows data to be rewritten. The storage unit 30 stores logic data 31 for a communication circuit applied to the first programmable logic device 10 and logic data 32 for an inference circuit applied to the second programmable logic device 20.

[0037] The logic data 31 for the communication circuit is data for forming a communication circuit 13 for communication in the first programmable logic device 10. The circuit size of the communication circuit 13 is relatively small. Therefore, the amount of data in the logic data 31 for the communication circuit is small compared to the amount of data in the logic data 32 for the inference circuit.

[0038] The logic data 32 for the inference circuit is data for forming an inference circuit 23 that causes the second programmable logic device 20 to perform inference processing according to the learned model. The logic data 32 for the inference circuit is updated as a new learned model is generated. The amount of data in the logic data 32 for the inference circuit increases each time it is updated. Therefore, the circuit size of the inference circuit 23 tends to be relatively large. The amount of data in the logic data 32 for the inference circuit is larger than the amount of data in the logic data 31 for the communication circuit.

[0039] When the formation of the communication circuit 13 begins in the first programmable logic device 10, the configuration circuit 11 notifies the processor 2 via the bus 3 that the circuit is being formed. This allows the processor 2 to recognize that the communication circuit 13 is being formed in the first programmable logic device 10. Once the formation of the communication circuit 13 is complete, the configuration circuit 11 notifies the processor 2 via the bus 3 that the circuit formation is complete. This allows the processor 2 to recognize that the communication circuit 13 is now available in the first programmable logic device 10.

[0040] When the formation of the inference circuit 23 begins in the second programmable logic device 20, the configuration circuit 21 notifies the processor 2 via the bus 3 that the circuit is being formed. This allows the processor 2 to recognize that the inference circuit 23 is being formed in the second programmable logic device 20. Once the formation of the inference circuit 23 is complete, the configuration circuit 21 notifies the processor 2 via the bus 3 that the circuit formation is complete. This allows the processor 2 to recognize that the inference circuit 23 is now available in the second programmable logic device 20.

[0041] Once the circuit formation is complete, the communication circuit 13 connects to a network 8, such as a local area network (LAN). The communication circuit 13 then establishes a state where it can communicate with an external device 9 via the network 8. As a result, the processor 2 becomes capable of communicating with the external device 9 via the bus 3 and the communication circuit 13.

[0042] Furthermore, the communication circuit 13 is connected to the storage unit 30 via an internal bus 15 formed on the circuit board 5. Therefore, the communication circuit 13 can access the storage unit 30 via the internal bus 15 and rewrite the logic data 31 and 32 stored in the storage unit 30.

[0043] The acquisition unit 4 collects information detected by various sensors installed in the information processing system 1, for example, and acquires data for inference. The acquisition unit 4 then outputs the inference data collected from the sensors to the second programmable logic device 20. The acquisition unit 4 may also be connected to the bus 3. In that case, the acquisition unit 4 outputs the inference data to the second programmable logic device 20 via the bus 3.

[0044] Once circuit formation is complete, the inference circuit 23 performs inference processing according to the learning model on the inference data provided by the acquisition unit 4 and outputs the inference result. For example, the inference circuit 23 outputs the inference result to the processor 2.

[0045] Configuration circuits 11 and 21 are assigned a priority for circuit formation. The priority of configuration circuit 11 is set to be higher than that of configuration circuit 21. Configuration circuits 11 and 21 are connected by a communication line 14 formed on the board 5, and transmit and receive control signals via the communication line 14 when the power is turned on. These control signals contain information regarding the priority of circuit formation. Therefore, configuration circuits 11 and 21 recognize each other's priority by transmitting and receiving control signals when the power is turned on, and perform circuit formation based on that priority.

[0046] Figure 2 illustrates the circuit formation procedure in programmable logic devices 10 and 20. As shown in Figure 2, when power is supplied to the information processing system 1 (step S1), the configuration circuits 11 and 21 in the programmable logic devices 10 and 20 begin to operate. The configuration circuits 11 and 21 then send and receive control signals to each other (step S2). Through this transmission and reception of control signals, configuration circuit 11 recognizes that its priority is higher than that of configuration circuit 21.

[0047] Because the configuration circuit 11 has a higher priority than the configuration circuit 21, it starts circuit formation before the configuration circuit 21 (step S3). That is, the configuration circuit 11 accesses the memory unit 30 to read the logic data 31 for the communication circuit and expands the logic data 31 into the circuit formation area 12, thereby forming the communication circuit 13 in the circuit formation area 12. Since the amount of data in the logic data 31 for the communication circuit is relatively small, the time T1 required from the start to the completion of circuit formation of the communication circuit 13 is relatively short. Therefore, the configuration circuit 11 can quickly form the communication circuit 13 in the circuit formation area 12 of the first programmable logic device 10.

[0048] When the configuration circuit 11 begins forming the communication circuit 13, it notifies the processor 2 via the bus 3 that the communication circuit 13 is being formed. This allows the processor 2 to understand that the communication circuit 13 is being formed.

[0049] Once the communication circuit 13 is formed (step S4), the configuration circuit 11 sends a control signal to the configuration circuit 21 indicating that the circuit formation is complete (step S5). The configuration circuit 11 also notifies the processor 2 of the completion of the circuit formation via the bus 3. As a result, the processor 2 recognizes that the communication circuit 13 is now available in the first programmable logic device 10.

[0050] When the configuration circuit 21 receives a control signal from the configuration circuit 11 indicating the completion of circuit formation, it begins circuit formation (step S6). That is, the configuration circuit 21 begins circuit formation after the communication circuit 13 has been formed in the first programmable logic device 10. The configuration circuit 21 accesses the memory unit 30 to read the logic data 32 for the inference circuit and expands the logic data 32 into the circuit formation area 22, thereby forming the inference circuit 23 in the circuit formation area 22. The logic data 32 for the inference circuit is logic data based on a learning model. Therefore, the amount of data in the logic data 32 for the inference circuit is relatively large, and the time T2 required from the start to the completion of circuit formation of the inference circuit 23 is relatively long. In particular, the larger the learning model, the longer the time T2 required for circuit formation becomes. For this reason, the configuration circuit 21 takes a long time to form the inference circuit 23 in the circuit formation area 22 of the second programmable logic device 20.

[0051] When the configuration circuit 21 begins forming the inference circuit 23, it notifies the processor 2 via the bus 3 that the inference circuit 23 is being formed. This allows the processor 2 to understand that the inference circuit 23 is being formed. At this time, the communication circuit 13 is already operating in the first programmable logic device 10. Therefore, the processor 2 can notify the outside via the network 8 that the inference circuit 23 is being formed. Thus, a user attempting to use the information processing system 1 can understand that the information processing system 1 is forming the inference circuit 23 through the notification from the processor 2.

[0052] For example, if, as in conventional technology, notification from the processor 2 is not available, and the formation of the inference circuit 23 takes a long time, the user may mistakenly believe that the information processing system 1 has not started up properly. However, the information processing system 1 of this embodiment can notify the user that the inference circuit 23 is being formed by utilizing the communication circuit 13 that is formed earlier, thus preventing the user from having a mistaken belief.

[0053] Once the circuit formation of the inference circuit 23 is complete (step S7), the configuration circuit 21 notifies the processor 2 via the bus 3 that the circuit formation is complete. As a result, the processor 2 recognizes that the inference circuit 23 is now available in the second programmable logic device 20. Therefore, the processor 2 can notify the outside via the network 8 that the circuit formation of the inference circuit 23 is complete and that the information processing system 1 has started up successfully. Thus, a user who intends to use the information processing system 1 can understand from the notification from the processor 2 that inference processing by the information processing system 1 is now available.

[0054] In Figure 1, an example is shown in which logic data 31 for the communication circuit and logic data 32 for the inference circuit are stored in a single storage unit 30. However, the storage units for storing the logic data 31 for the communication circuit and the logic data 32 for the inference circuit may be provided separately. In that case, when power is supplied to the information processing system 1, the configuration circuits 11 and 21 can start circuit formation simultaneously. However, even in that case, the communication circuit 13 in the first programmable logic device 10 will be completed before the inference circuit 23 in the second programmable logic device 20. Therefore, the processor 2 can use the communication circuit 13, which is completed first, to notify the outside that the inference circuit 23 is being formed.

[0055] As described above, the information processing system 1 of this embodiment includes a first programmable logic device 10 that forms a communication circuit 13, and a second programmable logic device 20 that forms an inference circuit 23 that performs inference processing according to the learning model. Therefore, even if it takes a long time to form the inference circuit 23, the information processing system 1 can use the communication circuit 13, which is formed relatively early in the first programmable logic device 10, to notify the outside that the inference circuit 23 is being formed.

[0056] Furthermore, the information processing system 1 is configured such that, upon startup after power-on, the first programmable logic device 10 forms the communication circuit 13 before the second programmable logic device 20. Therefore, the information processing system 1 can use the communication circuit 13 formed first in the first programmable logic device 10 to notify the outside that the inference circuit 23 is in the process of forming.

[0057] Furthermore, the information processing system 1 can rewrite the logic data 31 for the communication circuit and the logic data 32 for the inference circuit stored in the memory unit 30 via the communication circuit 13 formed in the first programmable logic device 10. For example, the processor 2 may receive new logic data 32 for the inference circuit based on a new learning model. In that case, the processor 2 can access the memory unit 30 via the communication circuit 13 and rewrite the logic data 32 for the inference circuit stored in the memory unit 30 with the new logic data 32 for the inference circuit.

[0058] If the learning model is enormous, the amount of data in the inference circuit logic data 32 will also be enormous. Therefore, the time required for the processor 2 to rewrite the inference circuit logic data 32 in the memory unit 30 will be long. There is a possibility that the power supply to the information processing system 1 may be cut off while the processor 2 is rewriting the inference circuit logic data 32 via the communication circuit 13. If the power supply to the information processing system 1 is cut off while the inference circuit logic data 32 is being rewritten, there is a possibility that the inference circuit logic data 32 in the memory unit 30 may be corrupted.

[0059] However, in this embodiment, the information processing system 1 can form a communication circuit 13 in the first programmable logic device 10 even if the logic data 32 for the inference circuit in the storage unit 30 is corrupted. Therefore, when the inference circuit 23 is not formed properly in the second programmable logic device 20, the processor 2 can notify the outside via the communication circuit 13 that there has been an error in the circuit formation of the inference circuit 23. Furthermore, by utilizing the normally functioning communication circuit 13, the information processing system 1 can transfer new logic data 32 for the inference circuit to the storage unit 30 again. In other words, the information processing system 1 can rewrite the corrupted logic data 32 for the inference circuit with uncorrupted logic data 32. This restores the logic data 32 for the inference circuit in the storage unit 30. After restoring the logic data 32 for the inference circuit, the information processing system 1 is restarted, and the inference circuit 23 corresponding to the new learning model is formed properly in the second programmable logic device 20.

[0060] Therefore, even if a power outage occurs while the logic data 32 for the inference circuit is being rewritten, the information processing system 1 of this embodiment can recover the logic data 32 for the inference circuit and can be used continuously without replacing the board 5.

[0061] (Second Embodiment) Next, a second embodiment of the present invention will be described. Figure 3 is a diagram showing an information processing system 1 in the second embodiment of the present invention. This information processing system 1 includes a power supply circuit 6. When power is supplied to the information processing system 1, the power supply circuit 6 supplies power to the processor 2 and operates the processor 2. At this time, the power supply circuit 6 does not supply power to the first programmable logic device 10 and the second programmable logic device 20. Therefore, the first programmable logic device 10 and the second programmable logic device 20 do not start circuit formation. The power supply circuit 6 may also start supplying power to the storage unit 30 at the same time as supplying power to the processor 2.

[0062] When the processor 2 starts operation, it controls the power supply circuit 6 so that power is supplied sequentially to the first programmable logic device 10 and the second programmable logic device 20.

[0063] First, the processor 2 outputs a first instruction to the power supply circuit 6, initiating the supply of power to the first programmable logic device 10. This causes the configuration circuit 11 to operate in the first programmable logic device 10, and the communication circuit 13 is formed. Once the formation of the communication circuit 13 is complete, the configuration circuit 11 notifies the processor 2 that the circuit formation is complete.

[0064] When the processor 2 receives notification from the first programmable logic device 10 that circuit formation is complete, it outputs a second instruction to the power supply circuit 6, initiating power supply to the second programmable logic device 20. This causes the configuration circuit 21 to operate in the second programmable logic device 20, and the inference circuit 23 is formed. Once the formation of the inference circuit 23 is complete, the configuration circuit 21 notifies the processor 2 that circuit formation is complete.

[0065] In other words, the information processing system 1 can form the communication circuit 13 of the first programmable logic device 10 before the inference circuit 23 of the second programmable logic device 20, without the configuration circuits 11 and 21 communicating with each other. Furthermore, other than the above, the information processing system 1 is the same as described in the first embodiment.

[0066] (Third embodiment) Next, a third embodiment of the present invention will be described. In this embodiment, an example is described in which logic data 32 for an inference circuit corresponding to a novel learning model is generated by an external device 9. Figure 4 is a diagram showing an example of the configuration of the information processing system 1 and the external device 9 in this embodiment. The information processing system 1 has the same configuration as described in the first embodiment. However, the information processing system 1 may have the same configuration as in the second embodiment.

[0067] The external device 9 is installed on a cloud, such as the internet. Therefore, the external device 9 can communicate with multiple information processing systems 1 via a network 8, such as the internet.

[0068] The external device 9 comprises a learning model generation unit 9a and a logic conversion unit 9b. The learning model generation unit 9a receives training data 7 to improve the accuracy of the inference process in the inference circuit 23. The learning model generation unit 9a performs machine learning based on the training data 7 and generates a new learning model. The logic conversion unit 9b receives the new learning model generated by the learning model generation unit 9a. The logic conversion unit 9b converts the new learning model into logic data and generates logic data 32 for the inference circuit corresponding to the new learning model.

[0069] When the external device 9 generates logic data 32 for an inference circuit corresponding to a new learning model, it provides the logic data 32 for the inference circuit to the information processing system 1 via the network 8. For example, the external device 9 connects to the communication circuit 13 and rewrites the logic data 32 for the inference circuit stored in the memory unit 30 from the outside via the communication circuit 13.

[0070] Furthermore, the external device 9 may notify the processor 2 of the information processing system 1 that the logic data 32 for the inference circuit has been updated. In this case, the processor 2 accesses the external device 9 and obtains the updated logic data 32 for the inference circuit from the external device 9. Subsequently, the processor 2 accesses the storage unit 30 via the communication circuit 13 and rewrites the logic data 32 for the inference circuit stored in the storage unit 30 from the outside.

[0071] In this embodiment, the information processing system 1 acquires the logic data 32 for the inference circuit generated by the external device 9 and updates the logic data 32 for the inference circuit stored in the storage unit 30.

[0072] (Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. Figure 5 is a diagram showing the schematic configuration of an information processing system 1, which is the fourth embodiment of the present invention. This information processing system 1 is configured as an image forming system 100 that forms and outputs an image on paper (sheet) such as printing paper.

[0073] The image forming system 100 comprises a paper feeder 120, a paper characteristics detection device 130, an image forming device 110, an image inspection device 140, and a post-processing device 150. The paper feeder 120, paper characteristics detection device 130, image forming device 110, image inspection device 140, and post-processing device 150 are arranged sequentially along the X direction shown in Figure 1 and are mechanically and electrically connected to each other. When the execution of a print job is started, the image forming system 100 feeds sheet-like paper 109, such as printing paper, from the paper feeder 120 and transports the paper 109 along the transport path 160. That is, the paper 109 fed from the paper feeder 120 is transported sequentially through the paper characteristics detection device 130, the image forming device 110, the image inspection device 140, and the post-processing device 150. The image forming system 100 forms an image on the paper 109 as it passes through the image forming device 110 while being transported. The paper 109 on which the image has been formed undergoes post-processing such as stapling and punching in the post-processing device 150, and is then discharged into the output trays 151 and 152.

[0074] The paper feeder 120 is equipped with multiple paper trays 121. Multiple sheets of paper 109 are stored in these multiple paper trays 121 in a stacked state. The paper feeder 120 is equipped with a paper transport unit 122. The paper transport unit 122 picks up one sheet of paper 109 at a time from the paper trays 121 specified in the job and sends it to the transport path 160. The paper 109 sent out from the paper feeder 120 is transported to the paper characteristic detection device 130.

[0075] The paper characteristics detection device 130 detects the characteristics of the paper 109 fed from the paper feeder 120. For example, the paper characteristics detection device 130 detects various physical properties of the paper 109 as its characteristics. The paper characteristics detection device 130 has two transport paths 160 for transporting the paper 109: a first transport path 161 and a second transport path 162. The first transport path 161 is the path that sends the paper 109 sent from the paper feeder 120 to the image forming apparatus 110, and is the path that transports the paper 109 for which an image is formed. The first transport path 161 is formed as a path that penetrates the inside of the paper characteristics detection device 130 in the left-right direction (X direction). The second transport path 162 branches off from the first transport path 161 inside the paper characteristics detection device 130 and is a path that purges and discharges the paper 109 without sending it to the image forming apparatus 110. The second transport path 162 is formed upward (in the Z direction) from a branching section 165 provided in the first transport path 161, and discharges the paper 109 into a purge tray 167 provided at the top of the device. The branching section 165 is provided with a wing-shaped switching member that switches whether the paper 109 is guided to the first transport path 161 or the second transport path 162.

[0076] A first physical property detection unit 134 is provided upstream of the branching section 165 in the first transport path 161. The first physical property detection unit 134 is equipped with multiple physical property detection sensors to detect the physical properties of the paper 109 being transported along the first transport path 161. For example, the first physical property detection unit 134 includes a moisture content detection sensor, a paper thickness detection sensor, and a basis weight detection sensor. The moisture content detection sensor detects the moisture content contained in the paper 109 while it is being transported along the first transport path 161. The paper thickness detection sensor detects the paper thickness of the paper 109 while it is being transported along the first transport path 161. The basis weight detection sensor detects the basis weight of the paper 109 while it is being transported along the first transport path 161. Therefore, the first physical property detection unit 134 detects the moisture content, paper thickness, and basis weight as physical property values ​​of the paper 109.

[0077] A second physical property detection unit 136 is provided in the second transport path 162. The second physical property detection unit 136 is equipped with multiple physical property detection sensors to detect the physical properties of the paper 109 being transported along the second transport path 162. For example, the second physical property detection unit 136 includes a stiffness detection sensor, a surface quality detection sensor, and a resistance detection sensor. The stiffness detection sensor detects the stiffness of the paper 109 being transported along the second transport path 162. The surface quality detection sensor detects the surface condition of the paper 109 being transported along the second transport path 162. The resistance detection sensor applies a high voltage to the paper 109 being transported along the second transport path 162 and detects the electrical resistance of the paper 109. Therefore, the second physical property detection unit 136 detects stiffness, surface quality, and electrical resistance as physical property values ​​of the paper 109. Furthermore, the second physical property detection unit 136 may detect the physical properties of the paper 109 when the paper 109 reaches a predetermined position in the second transport path 162, while the transport of the paper 109 is stopped.

[0078] For example, before the execution of a print job begins, the paper characteristics detection device 130 transports the paper 109 to be used in that print job to the second transport path 162. The paper characteristics detection device 130 then detects the physical properties of the paper 109 using the first physical property detection unit 134 and the second physical property detection unit 136, and generates physical property information about the paper 109. This physical property information is output to the image forming apparatus 110. Based on this physical property information, the image forming apparatus 110 sets the optimal image forming parameters for the paper 109 when the execution of the print job begins.

[0079] Furthermore, after the execution of a print job has started, the paper characteristic detection device 130 detects the paper properties such as moisture content, paper thickness, and basis weight as the paper 109 fed from the paper feeder 120 passes through the first physical property detection unit 134, and generates physical property information. The paper characteristic detection device 130 then outputs the physical property information to the image forming apparatus 110 each time it detects the physical properties of the paper 109. Therefore, the image forming apparatus 110 can appropriately adjust the image forming parameters based on the physical property information obtained from the paper characteristic detection device 130 during the execution of a print job.

[0080] The image forming apparatus 110 comprises a control unit 111, an operation panel 113, and an image forming unit 115. The control unit 111 comprehensively controls the image forming operation in the image forming system 100. The control unit 111 sets the print job based on user operations performed on the operation panel 113. Then, based on the physical property information output from the paper characteristic detection device 130, the control unit 111 sets the optimal image forming parameters for the paper 109 and controls the operation of the image forming unit 115 to form an image on the paper 109.

[0081] Inside the image forming apparatus 110, there is a paper reversal path 163 that branches off from the transport path 160. When double-sided printing of the paper 109 is specified, the image forming apparatus 110 guides the paper 109, which has an image formed on one side in the image forming unit 115, from the transport path 160 to the paper reversal path 163. The image forming apparatus 110 then reverses the front and back sides of the paper 109 in the paper reversal path 163 and supplies the paper 109 back to the image forming unit 115. This performs double-sided printing on the paper 109.

[0082] The image forming unit 115 forms an image on the paper 109 as it passes a predetermined image forming position P along the transport path 160. The image forming unit 115 forms the image on the paper 109, for example, by an electrophotographic method. The image forming unit 115 can form a color image on the paper 109 by superimposing images corresponding to each color, Y (yellow), M (magenta), C (cyan), and K (black), onto the paper 109.

[0083] The image inspection device 140 receives the paper 109 on which an image has been formed in the image forming device 110 and transports it along the transport path 160. The image inspection device 140 is equipped with image sensors 141 and 142 arranged along an internal transport path 16. Image sensor 141 is located upstream of image sensor 142 and below the transport path 160, and reads the image formed on the first surface of the paper 109. Image sensor 142 is located downstream of image sensor 141 and above the transport path 160, and reads the image formed on the second surface of the paper 109.

[0084] The image inspection device 140 includes an image inspection unit 143. The image inspection unit 143 acquires images read by image sensors 141 and 142, inspects the images formed on the paper 109, and generates evaluation information. For example, if the image formed on the paper 109 is a defective image, the image inspection unit 143 notifies the control unit 111 that a defective image has been detected. Furthermore, when the image inspection unit 143 detects a defective image, it instructs the post-processing device 150 to purge and eject the paper 109 in which the defective image was detected.

[0085] The post-processing device 150 comprises output trays 151 and 152, and a post-processing unit 153. The post-processing device 150 branches the transport path 160 into two internally, with output trays 151 and 152 provided at the end of each transport path 160. The post-processing unit 153 is located on one of the branched transport paths 160 and performs post-processing on the paper 109. Post-processing performed by the post-processing unit 153 may include stapling, punching, cutting, folding, and binding. The post-processing unit 153 only needs to perform at least one of these processes. The post-processing unit 153 discharges the processed paper 109 to the output tray 151. Furthermore, if the post-processing device 150 receives notification from the image inspection device 140 that a defective image has been formed, it discharges the paper 109 with the defective image to the output tray 152.

[0086] Figure 6 is a block diagram showing an example configuration of the control unit 111. As shown in Figure 6, the control unit 111 of the image forming system 100 has the same configuration as the information processing system 1 described in the first embodiment. The acquisition unit 4 acquires physical property information about the paper 109 from the first physical property detection unit 134 and the second physical property detection unit 136. When the acquisition unit 4 acquires physical property information about the paper 109, it supplies that physical property information to the inference circuit 23 of the second programmable logic device 20. The acquisition unit 4 may also supply the physical property information to the inference circuit 23 via the processor 2.

[0087] The inference circuit 23 of the second programmable logic device 20 starts inference processing based on a learned model when it acquires physical property information. That is, the inference circuit 23 performs inference processing based on various physical property values ​​included in the physical property information and outputs optimal image formation parameters for the paper 109. When the processor 2 receives image formation parameters corresponding to the physical property information output from the inference circuit 23, it applies those image formation parameters to the image formation unit 115. As a result, when the image formation unit 115 performs image formation on the paper 109, a high-quality image can be formed on the paper 109. The learned model in this case is a model that has learned training data in which the physical property information of the paper 109, the image formation parameters applied when forming an image on the paper 109, and evaluation information indicating the evaluation result of the image formed on the paper 109 are interconnected.

[0088] In recent years, the types of paper 109 used in image formation have become more diverse. Therefore, the image formation system 100 can determine the optimal image formation parameters for the paper 109 used in a print job by performing inference processing based on a learning model that has learned the physical property information of various types of paper 109.

[0089] As shown in Figure 6, the acquisition unit 4 acquires evaluation information indicating the image inspection results by the image inspection unit 143. Upon acquiring the evaluation information, the acquisition unit 4 outputs it to the processor 2. The processor 2 generates training data based on the physical property information acquired by the acquisition unit 4, the image formation parameters determined by the inference circuit 23, and the evaluation information acquired by the acquisition unit 4. The processor 2 then transmits the training data to the external device 9 via the communication circuit 13 of the first programmable logic device 10, causing the external device 9 to perform machine learning. As a result, a new learning model is generated in the external device 9, and the logic data 32 for the inference circuit in the memory unit 30 is updated.

[0090] As described above, the information processing system 1 of this embodiment is installed in the image forming system 100. The information processing system 1 is configured to determine the optimal image forming parameters for the paper 109 used in the print job by performing inference processing based on a learning model that has learned the physical property information of various types of paper 109. Therefore, with this information processing system 1, high-quality images can be formed on various types of paper 109.

[0091] In this embodiment, configurations and operations other than those described above may be those described in any of the first to third embodiments.

[0092] (modified version) Preferred embodiments of the present invention have been described above. However, the present invention is not limited to those described in the above embodiments, and various modifications are applicable.

[0093] For example, in the above embodiment, an example was described in which the logic data of the storage unit 30 is rewritten via a communication circuit 13 formed in the first programmable logic device 10. However, the rewriting of the logic data of the storage unit 30 may be performed using an interface different from the communication circuit 13 of the first programmable logic device 10.

[0094] Furthermore, in the fourth embodiment described above, an example was given in which the information processing system 1 is applied to the image forming system 100. However, the system to which the information processing system 1 described above can be applied is not limited to the image forming system 100.

[0095] Furthermore, in the above embodiment, an example was given in which logic data based on the learning model is generated in an external device 9. However, the logic data based on the learning model may also be generated in the information processing system 1.

[0096] Furthermore, the above embodiment primarily illustrates that the logic data 32 for the inference circuit of the memory unit 30 is rewritten. However, not only the logic data 32 for the inference circuit, but also the logic data 31 for the communication circuit of the memory unit 30 can be rewritten in the same way. For example, if the communication protocol of the communication circuit 13 is changed, the processor 2 rewrites the logic data 31 for the communication circuit of the memory unit 30 via the communication circuit 13. As a result, the first programmable logic device 10 can form a communication circuit 13 with the changed communication protocol at the next startup. [Explanation of symbols]

[0097] 1. Information Processing System 2 processors 4 Acquisition part 9 External device 10. First Programmable Logic Device 11. Configuration Circuit 13 Communication Circuits 20. Second Programmable Logic Device 21 Configuration Circuit 23 Inference circuit 30 Storage section 31. Logic data for communication circuits (first logic data) 32 Logic data for inference circuit (second logic data) 100 Image Forming Systems (Information Processing Systems) 110 Image forming apparatus 115 Image forming unit 120 Paper feeder 130 Paper Characteristics Detection Device 134 First physical property detection unit (physical property detection unit) 136 Second physical property detection unit (physical property detection unit) 140 Image inspection equipment 143 Imaging Inspection Department 150 Post-processing equipment

Claims

1. A first programmable logic device that forms a communication circuit for communication, A second programmable logic device that forms an inference circuit that performs inference processing according to the learning model, An information processing system characterized by comprising the following features.

2. The information processing system according to claim 1, characterized in that, at startup, the first programmable logic device forms the communication circuit before the second programmable logic device.

3. The information processing system according to claim 2, characterized in that the second programmable logic device starts forming the inference circuit after the communication circuit has been formed in the first programmable logic device.

4. A storage unit that stores first logic data for forming the communication circuit and second logic data for forming the inference circuit. Furthermore, The first programmable logic device forms the communication circuit by reading and expanding the first logic data from the storage unit. The information processing system according to claim 1, characterized in that the second programmable logic device forms the inference circuit by reading and expanding the second logic data from the storage unit.

5. The information processing system according to claim 4, characterized in that the second logic data is rewritten in accordance with the update of the learning model.

6. The information processing system according to claim 5, characterized in that the communication circuit is capable of rewriting the second logic data stored in the memory unit.

7. A processor connected to the first programmable logic device and the second programmable logic device, Furthermore, The information processing system according to claim 2, characterized in that the processor can communicate with the outside via the communication circuit after the communication circuit is formed in the first programmable logic device.

8. The first programmable logic device has a first configuration circuit that forms the communication circuit, The information processing system according to claim 7, characterized in that the first configuration circuit notifies the processor of the formation state of the communication circuit.

9. The second programmable logic device has a second configuration circuit that forms the inference circuit, The information processing system according to claim 8, characterized in that the second configuration circuit notifies the processor of the formation state of the inference circuit.

10. The information processing system according to claim 9, characterized in that the processor notifies the external party of the formation state of the inference circuit via the communication circuit.

11. The information processing system according to claim 10, characterized in that the processor provides error notification via the communication circuit when the inference circuit is not formed in the second programmable logic device.

12. The information processing system according to claim 10, characterized in that the processor notifies the start-up / end-up of the inference circuit via the communication circuit when the formation of the inference circuit in the second programmable logic device is completed.

13. An acquisition unit that acquires physical property information of paper. Furthermore, The information processing system according to any one of claims 1 to 12, characterized in that the inference circuit outputs image formation parameters for the paper by performing the inference process based on the physical property information acquired by the acquisition unit.

14. The information processing system according to claim 13, characterized in that the learning model is a learning model that has learned training data in which the physical property information of the paper, the image formation parameters applied when forming an image on the paper, and the evaluation information indicating the evaluation result of the image formed on the paper are mutually associated.

15. A paper feeder for feeding paper, An image forming unit that forms an image on paper fed from the aforementioned paper feeding device, In the paper transport path, a physical property detection unit is positioned between the paper feed device and the image forming unit, which detects the physical properties of the paper and generates physical property information. Furthermore, The information processing system according to claim 14, characterized in that the acquisition unit acquires the physical property information from the physical property detection unit.

16. In the paper transport path, an image inspection unit is provided downstream of the image forming unit and inspects the image formed on the paper in the image forming unit to generate the evaluation information. The information processing system according to claim 15, further comprising the above.

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