Gate drive unit and display device including the same

Abstract

The present invention provides a gate drive unit capable of controlling the drive frequency for each area of ​​the display panel, and a display device including the same. [Solution] The gate drive unit is a light-emitting drive unit including a plurality of cascaded light-emitting stages, wherein the plurality of light-emitting stages output a plurality of light-emitting control signals based on a light-emitting start signal and a plurality of light-emitting clock signals. The output control unit includes a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light-emitting control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages includes an output unit that outputs a pull-up control signal and a pull-down control signal based on a light-emitting control signal, a clock signal, a carry unit that outputs a carry signal, a control clock signal, a first power supply and a second power supply.

Claims

1. A light-emitting drive unit including a plurality of cascaded light-emitting stages, wherein the plurality of light-emitting stages output a plurality of light-emitting control signals based on a light-emitting start signal and a plurality of light-emitting clock signals, and An output control unit including a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on the plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply, Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on at least one of the plurality of light emission control signals, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and A gate drive unit including an output unit that outputs the pull-up control signal and the pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply and the second power supply.

2. The gate drive unit according to claim 1, further comprising a scan drive unit including a plurality of cascaded gate stages, wherein the plurality of gate stages output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals, and the plurality of pull-up control signals and the plurality of pull-down control signals.

3. The gate drive unit according to claim 2, wherein the signal levels of the plurality of gate signals are controlled based on the plurality of pull-up control signals and the plurality of pull-down control signals.

4. The gate drive unit according to claim 3, wherein each of the plurality of pull-up control signals and each of the plurality of pull-down control signals have opposite phases to each other.

5. The gate drive unit according to claim 2, wherein each of the plurality of control clock signals has a waveform that toggles between a gate-on level and a gate-off level or is maintained at a gate-on level.

6. In the interval where at least one control clock signal has a gate-on level, the scan drive unit outputs the gate signal having a gate-on level pulse. The gate drive unit according to claim 5, wherein, in the interval during which the at least one control clock signal toggles between a gate-on level and a gate-off level, the scan drive unit outputs the gate signal which is maintained at the gate-off level.

7. The aforementioned multiple gate stages are divided into multiple gate stage groups, The gate drive unit according to claim 2, wherein each of the plurality of gate stage groups receives the same pull-up control signal from the plurality of pull-up control signals and receives the same pull-down control signal from the plurality of pull-down control signals.

8. The aforementioned carrying section is, A first transistor including a gate electrode connected between a first input terminal to which the light emission control signal is provided and a first control node, and connected to a second input terminal to which at least one clock signal is provided, A second transistor, which includes a gate electrode connected to the first input terminal and connected to the first input terminal, is connected between the second control node and the first power supply input terminal to which the voltage of the first power supply is supplied. A third transistor including a gate electrode connected between the second input terminal and the first QB node and connected to the second control node, A fourth transistor, including a gate electrode connected between the first power input terminal and the first QB node and connected to the first control node, A fifth transistor, including a gate electrode connected to the first Q node, is connected between the second power input terminal to which the voltage of the second power supply is supplied and the first output terminal to which the carry signal is output. A sixth transistor, including a gate electrode connected between the first power input terminal and the first output terminal and connected to the first QB node, A first bridge voltage transistor, which includes a gate electrode connected between the first control node and the first Q node and connected to the second power input terminal, and The gate drive unit according to claim 1, further comprising a first capacitor connected between the second input terminal and the second control node.

9. The aforementioned carrying section is, A second capacitor connected between the first Q node and the first output terminal, and The gate drive unit according to claim 8, further comprising a third capacitor connected between the first QB node and the first power input terminal.

10. The output unit is, A seventh transistor including a gate electrode connected between the third input terminal to which the carry signal is provided and the third control node, and connected to the fourth input terminal to which at least one control clock signal is provided, An eighth transistor, including a gate electrode connected between the fourth control node and the first power input terminal to which the voltage of the first power supply is supplied, and which is connected to the third input terminal, A ninth transistor, which includes a gate electrode connected between the fourth input terminal and the second QB node and connected to the fourth control node, A tenth transistor, including a gate electrode connected between the first power input terminal and the second QB node and connected to the third control node, An eleventh transistor, including a gate electrode connected to the second Q node, is connected between the second power input terminal to which the voltage of the second power supply is supplied and the second output terminal to which the pull-up control signal is output. A twelfth transistor, including a gate electrode connected between the first power input terminal and the second output terminal and connected to the second QB node, A second bridge voltage transistor, which includes a gate electrode connected between the third control node and the second Q node and connected to the second power input terminal, and It includes a fourth capacitor connected between the fourth input terminal and the fourth control node, The gate drive unit according to claim 1, wherein the pull-down control signal is output through a third output terminal connected to the second QB node.

11. The output unit is, A fifth capacitor connected between the second Q node and the second output terminal, and The gate drive unit according to claim 10, further comprising a sixth capacitor connected between the second QB node and the first power input terminal.

12. Each of the aforementioned multiple gate stages is A gate signal generation unit that controls the voltage of the output node based on the gate start signal, the plurality of gate clock signals, the first power supply and the second power supply, and The gate drive unit according to claim 2, further comprising a masking unit that controls the signal level of the gate signal based on the pull-up control signal and the pull-down control signal.

13. The aforementioned masking portion is A first masking transistor, which includes a gate electrode that receives the pull-up control signal, is connected between the output node and the gate output terminal to which the gate signal is output, and The gate drive unit according to claim 12, further comprising a second masking transistor connected between the gate output terminal and a first power input terminal to which the voltage of the first power supply is supplied, or between the gate output terminal and a second power input terminal to which the voltage of the second power supply is supplied, and including a gate electrode that receives the pull-down control signal.

14. The gate drive unit according to claim 1, further comprising a voltage selection unit including a plurality of cascaded selection stages, wherein the plurality of selection stages output a plurality of bias voltages based on the plurality of pull-up control signals, the plurality of pull-down control signals, a first voltage, and a second voltage having a voltage level different from the first voltage.

15. The gate drive unit according to claim 14, wherein, based on the plurality of pull-up control signals and the plurality of pull-down control signals, the plurality of bias voltages have the voltage level of the first voltage or the voltage level of the second voltage.

16. The aforementioned voltage selection unit is A first selection transistor, which includes a gate electrode that receives the pull-up control signal, is connected between a first voltage terminal to which the first voltage is supplied and a voltage output terminal to which the bias voltage is output, and The gate drive unit according to claim 14, further comprising a second selection transistor connected between the voltage output terminal and the second voltage terminal to which the second voltage is supplied, and including a gate electrode that receives the pull-down control signal.

17. An output control unit including a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply, and A scan drive unit including a plurality of cascaded gate stages, wherein the plurality of gate stages output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals, a plurality of pull-up control signals, and a plurality of pull-down control signals, Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on at least one of the plurality of light emission control signals, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and A gate drive unit including an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply and the second power supply.

18. Display panel containing multiple pixels, A scan drive unit that outputs multiple gate signals to the multiple pixels, A light-emitting drive unit that outputs multiple light-emitting control signals to the multiple pixels, and The output control unit includes a plurality of stages that output a plurality of pull-up control signals and a plurality of pull-down control signals based on the plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on at least one of the plurality of light emission control signals, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and A display device including an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply and the second power supply.

19. The display device according to claim 18, wherein each of the plurality of pull-up control signals and each of the plurality of pull-down control signals have opposite phases to each other.

20. The display area of ​​the aforementioned display panel is divided into a plurality of sub-display areas. The display device according to claim 18, wherein the scan drive unit outputs different gate signals from each of the multiple sub-display areas.

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