Non-volatile integrated circuits

Abstract

In light of the problems associated with intermittent computing, the objective is to provide a non-volatile integrated circuit that can significantly reduce energy overhead. [Solution] The above problem is solved by a non-volatile integrated circuit that stores and holds bit information of multiple flip-flops when power is supplied, and saves and stores this information in a non-volatile memory area when power is cut off, comprising: multiple non-volatile memory elements whose state is written to and read out in accordance with each of the multiple flip-flops; and a reference element that does not correspond to each of the multiple flip-flops individually, wherein the non-volatile memory elements are connected to only one output of the complementary outputs of the corresponding flip-flops, and the state of the reference element is read out in common for one of the flip-flops, which is a natural number of the multiple flip-flops, using a non-volatile register.

Description

[Technical Field]

[0001] This invention relates to a non-volatile integrated circuit in which a non-volatile memory element is incorporated inside the chip. [Background technology]

[0002] The power consumption of a semiconductor integrated circuit consists of dynamic power consumption and static power consumption. Dynamic power consumption is the power consumed when the circuit is operating, i.e., when the transistor circuit is switching, while static power consumption is the power that is constantly consumed regardless of whether the circuit is operating or not due to the leakage current of the transistors. With the increasing integration of circuits, the proportion of static power consumption in the power consumption of semiconductor integrated circuits has been increasing in recent years, and how to reduce static power consumption has become a challenge. In particular, in IoT technology, edge devices such as mobile terminals and in-vehicle products remain in a standby state for a while after processing, so reducing static power consumption is an urgent issue.

[0003] Generally, a method is used to prevent static power consumption by cutting off the power supply when not performing calculations and saving the information held in volatile memory to external non-volatile memory. This method is called power gating technology. Figure 1 is a graph illustrating the concept of power consumption reduction in power gating technology, with the horizontal axis representing time and the vertical axis representing power consumption. Of the two graphs shown in Figure 1, the left graph shows the trend in power consumption of a conventional semiconductor circuit, and the right graph shows the trend in power consumption of a semiconductor integrated circuit using power gating technology.

[0004] The graph on the left shows that the computation execution period, i.e., the period during which dynamic power consumption occurs, is interrupted, while the period during which static power consumption occurs due to transistor leakage current is continuous. On the other hand, the graph on the right shows that, due to power gating technology, no static power consumption occurs during the period when the power supply is cut off. However, even when transitioning from the computation execution period to the period when the power supply is cut off, i.e., the power gating period, power consumption occurs because a backup process is performed to save information held in volatile memory to external non-volatile memory. Similarly, when transitioning from the power gating period to the computation execution period, power consumption occurs because a restore process is performed to return the information saved to external non-volatile memory back to volatile memory. The energy loss and loss of circuit utilization opportunities, which are the sum of the time required for processing associated with these power consumption, are called overhead. Overhead reduces the power consumption reduction effect of power gating technology and decreases the period during which computation operations can be performed. According to previous research, the energy consumed when exchanging data with memory such as DRAM is said to be 10,000 times greater than the energy consumed during computation, which is a major cause of increased overhead. If overhead can be reduced, the power reduction effect of power gating technology can be greatly increased, and the period during which computation can be performed can be extended.

[0005] To reduce overhead, instead of saving information held in volatile memory to external non-volatile memory, non-volatile LSIs incorporating non-volatile memory elements within the chip have been proposed. Non-volatile LSIs are a fusion of logic-in-memory integrated circuit technology and non-volatile device technology. Logic-in-memory integrated circuit technology significantly reduces global wiring by distributing memory functions within the arithmetic circuit, thereby preventing transfer delays and reducing dynamic power consumption. Non-volatile device technology eliminates the need for data transfer to external memory, allowing for rapid power supply cutoff and power savings. Furthermore, non-volatile device technology significantly reduces circuit size by directly stacking memory devices on CMOS. As a non-volatile device, non-volatile logic circuit technology utilizing magnetic tunnel junction elements (MTJ elements), which are a type of spintronic element, is known. For example, Non-Patent Document 1 shows a non-volatile flip-flop using an MTJ element as non-volatile memory. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] K. Usami, D. Yokoyama, A. Kamei and H. Amano, “Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations,” 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, pp.1-7, 2022. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] Non-volatile power gating using non-volatile logic circuits allows for the non-volatile nature of all modules in an integrated circuit, enabling fine-grained power gating. Therefore, it is expected to significantly reduce wasted power consumption compared to conventional power gating that combines volatile logic circuits and external storage circuits. Figure 2 is a graph illustrating the difference in power consumption reduction between conventional power gating and non-volatile power gating, with the horizontal axis representing time and the vertical axis representing stored energy. Of the two graphs shown in Figure 2, the upper one represents conventional power gating combining volatile logic circuits and external storage circuits, while the lower one represents non-volatile power gating.

[0008] In the upper graph, the difference in stored energy is small during the restore process, and the overhead is not particularly large, but the difference in stored energy is large during the backup process, and the overhead is large. On the other hand, in the lower graph, the difference in stored energy is small even during the backup process, and the overhead is reduced. Comparing the upper and lower graphs, it can be seen that the slope of the energy change during the dynamic power consumption period, i.e., the computation execution period, is the same, indicating that the dynamic power consumption period, that is, the energy that can be spent to perform the computation and the period during which the computation can be performed, is significantly larger.

[0009] Incidentally, in IoT technology, energy harvesting, which extracts and utilizes energy from the surrounding light and vibrations, has been attracting attention in recent years. Energy harvesting has the potential to provide virtually unlimited energy and realize battery-less edge devices. However, the energy supplied by energy harvesting is weak and unstable, and in order for edge devices to stably process information, it is necessary to repeatedly store energy and then consume it by executing tasks once a certain amount has been accumulated. This kind of stepwise task execution through power management is called intermittent computing, and the development of this technology is extremely important for using energy harvesting as an energy source.

[0010] Intermittent computing theoretically utilizes the same mechanism as the aforementioned power gating technology that does not rely on energy harvesting. However, while power gating technology that does not rely on energy harvesting saves data just before entering a standby state after a series of processes have finished, intermittent computing, which executes tasks in stages, frequently requires cutting off the power supply midway through processing to save data. Therefore, overhead needs to be kept as small as possible.

[0011] In view of the problems associated with such intermittent computing, the present invention aims to provide a non-volatile integrated circuit that can significantly reduce energy overhead. [Means for solving the problem]

[0012] In order to solve such problems, the present invention is a non-volatile integrated circuit that stores each bit of information held by a plurality of flip-flops during power supply in a non-volatile memory area and retains it when the power is cut off. The non-volatile integrated circuit includes a plurality of non-volatile memory elements whose states are written and read in correspondence with the plurality of flip-flops individually, and a reference element that does not correspond to the plurality of flip-flops individually. The non-volatile memory element is connected only to one of the complementary outputs of the corresponding flip-flop, and the reference element is characterized in that its state is read in common for one natural number of the plurality of flip-flops.

[0013] Further, the present invention is characterized in that the non-volatile memory element is a magnetic tunnel junction element.

[0014] Further, the present invention is characterized in that the reference element is a reference resistor whose resistance value does not change.

[0015] Further, the present invention is characterized in that the reference element uses the same element as the non-volatile memory element connected to the flip-flop, but is configured so that its resistance does not change.

[0016] Further, the present invention is characterized in that it has a selection circuit that selects a magnetic tunnel junction element for writing or reading.

[0017] Further, the present invention is characterized in that reading from the non-volatile memory element is performed by amplifying a voltage difference based on the difference between the resistance value of each non-volatile memory element corresponding to each flip-flop and the resistance value of the reference element with a sense amplifier.

[0018] Further, the present invention is characterized in that a sense amplifier is provided for each flip-flop.

[0019] Further, the present invention is characterized in that a sense amplifier is provided in common for one natural number of the plurality of flip-flops.

[0020] Further, the present invention is a non-volatile integrated circuit that stores and retains each bit of information stored in a plurality of flip-flops during power supply interruption in a non-volatile memory area during power supply interruption. The non-volatile integrated circuit includes a plurality of non-volatile memory elements whose states are written and read in correspondence with the plurality of flip-flops individually, a reference element that does not correspond to the plurality of flip-flops individually, and a control unit. The control unit executes the writing and reading of the state according to the magnitude relationship between the resistance value of the non-volatile memory element and the resistance value of the reference element.

Effects of the Invention

[0021] According to the present invention, it is possible to provide a non-volatile integrated circuit that can significantly reduce energy overhead. This is useful not only for intermittent computing relying on energy harvesting, but also for general power gating techniques that do not rely on energy harvesting.

Brief Description of the Drawings

[0022] [Figure 1] A graph for explaining the concept of power consumption reduction in power gating technology. [Figure 2] A graph for explaining the difference in power consumption reduction between conventional power gating and non-volatile power gating. [Figure 3] A diagram for explaining the characteristics of a magnetic tunnel junction element (MTJ element). [Figure 4] A circuit diagram of a non-volatile flip-flop constituting a conventional non-volatile integrated circuit. [Figure 5] An explanatory diagram showing how a conventional non-volatile integrated circuit holds bit information. [Figure 6] An explanatory diagram showing how a non-volatile integrated circuit of a shared reference method holds bit information. [Figure 7] A circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention. [Figure 8]This figure illustrates the restoration process of a non-volatile integrated circuit according to an embodiment of the present invention. [Figure 9] This figure illustrates the backup process of a non-volatile integrated circuit according to an embodiment of the present invention. [Figure 10] This is a diagram illustrating the internal structure of the backup circuit. [Figure 11] This is an explanatory diagram showing the sub-register block structure of a non-volatile integrated circuit (non-volatile register). [Figure 12] This graph shows the verification results regarding the sub-register block structure. [Figure 13] This is a circuit diagram of a non-volatile integrated circuit according to another embodiment of the present invention. [Modes for carrying out the invention]

[0023] This invention is based on logic-in-memory integrated circuit technology and non-volatile device technology, enabling high density and overhead reduction. To understand the technical concept of this invention, it is essential to first understand the characteristics of non-volatile memory elements and how non-volatile registers and non-volatile flip-flops hold bit information. This point will be explained first. The following explanation will use drawings, but these drawings are created for explanatory purposes and may intentionally omit elements that are not necessary for the explanation in order to make it easier to understand. Also, for explanatory purposes, some elements may be intentionally made larger or smaller in the drawings and do not represent the exact scale.

[0024] <Prerequisite Technical Elements> (Characteristics of magnetic tunnel junction elements) Realizing non-volatile LSIs requires non-volatile memory elements embedded within the chip. Non-volatile memory elements can be those whose resistance changes under certain conditions, such as tunnel magnetoresistance or electric field-induced giant resistance changes, but whose resistance remains stable in a static state. Examples of such elements include MTJ elements (magnetic tunnel junction elements), ReRAM (resistive random-access memory), and PCM (phase-change memory). In the embodiment of this invention, an MTJ element is used. MTJ elements have advantageous characteristics compared to other non-volatile memory elements in terms of write time, write endurance, and compatibility with CMOS.

[0025] Figure 3 illustrates the characteristics of a magnetic tunnel junction (MTJ) element. An MTJ element, a type of spintronic element, has a three-layer structure with an insulating layer between two magnetic layers. In the figure, the upper magnetic layer is a free layer where the sign of the spin current changes depending on the sign of a current of a certain magnitude, while the lower magnetic layer is a fixed layer where the sign of the spin current does not change regardless of the sign of the current. By applying a rewriting current above an inversion threshold, the MTJ element can take on two states: a parallel state where the spin currents of the two magnetic layers are in the same direction, and an antiparallel state where the spin currents of the two magnetic layers are in opposite directions. The MTJ element exhibits low resistance (R) in the parallel state. P ) results in high resistance (R) in the antiparallel state. AP ) . As shown in the resistance-current characteristics of Figure 3, high resistance (R AP ) at the time, I AP-P When the above current is passed through, the low resistance (R P Although the resistance value changes, the resistance value does not change even if the applied current is removed in this state. P-AP If the above current is passed in the reverse direction, high resistance (R AP The resistance value changes accordingly. These two resistance values ​​are used as bit information. Thus, an MTJ element can be described as an element that possesses the dual properties of a variable resistor and a non-volatile memory.

[0026] (Regarding the retention of bit information in non-volatile flip-flops) FIG. 4 is a circuit diagram of a non-volatile flip-flop that constitutes a non-volatile register of a conventional method. Arranging as many non-volatile flip-flops as the number of bits required will function as a non-volatile register. A non-volatile flip-flop is a flip-flop equipped with the function of non-volatile power gating. In the example shown here, a master-slave type D flip-flop is provided with the function of storing data in the MTJ element and the function of restoring data from the MTJ element.

[0027] While power is being supplied, data is held by two latches in the same way as a normal flip-flop. On the other hand, just before the power is cut off, a backup circuit applies a rewrite current to the MTJ element to execute a backup process. After that, when the power is restored, the slave latch becomes a sense amplifier to read the resistance difference, and a restore process is executed to return the bit information held by the MTJ element to the D flip-flop.

[0028] Thus, the non-volatile flip-flop that constitutes the non-volatile register of the conventional method corresponds two MTJ elements to the complementary outputs of the flip-flop, and holds bit information by the difference in their resistance states. Therefore, both are written so that the two MTJ elements become either complementary resistance states of R P , R AP or R AP , R P However, since a relatively large current is required to write to the MTJ element, as shown in the upper graph of FIG. 2, it will lead to a situation where the backup process occupies most of the energy consumption overhead.

[0029] In addition to the overhead of energy consumption, non-volatile flip-flops require large transistors capable of applying sufficient current to the MTJ element. The inversion threshold current of the MTJ element is around 100 μA at room temperature, which cannot be handled by conventionally sized transistors. Only by using multiple dedicated backup control transistors with gate widths 4 to 12 times larger can data be written. Thus, since the writing transistor occupies most of the non-volatile flip-flop, the area overhead is also large. For this reason, the inventors propose a new non-volatile register, which could be called a shared reference type, as an alternative to conventional non-volatile registers. The advantages of the shared reference type over the conventional type will be explained below based on the differences in the mechanism for retaining bit information.

[0030] (Comparison of old and new bit information retention methods for non-volatile integrated circuits) Figure 5 is an explanatory diagram showing how a conventional non-volatile integrated circuit holds bit information, and Figure 6 is an explanatory diagram showing how the shared reference type non-volatile integrated circuit of the present invention holds bit information.

[0031] Conventional non-volatile integrated circuits, or more precisely, conventional non-volatile flip-flops, when storing bit information, use two MTJ elements per bit to create and compare the resistance difference necessary for the restore process from the MTJ elements, as shown in Figure 5. P ,R AP or R AP ,R P Both MTJ elements are programmed to achieve one of the complementary resistance states.

[0032] In contrast, the newly proposed shared reference method, as shown in Figure 6, uses a reference MTJ element with a resistance value intermediate between high and low resistance. Bit information is read by comparing the resistance value of this reference MTJ element with that of the data-holding MTJ element. In the shared reference method, the number of MTJ elements used for writing per bit is reduced from two to one compared to the conventional method. This makes it possible to significantly reduce the energy required to write to the MTJ elements that rewrite values.

[0033] As shown in Figure 6, the reference MTJ element with a resistance value intermediate between high and low resistance employs a structure that achieves an intermediate resistance value by combining four MTJ elements with the same resistance value as the data-holding MTJ element. If a resistor with an intermediate value between two resistance values ​​of MTJ elements can be prepared, it is not necessarily required to construct a constant resistance using MTJ elements. However, when actually designing a circuit, if a fixed resistor is manufactured using a semiconductor process, area overhead occurs, and changes in resistance value due to manufacturing variations become a problem. In this regard, since MTJ elements are mounted three-dimensionally on the wiring layer above the semiconductor, it is expected that the area overhead will be small. However, it is technically difficult to mount MTJ elements with different resistance values ​​on a single chip. For these reasons, four MTJ elements are combined to form a constant resistance, but if the above-mentioned problems can be overcome, it is of course possible to use other constant resistance elements as the reference element. Having explained the premises of the present invention, embodiments of the present invention will now be described.

[0034] <Embodiments of the Invention> (Configuration of non-volatile registers) Figure 7 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention. Here, an example of a non-volatile register is shown. The non-volatile register 100 according to the embodiment of the present invention is an N-bit register and, as shown in Figure 7, comprises N bit information storage units 1, a shared read circuit 2, a controller circuit 3, and a backup circuit 4.

[0035] The bit information storage unit 1 incorporates a data-holding MTJ element 12 as a non-volatile memory element into the chip, thereby possessing the functions of both volatile and non-volatile memory. This is achieved by directly stacking the MTJ element, which is the memory device, on the CMOS. The bit information storage unit 1 includes a flip-flop 11 as volatile memory and a sense amplifier 13 for reading bit information. The flip-flop 11 is a D flip-flop.

[0036] The shared read circuit 2 consists of a reference MTJ element 21 as a reference element and an MTJ selector circuit 22. The MTJ selector circuit 22 is positioned between the sense amplifier 13 and the reference MTJ element 21 and plays the role of selecting and connecting to individual bit information storage units 1. The fact that the reference MTJ element 21 is shared among individual bit information storage units 1 is the most distinctive feature of the present invention and is the origin of the name "shared reference method." Furthermore, in the non-volatile register 100 according to the embodiment of the present invention, in addition to the sharing of the reference MTJ element 21 as a reference element, the circuit functions are also shared.

[0037] Conventional non-volatile registers can be constructed by simply arranging their non-volatile flip-flop components. However, in order to share the reference MTJ element and circuit functions, it becomes necessary to redesign the entire register's circuit structure. Furthermore, since the reference MTJ element 21 is shared among the individual bit information storage units 1, the operation that was performed all at once in the conventional method must now be performed bit by bit sequentially, requiring the incorporation of a circuit to control this operation. The circuits for this purpose are the controller circuit 3, the shared read circuit 2, and the backup circuit 4.

[0038] The controller circuit 3 outputs signals to select bits for backup and restore processing. Specifically, the controller circuit 3 receives signals WB and LB from outside the non-volatile register 100 and outputs bit selection signals S1 to SN. Specifically, in backup processing, when the pulse signal WB is input N times, the values ​​of the bit selection signals S1 to SN are switched sequentially accordingly, and a write current flows to the data holding MTJ element 12 that holds the data of the selected bits. In restore processing, when the pulse signal LB is input N times, the values ​​of the bit selection signals S1 to SN are switched sequentially accordingly, the selected sense amplifier 13 and reference MTJ element 21 are electrically connected, and the value stored in the data holding MTJ element 12 is read out to the flip-flop 11.

[0039] In the shared read circuit 2, the MTJ selector circuit 22 receives a bit selection signal Sn output from the controller circuit 3 and connects the corresponding nth sense amplifier 13 and the reference MTJ element 21 by turning on an internal NMOS transistor. The sense amplifier 13 amplifies the voltage difference based on the resistance value of the data-holding MTJ element 12 and the resistance value of the reference MTJ element 21. This result is read into the flip-flop 11, which acts as volatile memory, and a restore process is performed.

[0040] The backup circuit 4 is integrated and incorporated into the entire non-volatile register 100. Details of the backup circuit 4 will be described after the explanation of the restore and backup processes.

[0041] (Data restoration process) The data restoration process will now be explained. Figure 8 is a diagram illustrating the restoration process of a non-volatile integrated circuit (non-volatile resistor) according to an embodiment of the present invention, and is a partial circuit diagram extracted from the rectangular region A shown by the dashed line in the circuit diagram of Figure 7.

[0042] In the restore process, first, the controller circuit 3 outputs bit selection signals S1 to SN, and one of the bit selection signals S1 to SN is input to the MTJ selector circuit 22. Next, the MTJ selector circuit 22 connects the selected sense amplifier 13 to the reference MTJ element 21. At this time, the controller circuit 3 provides a readout signal LB to the sense amplifier 13. In response, the sense amplifier 13 outputs a readout current I to the data holding MTJ element 12 and the reference MTJ element 21. READ By applying a voltage and amplifying the voltage difference resulting from the difference in current due to the difference in resistance between the two MTJ elements, information is read out.

[0043] As described above, the bit information stored in the data-holding MTJ element 12 is restored to the flip-flop 11. The series of restore operations is performed within one clock cycle for each bit. Therefore, for example, if the bit length of the register is 32 bits, 32 clock cycles are required for restoration.

[0044] (Data backup process) The data backup process will now be explained. Figure 9 is a diagram illustrating the backup process of a non-volatile integrated circuit (non-volatile register) according to an embodiment of the present invention, and is a partial circuit diagram extracted from the rectangular area B shown by the dashed line in the circuit diagram of Figure 7. Figure 10 is a diagram illustrating the internal structure of the backup circuit, with the left side showing the internal structure of a backup circuit in a conventional non-volatile register and the right side showing the internal structure of a backup circuit in a shared reference type non-volatile register.

[0045] In the backup process, the controller circuit 3 inputs bit selection signals S1 to SN and a write signal WB to the backup circuit 4. The backup circuit 4 applies write current only to the data holding MTJ element 12 selected by the bit selection signals S1 to SN. At this time, the backup circuit 4 determines the direction of the current to flow according to the bit information of the selected flip-flop 11.

[0046] As shown on the left of Figure 10, in the backup circuit of a conventional non-volatile resistor, eight writing transistors were used per bit to supply writing current to the MTJ element. In contrast, as shown on the right of Figure 10, in the backup circuit of a shared-reference non-volatile resistor, two writing transistors are used per bit, and these two writing transistors are shared. As indicated by the arrow on the right of Figure 10, one of the writing transistors and the shared writing transistor create a current path, allowing writing current to be supplied only to a specific MTJ element. Therefore, the shared-reference method uses only one-quarter of the writing transistors as the conventional method, resulting in a significant reduction in area overhead.

[0047] Regarding energy overhead, although the write operation, which was performed once in a conventional non-volatile register, now needs to be performed N times depending on the number of bits, the number of MTJ elements targeted in a single write operation is 1 / N, so this has little impact on the overhead. Rather, the effect of reducing transistors contributes significantly not only to area reduction but also to energy overhead reduction.

[0048] On the other hand, the time required for read and write operations is N times, which is larger than in conventional methods. However, while the typical interval between intermittent operations in intermittent computing is several milliseconds, the time required for register backup and restore operations is at most several microseconds. Since the former is considerably longer than the latter, the increase in the time required for read and write operations does not pose a major problem.

[0049] (Performance evaluation) In the previous descriptions of the embodiments, an N-bit register was described as having N flip-flops integrated into it. However, with a shared-reference non-volatile register, the number of integrated flip-flops can be freely selected. For example, even if the total bit length is 32 bits, in addition to 32 integrated flip-flops, there are several other options, such as eight sub-register blocks integrated in 4-bit units, or four sub-register blocks integrated in 8-bit units. Increasing the integration density of the non-volatile register allows for a more compact circuit configuration, but it complicates the control of backup and restore.

[0050] To find the optimal integration granularity, 32-bit non-volatile registers were integrated at multiple granularities and verified. Figure 11 is an explanatory diagram showing the sub-register block structure of a non-volatile register to illustrate this. (1) shows a conventional non-volatile register with 32 conventional non-volatile flip-flops arranged in a row, each having two MTJ elements per bit. (2) shows a 32-bit non-volatile register designed so that data is written to only one MTJ element by replacing one of the MTJ elements with a reference resistor. (3) schematically shows sub-register block structures integrated in units of 2, 4, 8, 16, and 32 bits for a non-volatile register with a total bit length of 32 bits (4-bit and 8-bit are shown as representative examples in the figure). These non-volatile registers were designed using 55nm CMOS / MTJ hybrid process technology and evaluated using the circuit simulator "HSPICE".

[0051] Figure 12 is a graph showing the verification results for the sub-register block structure. The graph on the left shows the circuit area in terms of the number of transistors, specifically the area calculated by converting the sum of the products of the gate width W, gate length L, and parallel number M of the transistors constituting the non-volatile register to the minimum number of transistors. The graph in the upper right shows the energy consumption during backup processing, and the graph in the lower right shows the energy consumption during restore processing.

[0052] When 32-bit non-volatile registers were integrated at an 8-bit granularity, the circuit area was reduced by 39% and power consumption by 49% compared to conventional non-volatile registers. However, it was confirmed that increasing the integration density to 16 bits and 32 bits increased the circuit area and slightly increased the restore energy consumption due to the increased complexity of the control circuit.

[0053] <Another Embodiment of the Invention> Figure 13 is a circuit diagram of a non-volatile integrated circuit according to another embodiment of the present invention. The non-volatile register 100A according to another embodiment of the present invention, using an 8-bit register as an example, comprises eight flip-flops 11A, eight data-holding MTJ elements 12A, one reference MTJ element 21A, a shared read circuit 2A, one shared sense amplifier 13A, an MTJ selector circuit 22A, a controller circuit 3A, a backup circuit 4A, and a demultiplexer 5A, as shown in Figure 13. The fact that the shared read circuit 2A has a reference MTJ element 21A is the same as in the previously described embodiment, but the fact that the shared read circuit 2A has one shared sense amplifier 13A is different from the previously described embodiment. That is, the previously described embodiment had the same number of sense amplifiers as the number of bits, but the other embodiment has only one sense amplifier.

[0054] Regarding the operation process, the operation of the flip-flop during the dynamic power consumption period and the backup process are the same as in the previously described embodiment. Only the restore process differs in specifications. Specifically, the bit selection signal, switched by the input of the pulse signal LB, turns on the NMOS transistor inside the MTJ selector circuit 22A, and the data-holding MTJ element 12A is connected to the shared read circuit 2A. The bit selection signal also simultaneously controls the demultiplexer 5A located between the shared read circuit 2A and the flip-flop 11A, and the data is restored to the designated flip-flop 11A. The area reduction due to the sharing of the sense amplifier may not be significant, but it is shown here because it allows for alternative circuit designs.

[0055] Although embodiments of the present invention and non-volatile integrated circuits according to other embodiments have been described in detail above, the specific configuration is not limited to these embodiments, and design changes and the like that do not depart from the gist of the present invention are also included in the present invention. For example, instead of registers, static random access memory (SRAM) may be used, the NMOS described as a transistor switch configuration may be configured as CMOS, and the flip-flop described as a D flip-flop may be configured as an RS flip-flop or a JK flip-flop. The non-volatile memory element is not limited to MTJ elements, but other non-volatile memory elements such as ReRAM (resistive random-access memory) and PCM (phase-change memory) may be used.

[0056] However, the technical advantage of sharing a reference MTJ element reduces the energy consumption for writing to the MTJ element, significantly lowering energy overhead. This leads to an increase in available computation time, to the point where the length of backup processing becomes negligible, and its superiority should be properly understood. [Explanation of Symbols]

[0057] 1-bit information storage unit 11 Flip-flops 12 MTJ elements for data retention 13 Sense Amp 2 Shared readout circuit 21 Reference MTJ element 22 MTJ Selector Circuit 3. Controller Circuit 4. Backup circuit 100 Non-volatile register 11A Flip-Flop 12A Data Retention MTJ Element 13A Sense Amplifier 2A shared readout circuit 21A Reference MTJ element 22A MTJ Selector Circuit 3A controller circuit 4A backup circuit 5A Demultiplexer 100A Non-volatile resistor

Claims

1. A non-volatile integrated circuit that stores and holds bit information in multiple flip-flops when power is supplied, and saves and stores this information in a non-volatile memory area when power is cut off, Multiple non-volatile memory elements whose states are written to and read out in accordance with the multiple flip-flops, The system includes a reference element that does not correspond to each of the aforementioned multiple flip-flops individually, The non-volatile memory element is connected to only one of the complementary outputs of the corresponding flip-flop. The state of the aforementioned reference element is read in common from one in a natural number of the flip-flops. A non-volatile integrated circuit characterized by the following features.

2. The non-volatile memory element is a magnetic tunnel junction element. The non-volatile integrated circuit according to feature 1.

3. The aforementioned reference element is a reference resistor whose resistance value does not change. The non-volatile integrated circuit according to feature 2.

4. The reference element uses the same element as the non-volatile memory element connected to the flip-flop, but is configured so that its resistance does not change. The non-volatile integrated circuit according to feature 2.

5. It has a selection circuit that selects the magnetic tunnel junction element to be written to or read from. The non-volatile integrated circuit according to feature 4.

6. Readout from the non-volatile memory elements is performed by amplifying the voltage difference, which is based on the difference between the resistance value of each non-volatile memory element corresponding to each flip-flop and the resistance value of the reference element, using a sense amplifier. The non-volatile integrated circuit according to feature 5.

7. The sense amplifier is provided for each flip-flop. The non-volatile integrated circuit according to feature 6.

8. The sense amplifier is provided in common to one of the flip-flops, which is a natural number of the plurality of flip-flops. The non-volatile integrated circuit according to feature 6.

9. A non-volatile integrated circuit that stores and holds bit information in multiple flip-flops when power is supplied, and saves and stores this information in a non-volatile memory area when power is cut off, Multiple non-volatile memory elements whose states are written to and read out in accordance with the multiple flip-flops, A reference element that does not correspond individually to the aforementioned multiple flip-flops, It comprises a control unit and, The control unit performs writing and reading of the state according to the magnitude of the resistance value of the non-volatile memory element and the resistance value of the reference element. A non-volatile integrated circuit characterized by the following features.

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