Scan drive circuit and display device including the same

Abstract

The present invention provides a scan drive circuit and a display device including the same. [Solution] The invention provides a substrate including a display area and a non-display area; a pixel circuit located in the display area for driving a light-emitting element; and a scan drive circuit for supplying a scan signal to the pixel circuit, wherein the scan drive circuit includes a logic section that receives input from a plurality of clock signals and outputs a logic signal via a logic output terminal; and an inverter section that receives input from the logic signal and outputs the scan signal with its phase inverted via a gate output terminal, wherein the inverter section includes an n-type first inverter transistor and a p-type second inverter transistor, each having its gate electrode connected to the logic output terminal and positioned on either side of the gate output terminal, and the first inverter transistor includes an oxide semiconductor.

Description

Technical Field

[0001] This specification relates to a scan driving circuit and a display device including the same.

Background Art

[0002] Display devices for displaying images on televisions, monitors, smartphones, tablet PCs, and notebook computers use various methods and forms.

[0003] The display device includes a display panel having a plurality of light-emitting elements or liquid crystals for embodying an image, and transistors for controlling the operation of each light-emitting element or liquid crystal, and displays the image as intended through the plurality of light-emitting elements or liquid crystals.

[0004] Recent display devices include various flat display devices such as an electroluminescence display device including an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, and a micro light-emitting diode (Micro-LED) display device.

[0005] The display device may include a display panel for displaying an image and a driving unit for driving the display panel. The display panel includes a plurality of pixels including light-emitting elements, and the driving unit may include a plurality of driving and switching elements for driving and controlling the light-emitting elements provided in each pixel.

[0006] The driving unit may include a scan driving circuit that supplies a scan signal synchronized with a data signal to a gate line provided in a plurality of pixels.

Summary of the Invention

Problems to be Solved by the Invention

[0007] One technical objective of the embodiments described herein is to provide a scan drive circuit with improved reliability and a display device including the same.

[0008] One of the technical objectives of the embodiments described herein is to provide a scan drive circuit structure that can reduce the number of clock signals and simplify operation.

[0009] One of the technical objectives of the embodiments described herein is to provide a structure that can improve operational errors in scan drive circuits that may occur due to Positive Bias Thermal Stress (PBTS).

[0010] The embodiments described herein address the technical challenge of realizing ESG (Environmental, Social, and Governance) through improved reliability and reduced power consumption of display devices. [Means for solving the problem]

[0011] A display device according to one embodiment of this specification includes a substrate including a display area and a non-display area, a pixel circuit located in the display area for driving a light-emitting element, and a scan drive circuit for supplying a scan signal to the pixel circuit. The scan drive circuit includes a logic section that receives input of a plurality of clock signals and outputs a logic signal via a logic output terminal, and an inverter section that receives input of the logic signal and outputs the scan signal with its phase inverted via a gate output terminal. The inverter section includes an n-type first inverter transistor and a p-type second inverter transistor, each having a gate electrode connected to a logic output terminal and positioned on either side of the gate output terminal, the first inverter transistor including an oxide semiconductor.

[0012] The period during which the gate high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor may be longer than the period during which the gate low voltage of the logic signal is supplied.

[0013] The second inverter transistor may include a semiconductor formed from low-temperature polysilicon (LTPS).

[0014] The first inverter transistor may have its gate electrode connected to the logic output terminal, with a gate low voltage (VGL) supplied to one end and the other end connected to the gate output terminal, while the second inverter transistor may have its gate electrode connected to the logic output terminal, with a gate high voltage (VGH) supplied to one end and the other end connected to the gate output terminal.

[0015] The first inverter transistor may be turned on by the logic signal having a gate high voltage and output the scan signal having a gate low voltage to its gate output terminal, and the second inverter transistor may be turned on by the logic signal having a gate low voltage and output the scan signal having a gate high voltage to its gate output terminal.

[0016] The logic section includes a plurality of logic transistors, and the plurality of logic transistors may include semiconductors made of low-temperature polysilicon (LTPS).

[0017] The logic section comprises: a first logic transistor whose gate electrode is connected to a Q node, with a second clock signal input to one end and the other end connected to the logic output terminal; a second logic transistor whose gate electrode is connected to a QB node, with a gate high voltage supplied to one end and the other end connected to the logic output terminal; a third logic transistor whose gate electrode is connected to a Q node, with the second clock signal input to one end and the other end connected to a Q node; and a gate electrode connected to the Q node, with a fourth second clock signal connected to the QB node and one end connected to a gate R - A fifth logic transistor to which a voltage is input and whose other end is connected to the QB node; a sixth logic transistor whose gate electrode is connected to the QB node and which outputs a gate high voltage supplied to one end to the other end; a seventh logic transistor to which a first clock signal is input at its gate electrode, whose one end is connected to the sixth logic transistor and whose other end is connected to the Q node; a first capacitor whose one end is connected to the QB node and whose other end is connected to the logic output terminal; and a second capacitor whose one end is connected to the QB node and to which a logic high voltage is supplied at the other end.

[0018] The logic section may further include an eighth logic transistor to which a gate-low voltage is supplied to the gate electrode and which is connected between the gate electrode of the first logic transistor and the other end of the third logic transistor.

[0019] During the first period, the start signal and the second clock signal have a logic low voltage, and the first clock signal has a logic high voltage. During the second period following the first period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage. During the third period following the second period, the second clock signal has a logic low voltage, and the first clock signal and the start signal have logic high voltages. During the fourth period following the third period, the first clock signal may have a logic low voltage, and the second clock signal may have a logic high voltage.

[0020] The first inverter transistor includes a bottom electrode located on the other side of the gate electrode, centered on the oxide semiconductor, and further includes a first switch with one end connected to the gate electrode and the other end connected to the bottom electrode; and a second switch with one end commonly connected to the bottom electrode and the first switch, to which a constant voltage is supplied.

[0021] While the scan drive circuit outputs the scan signal at a first scan rate or higher, the first switch may be turned on and the second switch may be turned off.

[0022] While the scan drive circuit outputs the scan signal at a scan rate less than the first scan rate, the first switch may be turned off and the second switch may be turned on.

[0023] A scan drive circuit according to one embodiment of this specification includes a logic unit that receives a plurality of clock signals as input and outputs logic signals via logic output terminals, and an inverter unit that receives the logic signals as input and outputs the scan signal whose phase is inverted via gate output terminals, for supplying a scan signal to a pixel circuit located in the display area of ​​a substrate. The inverter unit includes an n-type first inverter transistor and a p-type second inverter transistor located between the gate output terminals, and the first inverter transistor includes an oxide semiconductor.

[0024] The period during which the logic high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor may be longer than the period during which the logic low voltage of the logic signal is supplied.

[0025] The aforementioned second inverter transistor may include a semiconductor formed from low-temperature polysilicon (LTPS).

[0026] The first inverter transistor has a gate electrode connected to the logic output terminal, a gate low voltage (VGL) supplied to one end, and the other end connected to the gate output terminal. The second inverter transistor may have a gate electrode connected to the logic output terminal, a gate high voltage (VGH) supplied to one end, and the other end connected to the gate output terminal.

[0027] The first inverter transistor is turned on by the logic signal having a gate high voltage and outputs the scan signal having the gate low voltage to the gate output terminal. The second inverter transistor may be turned on by the logic signal having a gate low voltage and output a scan signal having a gate high voltage to the gate output terminal.

[0028] The first inverter transistor may further include a first switch including a gate electrode located on one side centered on the oxide semiconductor and a bottom electrode located on the other side, one end connected to the gate electrode, and the other end connected to the bottom electrode; and a second switch commonly connected to the bottom electrode and the other end of the first switch and controlling the supply of a constant voltage.

[0029] While the scan driving circuit outputs the scan signal at a first scanning rate or higher, the first switch may be turned on and the second switch may be turned off.

[0030] While the scan driving circuit outputs the scan signal at less than the first scanning rate, the first switch may be turned off and the second switch may be turned on.

Advantages of the Invention

[0031] An embodiment of this specification includes an inverter section including an n-type first inverter transistor and a p-type second inverter transistor commonly connected to a logic output terminal of a logic section of a scan driving circuit, thereby reducing the number of clock signals and simplifying the operation.

[0032] The embodiments described herein may include an oxide semiconductor in the first inverter transistor to prevent the scan signal from becoming unstable due to leakage current in the first inverter transistor and to minimize malfunctions of the pixel circuit.

[0033] In the embodiments described herein, the first inverter transistor includes a bottom electrode, but further comprises a first switch that connects the gate electrode and the bottom electrode of the first inverter transistor during high-speed driving, and a second switch that connects the bottom electrode of the first inverter transistor to a constant voltage during low-speed driving. This prevents Positive Bias Thermal Stress (PBTS) of the first inverter transistor, which is likely to occur during low-speed driving, and improves the operation errors of the scan drive circuit. [Brief explanation of the drawing]

[0034] [Figure 1] This figure illustrates an example of a display device applicable to the present invention. [Figure 2] This figure illustrates an example of an equivalent circuit for subpixels (SP) applicable to the display device of the present invention. [Figure 3] This is a diagram illustrating a scan drive circuit according to a first embodiment of the present invention. [Figure 4] This figure illustrates an example of a timing diagram applied to the scan drive circuit according to the first embodiment. [Figure 5] Figure 4 is a timing diagram illustrating how the scan drive circuit according to the first embodiment operates. [Figure 6] Figure 4 is a timing diagram illustrating how the scan drive circuit according to the first embodiment operates. [Figure 7] Figure 4 is a timing diagram illustrating how the scan drive circuit according to the first embodiment operates. [Figure 8]Figure 4 is a timing diagram illustrating how the scan drive circuit according to the first embodiment operates. [Figure 9] This is a diagram illustrating a scan drive circuit according to a second embodiment of the present invention. [Figure 10] This diagram illustrates the operation of the scan drive circuit according to the second embodiment during high-speed driving at a scan rate greater than or equal to the first scan rate. [Figure 11] This diagram illustrates the operation of the scan drive circuit according to the second embodiment during low-speed driving below the first scan rate. [Modes for carrying out the invention]

[0035] The following describes an embodiment with reference to the drawings.

[0036] Identical drawing reference numerals refer to the same component. Furthermore, parts of the drawing may be exaggerated to effectively illustrate the thickness, proportions, and dimensions of components. The scale of components shown in the drawing may differ from the actual scale for illustrative purposes and is not limited to the scale shown in the drawing.

[0037] In this specification, when a component (or region, layer, part, etc.) is referred to as "on top of," "connected to," or "joined" another component, it means that it may be directly connected to / joined to the other component, or a third component may be positioned between them.

[0038] "and / or" includes all possible combinations of one or more related configurations.

[0039] Terms such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing the scope of the rights of this embodiment, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0040] Terms such as "below," "below," "above," and "upper" are used to describe the relationships between components illustrated in a drawing. These terms are relative concepts and are described in relation to the direction shown in the drawing. For example, unless "immediately" or "directly" is used, one or more different parts may be located between two parts. Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" can be used to easily describe the correlation between one element or component and another, as shown in the drawing. Therefore, for example, "below" and "below" relative to the first component may be in the opposite direction to "above" and "upper" relative to the first component.

[0041] Spatially relative terms must be understood to include not only the directions illustrated in the drawings, but also the different directions of elements in use or operation. For example, if elements illustrated in a drawing are flipped over, an element described as "below" or "beneath" another element may be placed "above" another element. Therefore, the illustrative term "below" may include both downward and upward directions.

[0042] Terms such as "includes" or "has" are intended to specify the presence of features, numbers, stages, operations, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the possibility of the presence or addition of one or more other features, numbers, stages, operations, components, parts, or combinations thereof.

[0043] The features of each of the multiple embodiments described herein can be combined or combined in part or in whole, enabling a variety of technical interdependencies and drives, and each embodiment may be implemented independently of the others, or together in relation to one another.

[0044] Below, the gate-on voltage can be the gate signal voltage at which a transistor may be turned on. The gate-off voltage can be the voltage at which a transistor may be turned off. For a P-type transistor, the gate-on voltage can be the logic low voltage (VL), and the gate-off voltage can be the logic high voltage (VH). For an N-type transistor, the gate-on voltage can be the logic high voltage, and the gate-off voltage can be the logic low voltage.

[0045] The display devices described herein will be examined below through the attached drawings and examples.

[0046] Figure 1 is a diagram illustrating an example of a display device applicable to the present invention, and Figure 2 is a diagram illustrating an example of an equivalent circuit for a subpixel (SP) applicable to the display device of the present invention.

[0047] Referring to Figures 1 and 2, the display device 100 according to this specification includes a display panel 110, which may include a display area AA and a non-display area NA.

[0048] Display area AA may be the area where the image is displayed. Display area AA of the display panel 110 may contain numerous subpixels SP, and the image may be displayed using these numerous subpixels SP. The area where numerous subpixels SP are located becomes display area AA, and areas other than display area AA may become non-display area NA.

[0049] The non-display area (NA) may be located in the edge region surrounding the display area (AA) where the image is displayed. The non-display area (NA) may contain at least one drive unit (not shown) for driving a number of subpixels (SP). The drive unit may be a gate-in-panel (GIP).

[0050] At least one drive unit may include a scan drive circuit that supplies scan signals to a number of subpixels SP located in the display area AA. In addition, various additional elements may be located in the non-display area NA for driving the subpixels SP within the display area AA.

[0051] However, the present invention is not necessarily limited to this, and for example, the scan drive circuit can be distributed within the display area AA. For example, within the display area AA, pixel areas where pixels are located and circuit areas where scan drive circuits are located can be alternately arranged in the horizontal direction.

[0052] Furthermore, the display device 100 of the present invention may include a timing controller (not shown) that supplies timing control signals, including, for example, clock signals CLK1, CLK2, and a start signal GVST, to the scan drive circuit, and may also include a power supply circuit (not shown) for supplying, for example, power supplies VGL, VGH, EVDD, and EVSS necessary for driving the scan drive circuit and subpixels.

[0053] Each of the multiple subpixels SP may control the light emission of the light-emitting element OLED by a data voltage supplied in synchronization with the scan signal. The scan signal may be supplied from the scan drive circuit via the gate line GL, and the data voltage may be supplied in synchronization with the scan signal via the data line DL.

[0054] For example, as shown in Figure 2a and Figure 2b, at least one of the multiple subpixels SP may be represented by an equivalent circuit including a first switching transistor ST1, a driving transistor DT, a capacitor Cst, and a light-emitting element OLED.

[0055] The first electrode of the first switching transistor ST1, for example, the drain electrode, may be electrically connected to the data line DL, the second electrode, for example, the source electrode, may be electrically connected to the first node N1, and the gate electrode of the first switching transistor ST1 may be electrically connected to the gate line GL. The first switching transistor ST1 may transmit a data signal supplied via the data line DL to the first node N1 in response to a scan signal supplied via the gate line GL.

[0056] Capacitor Cst is electrically connected to the first node N1 and may charge the voltage applied to the first node N1.

[0057] The first electrode of the drive transistor DT, for example, the drain electrode, is authorized to receive a high potential drive voltage EVDD, and the second electrode, for example, the source electrode, may be electrically connected to the first electrode of the light-emitting element OLED, for example, the anode electrode. The drive transistor DT may control the amount of drive current flowing to the light-emitting element OLED in response to the voltage applied to the gate electrode.

[0058] The active layer of the first switching transistor ST1 and / or the driving transistor DT may contain, but is not limited to, an oxide such as IGZO (Indium-Gallium-Zinc-Oxide).

[0059] OLED light-emitting elements may emit light corresponding to the duct current. OLED light-emitting elements may emit light corresponding to one of the following colors: red (R), green (G), blue (B), and white.

[0060] A light-emitting element (OLED) may include an anode electrode, a light-emitting layer placed on the anode electrode, and a cathode electrode that supplies a common voltage. The light-emitting layer may be implemented to emit light of the same color per pixel, such as white light, or to emit different colors per subpixel SP, such as red (R), green (G), or blue (B) light.

[0061] OLED light-emitting diodes can be either front-emitting or back-emitting diodes.

[0062] Figure 2a shows an example where the drive transistor DT is directly connected to the light-emitting element OLED, but the present invention is not limited to this. As shown in Figure 2b, the drive transistor DT can also be connected to the light-emitting element OLED via a second switching transistor ST2.

[0063] Specifically, as shown in Figure 2b, the second switching transistor ST2 may be positioned between the drive transistor DT and the light-emitting element OLED. The first electrode of the second switching transistor ST2 may be connected to the drive transistor DT, and the second electrode of the second switching transistor ST2 may be electrically connected to the light-emitting element OLED. In response to the light-emitting signal applied to the gate electrode of the drive transistor DT, the on / off switching of the drive current applied from the drive transistor DT to the light-emitting element OLED may be controlled.

[0064] Furthermore, although not shown in Figures 2a and 2b, a compensation circuit (not shown) may be provided within the subpixel SP to compensate for threshold voltages of the driving transistor DT. The compensation circuit may include at least one transistor connected to the driving transistor DT and may be provided within the subpixel SP.

[0065] The compensation circuit can consist of various structures depending on the configuration, such as 3T1C, which includes three transistors and one capacitor Cst within the subpixel SP, or 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, which include four transistors and two capacitor Csts.

[0066] The following section describes the scan drive circuit that supplies the scan signal to the pixel circuit shown in Figure 2.

[0067] Figure 3 is a diagram illustrating a scan drive circuit according to the first embodiment of the present invention, and Figure 4 is a diagram illustrating an example of a timing diagram applied to the scan drive circuit according to the first embodiment.

[0068] As shown in Figure 3, the scan drive circuit 200 according to the first embodiment of the present invention may include a logic unit 210 and an inverter unit 220.

[0069] The logic unit 210 may receive multiple clock signals CLK1, CLK2 and a start signal GVST from a timing controller (not shown) and output a logic signal through the logic output terminal OUT_Logic. If the scan drive circuit 200 includes multiple stages, the logic unit 210 included in the first stage that first supplies the scan signal may receive a start signal GVST from the timing controller, while the logic units 210 included in the second and subsequent stages may receive the carry signal from the preceding stage as a start signal GVST.

[0070] To output logic signals, the logic unit 210 may include multiple logic transistors and multiple capacitors. The multiple logic transistors included in the logic unit 210 may include p-type transistors that include semiconductors formed from low-temperature polysilicon (LTPS) to improve the response rate characteristics of the transistors.

[0071] The inverter unit 220 may receive a logic signal and output a phase-inverted scan signal through the gate output terminal OUT_AA. In other words, the scan signal output by the inverter unit 220 may be a signal with the phase inverted of the logic signal. For example, if a logic signal with a gate high voltage VGH is input from the logic unit 210, the inverter unit 220 may output a scan signal with a gate low voltage VGL, and if a logic signal with a gate low voltage VGL is input from the logic unit 210, the inverter unit 220 may output a scan signal with a gate high voltage VGH.

[0072] The gate output terminal OUT_AA may be electrically connected to the gate line GL in Figure 1. The scan signal from the inverter unit 220 may be input to the first switching transistor ST1 of the subpixel SP via the gate line GL.

[0073] The inverter section 220 includes an n-type first inverter transistor T8_O and a p-type second inverter transistor T9, whose gate electrodes are connected to the logic output terminal OUT_Logic and which are located on either side of the gate output terminal OUT_AA. The first inverter transistor T8_O is made of an oxide semiconductor, and the second inverter transistor T9 may be made of a semiconductor formed from low-temperature polysilicon (LTPS). In other words, the first inverter transistor T8_O may be a different type of transistor than the second inverter transistor T9.

[0074] Specifically, the first inverter transistor T8_O may have its gate electrode connected to the logic output terminal OUT_Logic, with a gate low voltage VGL supplied to one end and the other end connected to the gate output terminal OUT_AA. The second inverter transistor T9 may have its gate electrode connected to the logic output terminal OUT_Logic, with a gate high voltage VGH supplied to one end and the other end connected to the gate output terminal OUT_AA.

[0075] As a result, the first inverter transistor T8_O may be turned on by a logic signal with a gate high voltage VGH and output a gate low voltage VGL at its gate output terminal OUT_AA, and the second inverter transistor T9 may be turned on by a logic signal with a gate low voltage VGL and output a gate high voltage VGH at its gate output terminal OUT_AA.

[0076] In the inverter unit 220 of the present invention, since the first and second inverter transistors are controlled by logic signals output via the logic output terminal OUT_Logic, a separate clock signal is not required to control the first and second inverter transistors, which can reduce the number of clock signals. As a result, the structure of the inverter unit 220 of the present invention can be made simpler in terms of circuit structure, and the number of clock signal lines arranged on the display panel can be reduced. For example, since the inverter unit 220 can use n-type transistors and p-type transistors, the inverter unit 220 can be effectively controlled by the same logic signals output via the logic output terminal OUT_Logic.

[0077] The logic unit 210, as illustrated in Figure 3, can be configured in various forms including Q nodes and QB nodes, and as mentioned above, may include multiple logic transistors and multiple capacitors. The present invention is not limited to the configuration of the logic unit 210 shown in Figure 3. As long as it outputs logic signals including gate high voltage VGH and gate low voltage VGL via the logic output terminal OUT_Logic, the configuration of the logic unit 210 is not limited.

[0078] For example, as shown in Figure 3, the logic unit 210 may include a first logic transistor T1 to a seventh logic transistor T7 having p-type, and first and second capacitors CQ and CQB.

[0079] The first logic transistor T1 may have its gate electrode connected to the Q node, with the first clock signal CLK1 input to one end and the other end connected to the logic output terminal OUT_Logic. Depending on the potential of the Q node, the first logic transistor T1 may output the voltage of the second clock signal CLK2 to the logic output terminal OUT_Logic.

[0080] The second logic transistor T2 may have its gate electrode connected to the QB node, with a gate high voltage VGH supplied to one end and the other end connected to the logic output terminal OUT_Logic. Depending on the potential of the QB node, the logic output terminal OUT_Logic may output a gate high voltage VGH.

[0081] The third logic transistor T3 may have the second clock signal CLK2 input to its gate electrode, the start signal GVST input to one end, and the other end connected to the Q node via the eighth logic transistor TA. The third logic transistor T3 may apply the potential of the start signal GVST to the Q node via the second clock signal CLK2.

[0082] The fourth logic transistor T4 may have its gate electrode connected to the Q node via the eighth logic transistor TA, with the second clock signal CLK2 input to one end and the other end connected to the QB node. The fourth logic transistor T4 may apply the potential of the second clock signal CLK2 to the QB node through the potential of the Q2 node.

[0083] The fifth logic transistor T5 may have the second clock signal CLK2 input to its gate electrode, the gate low voltage VGL input to one end, and the other end connected to the QB node. The fifth logic transistor T5 may supply the gate low voltage VGL to the QB node via the second clock signal CLK2.

[0084] The sixth logic transistor T6 has its gate electrode connected to the QB node and may output a gate high voltage VGH supplied to one end to the other end. The sixth logic transistor T6 may output a gate high voltage VGH to the seventh logic transistor T7 depending on the potential of the QB node.

[0085] The seventh logic transistor T7 has the first clock signal CLK1 as its gate electrode, one end of which is connected to the sixth logic transistor T6, and the other end of which may be connected to the Q node via the eighth logic transistor TA. The seventh logic transistor T7 may supply the Q node with a gate high voltage VGH supplied via the sixth logic transistor T6 by the first clock signal CLK1.

[0086] The eighth logic transistor TA may have a gate-low voltage VGL supplied to its gate electrode and be connected between the gate electrode of the first logic transistor T1 and the other end of the third logic transistor T3. In other words, the eighth logic transistor TA may be located on the Q node.

[0087] In Figure 3, for convenience, one side of the eighth logic transistor TA is shown as the Q2 node and the other side as the Q node. However, since the eighth logic transistor TA is always supplied with the gate low voltage VGL at its gate electrode and remains turned on, the potentials of the Q node and the Q2 node may be substantially the same as long as the logic unit 210 is operating normally.

[0088] The eighth logic transistor TA may prevent damage to the first logic transistor T1 due to overvoltage. Specifically, in the absence of the eighth logic transistor TA, if an overvoltage exceeding the drive range is applied to the Q2 node due to a circuit malfunction or other reason, the first logic transistor T1 may be damaged.

[0089] However, when the eighth logic transistor TA is present, if an overvoltage is applied to the Q2 node, the eighth logic transistor TA may be turned off, electrically isolating the Q2 node from the Q node, preventing the overvoltage at the Q2 node from being transmitted to the Q node, and thus preventing damage to the first logic transistor T1.

[0090] The first capacitor CQ may have one end connected to the Q node and the other end connected to the logic output terminal OUT_Logic. The first capacitor CQ may charge and maintain the potential applied to the Q node. Therefore, unless the Q node is floating or the current applied potential to the Q node is the same as the previous applied potential, the potential of the Q node may be maintained at the same potential by the first capacitor CQ.

[0091] The second capacitor CQB may have one end connected to the QB node and the other end supplied with a logic high voltage VH. The second capacitor CQB may charge and maintain the potential applied to the QB node.

[0092] Here, the gate high voltage VGH and gate low voltage VGL may be supplied from the power supply unit, and the first and second clock signals CLK1 and CLK2 and the start signal GVST may be supplied from the timing controller.

[0093] As shown in Figure 4, the timing degree applied to the scan drive circuit 200 according to the first embodiment may include a first period P1 to a fourth period P4 during one cycle.

[0094] During the first period P1, the start signal GVST and the second clock signal CLK2 may have a logic low voltage VL, and the first clock signal CLK1 may have a logic high voltage VH. As a result, the logic unit 210 may output a gate high voltage VGH via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate low voltage VGL via the gate output terminal OUT_AA.

[0095] After the first period P1, in the second period P2, the first clock signal CLK1 may have a logic low voltage VL, and the second clock signal CLK2 and the start signal GVST may have a logic high voltage VH. As a result, the logic unit 210 may output a gate low voltage VGL via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate high voltage VGH via the gate output terminal OUT_AA.

[0096] After the second period P2, in the third period P3, the second clock signal CLK2 may have a logic low voltage VL, while the first clock signal CLK1 and the start signal GVST may have a logic high voltage VH. As a result, the logic unit 210 may output a gate high voltage VGH via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate low voltage VGL via the gate output terminal OUT_AA.

[0097] After the third period P3, in the fourth period P4, the first clock signal CLK1 may have a logic low voltage VL, and the second clock signal CLK2 and the start signal GVST may have a logic high voltage VH. As a result, the logic unit 210 may output a gate high voltage VGH via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate low voltage VGL via the gate output terminal OUT_AA.

[0098] In the following section, the operation method of the scan drive circuit 200 according to the first embodiment will be specifically described according to the timing diagram shown in Figure 4.

[0099] Figures 5 to 8 are diagrams illustrating how the scan drive circuit according to the first embodiment operates, as shown in the timing diagram of Figure 4.

[0100] During the first period P1 through the fourth period P4, the gate low voltage VGL is supplied to the gate electrode of the eighth logic transistor TA. Therefore, the eighth logic transistor TA may turn on during the first period P1 through the fourth period P4, and the potential of the Q2 node may be the same as the potential of the Q node.

[0101] During the first period P1, the start signal GVST and the second clock signal CLK2 may have a logic low voltage VL, and the first clock signal CLK1 may have a logic high voltage VH. As a result, the third logic transistor T3 is turned on by the second clock signal CLK2, the logic low voltage VL of the start signal GVST is supplied to the Q2 node and the Q node, and the Q node may be charged with the logic low voltage VL by the first capacitor CQ.

[0102] Additionally, the first logic transistor T1 may be turned on by the logic low voltage VL of the Q node, and the logic high voltage VH of the first clock signal CLK1 may be output via the logic output terminal OUT_Logic.

[0103] Additionally, the logic low voltage VL of the Q2 node may turn on the fourth logic transistor T4, supplying the logic low voltage VL of the second clock signal CLK2 to the QB node, which may turn on the fifth logic transistor T5, supplying the gate low voltage VGL to the QB node.

[0104] As a result, the QB node may be charged with a gate low voltage VGL by the second capacitor CQB. Depending on the logic low voltage VL of the QB node, the second logic transistor T2 is also turned on, and the gate high voltage VGH is also output via the logic output terminal OUT_Logic through the second logic transistor T2.

[0105] As a result, the first inverter transistor T8_O is turned on by receiving a gate high voltage VGH via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate low voltage VGL via the gate output terminal OUT_AA.

[0106] During the second period P2, the first clock signal CLK1 may have a logic low voltage VL, and the second clock signal CLK2 may have a logic high voltage VH. As a result, the third logic transistor T3 is turned off, blocking the start signal GVST, and the Q2 node and Q node may maintain the logic low voltage VL of the first period P1 due to the charge potential of the first capacitor CQ. As a result, the first logic transistor T1 is turned on, and the logic low voltage VL of the first clock signal CLK1 is output via the logic output terminal OUT_Logic.

[0107] Furthermore, when the Q2 node maintains a logic low voltage VL, the fourth logic transistor T4 is turned on and the fifth logic transistor T5 is turned off. This applies the logic high voltage VH of the second clock signal CLK2 to the QB node, which may charge the second capacitor CQB with the logic high voltage VH. The logic high voltage VH of the QB node may turn off the second logic transistor T2 and the sixth logic transistor T6.

[0108] As a result, the second inverter transistor T9 is turned on by inputting a gate low voltage VGL from the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate high voltage VGH via the gate output terminal OUT_AA.

[0109] During the third period P3, the second clock signal CLK2 may have a logic low voltage VL, while the first clock signal CLK1 and the start signal GVST may have a logic high voltage VH.

[0110] The third logic transistor T3 is turned on by the second clock signal CLK2, and the logic high voltage VH of the start signal GVST is supplied to the Q2 node and the Q node. The Q node is then charged with the logic high voltage VH by the first capacitor CQ. In addition, the first logic transistor T1 may be turned off depending on the logic high voltage VH of the Q node.

[0111] Furthermore, in response to the logic low voltage VL of the second clock signal CLK2, the fifth logic transistor T5 is turned on, supplying the gate low voltage VGL to the QB node. This may charge the QB node with the gate low voltage VGL via the second capacitor CQB. In response to the logic low voltage VL of the QB node, the second logic transistor T2 is turned on, and the gate high voltage VGH is output via the logic output terminal OUT_Logic.

[0112] As a result, the first inverter transistor T8_O turns on when it receives a gate high voltage VGH input via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal having a gate low voltage VGL via the gate output terminal OUT_AA.

[0113] During the fourth period P4, the first clock signal CLK1 may have a logic low voltage VL, and the second clock signal CLK2 may have a logic high voltage VH. This may cause the seventh logic transistor T7 to be turned on, and the third logic transistor T3 to be turned off.

[0114] The potential of the QB node may be maintained at the same logic low voltage VL as the potential in the third period P3. The logic low voltage VL of the QB node allows the second logic transistor T2 and the sixth logic transistor T6 to be turned on. The second logic transistor T2 may be turned on, and a gate high voltage VGH may be output through the logic output terminal OUT_Logic. Also, the sixth logic transistor T6 may be turned on, and a gate high voltage VGH may be supplied to the Q node via the seventh logic transistor T7.

[0115] As a result, the first inverter transistor T8_O is turned on by receiving a gate high voltage VGH via the logic output terminal OUT_Logic, and the inverter unit 220 may output a scan signal with a gate low voltage VGL via the gate output terminal OUT_AA.

[0116] Thus, the present invention may reduce the number of clock signals by providing an n-type first inverter transistor T8_O and a p-type second inverter transistor T9, both of which are commonly connected to the logic output terminal OUT_Logic, in the inverter unit 220. For example, by using a configuration design in the inverter unit 220 that connects a pair of different types of transistors (e.g., one n-type and one p-type) to the same output, this particular combination provides a more elegant circuit design and can operate with fewer clock signals.

[0117] Furthermore, by including an oxide semiconductor in the first inverter transistor T8_O, a scan signal with a gate low voltage VGL can be stably supplied to the pixel circuit via the gate output terminal OUT_AA. This allows the scan drive circuit 200 of the present invention to minimize malfunctions of the pixel circuit. For example, the oxide semiconductor can prevent glitching and malfunctions in the pixel by ensuring that the first inverter transistor T8_O supplies a stable and consistent low-voltage signal to the pixel.

[0118] On the other hand, the scan drive circuit 200 according to the first embodiment may supply a scan signal with a gate high voltage VGH for a very short period during one frame period, and a scan signal with a gate low voltage VGL for the remainder of the frame period.

[0119] As a result, the period during which the gate high voltage VGH of the logic signal is supplied from the inverter unit 220 to the gate electrode of the first inverter transistor T8_O may be longer than the period during which the gate low voltage VGL of the logic signal is supplied. For example, the first inverter transistor T8_O may turn on during the first, third, and fourth periods P1, P3, and P4, excluding the second period P2.

[0120] In other words, while the scan drive circuit 200 according to the first embodiment outputs a scan signal with a gate low voltage VGL, the first inverter transistor T8_O, which includes an oxide semiconductor, may remain continuously turned on.

[0121] When the first inverter transistor T8_O, which contains an oxide semiconductor, is continuously turned on, the first inverter transistor T8_O may be subjected to Positive Bias Thermal Stress (PBTS), and the threshold voltage Vth of the first inverter transistor T8_O may be shifted in the positive direction by the PBTS.

[0122] Such PBTS may worsen when the scan drive circuit 200 is driven at a low speed, in a high-temperature environment, or under conditions of prolonged operation. This can lead to operational errors in the first inverter transistor T8_O, preventing the gate low voltage VGL of the scan signal from being stably maintained, resulting in drive failure and a decrease in the reliability of the display device 100.

[0123] Taking these points into consideration, the present invention may include a structure to prevent malfunction of the first inverter transistor T8_O.

[0124] Figure 9 is a diagram illustrating a scan drive circuit according to a second embodiment of the present invention, Figure 10 is a diagram illustrating the operation of the scan drive circuit according to the second embodiment during high-speed driving at a first scan rate or higher, and Figure 11 is a diagram illustrating the operation of the scan drive circuit according to the second embodiment during low-speed driving at a rate lower than the first scan rate.

[0125] In Figures 9 through 11, any content that overlaps with what was explained in Figures 3 through 8 is replaced with the content from Figures 3 through 8, and the explanation focuses on other parts.

[0126] The scan drive circuit 200 according to the second embodiment shown in Figure 9 may compensate for the phenomenon in which the first inverter transistor T8_O deteriorates and undergoes a positive shift under low-speed drive conditions, high-temperature environmental conditions, or long-duration drive conditions.

[0127] Specifically, in the scan drive circuit 200 according to the second embodiment of the present invention, the first inverter transistor T8_O includes a bottom electrode BE located on the other side of the gate electrode, centered on an oxide semiconductor, and may further include a first switch SW1 and a second switch SW2.

[0128] The first switch SW1 may have one end connected to the gate electrode and the other end connected to the bottom electrode BE, and the second switch SW2 may have one end connected to both the bottom electrode BE and the first switch SW1, with a constant voltage Vbg supplied to the other end. For example, the first switch SW1 and the second switch SW2 may include P-type transistors. For example, the first inverter transistor T8_O may have a sandwich-like arrangement in which the bottom electrode BE is located on one side of the oxide material and the gate electrode is located on the other side (for example, the gate electrode may be located on the semiconductor layer of T8_O and the bottom electrode BE may be located below the semiconductor layer of T8_O). This arrangement may also be connected to two switches (SW1 and SW2).

[0129] The first switch SW1 may increase the response speed of the first inverter transistor T8_O by connecting the gate electrode and bottom electrode BE of the first inverter transistor T8_O when the scan drive circuit 200 according to the second embodiment is in normal or high-speed drive mode. For example, in normal or high-speed operation, the first switch SW1 may connect the upper gate electrode and bottom electrode of the transistor, and this direct connection can improve the response speed of the first inverter transistor T8_O. In other words, in normal or high-speed operation, the first switch SW1 may operate as a dual-gate transistor, in which case a stronger electric field may be applied to the opposite side of the semiconductor layer to form a better conductive channel (e.g., higher drive current and faster response time).

[0130] The second switch SW2, during low-speed operation, connects a buck bias power supply with a constant voltage Vbg to the bottom electrode BE of the first inverter transistor T8_O, thereby compensating for the phenomenon of the first inverter transistor T8_O degrading and undergoing a positive shift. For example, during low-speed operation (which can stress the transistor), the second switch SW2 may be turned on, applying a stable and calibrating voltage (e.g., "buck bias") to the bottom electrode of the first inverter transistor T8_O. This can offset the stress and prevent changes in the transistor's electrical characteristics.

[0131] More specifically, while the scan drive circuit 200 outputs a scan signal at a first scan rate or higher, the first switch SW1 may be turned on and the second switch SW2 may be turned off, as shown in Figure 10a.

[0132] The first scan rate may be set to a reference value of, for example, 60 Hz. However, the present invention is not limited to this, and the reference value for the first scan rate may change. However, for the sake of explanation, the case where the first scan rate is 60 Hz will be explained below as an example.

[0133] Therefore, when the scan drive circuit 200 according to the second embodiment performs a general drive and outputs a scan signal at a speed of 60 Hz, or when the scan drive circuit 200 performs a high-speed drive and outputs a scan signal at a fast speed of 120 Hz, the first switch SW1 may be turned on and the second switch SW2 may be turned off. Therefore, for example, as shown in Figure 10b, during the first period P1 to the fourth period P4, a logic low voltage VL signal may be applied to the gate electrode of the first switch SW1 to turn on the first switch SW1, and a logic high voltage VH signal may be applied to the gate electrode of the second switch SW2 to turn off the second switch SW2.

[0134] As a result, the gate electrode and bottom electrode BE of the first inverter transistor T8_O are connected by the first switch SW1, which can increase the reaction rate of the first inverter transistor T8_O.

[0135] Furthermore, while the scan drive circuit 200 according to the second embodiment outputs a scan signal at a scan rate less than the first scan rate, the first switch SW1 may be turned off and the second switch SW2 may be turned on, as shown in Figure 11a.

[0136] Therefore, if the scan drive circuit 200 according to the second embodiment is driven at a low speed and outputs a scan signal at a speed lower than 60 Hz, for example, 30 Hz or 1 Hz, or if the scan drive circuit 200 operates at a first temperature higher than a preset temperature, or operates for a long period of time longer than a preset time, the first switch SW1 may be turned on and the second switch SW2 may be turned off.

[0137] Therefore, for example, as shown in Figure 11b, during the first period P1 to the fourth period P4, a logic high voltage VH signal may be applied to the gate electrode of the first switch SW1 to turn off the first switch SW1, and a logic low voltage VL signal may be applied to the gate electrode of the second switch SW2 to turn on the second switch SW2.

[0138] This connects the back bias power supply to the bottom electrode BE of the first inverter transistor T8_O, preventing PBTS of the first inverter transistor T8_O, improving the reliability of the scan drive circuit 200 and the display device 100. For example, if a back bias is not applied during low-speed driving, the threshold voltage of the first inverter transistor T8_O may increase due to PBTS stress. That is, the minimum gate voltage required to turn on the transistor becomes higher, leading to power waste over time and potentially causing image defects or timing errors.

[0139] Thus, in this embodiment of the present invention, by providing an inverter section that includes an n-type first inverter transistor and a p-type second inverter transistor, which are commonly connected to the logic output terminal of the logic section of the scan drive circuit, the number of clock signals can be reduced and the operation can be simplified.

[0140] In this embodiment of the present invention, by including an oxide semiconductor in the first inverter transistor, it is possible to prevent the scan signal from becoming unstable due to leakage current of the first inverter transistor and minimize malfunctions of the pixel circuit.

[0141] In embodiments of the present invention, the first inverter transistor includes a bottom electrode, and by further comprising a first switch and a second switch connected to the bottom electrode, positive bias thermal stress (PBTS) of the first inverter transistor can be prevented and operational errors of the scan drive circuit can be improved.

[0142] As explained above, those skilled in the art will understand that a variety of changes and modifications are possible without departing from the technical concept of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the claims. [Explanation of Symbols]

[0143] 110 Display Panel SP Subpixel DL Dataline GL Gate Line ST1 First Switching Transistor DT drive transistor ST2 Second Switching Transistor OLED light-emitting element 200 scan drive circuit 210 Logic section 220 Inverter section

Claims

1. A substrate including a display area and a non-display area, A pixel circuit located in the aforementioned display area for driving a light-emitting element, and Includes a scan drive circuit that supplies a scan signal to the aforementioned pixel circuit, The aforementioned scan drive circuit is A logic unit that receives multiple clock signals as input and outputs logic signals via a logic output terminal, and The inverter unit includes a unit that receives the logic signal input and outputs the scan signal, whose phase has been inverted, via a gate output terminal. The inverter section includes an n-type first inverter transistor and a p-type second inverter transistor, each having its gate electrode connected to the logic output terminal and positioned on either side of the gate output terminal. The first inverter transistor is a display device containing an oxide semiconductor.

2. The display device according to claim 1, wherein the period during which the gate high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than the period during which the gate low voltage of the logic signal is supplied.

3. The display device according to claim 1, wherein the second inverter transistor includes a semiconductor formed of low-temperature polysilicon (LTPS).

4. The first inverter transistor has a gate electrode connected to the logic output terminal, a gate low voltage (VGL) supplied to one end, and the other end connected to the gate output terminal. The display device according to claim 1, wherein the second inverter transistor has a gate electrode connected to the logic output terminal, a gate high voltage (VGH) supplied to one end, and the other end connected to the gate output terminal.

5. The first inverter transistor is turned on by the logic signal having a gate high voltage and outputs the scan signal having a gate low voltage to the gate output terminal. The display device according to claim 1, wherein the second inverter transistor is turned on by the logic signal having a gate low voltage and outputs the scan signal having a gate high voltage to the gate output terminal.

6. The logic section includes a plurality of logic transistors, The display device according to claim 1, wherein the plurality of logic transistors include semiconductors formed of low-temperature polysilicon (LTPS).

7. The logic unit is, A first logic transistor in which the gate electrode is connected to a Q node, a first clock signal is input to one end, and the other end is connected to the logic output terminal, A second logic transistor, in which the gate electrode is connected to a QB node, a gate high voltage is supplied to one end, and the other end is connected to the logic output terminal, A third logic transistor is provided with a second clock signal input to its gate electrode, a start signal input to one end, and the other end connected to the Q node. A fourth logic transistor, the gate electrode of which is connected to the Q node, the second clock signal input to one end, and the other end of which is connected to the QB node, A fifth logic transistor, to which the second clock signal is input to the gate electrode, to which the gate low voltage is input to one end, and to which the other end is connected to the QB node, A sixth logic transistor whose gate electrode is connected to the QB node and which outputs a gate high voltage supplied to one end to the other end, The first clock signal is input to the gate electrode of a seventh logic transistor, one end of which is connected to the sixth logic transistor and the other end of which is connected to the Q node. A first capacitor, one end of which is connected to the Q node and the other end of which is connected to the logic output terminal, The display device according to claim 1, comprising a second capacitor to which one end is connected to the QB node and to which a logic high voltage is supplied to the other end.

8. The logic section is The display device according to claim 7, further comprising an eighth logic transistor to which a gate-low voltage is supplied to the gate electrode and which is connected between the gate electrode of the first logic transistor and the other end of the third logic transistor.

9. During the first period, the start signal and the second clock signal have a logic low voltage, and the first clock signal has a logic high voltage. In the second period following the first period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage. In the third period following the second period, the second clock signal has a logic low voltage, and the first clock signal and the start signal have logic high voltages. The display device according to claim 7, wherein in a fourth period following the third period, the first clock signal has a logic low voltage and the second clock signal has a logic high voltage.

10. The first inverter transistor includes a bottom electrode located on the other side of the gate electrode, centered on the oxide semiconductor. A first switch, one end of which is connected to the gate electrode and the other end of which is connected to the bottom electrode, The display device according to claim 1, further comprising a second switch, one end of which is commonly connected to the bottom electrode and the first switch, and to which a constant voltage is supplied to the other end.

11. The display device according to claim 10, wherein the first switch is turned on and the second switch is turned off while the scan drive circuit outputs the scan signal at a first scan rate or higher.

12. The display device according to claim 10, wherein the first switch is turned off and the second switch is turned on while the scan drive circuit outputs the scan signal at a scan rate less than the first scan rate.

13. A logic unit that receives multiple clock signals as inputs and outputs logic signals via a logic output terminal in order to supply scan signals to pixel circuits located in the display area of ​​the board, and The inverter unit includes a unit that receives the logic signal input and outputs the scan signal, whose phase is inverted, via a gate output terminal. The inverter section includes an n-type first inverter transistor and a p-type second inverter transistor located on either side of the gate output terminal. The first inverter transistor is a scan drive circuit containing an oxide semiconductor.

14. The scan drive circuit according to claim 13, wherein the period during which the logic high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than the period during which the logic low voltage of the logic signal is supplied.

15. The scan drive circuit according to claim 13, wherein the second inverter transistor includes a semiconductor formed of low-temperature polysilicon (LTPS).

16. The first inverter transistor has a gate electrode connected to the logic output terminal, a gate low voltage (VGL) supplied to one end, and the other end connected to the gate output terminal. The scan drive circuit according to claim 13, wherein the second inverter transistor has a gate electrode connected to the logic output terminal, a gate high voltage (VGH) supplied to one end, and the other end connected to the gate output terminal.

17. The first inverter transistor is turned on by the logic signal having a gate high voltage and outputs the scan signal having a gate low voltage to the gate output terminal. The scan drive circuit according to claim 13, wherein the second inverter transistor is turned on by the logic signal having a gate low voltage and outputs the scan signal having a gate high voltage to the gate output terminal.

18. The first inverter transistor includes a gate electrode located on one side of the oxide semiconductor and a bottom electrode located on the other side. A first switch, one end of which is connected to the gate electrode and the other end of which is connected to the bottom electrode, The scan drive circuit according to claim 13, further comprising a second switch that is commonly connected to the bottom electrode and the other end of the first switch and controls the supply of a constant voltage.

19. The scan drive circuit according to claim 18, wherein the first switch is turned on and the second switch is turned off while the scan drive circuit outputs the scan signal at a first scan rate or higher.

20. The scan drive circuit according to claim 18, wherein the first switch is turned off and the second switch is turned on while the scan drive circuit outputs the scan signal at a scan rate less than the first scan rate.

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