Data storage device capable of backing up data in the event of external power loss, and its operating method.

Abstract

This invention provides a data storage device and its operating method that can back up data in the event of external power supply loss. [Solution] The data storage device 200 according to one embodiment may include a non-volatile memory device 220 and a controller 210. The controller 210 can be configured to enter a power loss recovery mode due to an external power loss, set a first threshold time associated with the power loss recovery operation, and back up debug data to the non-volatile memory device 220 when the first threshold time has elapsed.

Description

Technical Field

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[0005]

[0001] The present technology relates to a semiconductor device, and more particularly to a data storage device capable of backing up data due to an external power loss and an operation method thereof.

Background Art

[0002] A data storage device using a non-volatile memory device as a storage medium can operate by being supplied with power from an external device.

[0003] When a SPO (Sudden Power Off) situation occurs where power is suddenly cut off during the operation of the data storage device, the data stored in the operation memory or cache memory of the data storage device may be lost, or the operation in progress (for example, an erase operation or a write operation) may not be completed from the non-volatile memory device.

[0004] In response to such a situation, the data storage device can use an auxiliary power supply device to complete the operation in progress or store data related to the operation state at the time of occurrence of SPO in the non-volatile memory device.

Summary of the Invention

Problems to be Solved by the Invention

[0005] A data storage device according to an embodiment of the present technology includes a non-volatile memory device and a controller configured to enter a power loss recovery mode due to an external power loss, set a first threshold time related to a power loss recovery operation, and when the first threshold time elapses, back up debug data to the non-volatile memory device.

[0006] A data storage device according to one embodiment of this technology includes a volatile memory device, a non-volatile memory device, and a controller. The controller can be configured to enter a power loss recovery mode due to external power loss, back up recovery data stored in the volatile memory device to the non-volatile memory device, and back up debug data to the non-volatile memory device if a predetermined error occurs during the backup operation of the recovery data.

[0007] An operating method for a data storage device according to one embodiment of this technology is an operating method for a data storage device including a non-volatile memory device and a controller that controls the non-volatile memory device, wherein the device enters a power loss recovery mode due to an external power loss, and the controller sets a first threshold time associated with the power loss recovery operation, and the controller backs up debug data to the non-volatile memory device when the first threshold time has elapsed. [Effects of the Invention]

[0008] This technology allows for the safe backup of debugging data necessary for recovery after a power loss occurs in the data storage device.

[0009] This ensures that even if data backup is not completed at the time of external power loss, the data storage device can be driven normally using debug data once power is restored. [Brief explanation of the drawing]

[0010] [Figure 1] This is a configuration diagram of an electronic system according to one embodiment. [Figure 2] This is a configuration diagram of a non-volatile memory device according to one embodiment. [Figure 3] This is a diagram illustrating the data stored in a buffer memory device according to one embodiment. [Figure 4] This is a diagram showing the configuration of a PLP manager according to one embodiment. [Figure 5] This is a conceptual diagram illustrating a method for backing up debug data according to one embodiment. [Figure 6] This is a conceptual diagram illustrating a method for backing up debug data according to one embodiment. [Figure 7] This is a conceptual diagram illustrating a method for backing up debug data according to one embodiment. [Figure 8] This is a flowchart illustrating the operation method of a data storage device according to one embodiment. [Modes for carrying out the invention]

[0011] The following describes embodiments of this technology in more detail, based on the attached drawings.

[0012] Figure 1 is a diagram showing the configuration of an electronic system according to one embodiment.

[0013] Referring to Figure 1, the electronic system 10 may include an external device 100 and a data storage device 200.

[0014] The external device 100 may be a processing device that controls the data storage device 200 in order to store data.

[0015] The external device 100 may include at least one of the following: CPU (Central Processing Unit), ISP (Image Signal Processing Unit), DSP (Digital Signal Processing Unit), GPU (Graphics Processing Unit), VPU (Vision Processing Unit), FPGA (Field Programmable Gate Array), and NPU (Neural Processing Unit).

[0016] The data storage device 200 may include a controller 210, a non-volatile memory device 220 (220-0 to 220-k), a buffer memory device 230, a power supply 240, a signal connector 1101, and a power connector 1103.

[0017] The controller 210 can control all operations of the data storage device 200.

[0018] The data storage device 200 receives command signals (CMD) and address signals (ADDR) from the external device 100 via the signal connector 1101, and transmits and receives data (DT) with the external device 100. The signal connector 1101 can consist of various types of connectors depending on the interface method of the external device 100 and the data storage device 200.

[0019] The interface method of the external device 100 and the data storage device 200 may include at least one of a variety of interface protocols, such as USB (Universal Serial Bus) protocol, MMC (multimedia card) protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-express) protocol, ATA (Advanced Technology Attachment) protocol, SATA (Serial-ATA) protocol, PATA (Parallel-ATA) protocol, SCSI (small computer system interface) protocol, ESDI (enhanced small disk interface) protocol, IDE (Integrated Drive Electronics) protocol, private protocol, SMBus (System Management Bus) protocol, I2C (Inter-Integrated Circuit) protocol, and I3C (Improved Inter-Integrated Circuit) protocol.

[0020] The controller 210 can analyze and process signals input from the external device 100. The controller 210 can control the operations of the functional block group it has inside based on firmware or software for driving the data storage device 200. Although not shown in the figure, the controller 210 can include a volatile memory device as a cache memory inside it.

[0021] The buffer memory device 230 can temporarily store data stored in the non-volatile memory device 220. Also, the buffer memory device 230 can temporarily store data read from the non-volatile memory device 220. The data temporarily stored in the buffer memory device 230 can be transferred to the external device 100 or the non-volatile memory device 220 under the control of the controller 210. In some embodiments, the data storage device 200 can be a DRAM-Less device that does not include the buffer memory device 230.

[0022] The non-volatile memory device 220 can be used as a storage medium of the data storage device 200. Each of the non-volatile memory devices 220 can be connected to the controller 210 via a plurality of channels (CH1 to CHk) (k is a natural number). One or more non-volatile memory devices (NVM) can be connected to one channel. The non-volatile memory devices (NVM) connected to one channel can be connected to the same signal bus and data bus.

[0023] The power supply unit 240 can convert the levels of external power supply voltages (VES1 to VEST) input via a power connector 1103 containing multiple power lines (PL1 to PLt) to generate multiple internal power supply voltages (VIS1 to VISn). The multiple internal power supply voltages (VIS1 to VISn) generated by the power supply unit 240 can be supplied to the controller 210, non-volatile memory device 220, buffer memory device 230, and other circuit parts (OTHER CIRCUIT(S)) of the data storage device 200. The power supply unit 240 may include an auxiliary power supply unit 241. The auxiliary power supply unit 241 can supply internal power supply voltages (VIS1 to VISn) to properly shut down the data storage device 200 if SPO (External Power Loss) is detected. The auxiliary power supply unit 241 may, but is not limited to, include large-capacity capacitors. The auxiliary power supply unit 241 may be installed outside the power supply unit 240.

[0024] On the other hand, the controller 210 may internally include various functional blocks (not shown), such as a processor, an external interface device, an operating memory, an error detection and correction circuit (ECC), a memory interface device, and other components necessary for controlling data exchange between the external device 100 and the non-volatile memory device 220.

[0025] In particular, the controller 210 according to an embodiment of this technology may include a PLP manager 250. In one embodiment, the PLP manager 250 can enter Power Loss Protection (PLP) mode when an external power loss (SPO) event occurs, such as when the level of the external power supply voltage supplied to the power supply unit falls below a reference value. By entering PLP mode, the PLP manager 250 can back up recovery data to a non-volatile memory device 220. The PLP manager 250 can back up debug data to the non-volatile memory device 220 when a threshold time determined in relation to the PLP mode has elapsed.

[0026] The recovered data may include data that the data storage device 200 was processing or using at the time of the SPO, such as user data, mapping data, and housekeeping (HK) operation-related metadata. In one embodiment, the debug data may include data for recovering the data storage device 200 when power is restored after the SPO, such as hardware (HW) information, firmware (FW) information, and log information of the data storage device 200.

[0027] It is possible that recovery data cannot be backed up to the non-volatile memory device 220 while the auxiliary power supply 241 is providing support after an SPO occurs. Subsequently, when power is restored to the data storage device 200, the data storage device 200 can be restored to its state before the SPO occurred using the debug data.

[0028] If the debug data cannot be backed up while the auxiliary power supply 241 is assisting after an SPO occurs, the data storage device 200 may enter an open fail state, rendering it inoperable even after power is restored. Therefore, if an SPO is detected, the debug data must be safely backed up within the time limit.

[0029] Figure 2 is a diagram showing the configuration of a non-volatile memory device according to one embodiment.

[0030] Referring to Figure 2, the non-volatile memory device 220-n may contain one or more memory dies (Die1, Die2, Die3, Die4). Each die (Die1, Die2, Die3, Die4) may contain one or more planes (Plane1, Plane2, Plane3, Plane4). Figure 2 illustrates a state in which multiple dies (Die1 to Die4) each contain one plane.

[0031] Each plane (Plane1, Plane2, Plane3, Plane4) can contain multiple memory blocks (Block11-Block18, Block21-Block28, Block31-Block38, Block41-Block48). Each of the multiple memory blocks (Block11-Block48) can contain multiple pages (not shown), and each of the multiple pages can contain multiple memory cells (not shown) connected to a word line.

[0032] Multiple planes (Plane1, Plane2, Plane3, Plane4) can operate independently of each other. In order to improve the parallel processing performance of the data storage device 200, the controller 210 can logically link the memory block groups contained in each of the multiple planes (Plane1, Plane2, Plane3, Plane4) to form a single superblock. Figure 2 illustrates a first superblock (Superblock1) consisting of the 11th, 21st, 31st, and 41st blocks (Block11, Block21, Block31, Block41) present in each of the multiple planes (Plane1 to Plane4).

[0033] Multiple memory blocks (Block 11 to Block 48) can be divided into multiple areas, including a first area (R1) and a second area (R2). The first area (R1) may be an area for storing user data transmitted and received with the external device 100. The second area (R2) may be a dump area allocated to back up recovery data and debug data when the SPO of the data storage device 200 is detected. In other words, the second area (R2) may be an area for temporarily storing data depending on the power supply state applied to the data storage device 200.

[0034] Figure 3 is a diagram illustrating the data stored in a buffer memory device according to one embodiment.

[0035] Referring to Figure 3, the buffer memory device 230 can store recovery data 231 and debug data 233.

[0036] The recovered data 231 may include data that the data storage device 200 was processing or using at the time of SPO, such as user data 2311, mapping data 2313, and housekeeping (HK) metadata 2315 related to the internal operation of the data storage device 200.

[0037] User data 2311 may be data resulting from a write request from an external device 100 that is not programmed into the non-volatile memory device 220 and is stored in the buffer memory device 230 or a cache memory (not shown) in the controller 210.

[0038] The mapping data 2313 may be data indicating mapping information between the logical address of the external device 100 and the physical address of the non-volatile memory device 220. The mapping data 2313 can be at least partially loaded from the non-volatile memory device 220 to the buffer memory device 230 or the cache memory (not shown) in the controller 210 when the data storage device 200 is operating.

[0039] The HK metadata 2315 may include block management information and data status (enabled / disabled) information for the non-volatile memory device 220 used by the controller 210 for internal operations to manage the data storage device 200, such as wear leveling and garbage collection operations.

[0040] On the other hand, the debug data 233 may include data for restoring and driving the data storage device 200 to its previous state before the SPO when power is restored after the SPO, such as hardware (HW) information 2331, firmware (FW) information 2333, and log information 2335 of the data storage device 200.

[0041] The hardware information 2331 may include state information of the controller 210 at the time of SPO occurrence, such as system register information, instruction waiting list information, instruction in progress information, incomplete instruction information, and charge status and discharge records of the auxiliary power supply 241.

[0042] The firmware information 2333 may include instructions being processed by the firmware executed by the controller 210 at the time of SPO occurrence, call stack information, and data such as global variables and static variables stored during firmware operation (data stack).

[0043] Log information 2335 may include the command and work history being performed by the data storage device 200 at the time the SPO occurred, error records prior to the SPO event, and firmware error records.

[0044] From another perspective, debug data 233 may be the minimum essential data necessary to recover user data 2311 even if it is lost due to SPO.

[0045] Figure 4 is a diagram showing the configuration of a PLP manager according to one embodiment.

[0046] Referring to Figure 4, the PLP manager 250 according to one embodiment may include a power status confirmation circuit 251, a debug data management circuit 253, a dump circuit 255, and an error detection circuit 257.

[0047] The power status check circuit 251 can detect whether the level of the external power supply voltage (VEXT) supplied to the power supply unit 240 falls below a predetermined reference value. If the level of the external power supply voltage (VEXT) falls below the reference value, the power status check circuit 251 outputs an SPO event signal and can switch the data storage device 200 to PLP mode.

[0048] The power status confirmation circuit 251 can measure the remaining lifespan of the auxiliary power supply 241, for example, the time remaining until the auxiliary power supply 241 is discharged.

[0049] In one embodiment, the debug data management circuit 253 can collect debug data and calculate the size of the debug data in response to an SPO event generation signal. The debug data management circuit 253 can determine the minimum time for backing up the debug data and a first threshold time based on the size of the debug data. The debug data management circuit 253 can provide the determined first threshold time to the error sensing circuit 257.

[0050] In one embodiment, the debug data management circuit 253 can calculate the size of each type of recovered data, namely user data 2311, mapping data 2313, and HK metadata 2315. Based on the size of each type of recovered data, the debug data management circuit 253 can determine a second threshold time for completing the backup of each type of recovered data. The debug data management circuit 253 can provide the error sensing circuit 257 with the second threshold time determined for each type of recovered data.

[0051] The debug data management circuit 253 may further consider the remaining lifespan of the auxiliary power supply 241 in order to determine the first threshold time or the second threshold time.

[0052] The dump circuit 255 can back up recovery data to the non-volatile memory device 220 in response to an SPO event signal. The dump circuit 255 can also back up debug data to the non-volatile memory device 220 in response to an error signal output from the error sensing circuit 257.

[0053] In one embodiment, if the backup of (type-specific) recovery data is not completed when the first threshold time or the second threshold time has elapsed, the error sensing circuit 257 can output an error signal, and the dump circuit 255 can back up debug data in response to the error signal.

[0054] The error sensing circuit 257 can determine whether a predetermined error has occurred in the data storage device 200 after it has been switched to PLP mode, and can output an error signal.

[0055] In one embodiment, the error detection circuit 257 can detect an abnormal operation error (ASSERT) of the controller 210 and output an error signal.

[0056] In one embodiment, after starting PLP mode, the error sensing circuit 257 checks whether the backup of recovery data has been completed within a first threshold time determined by the debug data management circuit 253, and if the backup of recovery data has not been completed, it can output an error signal.

[0057] In one embodiment, after starting PLP mode, the error sensing circuit 257 can check whether the backup of recovery data for each type has been completed within a second threshold time determined by the debug data management circuit 253 for each type of debug data. If the backup of the corresponding type of recovery data is not completed within the second threshold time determined for each type, the error sensing circuit 257 can output an error signal.

[0058] When an error signal is output from the error detection circuit 257, the dump circuit 255 can back up the debug data to the non-volatile memory device 220.

[0059] Figures 5 to 7 are conceptual diagrams illustrating a method for backing up debug data according to one embodiment.

[0060] Referring to Figure 5, when the level of the external power supply voltage (VEXT) drops below a predetermined reference value, the controller 210 detects an SPO event and switches the data storage device 200 to PLP mode, allowing it to back up the recovered data.

[0061] If the controller 210 detects an abnormal operational error (ASSERT) during the backup of recovery data, it can output an error signal. In response to the error signal, the controller 210 can back up debug data to the non-volatile memory device 220.

[0062] Referring to Figure 6, when the level of the external power supply voltage (VEXT) drops below a predetermined reference value, the controller 210 detects an SPO event and switches the data storage device 200 to PLP mode, allowing it to back up the recovered data.

[0063] The controller 210 can check whether the backup of the recovery data is complete if a first threshold time (T_TH) determined based on the size of the debug data, or the size of the debug data and the remaining lifespan of the auxiliary power supply 241, has elapsed during the backup of the recovery data.

[0064] If the backup of recovery data is not completed when the first threshold time (T_TH) has elapsed, the controller 210 can back up debug data in response to the error signal.

[0065] Referring to Figure 7, when the level of the external power supply voltage (VEXT) drops below a predetermined reference value, the controller 210 detects an SPO event and switches the data storage device 200 to PLP mode, allowing it to back up the recovered data.

[0066] The controller 210 can determine a second threshold time for backing up recovery data of each type, depending on the type of recovery data. For example, it can determine a second threshold time (T_TH1) for backing up a first type of recovery data, a second threshold time (T_TH2) for backing up a second type of recovery data, and a second threshold time (T_TH3) for backing up a third type of recovery data.

[0067] If the controller 210 fails to complete the backup of recovery data of a particular type within a second threshold time (T_TH1, T_TH2, T_TH3) determined for each type of recovery data, it can back up debug data to the non-volatile memory device 220 in response to an error signal.

[0068] Figure 7(a) shows the second threshold times (T_TH1, T_TH2, T_TH3) determined for backing up each of the Type A recovery data (TYPE_A), Type B recovery data (TYPE_B), and Type C recovery data (TYPE_C), and (b) shows the time it takes to actually back up each of the Type A recovery data (TYPE_A), Type B recovery data (TYPE_B), and Type C recovery data (TYPE_C).

[0069] Recovery data for Type A (TYPE_A) and Type B (TYPE_B) were backed up within the determined second threshold time (T_TH1, T_TH2), respectively, but recovery data for Type C (TYPE_C) was not backed up within the determined second threshold time (T_TH3).

[0070] If the controller 210 fails to complete the backup of the Type C recovery data (TYPE_C) within the determined second threshold time (T_TH3), and the second threshold time (T_TH3) has elapsed, it can back up the debug data to the non-volatile memory device 220.

[0071] Figure 8 is a flowchart illustrating the operation method of a data storage device according to one embodiment.

[0072] While the data storage device 200 is operating or in standby mode (S101), the controller 210 can determine whether an external power loss (SPO) event occurs, in which the level of the external power supply voltage (VEXT) drops below a predetermined reference value (S103).

[0073] If no SPO event is detected (S103:N), the controller 210 can continue to monitor whether or not an SPO event will occur (S103).

[0074] When the controller 210 detects an SPO event (S103:Y), it can switch the data storage device 200 to PLP mode, collect debug data, and calculate the size of the debug data (S105). The debug data may include hardware information, firmware information, and log information.

[0075] In addition, the controller 210 can measure the remaining lifespan of the auxiliary power supply 241, for example, the lifespan remaining until the auxiliary power supply 241 is discharged.

[0076] The controller 210 can determine the minimum time required to back up the debug data and a first threshold time based on the size of the debug data (S107). In one embodiment, the first threshold time can be determined based on the size of the debug data, or based on the size of the debug data and the lifespan of the auxiliary power supply 241. For example, the first threshold time can be determined by applying the time required to back up the debug data to the time when the lifespan of the auxiliary power supply 241 ends.

[0077] The controller 210, which has switched the data storage device 200 to PLP mode, can back up the recovered data to the non-volatile memory device 220 (S109).

[0078] The controller 210 checks whether the backup of the recovery data is complete (S111), and if the backup of the recovery data is complete (S111:Y), it can shut down the data storage device.

[0079] The controller 210 checks whether the backup of the recovery data has been completed (S111), and if the backup of the recovery data has not been completed (S111:N), it can determine whether an error has been detected (S113).

[0080] In one embodiment, the controller 210 can detect an abnormal operational error (ASSERT) of the controller 210 during the backup of recovery data, thereby detecting that an error has occurred.

[0081] In one embodiment, the controller 210 can detect an error if the backup of recovery data is not completed when a first threshold time has elapsed, which is determined based on the size of the debug data or the size of the debug data and the remaining lifespan of the auxiliary power supply 241.

[0082] In one embodiment, the controller 210 can detect an error if, based on the size of each type of recovery data, the backup of that type of recovery data is not completed when a second threshold time for backing up each type of recovery data has elapsed.

[0083] If the controller 210 detects an error in backing up recovery data (S113:Y), it can back up debug data to the non-volatile memory device 220 (S115).

[0084] If the controller 210 does not detect any errors in backing up the recovery data (S113:N), it can continue backing up the recovery data to the non-volatile memory device 220 (S109).

[0085] This allows debug data to be backed up to the non-volatile memory device 220 even if recovery data is not backed up to the non-volatile memory device 220. Subsequently, when power is restored to the data storage device 200 and it boots up, the data storage device 200 can be driven normally using the backed-up debug data.

[0086] Thus, a person of ordinary skill in the art to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, it must be understood that the examples described above are illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims described below rather than by the detailed description, and it must be understood that all modified or altered forms derived from the meaning and scope of the claims and their equivalent concepts are included within the scope of the present invention. [Explanation of Symbols]

[0087] 10 Electronic Systems 100 External device 200 Data Storage Devices 210 Controller 220 Non-volatile memory devices 230 Buffer memory device 231 Recovered Data 233 Debug data 240 Power Supply 241 Auxiliary power supply 250 PLP Managers 251 Power Status Check Circuit 253 Debug data management circuit 255 Dump Circuit 257 Error detection circuit

Claims

1. Non-volatile memory device and A data storage device including a controller configured to enter a power loss recovery mode due to an external power loss, set a first threshold time associated with the power loss recovery operation, and back up debug data to the non-volatile memory device when the first threshold time has elapsed.

2. The data storage device according to claim 1, wherein the controller is configured to back up recovery data to the non-volatile memory device by entering the power loss recovery mode, and back up the debug data if the backup of the recovery data is not completed when the first threshold time has elapsed.

3. The recovered data consists of multiple types, The data storage device according to claim 2, wherein the controller is configured to determine a second threshold time for each type of recovery data, and when the second threshold time determined for each type has elapsed, if the backup of the corresponding recovery data is not completed, the debug data is backed up.

4. The data storage device according to claim 1, wherein the controller is configured to back up recovery data to the non-volatile memory device when it enters the power loss recovery mode, and to back up the debug data when an operational error of the controller is detected.

5. The data storage device according to claim 1, wherein the controller is configured to determine the threshold time based on the size of the debug data.

6. The data storage device further includes an auxiliary power supply, The data storage device according to claim 1, wherein the controller is configured to determine the first threshold time based on the size of the debug data and the discharge time of the auxiliary power supply.

7. A volatile memory device and Non-volatile memory device and Including the controller, The controller is a data storage device that, upon entering a power loss recovery mode due to external power loss, backs up recovery data stored in a volatile memory device to a non-volatile memory device, and backs up debug data to the non-volatile memory device if a predetermined error occurs during the backup operation of the recovery data.

8. The data storage device according to claim 7, wherein the default error includes an operational error of the controller.

9. The data storage device according to claim 7, wherein the default error includes an error in which the operation to back up the recovery data is not completed within a determined threshold time.

10. The data storage device according to claim 9, wherein the controller is configured to determine the threshold time based on the size of the debug data.

11. The data storage device further includes an auxiliary power supply, The data storage device according to claim 9, wherein the controller is configured to determine the threshold time based on the size of the debug data and the discharge time of the auxiliary power supply.

12. The recovered data consists of multiple types, The data storage device according to claim 7, wherein the default errors are configured to include errors in which the backup of the recovered data for which the second threshold time has elapsed is not completed when a second threshold time determined for each type of recovered data has elapsed.

13. The data storage device according to claim 7, wherein the controller is configured to enter the power loss recovery mode, collect the debug data, calculate the size of the debug data, and back up the recovery data.

14. A method for operating a data storage device including a non-volatile memory device and a controller for controlling the non-volatile memory device, The controller enters a power loss recovery mode due to an external power loss, and the controller sets a first threshold time associated with the power loss recovery operation. A method for operating a data storage device, comprising the step of the controller backing up debug data to the non-volatile memory device when the first threshold time has elapsed.

15. The operation method of the data storage device according to claim 14, wherein by entering the power loss recovery mode, the controller is configured to back up recovery data to the non-volatile memory device, and if the backup of the recovery data is not completed when the first threshold time has elapsed, it backs up the debug data.

16. The recovered data consists of multiple types, The method of operating the data storage device according to claim 15, wherein the controller is configured to determine a second threshold time for each type of recovery data, and when the second threshold time determined for each type has elapsed, if the backup of the corresponding recovery data is not completed, the debug data is backed up.

17. The method for operating a data storage device according to claim 14, wherein by entering the power loss recovery mode, the controller is configured to back up recovery data to the non-volatile memory device, and if an operational error of the controller is detected, the debug data is backed up.

18. The method for operating a data storage device according to claim 14, wherein the controller is configured to determine the threshold time based on the size of the debug data.

19. The data storage device further includes an auxiliary power supply, The method for operating a data storage device according to claim 14, wherein the controller is configured to determine the threshold time based on the size of the debug data and the discharge time of the auxiliary power supply.

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