Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device equipped with highly integrated memory cells and a method for manufacturing the same. [Solution] A method for manufacturing a semiconductor device may include the steps of: forming a first vertical stack in which a plurality of first semiconductor layers are stacked vertically on the upper part of a substrate; etching the first semiconductor layers of the first vertical stack to form first contact holes; epitaxially growing a dummy semiconductor layer from the uppermost first semiconductor layer of the first vertical stack; epitaxially growing a second semiconductor layer on the dummy semiconductor layer to form a second vertical stack; etching the second semiconductor layer of the second vertical stack to form second contact holes; and replacing the first and second semiconductor layers with pads.

Description

Technical Field

[0005]

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including three-dimensional memory cells and a method for manufacturing the same.

Background Art

[0002] In recent years, in order to cope with the increase in capacity and miniaturization of memory devices, three-dimensional memory devices in which a plurality of memory cells are stacked have been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a semiconductor device including highly integrated memory cells and a method for manufacturing the same.

Means for Solving the Problems

[0004] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include forming a first vertical stack in which a plurality of first semiconductor layers are vertically stacked on a substrate, etching the first semiconductor layer of the first vertical stack to form a first contact hole, epitaxially growing a dummy semiconductor layer from the uppermost first semiconductor layer of the first vertical stack, epitaxially growing a second semiconductor layer on the dummy semiconductor layer to form a second vertical stack, etching the second semiconductor layer of the second vertical stack to form a second contact hole, and replacing the first and second semiconductor layers with pads.

[0005] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a first vertical stack in which a first pad sheet is vertically stacked on top of a substrate; etching the first pad sheet of the first vertical stack to form a first contact hole; forming a first sacrificial plug that fills the first contact hole; forming a dummy stack comprising the first sacrificial plug and a dummy pad sheet on the first vertical stack; forming a second vertical stack in which a second pad sheet is vertically stacked on the dummy stack; etching the second pad sheet of the second vertical stack to form a second contact hole; forming a second sacrificial plug that fills the second contact hole; removing the second pad sheet and the first pad sheet to form a pad-shaped recess; forming a pad that fills the pad-shaped recess; and replacing the first and second sacrificial plugs with contact plugs.

[0006] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a first vertical array of first nanosheets and a first vertical array of first pad sheets extending horizontally from the first nanosheets of the first vertical array on the upper part of a substrate; etching the first pad sheets of the first vertical array to form first contact holes; forming a first sacrificial plug that fills the first contact holes; forming a dummy stack comprising a dummy pad sheet on the first sacrificial plug, the first vertical array of first nanosheets, and the first vertical array of first pad sheets; and forming a second vertical array of second nanosheets and a second na on the dummy stack. The process may include the steps of: forming a second vertical array of second pad sheets extending horizontally from a nanosheet; etching the second pad sheets of the second vertical array to form second contact holes; forming second sacrificial plugs to fill the second contact holes; forming a vertical array of horizontal conductive lines surrounding the first and second nanosheets, respectively; removing the second and first pad sheets to form pad-shaped recesses; forming pads connected to the horizontal conductive lines, respectively, while filling the pad-shaped recesses; and replacing the first and second sacrificial plugs with contact plugs.

[0007] A semiconductor device according to an embodiment of the present invention may include a first memory cell array including a vertical array of first memory cells, a second memory cell array including a vertical array of second memory cells, and a dummy memory cell array including a vertical array of dummy memory cells between the first memory cell array and the second memory cell array. [Effects of the Invention]

[0008] This technology utilizes multi-step high aspect ratio etching to form contact holes in the connecting regions of non-stepped structures, thereby reducing the contact hole pitch. This reduces the size of the connecting regions, ensuring mass production of net dies. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic perspective view of a memory cell according to one embodiment. [Figure 2] Figure 1 is a schematic cross-sectional view of a memory cell. [Figure 3] This is a schematic perspective view of a memory cell array (MCA) according to one embodiment. [Figure 4] This is a schematic plan view of a semiconductor device according to one embodiment. [Figure 5] This is a cross-sectional view along line A-A' in Figure 4. [Figure 6] This is a cross-sectional view along line B-B' in Figure 4. [Figure 7] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 11] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 12] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 13] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 14] This figure illustrates an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15]It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 17] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 18] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 19] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 20] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 21] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 22] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 23] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 24] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 26] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 27] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 28] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 29] It is a diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment.

Embodiments for Carrying Out the Invention

[0010] The embodiments described herein will be explained with reference to the cross-sectional view, plan view, and block diagram, which are ideal schematic representations of the present invention. Therefore, the form of the illustrative figures may be modified due to manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in form generated by the manufacturing process. Accordingly, the areas illustrated in the drawings have schematic attributes, and the shapes of the areas illustrated in the drawings are for illustrating specific forms of the element areas and are not intended to limit the scope of the invention.

[0011] The embodiments described later relate to three-dimensional memory cells, which can increase memory cell density and reduce parasitic capacitance by stacking memory cells vertically.

[0012] Figure 1 is a schematic perspective view of a memory cell according to one embodiment. Figure 2 is a schematic cross-sectional view of the memory cell.

[0013] As shown in Figures 1 and 2, the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0014] The first conductive line BL can be vertically oriented along a first direction D1. The first conductive line BL can comprise a bit line. The first conductive line BL can be referred to as a vertical conductive line, a vertically-oriented bit line, a vertically-extended bit line, or a pillar-shaped bit line. The first conductive line BL can contain a conductive material. The first conductive line BL can contain a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL can contain polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first conductive line BL can contain polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL can contain a titanium nitride / tungsten stack (TiN / W) in which titanium nitride and tungsten are stacked in that order.

[0015] The switching element TR has the function of controlling the voltage (or current) supplied to the data storage element CAP during data writing and data reading operations. The switching element TR may comprise a nanosheet (HL), a nanosheet insulating layer GD, and a second conductive line WL. The second conductive line WL may comprise a horizontal conductive line or a horizontal word line, and the nanosheet HL may comprise an active layer. The switching element TR may comprise a transistor, in which case the second conductive line WL may act as a gate electrode. The switching element TR may also be referred to as a nanosheet transistor, cell transistor, access element, or selection element. The second conductive line WL may be referred to as a horizontal gate electrode or a horizontal word line.

[0016] The nanosheet HL can extend along a second direction D2 intersecting a first direction D1. The second conductive line WL can extend along a third direction D3 intersecting the first and second directions D1 and D2. The first direction D1 can be the vertical direction, the second direction D2 can be the first horizontal direction, and the third direction D3 can be the second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second conductive line WL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as the "horizontal layer".

[0017] The nanosheet HL may comprise a channel (CH), a first doped region SR between channel CH and a first conductive line BL, and a second doped region DR between channel CH and a data storage element CAP. The first doped region SR can be electrically connected to the first conductive line BL, and the second doped region DR can be electrically connected to the data storage element CAP. The height of the second doped region DR along the first direction D1 may be greater than the height of the first doped region DR and channel CH along the first direction D1. The length of the second doped region DR along the second direction D2 may be less than the length of channel CH along the second direction D2. The lengths of the first doped region SR, channel CH, and second doped region DR along the third direction D3 may be the same as each other.

[0018] A nanosheet HL may comprise a first sheet region (NS) and a second sheet region (WS) arranged horizontally along a second direction D2. The second sheet region WS may extend from the first sheet region NS. The second sheet region WS may have a thickness that gradually increases along the second direction D2 from the first sheet region NS toward the data storage element CAP between the first sheet region NS and the data storage element CAP. The average vertical height (thickness) of the second sheet region WS along the first direction D1 may be greater than the average vertical height (thickness) of the first sheet region NS. Hereinafter, the first sheet region NS will be abbreviated as "Narrower sheet" and the second sheet region WS will be abbreviated as "Wider sheet".

[0019] The narrow sheet NS can be flat-plate shaped. The wide sheet WS can be fan-shaped, i.e., fan-shaped. The thickness of the wide sheet WS may gradually increase along the second direction D2. The narrow sheet NS can be called a flat plate-shaped sheet, and the wide sheet WS can be called a fan-shaped sheet. The boundary between the narrow sheet NS and the wide sheet WS may have curvature.

[0020] The first doped region SR and channel CH can be located within a narrow sheet NS, and the second doped region DR can be located within a wide sheet WS. The channel CH formed within the narrow sheet NS may be referred to as a narrow channel or a flat channel. One side of the wide sheet WS and one side of the second doped region DR that are in contact with the data storage element CAP may have a flat side shape.

[0021] In other embodiments, a portion of the second doped region DR may extend to be located within the narrow sheet NS. The second doped region DR may include a thicker portion located within the wide sheet WS and a thinner portion located within the narrow sheet NS. The horizontal length of the wide sheet WS along the second direction D2 can be less than the horizontal length of the narrow sheet NS. The narrow sheet NS may be called a long sheet, and the wide sheet WS may be called a short sheet.

[0022] Nanosheet HL can contain semiconductor materials. For example, nanosheet HL can contain polysilicon, single-crystal silicon, germanium, or silicon-germanium. In other embodiments, nanosheet HL can contain oxide semiconductor materials. For example, oxide semiconductor materials can include IGZO (Indium Gallium Zinc Oxide), InSnZnO, ZnSnO, or combinations thereof. In other embodiments, nanosheet HL can contain conductive metal oxides. In other embodiments, nanosheet HL can contain two-dimensional materials, such as MoS2, WS2, or MoSe2.

[0023] If the nanosheet HL is an oxide semiconductor material, the channel CH may also be made of an oxide semiconductor material, and the first and second doped regions SR and DR may be omitted. The nanosheet HL may also be referred to as the active layer or thin-body.

[0024] The first doped region SR and the second doped region DR may be doped with impurities of the same conductivity type. The first doped region SR and the second doped region DR may be doped with N-type conductivity impurities or P-type conductivity impurities. The first doped region SR and the second doped region DR may contain at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be electrically connected to the first conductive line BL, and the second doped region DR may be electrically connected to the data storage element CAP. The first and second doped regions SR and DR may be referred to as the first and second source / drain regions.

[0025] The nanosheet HL can be oriented horizontally along a second direction D2 from a first conductive line BL.

[0026] The second conductive line WL can be a gate all-around structure (GAA). For example, the second conductive line WL can extend along a third direction D3 while surrounding the nanosheet HL. A nanosheet insulating layer GD can be formed between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD can surround a portion of the nanosheet HL, for example, a channel CH of the nanosheet HL. The second conductive line WL can surround the nanosheet HL on the nanosheet insulating layer GD. The second conductive line WL can include a combination of a surrounding body and a surrounding merged portion. The surrounding body can surround the nanosheet HL on the nanosheet insulating layer GD. The surrounding merged portion can be located at both ends of the surrounding body. The surrounding body and the surrounding merged portion can be an integrated structure and be made of the same material. In other embodiments, the surrounding body and the surrounding merged portion may be referred to as the surrounding body and the surrounding merged portion, respectively. The switching element TR may include a GAA transistor.

[0027] The second conductive line WL may include a metal-base material, a semiconductor material, or a combination thereof. The second conductive line WL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductive line WL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less, and the P-type work function material may have a high work function of 4.5 eV or more. The second conductive line WL may include a stack of a low work function material and a high work function material.

[0028] The nanosheet insulating layer GD can be located between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD may be referred to as the "gate dielectric layer" or the "channel-side dielectric layer". The nanosheet insulating layer GD may include silicon oxide, silicon nitride, metal oxides, metal oxides and nitrides, metal silicates, high-k materials, ferroelectric materials, anti-ferroelectric materials, or combinations thereof. The nanosheet insulating layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The nanosheet insulating layer GD can be formed by a combination of deposition of the nanosheet insulating material and thermal oxidation of the nanosheet HL. In other embodiments, the nanosheet insulating layer GD can be deposited onto the nanosheet HL or formed by thermal oxidation of the nanosheet HL.

[0029] The data storage element CAP may include a memory element such as a capacitor. The data storage element CAP may be positioned horizontally along a second direction D2 from the switching element TR. The data storage element CAP may comprise a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally from a nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally along the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN can extend perpendicularly along the first direction D1, and the horizontal outer surface of the first electrode SN can extend horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode SN can be a three-dimensional space. The dielectric layer DE can conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN can be placed in the inner space of the first electrode SN on the dielectric layer DE. A portion of the outer surface of the first electrode SN can be electrically connected to the second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be connected to the common plate (PL). The first electrode SN can be referred to as a storage node.

[0030] The data storage element CAP can have a three-dimensional structure. The first electrode SN has a three-dimensional structure, but the three-dimensional structure of the first electrode SN can be a three-dimensional structure oriented horizontally along a second direction D2. As an example of a three-dimensional structure, the first electrode SN can have a cylinder shape. The cylinder shape of the first electrode SN can include a cylinder inner surface and a cylinder outer surface. A portion of the cylinder outer surface of the first electrode SN can be electrically connected to a second doped region DR of the nanosheet HL. A dielectric layer DE and a second electrode PN can be arranged on the cylinder inner surface and cylinder outer surface of the first electrode SN. In this embodiment, the first electrode SN can have a semi-cylinder shape. In addition, the semi-cylinder shape can refer to a structure in which the second electrode PN partially covers the outer surface of the first electrode SN.

[0031] In other embodiments, the first electrode SN may have a pillar shape or a cylinder shape. The cylinder shape may refer to a structure in which the pillar shape and the cylinder shape are merged.

[0032] The first electrode SN and the second electrode PN may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or combinations thereof. The second electrode PN may also include combinations of metal-based materials and silicon-based materials. For example, the second electrode PN can be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be a gap fill material filling the inside of the first electrode SN, titanium nitride (TiN) can play the role of the second electrode PN of the data storage element CAP, and tungsten nitride can be a low-resistance material. In other embodiments, the second electrode PN can include a stack of titanium nitride / tungsten / polysilicon (TiN / W / Poly-Si).

[0033] The dielectric layer DE may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer DE may include silicon oxide, silicon nitride, high dielectric constant materials, perovskite materials, or combinations thereof. High dielectric constant materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). In other embodiments, the dielectric layer DE may consist of a composite layer comprising two or more of the aforementioned high dielectric constant materials.

[0034] The dielectric layer DE can be formed from a zirconium-based oxide (Zr-base oxide). The dielectric layer DE can be a stack structure containing zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can be a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and ZAZ stack can be referred to as a zirconium oxide-base layer (ZrO2-base layer). In other embodiments, the dielectric layer DE can be formed from a hafnium-based oxide (Hf-base oxide). The dielectric layer DE can be a stack structure containing hafnium oxide (HfO2). The dielectric layer DE may include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. An HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). An HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. HA stacks and HAH stacks may be referred to as HfO2-base layers. In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, aluminum oxide (Al2O3) may have a larger band gap energy than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can contain stacks of high dielectric constant materials and high band gap materials, which have a band gap energy greater than that of high dielectric constant materials.The dielectric layer DE may also contain silicon oxide (SiO2) as another high-bandgap material in addition to aluminum oxide (Al2O3). Leakage current can be suppressed by including a high-bandgap material in the dielectric layer DE. The high-bandgap material can be thinner than the high-dielectric-constant material. In other embodiments, the dielectric layer DE may include a stacked structure in which high-dielectric-constant materials and high-bandgap materials are alternately layered. For example, the dielectric layer DE is a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, HAHAH ((HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack, HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stack, ZHZAZHZ (ZrO2 / The stacks may include HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2), HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2) stacks, or AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stacks. In such stack structures, the aluminum oxide (Al2O3) can be thinner than the zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0035] In other embodiments, the dielectric layer DE may include a high dielectric constant material and a high bandgap material, but may also include a laminated structure in which multiple high dielectric constant materials and multiple high bandgap materials are stacked, or a mixed structure in which the high dielectric constant material and the high bandgap material are intermixed.

[0036] In other embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0037] In other embodiments, the dielectric layer DE may include a combination of a high dielectric material and a ferroelectric material, a combination of a high dielectric material and an antiferroelectric material, or a combination of a high dielectric material or a ferroelectric material and an antiferroelectric material.

[0038] In other embodiments, an interface control layer for leakage current improvement may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0039] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a MIM (Metal-Insulator-Metal) capacitor. The data storage element CAP can also be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase conversion material, an MTJ (Magnetic Tunnel Junction), or a variable resistor material.

[0040] The memory cell MC may further comprise a first contact node BLC and a second contact node SNC. The first contact node BLC may be located between the first conductive line BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. The first contact node BLC may also include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be located between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. The second contact node SNC may also include doped silicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 can be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 can be greater than the height of the channel CH along the first direction D1.

[0041] In other embodiments, the second contact node SNC can be selectively grown from a wide sheet WS of a nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth SEG. For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The second contact node SNC can be a doped silicon epitaxial layer.

[0042] In other embodiments, the first contact node BLC can also be selectively grown from a narrow sheet WS of a nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth SEG. For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The first contact node BLC can be a doped silicon epitaxial layer.

[0043] The first contact node BLC can be a narrower sheet-side contact node, and the second contact node SNC can be a wider sheet-side contact node.

[0044] The nanosheet HL may comprise a first edge and a second edge. The first edge may represent a portion of a first doped region SR electrically connected to a first conductive line BL, and the second edge may represent a portion of a second doped region DR electrically connected to a first electrode SN of the data storage element CAP.

[0045] The memory cell MC may further comprise an ohmic contact layer BLO between a first contact node BLC and a first conductive line BL. The ohmic contact layer BLO may include a metal silicide. In other embodiments, it may further comprise an ohmic contact layer formed between a second contact node SNC and a first electrode SN of a data storage element CAP. The first conductive line BL, the ohmic contact layer BLO, the first contact node BLC, and the first doped region SR can be electrically interconnected. The second doped region DR, the second contact node SNC, and the first electrode SN of the data storage element CAP can be electrically interconnected.

[0046] The memory cell MC may further comprise a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be positioned between a second conductive line WL and a second doped region DR. The second spacer SP2 may be positioned between a first conductive line BL and a second conductive line WL. The first spacer SP1 and the second spacer SP2 may extend along a third direction D3 while surrounding the nanosheet HL. That is, the first and second spacers SP1 and SP2 may surround the nanosheet HL while being located on both side walls of the second conductive line WL.

[0047] The first spacer SP1 and the second spacer SP2 can be a double liner structure or a single liner structure. For example, the first spacer SP1 can be a single liner structure, and the second spacer SP2 can be a double liner structure. The second spacer SP2 can include a stack of the first liner L1 and the second liner L2. The first and second spacers SP1 and SP2 can include an insulating material. The first and second spacers SP1 and SP2 can include silicon oxide, silicon nitride, or a combination thereof. The first liner L1 of the second spacer SP2 can be silicon nitride, and the second liner L2 can be silicon oxide. The second liner L2 can partially fill the inner space of the first liner L1.

[0048] The first conductive line BL may comprise a plurality of horizontal extensions BLE1, BLE2, BLE3. The horizontal extensions BLE1, BLE2, BLE may extend along a second direction D2. The horizontal extensions BLE1, BLE2, BLE may comprise an inner horizontal extension BLE2 and outer horizontal extensions BLE1, BLE3. The inner horizontal extension BLE2 of the first conductive line BL may extend to be located within the gap between vertically adjacent first liners L1, thereby enabling the inner horizontal extension BLE2 of the first conductive line BL to be electrically connected to the ohmic contact layer BLO.

[0049] The outer horizontal extensions BLE1 and BLE3 of the first conductive line BL can extend so as to be located within one side surface of the second spacer SP2, thereby allowing them to contact the second liner L2 of the second spacer SP2. In other embodiments, the outer horizontal extensions BLE1 and BLE3 of the first conductive line BL can be omitted.

[0050] Figure 3 is a schematic perspective view of a semiconductor device according to one embodiment. Figure 4 is a schematic plan view of a semiconductor device according to one embodiment. Figure 5 is a cross-sectional view along line A-A' in Figure 4. Figure 6 is a cross-sectional view along line B-B' in Figure 4.

[0051] As shown in Figure 3, the semiconductor device may include a memory cell array (MCA). The memory cell array (MCA) may include a plurality of memory cells (MCs) stacked vertically along a first direction (D1). The memory cell array (MCA) may include a plurality of memory cells (MCs) arranged horizontally along a second direction (D2). The memory cell array (MCA) may include a plurality of memory cells (MCs) arranged horizontally along a third direction (D3).

[0052] An individual memory cell MC may comprise a first conductive line BL, a switching element TR, and a data storage element CAP, wherein the switching element TR may comprise a second conductive line WL, a nanosheet insulating layer GD, and a nanosheet HL. The memory cell MC may further comprise a first contact node BLC, an ohmic contact layer BLO, and a second contact node SNC. The memory cell MC may be identical to the memory cell MC in Figures 1 and 2.

[0053] A memory cell array (MCA) can comprise a column array (AR1) of memory cells (MCs) and a row array (AR2) of memory cells (MCs). The column array (AR1) can comprise a plurality of memory cells (MCs) stacked vertically along a first direction (D1). The memory cells (MCs) in the column array (AR1) can share a first conductive line (BL). The row array (AR2) can comprise a plurality of memory cells (MCs) arranged horizontally along a third direction (D3). The memory cells (MCs) in the row array (AR2) can share a second conductive line (WL). The second conductive line (WL) of the memory cell array (MCA) can have a structure in which a plurality of surrounding bodies and a plurality of surrounding merge portions are mutually merged. The surrounding merge portions can be located in the gaps between nanosheets (HL) on which a nanosheet insulating layer (GD) is formed.

[0054] The column array AR1 may include a vertical arrangement of nanosheets HL along a first direction D1, a first conductive line BL commonly connected to the vertically arranged nanosheets HL, and a second conductive line WL surrounding each of the vertically arranged nanosheets HL.

[0055] The low array AR2 may comprise a horizontal arrangement of nanosheets HL along a third direction D3, a first conductive line BL connected to each of the horizontally arranged nanosheets HL, and a second conductive line WL surrounding the horizontally arranged nanosheets HL.

[0056] The first direction D1 can be vertical, and the third direction D3 can be horizontal.

[0057] The semiconductor device 100 shown in Figures 4 to 6 can be similar to the memory cell array MCA shown in Figure 3. Detailed explanations of overlapping components are omitted below.

[0058] As shown in Figures 3, 4, 5, and 6, the semiconductor device 100 may include a memory cell array MCA, which may include a cell array region R1 and a linking region R2. The cell array region R1 may be the region where memory cells MC are formed, and the linking region R2 may be the region for supplying electrical signals to a portion of the memory cell MC. The linking region R2 may be called a pad region. The memory cell array MCA may include a lower memory cell array MCA1, an upper memory cell array MCA2, and a dummy memory cell array DMCA. The dummy memory cell array DMCA may be located between the lower memory cell array MCA1 and the upper memory cell array MCA2. The lower memory cell array MCA1, the upper memory cell array MCA2, and the dummy memory cell array DMCA may each include a cell array region R1 and a linking region R2.

[0059] The connecting region R2 may comprise a multi-layer pad WLP. Each pad WLP may be electrically connected to a contact plug CT. The contact plug CT may penetrate all of the pad WLPs. Contact spacers CTS may be formed on the outer wall of the contact plug CT. An inter-pad insulating layer IL4 may be located between the pad WLPs. The connecting region R2 may have a stair-less structure.

[0060] A memory cell array (MCA) may comprise multiple memory cells (MCs) stacked vertically along a first direction (D1). Each memory cell (MC) may have the same configuration as the memory cell (MC) shown in Figures 1 and 2. A memory cell array (MCA) may comprise multiple memory cells (MCs) arranged horizontally along a second direction (D2). A memory cell array (MCA) may comprise multiple memory cells (MCs) arranged horizontally along a third direction (D3). A memory cell array (MCA) may comprise multiple first conductive lines (BL). The switching elements (TR) of the memory cells (MCs) may be nanosheet transistors.

[0061] The first conductive line BL can extend perpendicularly along the first direction D1, the nanosheet HL can extend along the second direction D2, and the second conductive line WL can extend horizontally along the third direction D3.

[0062] A first inter-cell dielectric layer (IL1) may be placed between adjacent data storage elements CAP along a third direction D3. A second inter-cell dielectric layer (IL2) may be placed between second conductive lines WL stacked perpendicularly along the first direction D1. A third inter-cell dielectric layer (IL3) may be placed between the first electrodes SN of data storage elements CAP stacked perpendicularly along the first direction D1. The first to third inter-cell dielectric layers (IL1, IL2, IL3) may include silicon oxide, silicon oxide-bonded carbide (SiCO), silicon nitride, or a combination thereof. The first inter-cell dielectric layer (IL1) may be referred to as a device isolation layer.

[0063] The memory cell MC may further comprise a first contact node BLC and a second contact node SNC. The first contact node BLC may be located between the first conductive line BLA, BLB and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. The first contact node BLC may also include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be located between the nanosheet HL and the first electrode SN. The second contact node SNC may also include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. The second contact node SNC may also include doped polysilicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 can be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 can be greater than the height of the channel CH along the first direction D1.

[0064] The memory cell MC may further comprise an ohmic contact layer (see "BLO" in Figures 1 and 2) between the first contact node BLC and the first conductive line BL. The ohmic contact layer BLO may include a metal silicide.

[0065] The memory cell MC may further comprise a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be positioned between a second conductive line WL and a second doped region DR. The second spacer SP2 may be positioned between a first conductive line BL and a second conductive line WL. The first and second spacers SP1 and SP2 may include silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may cover one side of the second intercell insulating layer IL2. The first spacer SP1 may be cup-shaped.

[0066] The memory cell array MCA may comprise a plurality of second conductive lines WL stacked vertically along a first direction D1. The memory cell array MCA may comprise a plurality of nanosheets HL stacked vertically along the first direction D1. The memory cell array MCA may comprise a plurality of data storage elements CAP stacked vertically along the first direction D1. The memory cell array MCA may comprise a plurality of first conductive lines BL spaced apart along a third direction D3.

[0067] The multi-layered second conductive line WL may have extensions WLE, and the edges WP of the pads WLP may be located in the inner space (or inner surface) of the extensions WLE. Each extension WLE of the second conductive line WL can be electrically connected to a pad WLP. The extensions WLE of the second conductive line WL and the edges WP of the pads WLP can be in contact with a third spacer SP3. The extensions WLE of the second conductive line WL may be concave, and the edges WP of the pads WLP may be convex. The vertical stack of pads WLP may be stairless.

[0068] A pad WLP can be in contact with a pad supporter layer WSL. The pad supporter layer WSL can be located between adjacent pad WLPs along a second direction D2. The third spacer SP3 can be located between the second inter-cell insulating layer IL2 and the inter-pad insulating layer IL4. The first spacer SP1 and the third spacer SP3 can be made of the same material.

[0069] The memory cell array MCA may include a plurality of first and second bottom protection layers BT1 and BT2. The first bottom protection layer BT1 can prevent electrical contact between the bottom surface of the first conductive line BL and the lower structure LS. The second bottom protection layer BT2 can prevent electrical contact between the data storage element CAP and the lower structure LS.

[0070] A vertical separation layer BLF may be located between the first conductive lines BL. The vertical separation layer BLF may contain an insulating material.

[0071] Nanosheets HL of switching elements TR arranged horizontally along a third direction D3 can share one second conductive line WL. Nanosheets HL of switching elements TR arranged horizontally along a third direction D3 can be connected to different first conductive lines BL. Switching elements TR stacked along a first direction D1 can share one first conductive line BL. Switching elements TR arranged horizontally along a third direction D3 can share one second conductive line WL.

[0072] A pair of second conductive lines WL, spaced horizontally along the second direction D2, can share one pad WLP.

[0073] The second electrode PN of the data storage element CAP can be connected to the common plate (PL).

[0074] As described above, the lower memory cell array MCA1, the upper memory cell array MCA2, and the dummy memory cell array DMCA can each comprise multiple memory cells MC and multiple pads WLP. The lower memory cell array MCA1, the upper memory cell array MCA2, and the dummy memory cell array DMCA can each comprise memory cells MC of the same structure. The lower memory cell array MCA1, the upper memory cell array MCA2, and the dummy memory cell array DMCA can each comprise pads WLP of the same structure. The vertical stack of pads WLP can be a stair-less structure.

[0075] Figures 7 to 29 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. Figures 7 to 29 illustrate a manufacturing method along line A-A' in Figure 4.

[0076] As shown in Figure 7, a first mold stack SB1 can be formed on the substrate 11. The first mold stack SB1 may include an alternating stack of a first mold layer 12 and a second mold layer 13. The first mold layer 12 and the second mold layer 13 may be different semiconductor materials. The first mold layer 12 may include silicon germanium or single-crystal silicon germanium. The second mold layer 13 may include single-crystal silicon. The first mold layer 12 and the second mold layer 13 can be formed by epitaxial growth. The lowest level first mold layer 12 may act as a seed layer during the epitaxial growth process. The first mold layer 12 may be thinner than the second mold layer 13. The first mold layer 12 may include a first epitaxially grown layer, and the second mold layer 13 may include a second epitaxially grown layer.

[0077] In this embodiment, the first mold stack SB1 may consist of alternating layers of single-crystal silicon-germanium layers and single-crystal silicon layers. For example, the first mold layer 12 may be a single-crystal silicon-germanium layer, and the second mold layer 13 may be a single-crystal silicon layer. A stack of single-crystal silicon-germanium layers / single-crystal silicon layers ("SiGe / Si stack") may be stacked several times. The first mold layer 12 may be referred to as a "sacrificial layer," and the second mold layer 13 may be referred to as a nanosheet target layer or a recess target layer.

[0078] The first mold stack SB1 can be referred to as the first vertical stack. The first mold stack SB1 can alternately form a plurality of sacrificial layers and a plurality of nanosheet target layers. The sacrificial layers can be single-crystal silicon germanium layers, and the nanosheet target layers can be single-crystal silicon layers.

[0079] In the first mold stack SB1, the thickness ratio of the first mold layer 12 to the second mold layer 13 can be varied. For example, the thickness of the first mold layer 12 can be 5 to 20 nm, and the thickness of the second mold layer 13 can be 50 to 80 nm. The number of layers of the first mold layer 12 and the second mold layer 13 in the first mold stack SB1 can be varied. In another embodiment, a triple stack comprising the first mold layer 12 / second mold layer 13 / first mold layer 12 can be defined at the bottom and / or top of the first mold stack SB1. The second mold layer 13 of the triple stack can be thinner than the second mold layer 13 of the first mold stack SB1.

[0080] In this embodiment, the uppermost layer of the first mold stack SB1 can be a thin second mold layer 13.

[0081] The first mold stack SB1 may include a cell array region R1 and a linking region R2.

[0082] As shown in Figure 8, a portion of the first mold stack SB1 can be etched into the connecting region R2 to form the first inter-pad separation trench 14.

[0083] Next, after removing the first mold layer 12 from the connecting region R2 via the first inter-pad separation trench 14, a partial recess step can be performed on the second mold layer 13. The partial recessing of the second mold layer 13 can form the first pad sheet 15. The first pad sheet 15 of the connecting region R2 can be thinner than the second mold layer 13 of the cell array region R1. The first pad sheet 15 of the connecting region R2 and the second mold layer 13 of the cell array region R1 can be made of the same material. An inter-pad sheet recess 15R can be defined between the first pad sheets 15.

[0084] As shown in Figure 9, a first inter-pad insulating layer 16 can be formed that fills the inter-pad sheet recess 15R between the first pad sheets 15. The first inter-pad insulating layer 16 may contain silicon oxide.

[0085] As shown in Figure 10, a first pad separation layer 17 can be formed filling the first pad separation trench 14. The first pad separation layer 17 may contain an insulating material. The first pad separation layer 17 may contain silicon oxide, silicon nitride, or a combination thereof.

[0086] Next, first contact holes 18' can be formed that penetrate the stack of the first inter-pad insulating layer 16 and the first pad sheet 15. The first contact holes 18' can have different vertical depths from each other. The first contact holes 18' can expose the first pad sheet 15 corresponding to each level. For example, the deepest first contact hole 18' can expose the top surface of the lowest level of the first pad sheet 15 and penetrate the first pad sheets 15 at other levels.

[0087] As described above, the second mold layer 13 in the connecting region R2 can be replaced with the first pad sheet 15. Furthermore, a first vertical stack can be formed in the cell array region R1 and the connecting region R2, each including a vertical stack of the second mold layer 13 and a vertical stack of the first pad sheet 15.

[0088] As shown in Figure 11, a first sacrificial plug 18 can be formed to fill the first contact hole 18'. The first sacrificial plug 18 may contain an insulating material. In the connecting region R2, the first sacrificial plug 18 may partially expose the top-level first pad sheet 15. In the cell array region R1, the entire surface of the top-level second mold layer 13 may be exposed.

[0089] As shown in Figure 12, multiple first dummy mold layers 19 can be formed on the top-level second mold layer 13 and the top-level first pad sheet 15. The first dummy mold layers 19 can be selectively grown from the exposed surface of the top-level first pad sheet 15. The first dummy mold layers 19 formed on the top-level second mold layer 13 can be flat plate in shape. The first dummy mold layers 19 formed on the top-level first pad sheet 15 can be protruding in shape. Gaps can be defined between the first dummy mold layers 19 formed on the top-level first pad sheet 15.

[0090] The first dummy mold layer 19 can be made of the same material as the second mold layer 13. The first dummy mold layer 19 may contain single-crystal silicon. The first dummy mold layer 19 can be formed by selective epitaxial growth. In this embodiment, the first dummy mold layer 19 may comprise a single-crystal silicon layer. The first dummy mold layer 19 may be referred to as a dummy nanosheet target layer. The first dummy mold layer 19 can be thicker than the top-level second mold layer 13 and the top-level first pad sheet 15.

[0091] As shown in Figure 13, a second dummy mold layer 20 can be formed on the first dummy mold layer 19. The second dummy mold layer 20 can be epitaxially grown on the first dummy mold layer 19. The second dummy mold layer 20 may contain single-crystal silicon germanium. The second dummy mold layer 20 may be referred to as a dummy sacrificial layer. The second dummy mold layer 20 and the first mold layer 12 can be made of the same material. After the second dummy mold layer 20 is formed, a gap 20G may be formed between the first dummy mold layers 19.

[0092] As shown in Figure 14, an additional dummy mold layer 21 can be formed on the second dummy mold layer 20. The additional dummy mold layer 21 can be made of the same material as the first dummy mold layer 19. The additional dummy mold layer 21 can include single-crystal silicon. The additional dummy mold layer 21 can be formed by selective epitaxial growth. In this embodiment, the additional dummy mold layer 21 can comprise a single-crystal silicon layer. A portion of the additional dummy mold layer 21 can fill the gap between the first dummy mold layers 19 (20G in Figure 13) on the second dummy mold layer 20.

[0093] As shown in Figure 15, a second mold stack SB2 may be formed on the additional dummy mold layer 21. The stack of the first dummy mold layer 19, the second dummy mold layer 20, and the additional dummy mold layer 21 can become a dummy stack DSB. A dummy stack DSB may be formed on the first mold stack SB1, and a second mold stack SB2 may be formed on the dummy stack DSB.

[0094] In other embodiments, the number of layers of the first dummy mold layer 19, the second dummy mold layer 20, and the additional dummy mold layer 21 can be varied to form a dummy stack DSB.

[0095] The second mold stack SB2 may include an alternating stack of the first mold layer 22 and the second mold layer 23. The first mold layer 22 and the second mold layer 23 may be different semiconductor materials. The first mold layer 22 may include silicon germanium or single-crystal silicon germanium. The second mold layer 23 may include single-crystal silicon. The first mold layer 22 and the second mold layer 23 may be formed by epitaxial growth. The first mold layer 22 may be thinner than the second mold layer 23. The first mold layer 22 may comprise a first epitaxially grown layer, and the second mold layer 23 may comprise a second epitaxially grown layer.

[0096] In this embodiment, the second mold stack SB2 may consist of alternating layers of single-crystal silicon-germanium layers and single-crystal silicon layers. For example, the first mold layer 22 may be a single-crystal silicon-germanium layer, and the second mold layer 23 may be a single-crystal silicon layer. A stack of single-crystal silicon-germanium layers / single-crystal silicon layers ("SiGe / Si stack") may be stacked several times. The first mold layer 22 may be referred to as a "sacrificial layer," and the second mold layer 23 may be referred to as a nanosheet target layer or a recess target layer.

[0097] The second mold stack SB2 can be referred to as the second vertical stack. The second mold stack SB2 can alternately form multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layers can be single-crystal silicon germanium layers, and the nanosheet target layers can be single-crystal silicon layers.

[0098] In the second mold stack SB2, the thickness ratio between the first mold layer 22 and the second mold layer 23 can be varied. For example, the thickness of the first mold layer 22 can be 5 to 20 nm, and the thickness of the second mold layer 23 can be 50 to 80 nm. In the mold stack SB, the number of layers between the first mold layer 22 and the second mold layer 23 can be varied.

[0099] In this embodiment, the uppermost layer of the second mold stack SB2 can be a thin first mold layer 22.

[0100] The second mold stack SB2 may include a cell array region R1 and a linking region R2.

[0101] The first mold layer 12 of the first mold stack SB1 and the first mold layer 22 of the second mold stack SB2 can be made of the same material. The first mold layer 12 of the first mold stack SB1 and the first mold layer 22 of the second mold stack SB2 can have the same thickness. The second mold layer 13 of the first mold stack SB1 and the second mold layer 23 of the second mold stack SB2 can be made of the same material. The second mold layer 13 of the first mold stack SB1 and the second mold layer 23 of the second mold stack SB2 can have the same thickness. The second mold layers 13 and 23 of the first and second mold stacks SB1 and SB2 can be called semiconductor layers, and the first, second and additional dummy mold layers 19, 20, and 21 of the dummy stack DSB can be called dummy semiconductor layers.

[0102] The vertical heights of the first and second mold stacks SB1 and SB2 can be greater than the vertical height of the dummy stack DSB.

[0103] The dummy stack DSB can be the region where dummy memory cells are formed, and the first and second mold stacks SB1 and SB2 can be the regions where real memory cells are formed.

[0104] For example, when forming a 100-stage memory cell, a first mold stack SB1 can be formed with 50 stages, and a second mold stack SB2 can be formed with 50 stages. After forming the 50-stage first mold stack SB1, epitaxial growth can be performed on the upper part of the second mold layer 13 to form a dummy stack DSB, and after forming the dummy stack DSB, a 50-stage second mold stack SB2 can be formed. The first dummy mold layer 19, the second dummy mold layer 20, and the additional dummy mold layer 21 of the dummy stack DSB are abnormally grown epitaxial layers, and these abnormal epitaxial layers can be dummy-processed.

[0105] As shown in Figure 16, the second mold stack SB2 and dummy stack DSB can be etched in the connecting region R2 to form a second inter-pad separation trench 24. The second inter-pad separation trench 24 can expose the upper surface of the first pad separation layer 17.

[0106] Next, after removing the first mold layer 22 of the second mold stack SB2 and the dummy first mold layer 20 of the dummy stack DSB, a partial recess process can be performed on the second mold layer 23, the additional dummy mold layer 21, and the first dummy mold layer 19. The partial recessing of the second mold layer 23 may form the second pad sheet 25. The second pad sheet 25 of the connecting region R2 may be thinner than the second mold layer 23 of the cell array region R1. The second pad sheet 25 of the connecting region R2 and the second mold layer 23 of the cell array region R1 may be made of the same material. An inter-pad sheet recess 25R may be defined between the second pad sheets 25. A thin additional dummy mold layer 21 may remain between the first dummy mold layers 19.

[0107] As shown in Figure 17, a second inter-pad insulating layer 26 can be formed to fill the inter-pad sheet recess (25R in Figure 16) between the second pad sheets 25. The second inter-pad insulating layer 26 may contain silicon oxide.

[0108] As described above, the second mold layer 23 can be replaced with a second pad sheet 25. Furthermore, a second vertical stack can be formed in the cell array region R1 and the connecting region R2, each including a vertical stack of the second mold layer 23 and a vertical stack of the second pad sheet 25, respectively.

[0109] As shown in Figure 18, a second pad separation layer 27 can be formed filling the second pad separation trench 24. The second pad separation layer 27 may include silicon oxide, silicon nitride, or a combination thereof.

[0110] Next, second contact holes 28 may be formed that penetrate the stack of the second inter-pad insulating layer 26 and the second pad sheet 25. The second contact holes 28 may have the same vertical depth as each other. The second contact holes 28 may penetrate a portion of the dummy second mold layer 19 of the dummy stack DSB in order to expose the upper surface of the first sacrificial plug 18.

[0111] As shown in Figure 19, a second sacrificial plug 29 can be formed to fill the second contact hole 28. The second sacrificial plug 29 may contain an insulating material. The first sacrificial plug 19 and the second sacrificial plug 29 can overlap perpendicularly in the connecting region R2. The first sacrificial plug 19 and the second sacrificial plug 29 can be made of the same material.

[0112] As shown in Figure 20, the second mold stack SB2, the dummy stack DSB, and a portion of the first mold stack SB1 can be etched in the cell array region R1. This can form multiple linear openings 30. When viewed from a top view, the linear openings 30 can be line-shaped openings. The linear openings 30 can extend along a direction perpendicular to the surface of the substrate 11. The cross-section of the linear openings 30 can be rectangular.

[0113] The first mold layer 12 of the first mold stack SB1 and the first mold layer 22 of the second mold stack SB2 can be selectively recessed through the linear opening 30. To selectively recess the first mold layers 12 and 22, the difference in etching selectivity between the first mold layers 12 and 22 and the second mold layers 13 and 23 can be utilized. The first mold layers 12 and 22 can be removed using wet etching or dry etching. For example, if the first mold layers 12 and 22 comprise silicon germanium layers and the second mold layers 13 and 23 comprise single-crystal silicon layers, the silicon germanium layers can be etched using an etching solution or etching gas that has a selectivity ratio with respect to the single-crystal silicon layers.

[0114] As shown in Figure 21, the second mold layers 13, 23, the first dummy mold layer 19, and the additional dummy mold layer 21 can be recessed through the linear opening 30. Nanosheets 13P, 19P, 21P, and 23P can be formed by recessing the second mold layers 13, 23, the first dummy mold layer 19, and the additional dummy mold layer 21. Wet etching or dry etching can be used to recess the second mold layers 13, 23, the first dummy mold layer 19, and the additional dummy mold layer 21. Nanosheets 13P, 19P, 21P, and 23P may include dummy nanosheets 19P and 21P.

[0115] The recessing process for forming nanosheets 13P, 19P, 21P, and 23P can be referred to as a thinning process or trimming process of the second mold layers 13 and 23. To form nanosheets 13P and 23P, the top, bottom, and sides of the second mold layers 13 and 23 may be recessed. For example, HSC1 (Hot SC-1) can be used for the recessing process to form nanosheets 13P and 23P. HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a 1:4:20 ratio. The second mold layers 13 and 23 can be selectively etched using such HSC1. The first dummy mold layer 19 and the additional dummy mold layer 21 can also be reset during the resetting of the second mold layers 13 and 23 in order to form dummy nanosheets 19P and 21P.

[0116] Nanosheets 13P and 23P can be formed by the partial recess process on the second mold layers 13 and 23 as described above, and inter-nanosheet recesses (31) can be formed between vertically positioned nanosheets 13P and 23P. The nanosheets 13P and 23P can include horizontal and vertical arrangements. Nanosheets 13P and 23P in horizontal arrangements may have horizontal gaps between horizontally separated nanosheets 13P and 23P. Nanosheets 13P and 23P in vertical arrangements may have vertical gaps between vertically separated nanosheets 13P and 23P.

[0117] A nanosheet all-open recess (32A) can be formed in the cell array region R1, opening up all horizontally and vertically arranged nanosheets 13P, 19P, 21P, and 23P. The nanosheet all-open recess 32A may comprise multiple surrounding recesses 32. The surrounding recesses 32 can expose the horizontally arranged nanosheets 13P, 19P, 21P, and 23P. For example, any one surrounding recess 32 can surround all surfaces of nanosheets 13P, 19P, 21P, and 23P at the same horizontal level.

[0118] As shown in Figure 22, a nanosheet insulating layer 33 can be formed on the exposed portions of the nanosheets 13P, 19P, 21P, and 23P. The nanosheet insulating layer 33 may be referred to as a gate insulating layer. The nanosheet insulating layer 33 can be formed by oxidizing the surface of the nanosheets 13P, 19P, 21P, and 23P. In other embodiments, the nanosheet insulating layer 33 can be formed by a silicon oxide deposition process and an oxidation process. The nanosheet insulating layer 33 may include silicon oxide, silicon nitride, metal oxides, metal oxide nitrides, metal silicates, high-k materials, ferroelectric materials, anti-ferroelectric materials, or combinations thereof. The nanosheet insulating layer 33 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or combinations thereof. The nanosheet insulating layer 33 can be formed on all surfaces of the nanosheets 13P, 19P, 21P, and 23P.

[0119] A first spacer layer 34 can be formed on the nanosheet insulating layer 33. The first spacer layer 34 may contain silicon nitride. The first spacer layer 34 can surround and cover the nanosheets 13P, 19P, 21P, and 23P on the nanosheet insulating layer 33. The first spacer layer 34 may be thicker than the nanosheet insulating layer 33.

[0120] An inter-cell insulating layer 35 can be formed on the first spacer layer 34. The inter-cell insulating layer 35 may contain silicon dioxide.

[0121] The nanosheet insulating layer 33 and the first spacer layer 34 can also be formed on the surface of the substrate 11.

[0122] As shown in Figure 23, the first spacer layer 34 can be selectively recessed. The first spacer layer remaining in the connecting region R2 can become a boundary spacer 34S. By forming the boundary spacer 34S, linear surrounding recesses 36 can be formed on the nanosheet insulating layer 33 that surround the nanosheets 13P, 19P, 21P, and 23P. Intercellular insulating layers 35 can be located between the vertically arranged linear surrounding recesses 36. The intercellular insulating layer 35 can correspond to the second intercellular insulating layer IL2 in Figures 5 and 6. The boundary spacer 34S can correspond to the third spacer SP3 in Figure 5.

[0123] As shown in Figure 24, horizontal conductive lines 37 can be formed that fill the linear surrounding recess 36. The horizontal conductive lines 37 can extend horizontally. The step of forming the horizontal conductive lines 37 may include the step of depositing a conductive material that fills the linear surrounding recess 36 onto the nanosheet insulating layer 33 and a horizontal etch back step of the conductive material. Each of the horizontal conductive lines 37 can simultaneously surround nanosheets 13P, 19P, 21P, and 23P at the same level. The horizontal conductive lines 37 may include metal-base materials, semiconductor materials, or combinations thereof. The horizontal conductive lines 37 may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or combinations thereof. For example, the horizontal conductive lines 37 may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The horizontal conductive lines 37 may include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function lower than 4.5 eV, while P-type work function materials can have a high work function higher than 4.5 eV. Intercellular insulating layers 35 may be located between multiple horizontal conductive lines 37. The horizontal conductive lines 37 surrounding the nanosheets 13P, 19P, 21P, and 23P can be referred to as gate-all-around GAA electrodes. The nanosheets 13P, 19P, 21P, and 23P can be referred to as nanosheet channels, nanowires, or nanowire channels.

[0124] Some of the horizontal conductive lines 37 can be located in the dummy cell array region DMCA. That is, some of the horizontal conductive lines 37 can become dummy horizontal conductive lines 37D surrounding the dummy nanosheets 19P and 21P.

[0125] The horizontal conductive line 37 can correspond to the second conductive line WL as shown in Figures 3 and 4.

[0126] The horizontal conductive line 37 may include a concave extension 37E.

[0127] As shown in Figure 25, the first and second pad separation layers 17, 27 can be removed. This can form a merged trench 38. The merged trench 38 can be a single integrated structure that penetrates the first pad sheet 15, the second pad sheet 25, and the first and second inter-pad insulating layers 16, 26.

[0128] As shown in Figure 26, the first pad sheet 15 and the second pad sheet 25 can be selectively removed through the merged trench 38. Then, a portion of the nanosheet insulating layer 25 can be cut. This may expose the edge portion 29E of the horizontal conductive line 29 and the first spacer 26. This may form a pad-shaped recess 39. The pad-shaped recess 39 may have an edge portion 39A, and the edge portion 39A of the pad-shaped recess 39 may expose the extension portion 37E of the horizontal conductive line 37.

[0129] As shown in Figure 27, a pad 40 can be formed to fill the pad-shaped recess 39. The pad 40 may have a pad edge portion 40A, the pad edge portion 40A of the pad 40 may be in contact with the extended portion 37E of the horizontal conductive line 37. The pad edge portion 40A may be convex in shape. Of the pads 40, the pad that contacts the extended portion of the dummy horizontal conductive line 37D may be referred to as a "dummy pad".

[0130] As described above, the first and second pad sheets 15 and 25 can be replaced with the pad 40 through a series of steps.

[0131] As shown in Figure 28, a line-type pad separation layer 38L can be formed in the merged trench 38. The line-type pad separation layer 38L may contain an insulating material. The line-type pad separation layer 38L may be referred to as a supporter or slit.

[0132] Next, the first and second sacrificial plugs 18 and 29 can be removed to form a contact hole 41. The contact hole 41 may be described as a combination of the first contact hole 18' and the second contact hole 28.

[0133] As shown in Figure 29, a contact spacer 42 can be formed on the side wall of the contact hole 41. The contact spacer 42 may contain an insulating material.

[0134] Next, a contact plug 43 can be formed on the contact spacer 42 to fill the contact hole 41. The contact plug 43 may contain a conductive material. The contact plug 43 may contain a metal-based material.

[0135] As described above, the first and second sacrificial plugs 18 and 29 can be replaced with the contact plug 43.

[0136] Next, the first conductive line BL and data storage element CAP can be formed, as shown in Figures 3 and 4.

[0137] According to the embodiment described above, by forming a dummy stack DSB between the first mold stack SB1 and the second mold stack SB2, the etching process for forming the first contact hole 18' and the second contact hole 28 can be carried out in two separate steps. In this way, since the contact hole etching is carried out in two separate steps, the area of ​​the connecting region R2 can be reduced, thereby increasing mass productivity.

[0138] For example, when forming 100 tiers, this embodiment allows the mold stack to be formed in batches of 50 tiers. This allows the contact hole etching process to be carried out in batches of 50 tiers. As a comparative example, when forming contact holes in a 100-tier mold stack with only one etching pass, the spacing between contact holes can be made larger to avoid interference between them. When the spacing between contact holes is large, the area of ​​the connecting region inevitably becomes larger.

[0139] In this embodiment, instead of proceeding with a single high aspect ratio etching of the 100-step mold stack to form contact holes in the non-stepped connecting region R2, the etching can be divided into two 50-step portions and carried out in two high aspect ratio etchings. In this case, the etching depth required to form the contact holes is reduced, which can reduce the pitch of the contact holes. This reduces the size of the connecting region R2, thereby ensuring mass production of net dies.

[0140] The present invention described above is not limited by the embodiments described above and the accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. [Explanation of symbols]

[0141] BL First conductive line WL Second conductive line HL Nanosheet GD Nanosheet Insulating Layer CH Channel SR 1st Doped Area DR Second Doped Area TR switching element CAP data storage element SN First electrode DE dielectric layer PN Second electrode PL Common Plate MCA Memory Cell Array MC memory cell BLC First Contact Node SNC's second contact node IL1 First inter-cell insulating layer IL2 Second inter-cell insulating layer IL3 Third inter-cell insulating layer WLP Pad CT Contact Plug CTS Contact Spacer MCA1 Lower Memory Cell Array MCA2 Upper Memory Cell Array DMCA Dummy Memory Cell Array

Claims

1. The steps include forming a first vertical stack in which a plurality of first semiconductor layers are stacked vertically on the upper part of a substrate, The steps include etching the first semiconductor layer of the first vertical stack to form a first contact hole, The steps include: epitaxially growing a dummy semiconductor layer from the topmost first semiconductor layer of the first vertical stack; The steps include: epitaxially growing a second semiconductor layer on the dummy semiconductor layer in order to form a second vertical stack; The steps include etching the second semiconductor layer of the second vertical stack to form a second contact hole, The steps of replacing the first and second semiconductor layers with pads, A method for manufacturing a semiconductor device containing [a specific component].

2. After the step of forming the first contact hole, Step of forming a first sacrificial plug that fills the first contact hole. A method for manufacturing a semiconductor device according to claim 1, further comprising:

3. After the step of forming the second contact hole, The process includes the step of forming a second sacrificial plug that fills the second contact hole, The method for manufacturing a semiconductor device according to claim 2, wherein the first sacrificial plug and the second sacrificial plug overlap vertically.

4. After the step of replacing the first and second semiconductor layers with pads, The method for manufacturing a semiconductor device according to claim 3, further comprising the step of replacing the first and second sacrificial plugs with contact plugs.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer, the dummy semiconductor layer, and the second semiconductor layer are formed by epitaxial growth.

6. A method for manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer, dummy semiconductor layer, and second semiconductor layer include single-crystal silicon, single-crystal silicon germanium, or a single-crystal silicon / single-crystal silicon germanium stack.

7. The steps include forming a first vertical stack on the upper part of the substrate by vertically stacking first pad sheets, The steps include etching the first pad sheet of the first vertical stack to form a first contact hole, The steps include forming a first sacrificial plug that fills the first contact hole, The steps include forming a dummy stack comprising a dummy pad sheet on the first sacrificial plug and the first vertical stack, The steps include forming a second vertical stack by stacking a second pad sheet vertically on the dummy stack, The steps include etching the second pad sheet of the second vertical stack to form a second contact hole, The steps include forming a second sacrificial plug that fills the second contact hole, The steps include removing the second pad sheet and the first pad sheet to form a pad-shaped recess, The steps include forming a pad that fills the pad-shaped recess, The steps include replacing the first and second sacrificial plugs with contact plugs, A method for manufacturing a semiconductor device containing [a specific component].

8. The method for manufacturing a semiconductor device according to claim 7, wherein the first sacrificial plug and the second sacrificial plug overlap vertically.

9. The step of replacing the first and second sacrificial plugs with contact plugs is: The steps include removing the first and second sacrificial plugs to form a contact hole, The steps include forming a contact spacer on the side wall of the contact hole, The steps include filling the contact hole with a conductive material, A method for manufacturing a semiconductor device according to claim 7, including the following:

10. The method for manufacturing a semiconductor device according to claim 7, wherein the pads have the same horizontal length as the others, and the pads form a vertical stack in a non-stepped structure.

11. The method for manufacturing a semiconductor device according to claim 7, wherein the first pad sheet, the dummy pad sheet, and the second pad sheet include single-crystal silicon.

12. The steps include forming a first inter-pad insulating layer in the vertical gap of the first pad sheet, The steps include forming a second inter-pad insulating layer in the vertical gap of the second pad sheet, A method for manufacturing a semiconductor device according to claim 7, further comprising:

13. The steps include forming a first vertical arrangement of first nanosheets on the upper part of the substrate, and a first vertical arrangement of first pad sheets extending horizontally from the first nanosheets of the first vertical arrangement, The steps include etching the first vertically arranged first pad sheet to form a first contact hole, The steps include forming a first sacrificial plug that fills the first contact hole, The steps include forming a dummy stack comprising a dummy pad sheet on the first sacrificial plug, a first vertical arrangement of first nanosheets, and a first vertical arrangement of first pad sheets, The steps include forming a second vertical arrangement of second nanosheets on the dummy stack, and a second vertical arrangement of second pad sheets extending horizontally from the second nanosheets of the second vertical arrangement, The steps include etching the second pad sheet of the second vertical arrangement to form a second contact hole, The steps include forming a second sacrificial plug that fills the second contact hole, The steps include forming a vertical arrangement of horizontal conductive lines that surround the first and second nanosheets, respectively, The steps include removing the second pad sheet and the first pad sheet to form a pad-shaped recess, The steps include forming pads connected to the horizontal conductive lines while filling the pad-shaped recesses, The steps include replacing the first and second sacrificial plugs with contact plugs, A method for manufacturing a semiconductor device containing [a specific component].

14. The method for manufacturing a semiconductor device according to claim 13, wherein the first sacrificial plug and the second sacrificial plug overlap vertically.

15. The step of replacing the first and second sacrificial plugs with contact plugs is: The steps include removing the first and second sacrificial plugs to form a contact hole, The steps include forming a contact spacer on the side wall of the contact hole, The steps include filling the contact hole with a conductive material, A method for manufacturing a semiconductor device according to claim 13, including the method described above.

16. The method for manufacturing a semiconductor device according to claim 13, wherein the pads have the same horizontal length as the others, and the pads form a non-stepped vertical stack.

17. The method for manufacturing a semiconductor device according to claim 13, wherein the first and second nanosheets, the first and second pad sheets, and the dummy pad sheet each contain epitaxial single-crystal silicon.

18. The steps include forming a first inter-pad insulating layer in the vertical gap of the first pad sheet, The steps include forming a second inter-pad insulating layer in the vertical gap of the second pad sheet, A method for manufacturing a semiconductor device according to claim 13, further comprising:

19. A first memory cell array including a vertical arrangement of first memory cells, A second memory cell array including a vertical arrangement of second memory cells, A dummy memory cell array including a vertical arrangement of dummy memory cells between the first memory cell array and the second memory cell array, A semiconductor device equipped with a semiconductor device.

20. The semiconductor device according to claim 19, wherein the first memory cell, the second memory cell, and the dummy memory cell have the same structure.

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