Indication device

Abstract

The objective is to provide technology that enables improvement of video characteristics. [Solution] The display device includes a plurality of gate lines, a plurality of signal lines, a plurality of pixels, a display gate driver that sequentially scans the plurality of gate lines, and a pre-charge gate line selection unit that selects the plurality of gate lines collectively. One frame comprises a pre-charge period in which the pre-charge gate line selection unit selects the plurality of gate lines collectively and writes pre-charge gradation signals from the plurality of signal lines to the plurality of pixels; a first period after the pre-charge period in which the display gate driver sequentially scans the plurality of gate lines and writes gradation signals corresponding to video signals from the plurality of signal lines to the plurality of pixels; and a second period after the first period in which none of the plurality of gate lines are selected.

Description

Technical Field

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[0001] The present disclosure relates to a display device.

Background Art

[0002] As an electro-optical device with reduced video blurring, for example, Japanese Unexamined Patent Application Publication No. 2010-091967 has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to significantly improve the video characteristics of a liquid crystal panel, a method of combining the following two techniques is known. Technique 1) High-frequency driving (adopting a method of increasing the frame frequency). Technique 2) Impulse driving using a Blinking backlight (also called a backlight blinking method. Adopting a method of performing impulse driving by turning off the backlight in accordance with the scanning timing).

[0005] However, since there is an upper limit value for the response speed of the liquid crystal molecules themselves, even if the frame frequency is increased beyond the response speed of the liquid crystal molecules, it does not lead to an improvement in video characteristics and causes image quality degradation such as brightness unevenness.

[0006] An object of the present disclosure is to provide a technique that enables improvement of video characteristics. ​​​​​​​​​A brief overview of some of the representative aspects of this invention is as follows.

[0009] In other words, the display device is A plurality of gate lines extending in a first direction and adjacent to a second direction intersecting the first direction, A plurality of signal lines extending in the second direction and adjacent to the first direction, A plurality of pixels arranged in a matrix in the first direction and the second direction, A display gate driver that sequentially scans the plurality of gate lines, It includes a pre-charge gate line selection unit that selects the aforementioned multiple gate lines collectively, One frame is, The pre-charge gate line selection unit selects multiple gate lines collectively and writes pre-charge gradation signals from the multiple signal lines to the multiple pixels during the pre-charge period. After the pre-charge period, the display gate driver sequentially scans the plurality of gate lines and writes gradation signals corresponding to the video signals to the plurality of pixels from the plurality of signal lines in a first period, The system comprises a first period followed by a second period in which none of the plurality of gate lines are selected. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a diagram illustrating a first driving method for a display device according to a comparative example. [Figure 2] Figure 2 is a schematic diagram illustrating an example of image quality degradation. [Figure 3] Figure 3 illustrates a second driving method for a display device according to a comparative example. [Figure 4] Figure 4 shows an example of the configuration of the display device according to Example 1. [Figure 5] Figure 5 illustrates the grayscale signal supplied to the display device of Example 1. [Figure 6] Figure 6 illustrates the timing of the display device in Example 1. [Figure 7] FIG. 7 is a diagram for explaining a circuit configuration example of the logic circuits (GL1, GD1) in FIG. 4. [Figure 8] FIG. 8 is a diagram for explaining the timing of the logic circuits (GL1, GD1) in FIG. 7. [Figure 9] FIG. 9 is a diagram showing a configuration example of the display device according to Modification 1. [Figure 10] FIG. 10 is a diagram for explaining the timing of the display device of Modification 1. [Figure 11] FIG. 11 is a diagram showing a configuration example of the display device according to Modification 2. [Figure 12] FIG. 12 is a plan view schematically showing Configuration Example 1 of the display device according to Modification 3. [Figure 13] FIG. 13 is a plan view schematically showing Configuration Example 2 of the display device according to Modification 3. [Figure 14] FIG. 14 is a diagram for explaining a circuit configuration example corresponding to Configuration Example 2 of the display device in FIG. 13. [Figure 15] FIG. 15 is a diagram showing a configuration example in which the batch precharge period is divided into two. [Figure 16] FIG. 16 is a diagram showing a configuration example in which the batch precharge period is divided into three. [Figure 17] FIG. 17 is a diagram showing a configuration example in which the number of signal lines of the internal reset signal Int-XRST is increased according to the number of divisions of the batch precharge period.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

[0012] It should be noted that the disclosure is only an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, for the purpose of making the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is only an example and does not limit the interpretation of the present invention.

[0013] Furthermore, in this specification and in each figure, elements similar to those described above for previously shown figures are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0014] In this embodiment, a liquid crystal display device is disclosed as an example of a display device. This liquid crystal display device can be used in various devices such as AR / VR / MR terminals, smartphones, tablet terminals, mobile phone terminals, personal computers, television receivers, in-vehicle devices, and game devices.

[0015] The term "display device" refers to all display devices that display images using a display panel. The term "display panel" refers to a structure that displays images using an electro-optic layer. For example, the term "display panel" may refer to a display cell that includes an electro-optic layer, or it may refer to a structure in which a semiconductor device equipped with other optical components (e.g., polarizing components, backlights, touch panels, etc.) or a drive circuit such as a source driver IC is attached to the display cell. Here, the "electro-optic layer" may include liquid crystal layers, electrochromic (EC) layers, etc., as long as it does not create a technical contradiction. Therefore, although the embodiments described later will use a liquid crystal panel including a liquid crystal layer as an example of a display panel, this does not preclude its application to display panels including other electro-optic layers as described above.

[0016] (Embodiment) First, the problem will be explained using Figures 1, 2, and 3. Figure 1 illustrates the first driving method of the display device according to the comparative example. Figure 2 is a schematic diagram illustrating an example of image quality degradation. Figure 3 illustrates the second driving method of the display device according to the comparative example.

[0017] Figure 1 shows the drive duration for each frame in the display panel, specifically the Nth frame (N Frame) and the (N+1)th frame (N+1 Frame) following the Nth frame. Each claim specifies the following drive duration:

[0018] 1) First period T11: The first period T11 is the period during which gate lines (also called scan lines: G1, G2, G3...) are sequentially scanned and selected, and grayscale signals (grayscale potentials) corresponding to the video signal are written from the signal lines to multiple pixels in one line (one row) connected to the selected gate lines.

[0019] 2) Second period T12: The second period T12 is the response period of the liquid crystal molecules, based on the response speed of the liquid crystal molecules of the pixel on which the grayscale signal is written.

[0020] 3) Third period T13: The third period T13 is the period during which the backlight is turned on and an image based on the grayscale signals written to all pixels in the display panel is displayed.

[0021] Here, because liquid crystal molecules themselves have an upper limit to their response speed, increasing the frame rate beyond the response speed of the liquid crystal molecules will not lead to an improvement in video characteristics, but rather to image quality degradation such as brightness unevenness.

[0022] Figure 2 schematically shows the image quality degradation when the frame frequency is driven at a frequency higher than the response speed of the liquid crystal molecules. The display panel DISP is assumed to include, for example, 2n gate lines G1, G2, G3, ..., G2n-2, G2n-1, G2n, and is scanned sequentially as G1, G2, G3, ..., G2n-2, G2n-1, G2n. In this example, the case is shown where N frames display a black screen (BB) and N+1 frames attempt to display a white screen (WW).

[0023] For example, in the display panel region R11 of gate lines scanned relatively early, such as gate lines G1, G2, and G3, the response time of the liquid crystal molecules is sufficient, so a normal white (WW) is displayed. On the other hand, in the display panel region R12 of gate lines scanned later, such as gate lines G2n-2, G2n-1, and G2n, the response time of the liquid crystal molecules is not sufficient, so a normal white (WW) is not displayed, and the screen becomes slightly darker (dark white (DW) is displayed).

[0024] In other words, when the frame frequency is increased beyond the response speed of the liquid crystal molecules, if the response period T12 of the liquid crystal molecules becomes insufficient, the liquid crystal response may not keep up in the region corresponding to the latter half of the gate line scanning (the latter half of the display panel: the region of the display panel corresponding to the gate lines that are in the latter half of the scanning order), resulting in a problem where the intended brightness is not achieved.

[0025] To solve this problem, as shown in Figure 3, a method is known in which a period TPR1 is introduced before the first period T11 in which a grayscale signal corresponding to an intermediate tone, such as gray, is precharged to all pixels at once. In other words, as a countermeasure, a method is known in which the pixel capacitance (Cs) and liquid crystal capacitance (Clc) are precharged with a gray potential to all pixels at once, and the liquid crystal response to white, black, and other gray tones is completed quickly during the subsequent liquid crystal response period. However, in this case, there is a problem in that it is necessary to create a dedicated source driver IC that can drive it. [Examples]

[0026] Next, the display device according to Example 1 will be described using Figures 4, 5, 6, 7, and 8. Figure 4 is a diagram showing an example configuration of the display device according to Example 1. Figure 5 is a diagram illustrating the gradation signal supplied to the display device of Example 1. Figure 6 is a diagram illustrating the timing of the display device of Example 1. Figure 7 is a diagram illustrating an example circuit configuration of the logic circuit (GL1, GD1) in Figure 4. Figure 8 is a diagram illustrating the timing of the logic circuit (GL1, GD1) in Figure 7.

[0027] As shown in Figure 4, the display device 10 includes a display panel DISP and a source driver (Driver IC) 100. The display panel DISP includes an active area (active region / display area) AA provided with multiple gate lines, multiple signal lines, and multiple pixels, a display gate driver 101, and an additional shift register 102 for precharging. The active area AA has multiple pixels PIX arranged in a matrix along a first direction X and a second direction Y that intersects the first direction X. The multiple pixels PIX include, for example, multiple pixels PIX for red R, multiple pixels PIX for blue B, and multiple pixels PIX for green G. In this example, multiple pixels PIX arranged in a 2n x 4 matrix are typically shown, meaning 4 pixels in the first direction X (horizontal direction, row direction) and 2n pixels in the second direction Y (vertical direction, column direction) that intersects the first direction X. The additional shift register 102 for pre-charging can be described as a pre-charging gate line selection unit, or it can be described as part of the display gate driver.

[0028] The active region AA is arranged such that multiple gate lines (Gate_1, Gate_2, ..., Gate_2n) extend along the first direction X and are also arranged alongside the second direction Y. Multiple pixels of the first row are connected to gate line Gate_1. Similarly, multiple pixels connected to the corresponding row are connected to each of the gate lines (Gate_2, ..., Gate_2n). Gate lines can be rephrased as scan lines.

[0029] Furthermore, the active region AA is arranged such that multiple signal lines Sig(Sg1, Sg2, Sg3, Sg4) extend along the second direction Y and are aligned with the first direction X. Multiple pixels in the first column are connected to signal line Sg1. Similarly, multiple pixels connected to the corresponding column are connected to each of the signal lines Sg2, Sg3, and Sg4. Signal lines can be rephrased as source lines. In Figure 4, four signal lines are disclosed as an example, but other signal lines may be provided next to Sg4.

[0030] Thin-film transistors are used as switching elements Tr provided in each pixel PIX. Examples of thin-film transistors include bottom-gate transistors and top-gate transistors. A single-gate thin-film transistor is used as an example of a switching element Tr, but a double-gate transistor may also be used. One of the source and drain electrodes of the switching element Tr is connected to the signal line Sig (Sg1, Sg2, Sg3, Sg4), and the gate electrode is connected to the scan line, which is the gate line Gate_i (i=1, 2, ..., 2n). The other of the source and drain electrodes is connected to the pixel electrodes (P1, P2). The pixel electrodes face a common electrode (CE) via a liquid crystal (LC). The common electrode (CE) is connected to a common potential wiring COML. The liquid crystal (LC) forms a capacitance Clc with the pixel electrodes and the common electrode as a pair of capacitive electrodes. In addition, a retaining capacitance Cs is formed between the pixel electrodes (P1, P2) and the common electrode (CE) via a dielectric such as an insulating film. Furthermore, the common potential wiring COML is supplied with the common voltage VCOM from the common potential drive circuit.

[0031] The display gate driver 101 includes multiple shift registers S / R, gate line selection circuits GL1-GL2n, and gate line drive circuits GD1-GD2n. The additional shift register 102 includes multiple shift registers S / R_d, set-reset flip-flops SR-FF, and AND circuit AN. Each of the gate line selection circuits GL1-GL2n and the gate line drive circuits GD1-GD2n can be configured using NAND circuits.

[0032] The additional shift register 102 is provided for generating the pre-charge timing signal. The first shift register S / R_d has an input terminal to which a start pulse STV is supplied, a clock terminal to which a transfer clock CKV is supplied, a reset signal terminal to which a reset signal XRST is supplied, and an output terminal to which a transfer signal trn_d1 is output.

[0033] The second shift register S / R_d through the mth shift register S / R_d, like the first shift register S / R_d, have an input terminal, a clock terminal to which the transfer clock CKV is supplied, a reset signal terminal to which the reset signal XRST is supplied, and an output terminal to which the corresponding transfer signal trn_dn (n=2,···,m) is output. Each input terminal of the second shift register S / R_d through the mth shift register S / R_d is supplied with the transfer signal trn_dx from the preceding shift register S / R_d.

[0034] The second shift register S / R_d through the mth shift register S / R_d are supplied with the transfer clock CTV and the reset signal XRST, similar to the first shift register S / R_d. The transfer signal trn_d1, which is the output of the first shift register S / R_d, is supplied to the second shift register S / R_d. The transfer signal trn_d2, which is the output of the second shift register S / R_d, is supplied to the third shift register S / R_d. Similarly, the transfer signals trn_d3 through trn_dm-1, which are the outputs of the (m-1)th shift register S / R_d through the third shift register S / R_d, are supplied to the next stage shift register S / R_d. The transfer signal trn_dm, which is the output of the mth shift register S / R_d, is supplied to the first shift register S / R of the multiple shift registers S / R in the display gate driver 101.

[0035] When the first shift register S / R_d receives a high-level reset signal XRST, and the start pulse STV changes from a low level to a high level, and the transfer clock CKV also changes from a low level to a high level, it generates a transfer signal trn_d1 and supplies it to the second shift register S / R_d.

[0036] The second shift register S / R_d generates a transfer signal trn_d2 when the transfer clock CKV changes from a high level to a low level and supplies it to the third shift register S / R_d. In this way, the transfer signals trn_dx (x=1, ..., m) are sequentially transferred to the shift register S / R_d. Using the start pulse STV and any two signals from the transfer signals (trn_dx) of the additional shift register S / R_d, a signal is generated that can define (identify) the batch precharge period.

[0037] In Figure 4, in a set-reset flip-flop (SR-FF), the transfer signal trn_d1 is supplied to the set terminal S and the transfer signal trn_dm-2 is supplied to the reset terminal R to generate the output signal XQ. When the transfer signal trn_d1 transitions to a high level, the output signal XQ transitions from a high level to a low level. Then, when the transfer signal trn_dm-2 transitions to a high level, the output signal XQ transitions from a low level to a high level. The low-level period of the output signal XQ is the collective pre-charge period. Here, "collective" means that all gate lines (Gate_1, ..., Gate2n) are set to a selected level (high level: H), and the pixel electrodes (P1, P2) are pre-charged collectively to the desired gradation potential.

[0038] The AND circuit AN receives the reset signal XRST and the output signal XQ, and performs a logical AND operation between the reset signal XRST and the output signal XQ to generate the internal reset signal Int-XRST. In this example, the low level of the internal reset signal Int-XRST indicates the discharge period of the pixel electrodes (P1, P2) or the collective pre-charge period of the pixel electrodes (P1, P2). The additional shift register 102 for pre-charging, the set-reset flip-flop (SR-FF), and the AND circuit AN can be collectively referred to as the pre-charge setting circuit.

[0039] The multiple shift registers S / R within the display gate driver 101 have a reset terminal to which an internal reset signal Int-XRST is supplied, and a clock terminal to which a transfer clock CKV is supplied. The first shift register S / R of the multiple shift registers S / R has an input terminal to which a transfer signal trn_dm is supplied, and an output terminal that generates a transfer signal trn_1 and supplies it to the second shift register S / R. Similarly, the (n-1)th shift registers S / R from the second shift register S / R have an input terminal to which transfer signals trn_1 and trn_n-2 are supplied, and an output terminal that generates transfer signals trn_2 and trn_n-1 and supplies them to the corresponding next stage shift register S / R. The nth shift register S / R has an output terminal that generates and outputs a transfer signal trn_n.

[0040] Of the gate line selection circuits GL1-GL2n, gate line selection circuits GL1, GL3, GL5, ..., GL2n-1 have a first input terminal that receives a first enable signal EN1, while gate line selection circuits GL2, GL4, GL6, ..., GL2n have a first input terminal that receives a second enable signal EN2. In addition, gate line selection circuits GL1 and GL2 have a second input terminal that receives a transfer signal trn_1, and gate line selection circuits GL3 and GL4 have a second input terminal that receives a transfer signal trn_2. Similarly, gate line selection circuits (GL5, GL6), ..., gate line selection circuits (2n-1, 2n) have a second input terminal that receives a transfer signal trn_3, ..., and a transfer signal n. The output terminals of each gate line selection circuit GL1-GL2n are connected to the respective second input terminals of the gate line drive circuits GD1-GD2n.

[0041] Each of the first input terminals of the gate line drive circuits GD1-GD2n is connected to receive the internal reset signal Int-XRST. Each of the output terminals of the gate line drive circuits GD1-GD2n is connected to the gate lines (Gate_1, ..., Gate_2n), respectively.

[0042] A multiplexer 110 is provided between multiple signal lines Sig and a source line driver (Driver IC) 100. The multiplexer 110 is configured to include multiple first switches SW1 which are controlled to be on or off according to the level of a first selection signal MUX1, and multiple second switches SW2 which are controlled to be on or off according to the level of a second selection signal MUX2.

[0043] The source line driver 100 includes multiple source line terminals S1, S2, ... for supplying gradation signals to multiple signal lines Sig. The multiplexer 110 and the source line driver 100 can be described as a signal line drive circuit that supplies gradation signals to multiple signal lines.

[0044] The first source line terminal S1 is connected to signal line Sg1 via the first switch SW1, and also to signal line Sg2 via the second switch SW2. The second source line terminal S2 is connected to signal line Sg3 via the first switch SW1, and also to signal line Sg4 via the second switch SW2. Other source terminals not shown in Figure 4 are similarly connected to signal line (Sgm) via the first switch SW1, and to signal line (Sgm+1) via the second switch SW2.

[0045] In the display device 10 of Figure 4, the low level of the internal reset signal Int-XRST generated by the additional shift register 102 allows the gate line drive circuits GD1-GD2n to select all gate lines (Gate_1, ..., Gate_2n). At this time, the source line driver 100 is configured to supply pre-charge gradation signals (gradation potentials) to multiple signal lines Sig (Sg1, Sg2, Sg3, Sg4, ...) and pre-charge the pixel electrodes (P1, P2, ...) of all pixels PIX using the pre-charge gradation signals. Here, the pre-charge gradation signal can also be described as a third gradation signal between the first gradation signal corresponding to black and the second gradation signal corresponding to white. The pre-charge gradation signal can be, for example, a gradation signal corresponding to gray.

[0046] This allows, for example, all pixel electrodes (P1, P2, ...) of all pixels (PIX) to be pre-charged collectively to a gray tone signal, and then, during the subsequent liquid crystal response period T12, the liquid crystal response to white, black, or gray tone signals of other tones can be completed more quickly. Therefore, a technology that enables improved video characteristics can be provided.

[0047] As shown in Figure 5, this diagram illustrates the pre-charge period and the display period. The signal output specifications for the source line driver 100 should be as follows: The maximum number of vertical display stages (lines) during the pre-charge period is twice the number of stages m of the multiple shift registers S / R_d in the additional shift register 102 (2m), and the source line driver 100 should be configured to supply pre-charge gradation signals to multiple signal lines Sig during this period. The number of vertical display stages (lines) during the display period is 2n, which is the number of gate lines (Gate_1, ..., Gate_2n), and the source line driver 100 will supply display gradation signals to multiple signal lines Sig during this period.

[0048] Therefore, when generating video signals such as moving images using data processing equipment, the video signal is composed of 2(m+n) vertical stages, with the first 2m stages being used as a grayscale signal for precharging, and the remaining 2n stages being the actual video signal such as moving images to be displayed on the display panel DISP.

[0049] Figures 4 and 5 show examples where the shift register (S / R_d, S / R) has (m+n) stages and the enable signal has two systems (EN1 and EN2). If the shift register (S / R_d, S / R) has (m+n) stages and the enable signal has 4 systems, it is necessary to prepare 4 (m+n) stages of video signals (including pre-charge gradation signals). If the shift register (S / R_d, S / R) has (m+n) stages and the enable signal has 1 system, it is necessary to prepare (m+n) stages of video signals (including pre-charge gradation signals). However, the specifications of the source line driver 100 do not depend on the number of enable signal systems.

[0050] Next, the operation of the display device 10 will be explained using Figure 6. In Figure 6, S<1:x> indicates the state of the source line terminals S1, S2, ... S<1:x>, start pulse STV, transfer clock CKV, reset signal XRST, first enable signal EN1, second enable signal EN2, first selection signal MUX1, and second selection signal MUX2 are signals supplied from outside the display device 10. Signals other than those mentioned above are internal signals of the display device 10 (display panel DISP). Here, in the display device 10, one frame has a batch precharge period TPR1, a first period T11, a second period T12, and a third period T13, as explained in Figure 3. In Figure 6, the batch precharge period TPR1 and the first period T11 will be mainly explained.

[0051] First, the reset signal XRST is set to a low level, and the internal reset signal Int-XRST is also set to a low level, causing the pixel electrodes (P1, P2) of all pixels (PIX) to discharge. At this time, the pixel electrodes (P1, P2) are at ground potential (GND), such as 0V in this example. After the discharge is complete, the reset signal XRST and the internal reset signal Int-XRST are set to a high level.

[0052] Subsequently, the first shift register S / R_d is supplied with a start pulse STV that changes only once in a pulsed manner, followed by the transfer clock CKV. At the same time, the supply of the first enable signal EN1 and the second enable signal EN2 is initiated.

[0053] Based on the high level of the start pulse STV and the high level of the transfer clock CKV, the first shift register S / R_d generates a high-level transfer signal trn_d1 and supplies it to the second shift register S / R_d. Based on the high level of the high-level transfer signal trn_d1, the output signal XQ of the set-reset flip-flop (SR-FF) is changed from high to low, and the internal reset signal Int-XRST is changed from high to low, and the batch precharge period TPR1 begins. The batch precharge period TPR1 can also be referred to as the precharge period TPR1.

[0054] Subsequently, when the transfer clock CKV changes pulse-wise from high to low, the second shift register S / R_d generates the transfer signal trn_d2 and supplies it to the third shift register S / R_d. In this way, the transfer signals trn_dx (x=1, ..., m) are sequentially transferred from the first shift register S / R_d to the mth shift register S / R_d. The transfer signal trn_dm generated from the mth shift register S / R_d is supplied to the first shift register S / R. When the transfer signal trn_dm-2 changes from low to high, the internal reset signal Int-XRST changes from low to high, and the batch precharge period TPR1 ends.

[0055] During the batch precharge period TPR1, regardless of the signal levels of the first enable signal EN1 and the second enable signal EN2, all gate lines (Gate_1, ..., Gate_2n) are selected to a high level by the gate line drive circuits GD1-GD2n. At this time, gray tone signals corresponding to gray are supplied from all source terminals (S1, S2, ...) of the source line driver 100 to the corresponding signal lines (Sg1, Sg3:Sg2, Sg4, ...) based on the high levels of the first selection signal MUX1 and the second selection signal MUX2. As a result, the pixel electrodes (P1, P2, ...) of all pixels PIX are precharged collectively to the gray tone signal (Gray precharge). When the batch precharge period TPR1 ends, based on the high level of the internal reset signal Int-XRST, all gate lines (Gate_1, ..., Gate_2n) are set to a low-level, unselected state by the gate line drive circuits GD1-GD2n.

[0056] Here, the period from the end of the batch precharge period TPR1 to the generation of the transfer signal trn_1 for the first shift register S / R is defined as the reset release period TRR. The reset release period TRR is the period during which all circuits of the display gate driver 101 are reset simultaneously. Therefore, it is advisable to ensure that the reset release period TRR is sufficient, taking into account the time constants of all circuits of the display gate driver 101.

[0057] After the reset release period TRR ends, period T11 begins during which the display gate driver 101 performs gate line scanning. During period T11, grayscale signals for effective display are written to each pixel.

[0058] During period T11, the first shift register S / R, having received the transfer signal trn_dm, generates the transfer signal trn_1 when the transfer clock CKV changes from a low level to a high level and supplies it to the second shift register S / R. Subsequently, when the transfer clock CKV changes from a high level to a low level, the second shift register S / R generates the transfer signal trn_2 and supplies it to the third shift register S / R. In this manner, the transfer signals trn_x (x=1, ..., n) are sequentially transferred from the first shift register S / R to the nth shift register S / R.

[0059] When the transfer signal trn_1 is at a high level and the first enable signal EN1 is at a high level, the gate line Gate_1 is selected. At this time, when the first selection signal MUX1 is at a high level, gradation signals corresponding to the video signal are supplied to the signal lines Sg1 and Sg3, and these gradation signals are written to the pixel electrode P1 of the corresponding pixels (multiple pixels connected to the gate line Gate_1 and the signal lines Sg1, Sg3, ...). Also, when the second selection signal MUX2 is at a high level, gradation signals corresponding to the video signal are supplied to the signal lines Sg2 and Sg4, and these gradation signals are written to the pixel electrode P2 of the corresponding pixels (multiple pixels connected to the gate line Gate_1 and the signal lines Sg2, Sg4, ...).

[0060] When the transfer signal trn_1 is at a high level and the second enable signal EN2 is at a high level, the gate line Gate_2 is selected. At this time, when the first selection signal MUX1 is at a high level, gradation signals corresponding to the video signal are supplied to the signal lines Sg1 and Sg3, and these gradation signals are written to the pixel electrode P1 of the corresponding pixels (multiple pixels connected to the gate line Gate_2 and the signal lines Sg1, Sg3, ...). Also, when the second selection signal MUX2 is at a high level, gradation signals corresponding to the video signal are supplied to the signal lines Sg2 and Sg4, and these gradation signals are written to the pixel electrode P2 of the corresponding pixels (multiple pixels connected to the gate line Gate_2 and the signal lines Sg2, Sg4, ...).

[0061] When the transfer signal trn_2 is at a high level, the gate line Gate_3 is selected when the first enable signal EN1 is at a high level, and when the second enable signal EN2 is at a high level, the gate line Gate_4 is selected. At this time, when the first selection signal MUX1 is at a high level, gradation signals corresponding to the video signal are supplied to the signal lines Sg1 and Sg3, and these gradation signals are written to the pixel electrode P1 of the corresponding pixels (multiple pixels connected to the gate line Gate_3 or Gate_4 and the signal lines Sg1, Sg3, ...). Also, when the second selection signal MUX2 is at a high level, gradation signals corresponding to the video signal are supplied to the signal lines Sg2 and Sg4, and these gradation signals are written to the pixel electrode P2 of the corresponding pixels (multiple pixels connected to the gate line Gate_3 or Gate_4 and the signal lines Sg2, Sg4, ...).

[0062] Subsequently, when the transfer signals trn_3,... and trn_n are at a high level, the corresponding gate lines are selected based on the first enable signal EN1 and the second enable signal EN2, and the gradation signals corresponding to the video signal are supplied to the corresponding signal lines based on the first selection signal MUX1 and the second selection signal MUX2, and these gradation signals are written to the pixel electrodes (P1, P2) of the corresponding pixels (multiple pixels connected to the corresponding gate lines and corresponding signal lines).

[0063] After the grayscale signal is written to multiple pixels connected to the gate line Gate_2n (after the end of period T11), periods T12 and T13 are performed as described in Figure 3.

[0064] As a result, during the pre-charge period TPR1, the grayscale signal corresponding to gray is pre-charged to the pixel electrodes (P1, P2, ...) of all pixels (PIX). Then, during period T11, the grayscale signal corresponding to the video signal is written to the pixel electrodes (P1, P2, ...) of all pixels (PIX). Then, during the liquid crystal molecule response period T12, the liquid crystal response to the white grayscale signal, the black grayscale signal, or the grayscale signal of a different grayscale can be completed quickly. Therefore, a technology that enables improvement of video characteristics can be provided.

[0065] Next, using Figures 7 and 8, we will explain an example of the circuit configuration of the gate line selection circuit GL (GL1-GL2n) and the gate line driving circuit GD (GD1-GD2n) within the display gate driver 101, as well as the operation of the display gate driver 101.

[0066] As shown in Figure 7, the gate line selection circuit GL includes an inverter IV1, a P-channel transistor Q1, an N-channel transistor Q2, and an N-channel transistor Q3.

[0067] The output terminal of the shift register S / R, which outputs the transfer signal trn, is connected to the input terminal of inverter IV1, the gate terminal of transistor Q1, and the gate terminal of transistor Q3. The source terminal of transistor Q1 is connected to receive the internal reset signal Int-XRST. The source-drain paths of transistor Q1 and transistor Q3 are connected in series, and the source terminal of transistor Q3 is connected to the wiring that supplies a low potential VGL, such as the low level of the gate line Gate i. The source-drain path of transistor Q2 is connected in parallel with the source-drain path of transistor Q1, and the gate terminal of transistor Q2 is connected to the output terminal of inverter IV1, which outputs the inverted signal xtrn of the transfer signal trn.

[0068] The gate line drive circuit GD includes a P-channel transistor Q4, an N-channel transistor Q5, an N-channel transistor Q6, and a P-channel transistor Q7. The source terminal of transistor Q4 is connected to receive the first enable signal EN1 (or the second enable signal EN2). The drain terminal of transistor Q4 is connected to the gate line Gate i. The source-drain path of transistor Q4 and the source-drain path of transistor Q6 are connected in series. The gate terminal of transistor Q6 is connected to the drain terminal of transistor Q1, and the source terminal of transistor Q6 is connected to the wiring that supplies a low potential VGL, such as the low level of gate line Gate i. The source-drain path of transistor Q5 is connected in parallel with the source-drain path of transistor Q4, and the gate terminal of transistor Q5 is connected to the gate terminal of transistor Q1. The gate terminal of transistor Q7 is connected to receive the internal reset signal Int-XRST. The source-drain path of transistor Q7 is connected between the wiring that supplies a high potential VGH, such as the high level of gate line Gate i, and gate line Gate i.

[0069] As shown in Figure 8, the operation of the display gate driver 101 includes, similar to Figure 6, a discharge period, a batch precharge period TPR1, a reset release period TRR, and a period T11 for scanning the gate lines of the display gate driver 101.

[0070] First, when the internal reset signal Int-XRST is set to a low level, a discharge period begins. At this time, transistor Q7 is turned on, and the gate line Gate i is set to a high level. The transfer signal trn is low level, and its inverted signal xtrn is high level, so transistors Q1 and Q2 are on, transistor Q3 is off, signal trnR is low level, and transistors Q4, Q5, and Q6 are off.

[0071] After the discharge period ends, the internal reset signal Int-XRST is set to high level. The transfer signal trn is low level, and its inverse signal xtrn is high level. As a result, transistors Q1 and Q2 are turned on, transistor Q7 is turned off, and since the signal trnR is set to high level, transistor Q6 is turned on, and the gate line Gate i is set to a low level, unselected state.

[0072] Subsequently, the batch precharge period TPR1 begins. During this time, the internal reset signal Int-XRST is set to a low level, so, similar to the discharge period, transistor Q7 is turned on and gate line Gate i is selected to a high level state. At this point, the supply of the transfer clock CKV, the first enable signal EN1, and the second enable signal EN2 begins. At this time, the source line driver 100 supplies grayscale signals to all signal lines to precharge all pixels.

[0073] Subsequently, the reset release period TRR begins. During this time, the internal reset signal Int-XRST is set to high level. The transfer signal trn is low level, and its inverted signal xtrn is high level. Similar to the period after the discharge, the gate line Gate i is set to a low-level, unselected state.

[0074] After the reset release period TRR ends, period T11 begins in which the display gate driver 101 performs gate line scanning. During period T11, grayscale signals for effective display are written to each pixel. Here, the internal reset signal Int-XRST is high level, the transfer signal trn is high level, and its inverse signal xtrn is low level. As a result, transistors Q1 and Q2 are turned off, and transistor Q7 is turned off. Transistors Q3, Q4, and Q5 are turned on, and since the signal trnR is low level, transistor Q6 is turned off. Since transistors Q3 and Q4 are on, gate line Gate i is selected to a high level based on the high level of the first enable signal EN1 (or the second enable signal EN2).

[0075] (Variation 1) In Figure 4, the multiple shift registers S / R within the display gate driver 101 were supplied with the internal reset signal Int-XRST. However, the reset of the multiple shift registers S / R may also be performed using the reset signal XRST. Modification 1 describes an example configuration in which the reset signal XRST is supplied to the multiple shift registers S / R.

[0076] The display device of Modified Example 1 will be described below using Figures 9 and 10. Figure 9 is a diagram showing an example of the configuration of the display device according to Modified Example 1. Figure 10 is a diagram illustrating the timing of the display device of Modified Example 1.

[0077] The difference between the display device 10a in Figure 9 and the display device 10 in Figure 4 is that in the display device 10a, the reset signal XRST is supplied to multiple shift registers S / R. The other configurations of the display device 10a in Figure 9 are the same as those of the display device 10 in Figure 4, so redundant explanations are omitted.

[0078] In Figure 9, wiring L9 is provided so that the reset signal XRST supplied to one terminal of the AND circuit AN is supplied to multiple shift registers S / R.

[0079] For the multiple shift registers S / R within the display gate driver 101, a reset release operation can be performed when the reset signal XRST becomes high level.

[0080] The internal reset signal Int-XRST only needs to release the reset of the gate line drive circuit GD(GD1-GD2n), which is the last NAND gate. Therefore, it is possible to shorten the reset release period (TRR).

[0081] The reset signal XRST wiring L9 also needs to be formed in the layout placement area of ​​the display gate driver 101. However, if the number of wirings L9 is around one, it is thought that it will not have much impact on the layout placement.

[0082] The difference between the timing of the display device 10a in Figure 10 and the timing of the display device 10 in Figure 6 is that, after the discharge period, the reset release (TRR_SR) of multiple shift registers S / R within the display gate driver 101 is provided. The other timings of the display device 10a in Figure 10 are the same as the other timings of the display device 10 in Figure 4, so redundant explanations are omitted.

[0083] (Modification 2) In Example 1, a display device 10 capable of performing batch precharging by providing an additional shift register 102 was described. Here, if it is possible to select whether or not to perform batch precharging, and the number of pixels and drive frequency of the display panel DISP are such that it is difficult to decide which is better at the design stage, it is possible to evaluate after the display panel DISP is created and then decide which is better.

[0084] Modification 2 describes an example configuration of the display device 10b that can select "with / without bulk precharge" based on a control signal. Figure 11 is a diagram showing an example configuration of the display device according to Modification 2. The difference between the display device 10b in Figure 11 and the display device 10 in Figure 4 is that the display device 10b is provided with a control circuit CTRC. The other configurations of the display device 10b in Figure 11 are the same as the other configurations of the display device 10 in Figure 4, so redundant explanations are omitted.

[0085] The operation of the control circuit CTRC is controlled by the control signal RCTL. When the control signal RCTL is at a high level, the control circuit CTRC is configured to supply the start pulse STV to the first shift register S / R in the display gate driver 101, resulting in a display device 10b without a batch precharge. On the other hand, when the control signal RCTL is at a low level, the control circuit CTRC is configured to supply the start pulse STV to the first shift register S / R_d of the additional shift register 102, and also to supply the transfer signal trn_dm output by the mth shift register S / R_d of the additional shift register 102 to the first shift register S / R in the display gate driver 101, resulting in a display device 10b with a batch precharge. In other words, the control circuit CTRC can be considered a control circuit that controls the enabling and disabling of the additional shift register 102.

[0086] The control circuit CTRC includes inverter IV10, N-channel transistors Q10, Q12, Q14, and Q17, and P-channel transistors Q11, Q15, and Q16.

[0087] The input terminal of inverter IV10 is connected to the wiring to which the control signal RCTL is supplied, and the output terminal of inverter IV10 is connected to the gate terminals of transistors Q10, Q15, and Q17, respectively. The gate terminals of transistors Q11, Q12, Q14, and Q16 are connected to the wiring to which the control signal RCTL is supplied.

[0088] The source-drain path of transistor Q10 is connected in parallel with the source-drain path of transistor Q11 and in series with the source-drain path of transistor Q12.

[0089] The source-drain path of transistor Q10 is connected to the wiring that supplies the start pulse STV, and the source-drain path of transistor Q12 is connected to the wiring that supplies a low potential VGL, such as the low level of the gate wire Gate. The common connection point between the source-drain paths of transistor Q10 and transistor Q12 is connected to the input terminal of the first shift register S / R_d of the additional shift register 102.

[0090] The source-drain path of transistor Q14 is connected in parallel with the source-drain path of transistor Q15 and in series with the source-drain path of transistor Q16. The source-drain path of transistor Q16 is also connected in parallel with the source-drain path of transistor Q17. The source-drain path of transistor Q14 is connected to the wiring that supplies the start pulse STV, and the source-drain path of transistor Q16 is connected to the wiring that supplies the transfer signal trn_dm. The common connection point between the source-drain paths of transistor Q14 and transistor Q16 is connected to the input terminal of the first shift register S / R in the display gate driver 101.

[0091] When the control signal RCTL is at a high level, transistors Q12, Q14, and Q15 turn on, and transistors Q10, Q11, Q16, and Q17 turn off. As a result, the start pulse STV is supplied to the input terminal of the first shift register S / R in the display gate driver 101, and a low-level, low-potential VGL is supplied to the input terminal of the first shift register S / R_d of the additional shift register 102. Therefore, the display device 10b is configured without a batch precharge.

[0092] When the control signal RCTL is at a low level, transistors Q10, Q11, Q16, and Q17 turn on, and transistors Q12, Q14, and Q15 turn off. As a result, the start pulse STV is supplied to the input terminal of the first shift register S / R_d of the additional shift register 102, and the transfer signal trn_dm output by the mth shift register S / R_d of the additional shift register 102 is supplied to the input terminal of the first shift register S / R in the display gate driver 101. Therefore, the display device 10b is configured with a batch precharge.

[0093] (Variation 3) Modification 3 examines a configuration in which an additional shift register 102 is provided to the display device 10c (10, 10a, 10b).

[0094] Figure 12 is a schematic plan view showing configuration example 1 of the display device according to modified example 3. Figure 13 is a schematic plan view showing configuration example 2 of the display device according to modified example 3. Figure 14 is a diagram illustrating a circuit configuration example corresponding to configuration example 2 of the display device in Figure 13.

[0095] As shown in Figure 12, in a plan view, the display panel DISP has a rectangular active area AA positioned in the center, with display gate drivers 101 positioned in the left and right areas of the active area AA. In this example, since there is ample space in the upper area of ​​the active area AA, additional shift registers 102 are positioned in two locations in the upper area of ​​the active area AA, corresponding to the area above the display gate drivers 101 (opposite the source line driver 100, with respect to the display gate drivers 101). A multiplexer 110 is positioned in the lower area of ​​the active area AA.

[0096] The display panel DISP is provided with a pad FPCPAD for connection to a flexible printed circuit board (FPC), and is connected to the FPC. A multiplexer 110 and a source line driver 100 are positioned between the pad FPCPAD and the active area AA. Wiring LL is positioned between the source line driver 100 and the multiplexer 110. Although not shown in the diagram, wiring is also positioned between the source line driver 100 and the pad FPCPAD.

[0097] The difference between the display device 10d in Figure 13 and the display device 10c in Figure 12 is that, in a plan view, the area for arranging the additional shift register 102 is located in two areas corresponding to the lower side of the display gate driver 101 (the same side as the source line driver 100, relative to the display gate driver 101). If the upper area of ​​the active area AA is narrow and the area for arranging the additional shift register 102 cannot be provided in the upper area of ​​the active area AA, it is preferable to arrange the additional shift register 102 in two areas corresponding to the lower side of the display gate driver 101 (two areas on the lower edge of the display panel DISP), as shown in Figure 13. The other configurations of the display device 10d in Figure 13 are the same as the other configurations of the display device 10c in Figure 12, so redundant explanations are omitted.

[0098] The difference between the circuit configuration example corresponding to Configuration Example 2 of the display device 10d shown in Figure 14 and the circuit configuration example of the display device 10 in Figure 4 is that the additional shift register 102a is located below the display gate driver 101, and the transfer signal trn_dm output by the mth shift register S / R_d of the additional shift register 102a is supplied to the input terminal of the first shift register S / R in the display gate driver 101 via a relatively long wiring LL14. The additional shift register 102a is located in two areas corresponding to the area below the display gate driver 101 in Figure 13 (the part of the additional shift register 102 in Figure 13). Since a relatively long wiring LL14 is used, it is preferable to provide a buffer circuit BUF in the middle of the wiring LL14 to amplify and transmit the transfer signal trn_dm. The other configurations of the display device 10d in Figure 14 are the same as the other configurations of the display device 10 in Figure 4, so redundant explanations are omitted.

[0099] (Modification 4) Modification 4 describes a configuration in which the batch precharge period is divided into multiple parts instead of one. Figure 15 shows an example configuration in which the batch precharge period is divided into two parts. Figure 16 shows an example configuration in which the batch precharge period is divided into three parts. Figure 17 shows an example configuration in which the number of signal lines of the internal reset signal Int-XRST is increased in accordance with the number of divisions of the batch precharge period.

[0100] If the difference in LCD response between the top and bottom of the screen is not sufficiently filled even after performing a single precharge, there is a method of dividing the single precharge period TPR1 into two parts (Figure 15: TPR11, TPR12), three parts (Figure 16: TPR11, TPR12, TPR13), etc., and precharging different grayscale potentials.

[0101] In the first batch precharge period (TPR11), all pixels are precharged to the grayscale signal corresponding to gray, similar to the batch precharge period TPR1. The grayscale signal for precharging can also be described as the third grayscale signal between the first grayscale signal corresponding to black and the second grayscale signal corresponding to white. In the second batch precharge period (TPR12), for example, all pixels are precharged to the fourth grayscale signal between the second and third grayscale signals. In the third batch precharge period (TPR13), all pixels are precharged to the fifth grayscale signal between the second and fourth grayscale signals. Alternatively, in the second batch precharge period TPR12, for example, all pixels are precharged to the fourth grayscale signal between the first and third grayscale signals. During the third batch precharge period TPR13, all pixels are precharged to the fifth grayscale signal, which is between the first and fourth grayscale signals.

[0102] In such cases, as shown in Figure 17, it is preferable to increase the number of signal systems for the internal reset signal Int-XRST to match the number of divisions of the batch precharge period, such as the first internal reset signal Int-XRST1, the second internal reset signal Int-XRST2, and the third internal reset signal Int-XRST3.

[0103] The circuit configuration of the display device 10a in Figure 9 will make this clearer. For example, among the gate line drive circuits GD1-GD2n, the first internal reset signal Int-XRST1 can be supplied to gate line drive circuit GD1-GDi, the second internal reset signal Int-XRST2 can be supplied to gate line drive circuit GD(i+1)-GDl, and the third internal reset signal Int-XRST3 can be supplied to gate line drive circuit GD(l+1)-GD2n. The gate line drive circuits GD1-GDi can select a first set of gate lines (Gate_1, ..., Gate_i) from among multiple gate lines (Gate_1, ..., Gate_2n). The gate line drive circuit GD(i+1)-GDl allows selection of a second set of gate lines (Gate_i+1, ..., Gate_l) from among multiple gate lines (Gate_1, ..., Gate_2n). The gate line drive circuit GD(l+1)-GD2n allows selection of a third set of gate lines (Gate_l+1, ..., Gate_2n) from among multiple gate lines (Gate_1, ..., Gate_2n).

[0104] Three sets of set-reset flip-flops (SR-FF) and AND gates (AN) are prepared. The first set generates the first internal reset signal Int-XRST1, the second set generates the second internal reset signal Int-XRST2, and the third set generates the third internal reset signal Int-XRST3.

[0105] In the first set reset flip-flop (SR-FF) of the first set, a transfer signal tnr_d1 is supplied to the set terminal S, and a transfer signal trn_di is supplied to the reset terminal R. The first internal reset signal Int-XRST1 is generated from the first AND circuit AN of the first set.

[0106] In the second set of the second reset flip-flop (SR-FF), a transfer signal tnr_d(i+1) is supplied to the set terminal S, and a transfer signal trn_dl is supplied to the reset terminal R. The second internal reset signal Int-XRST2 is generated from the second AND circuit AN of the second set.

[0107] In the third set of the third reset flip-flop (SR-FF), a transfer signal tnr_d(l+1) is supplied to the set terminal S, and a transfer signal trn_dm-2 is supplied to the reset terminal R. The third internal reset signal Int-XRST3 is generated from the third AND circuit AN of the third set.

[0108] This allows for the precharging of different grayscale potentials in each of the multiple divisions of the batch precharge period, thereby significantly reducing the difference in LCD response between the top and bottom of the screen. This provides a technology that enables improved video characteristics.

[0109] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of this disclosure also fall within the scope of this disclosure, insofar as they encompass the gist of this disclosure.

[0110] Within the scope of the ideas presented hereto, a person skilled in the art will be able to conceive of various modifications and alterations, and such modifications and alterations will also be understood to fall within the scope of this disclosure. For example, any addition, deletion, or design change of components, or addition, omission, or modification of processes, made by a person skilled in the art to the above-described embodiments, will also fall within the scope of this disclosure, as long as they retain the essence of this disclosure.

[0111] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally provided by this disclosure.

[0112] Various disclosures can be formed by appropriately combining the multiple components disclosed in the above embodiments. For example, some components may be removed from all the components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of symbols]

[0113] 10, 10a, 10b, 10c, 10d: Display device, 100: Source driver (Driver IC), 101: Display gate driver, 102: Additional shift register for pre-charge (gate line selection section for pre-charge), Gate_1, Gate_2, ..., Gate_2n: Gate lines (scan lines), Sig, Sg1, Sg2, Sg3, Sg4: Signal lines (source lines) T11: First period, T12: Second period, DISP: Display panel, AA: active area; PIX: pixel, X: 1st direction, Y: Second direction S / R_d: Shift Register S / R: Shift Register GL1-GL2n: Gate wire selection circuit, GD1-GD2n: Gate wire drive circuit.

Claims

1. Multiple gate lines extending in a first direction and adjacent to a second direction intersecting the first direction, A plurality of signal lines extending in the second direction and adjacent to the first direction, A plurality of pixels arranged in a matrix in the first direction and the second direction, A display gate driver that sequentially scans the plurality of gate lines, It includes a pre-charge gate line selection unit that selects the aforementioned multiple gate lines collectively, One frame is, The pre-charge gate line selection unit selects multiple gate lines collectively and writes pre-charge gradation signals from the multiple signal lines to the multiple pixels during the pre-charge period, After the pre-charge period, there is a first period in which the display gate driver sequentially scans the plurality of gate lines and writes grayscale signals corresponding to the video signal to the plurality of pixels from the plurality of signal lines, A display device comprising: a first period followed by a second period in which none of the plurality of gate lines are selected.

2. In the display device according to claim 1, The aforementioned pre-charge grayscale signal corresponds to a third grayscale signal between the first grayscale signal corresponding to black and the second grayscale signal corresponding to white, in a display device.

3. In the display device according to claim 2, The aforementioned precharge period includes a first precharge period and a second precharge period following the first precharge period. During the first precharge period, select a first set of gate lines from the set of gate lines and write the third grayscale signal to all pixels connected to the first set of gate lines from the set of signal lines. A display device that, during the second precharge period, selects a second set of gate lines from among the set of gate lines that are different from the first set of gate lines, and writes a fourth grayscale signal between the third grayscale signal and the second grayscale signal to all pixels connected from the set of signal lines to the second set of gate lines.

4. In the display device according to claim 1, It has a display panel, The display panel has an active region including the plurality of gate lines, the plurality of signal lines, and the plurality of pixels. In a plan view, the aforementioned display panel is, The rectangular active region is located in the central part, The display gate drivers are arranged in the left and right regions of the active region. A display device in which the pre-charge gate line selection unit is located in an area corresponding to the area above the display gate driver.

5. In the display device according to claim 1, It has a display panel, The display panel has an active region including the plurality of gate lines, the plurality of signal lines, and the plurality of pixels. In a plan view, the aforementioned display panel is, The rectangular active region is located in the central part, The display gate drivers are arranged in the left and right regions of the active region. A display device in which the pre-charge gate line selection unit is located in an area corresponding to the area below the display gate driver.

6. In the display device according to claim 1, A display device having a source line driver that supplies grayscale signals to the plurality of signal lines.

7. In the display device according to claim 1, A display device having a control circuit for controlling the activation and deactivation of the pre-charge gate line selection unit.

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