Semiconductor device, method for controlling a semiconductor device, and control program

Abstract

To provide a semiconductor device, a control method for the semiconductor device, and a control program that can achieve high-speed operation while suppressing leakage current. [Solution] The semiconductor device according to the present disclosure comprises: a first electronic circuit including a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage; a second electronic circuit having the same logic configuration as the first electronic circuit and in which the proportion of the second group of semiconductor elements among the first group of semiconductor elements is greater than that of the first electronic circuit; a power supply connection unit for connecting either the first electronic circuit or the second electronic circuit to a power supply; a storage unit for storing power supply connection information; and a control circuit for controlling the power supply connection unit to connect either the first electronic circuit or the second electronic circuit selected based on the power supply connection information read from the storage unit to a power supply.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a control method for a semiconductor device, and a control program, and more particularly to a semiconductor device, a control method for a semiconductor device, and a control program capable of realizing high-speed operation while reducing leakage current.

Background Art

[0002] Patent Document 1 discloses a technique related to a computer system including a dual-core microcomputer capable of switching between a performance mode operating in parallel and a safety mode operating in duplicate comparison. The computer system can set one or more CPUs to interrupt for each interrupt factor. Further, the computer system can set a mode to execute in the performance mode or the safety mode for each interrupt factor.

[0003] In recent years, with the miniaturization of semiconductor processes, the development of semiconductor devices capable of realizing high-speed operation by using many semiconductor elements with low threshold voltages has been advanced.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when trying to speed up the processing of a semiconductor device, there is a problem that the leakage current becomes large particularly under high-temperature conditions. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure includes: a first electronic circuit including a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage; a second electronic circuit having the same logic configuration as the first electronic circuit, and in which the proportion of the second group of semiconductor elements among the first group of semiconductor elements and the second group of semiconductor elements is greater than that of the first electronic circuit; a power supply connection unit connecting either the first electronic circuit or the second electronic circuit to a power supply; a storage unit for storing power supply connection information; and a control circuit for controlling the power supply connection unit to connect either the first electronic circuit or the second electronic circuit selected based on the power supply connection information read from the storage unit to the power supply.

[0007] A semiconductor device control method according to this disclosure comprises: a first electronic circuit including a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage; and a second electronic circuit having the same logic configuration as the first electronic circuit, and in which the proportion of the second group of semiconductor elements among the first group of semiconductor elements and the second group of semiconductor elements is greater than that of the first electronic circuit; the method reads power connection information stored in a memory unit, and connects a power supply to either the first electronic circuit or the second electronic circuit selected based on the read power connection information.

[0008] The control program according to this disclosure is a control program that causes a computer to execute control processing for a semiconductor device comprising: a first electronic circuit including a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage; and a second electronic circuit having the same logical configuration as the first electronic circuit, and in which the proportion of the second group of semiconductor elements among the first group of semiconductor elements and the second group of semiconductor elements is greater than that of the first electronic circuit, the control program causes the computer to execute a process of reading power connection information stored in a memory unit, and a process of connecting either the first electronic circuit or the second electronic circuit selected based on the read power connection information to a power supply. [Effects of the Invention]

[0009] This disclosure provides a semiconductor device capable of high-speed operation while suppressing leakage current, a control method for the semiconductor device, and a control program. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram showing an example configuration of a semiconductor device in the conceptual stage. [Figure 2] Figure 2 is a block diagram showing an example configuration of a semiconductor device according to Embodiment 1. [Figure 3] Figure 3 is a flowchart showing how to replace logical cells. [Figure 4] Figure 4 is a diagram illustrating how to replace logical cells. [Figure 5] Figure 5 is a block diagram showing an example configuration of a semiconductor device in the conceptual stage. [Figure 6] Figure 6 is a block diagram showing an example configuration of a semiconductor device according to Embodiment 2. [Modes for carrying out the invention]

[0011] The embodiments will be described below with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be narrowly interpreted based on their depiction. Furthermore, the same elements are denoted by the same reference numerals, and redundant explanations are omitted.

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated, and one may be a modification, application, detailed explanation, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that specific number.

[0013] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it shall include those that substantially approximate or resemble the shape, etc., unless specifically stated or considered to be not in principle. The same applies to the numbers, etc. (including the number of items, numerical values, quantities, ranges, etc.) mentioned above.

[0014] <Conceptual semiconductor device 50 before reaching Embodiment 1> Figure 1 is a block diagram showing an example configuration of a semiconductor device 50 in the conceptual stage. The semiconductor device 50 is, for example, an MCU (Microcontroller Unit).

[0015] Specifically, the semiconductor device 50 includes a CPU (Central Processing Unit) 101, an SRAM (Static Random Access Memory) 104, an MRAM (Magnetoresistive Random Access Memory) 105, a cache SRAM 106, a peripheral circuit 107, a control circuit 108, a temperature sensor 109, a power supply circuit 110, a bus B1, and a switch SW11.

[0016] The CPU 101 is connected to the SRAM 104, MRAM 105, peripheral circuit 107, and temperature sensor 109 via bus B1. The cache SRAM 106 is directly connected to the CPU 101 without going through bus B1. Switch SW11 is located between the power supply circuit 110 and the CPU 101 and switches on and off based on a control signal from the control circuit 108.

[0017] SRAM 104 and cache SRAM 106 are a type of volatile memory and store programs and the like executed by CPU 101. CPU 101 is an arithmetic processing circuit that sequentially executes program instructions stored in SRAM 104, cache SRAM 106, or MRAM 105. Temperature sensor 109 detects the temperature of semiconductor device 50. More specifically, temperature sensor 109 detects the temperature of CPU 101. Peripheral circuit 107 operates in cooperation with CPU 101. Peripheral circuit 107 may include an analog circuit, a communication circuit for communicating with the outside, and the like. MRAM 105 is a type of non-volatile memory and stores programs executed by CPU 101, trimming information of the analog circuit provided in peripheral circuit 107, and the like.

[0018] Control circuit 108 resets CPU 101 and peripheral circuit 107 based on, for example, a reset signal (not shown) supplied to the reset terminal of semiconductor device 50 or an instruction from CPU 101. Then, based on the trimming information and the like read from MRAM 105, control circuit 108 performs initial setting of peripheral circuit 107, and then releases the reset of CPU 101 and peripheral circuit 107 and supplies a clock signal to operate the entire system of semiconductor device 50. Also, when the operation mode is set to the standby mode in which at least part of the operation of semiconductor device 50 is stopped to reduce power consumption, control circuit 108 stops the power supply from power supply circuit 110 to CPU 101 by switching switch SW11 from on to off. Thereafter, control circuit 108 maintains switch SW11 in the off state until a specific return factor is input.

[0019] CPU 101 is composed of a plurality of logic cells with a threshold voltage of LVt (hereinafter referred to as LVt cells) and a plurality of logic cells with a threshold voltage of HVt (hereinafter referred to as HVt cells). Note that LVt < HVt. For example, LVt is 0.3V and HVt is 0.5V.

[0020] The LVt cell is composed of a plurality of MOS transistors with a threshold voltage of LVt. Therefore, in the LVt cell, the operating speed is fast (the time from input to output is short), but the leakage current is large. Note that the LVt cell is not limited to the case where it is composed of a plurality of MOS transistors with a threshold voltage of LVt, and it may be composed of a plurality of semiconductor elements that switch conduction / non-conduction from one end to the other end based on whether the control voltage is equal to or higher than the threshold voltage LVt.

[0021] On the other hand, the HVt cell is composed of a plurality of MOS transistors with a threshold voltage of HVt. Therefore, in the HVt cell, the operating speed is slow (the time from input to output is long), but the leakage current is small. Note that the HVt cell is not limited to the case where it is composed of a plurality of MOS transistors with a threshold voltage of HVt, and it may be composed of a plurality of semiconductor elements that switch conduction / non-conduction from one end to the other end based on whether the control voltage is equal to or higher than the threshold voltage HVt.

[0022] Here, the CPU 101 is composed of more LVt cells than HVt cells in order to achieve high-speed operation. In other words, the CPU 101 is composed of more MOS transistors with a threshold voltage of LVt than MOS transistors with a threshold voltage of HVt. Therefore, in the CPU 101, the operating speed is fast (that is, the maximum operating frequency is high), but the leakage current is large. Especially due to the miniaturization of the process in recent years, the leakage current becomes significantly larger as the temperature rises. However, in the CPU 101 dominated by LVt cells, even if the operating frequency is lowered because of the high temperature, only the dynamic current associated with switching is reduced, and the significantly increased leakage current is not reduced. Therefore, the CPU 101 is suitable for high-speed operation under low-temperature conditions, but may not be suitable for low-power consumption operation under high-temperature conditions. In the present disclosure, the case where the maximum operating frequency of the CPU 101 is 800 MHz will be described as an example.

[0023] Thus, while the conceptual semiconductor device 50 can achieve high-speed operation under low-temperature conditions, it has the problem of increasing leakage current, especially under high-temperature conditions. Therefore, a semiconductor device 1 according to the present disclosure has been found that solves this problem and can achieve high-speed operation under low-temperature conditions while reducing leakage current, especially under high-temperature conditions.

[0024] <Embodiment 1> Figure 2 is a block diagram showing an example configuration of semiconductor device 1 according to Embodiment 1. Semiconductor device 1 is, for example, an MCU.

[0025] Compared to semiconductor device 50, semiconductor device 1 further includes a CPU 102, selectors SEL11 and SEL12, and a switch SW12. Specifically, semiconductor device 1 includes a CPU (first electronic circuit) 101, a CPU (second electronic circuit) 102, an SRAM 104, an MRAM 105, a cache SRAM 106, a peripheral circuit 107, a control circuit 108, a temperature sensor 109, a power supply circuit (power supply) 110, a bus B1, selectors SEL11 and SEL12, and switches SW11 and SW12.

[0026] CPU 102 has the same logical configuration as CPU 101. Like CPU 101, CPU 102 is composed of multiple LVt cells and multiple HVt cells. However, the proportion of HVt cells among the multiple logical cells used in CPU 102 is larger than that of CPU 101. Therefore, CPU 102 operates at a slower speed than CPU 101 (i.e., the maximum operating frequency of CPU 102 is lower than that of CPU 101), but the leakage current is lower than that of CPU 101. As a result, the increase in leakage current, which was particularly pronounced at high temperatures, is suppressed in CPU 102. In this disclosure, the case where the maximum operating frequency of CPU 102 is 400 MHz will be explained as an example.

[0027] Switch SW11 is located between the power supply circuit 110 and the CPU 101 and switches on and off based on a control signal from the control circuit 108. Switch SW12 is located between the power supply circuit 110 and the CPU 102 and switches on and off based on a control signal from the control circuit 108. Switches SW11 and SW12 constitute the power supply connection section and, when the operating mode is normal operating mode, switch on and off complementaryly based on a control signal from the control circuit 108, and when the operating mode is standby mode, both are turned off based on a control signal from the control circuit 108.

[0028] Selector SEL11 selects either a signal from CPU101 to bus B1 or a signal from CPU102 to bus B1 and outputs it to bus B1. The signal from bus B1 is input to either CPU101 or 102. Selector SEL12 selects either a signal from CPU101 to cache SRAM106 or a signal from CPU102 to cache SRAM106 and outputs it to cache SRAM106. The signal from cache SRAM106 is input to either CPU101 or 102.

[0029] In addition to the program executed by the CPU 101 and the trimming information of the analog circuit, the MRAM 105 also stores frequency setting information. Here, frequency setting information refers to the information of the maximum operating frequency required by the CPU. The frequency setting information can also be described as power connection information that determines which CPU among CPUs 101 and 102 the power supply circuit 110 is connected to.

[0030] The control circuit 108 resets the CPUs 101, 102 and peripheral circuits 107 based on a reset signal (not shown) supplied to the reset terminal of the semiconductor device 50, or an instruction from one of the CPUs 101 or 102 connected to the power supply circuit 110. Then, it performs initial setup of the peripheral circuits 107 based on trimming information read from the MRAM 105, and connects the power supply circuit 110 to either the CPU 101 or 102 based on frequency setting information read from the MRAM 105. Specifically, the control circuit 108 outputs control signals corresponding to the frequency setting information read from the MRAM 105 to switches SW11, SW12 and selectors SEL11, SEL12. As a result, switches SW11 and SW12 connect the CPU corresponding to the frequency setting information to the power supply circuit 110. Selectors SEL11 and SEL12 connect the signal lines between the CPU connected to the power supply circuit 110 and bus B1 and cache SRAM 106. Subsequently, the control circuit 108 activates the semiconductor device 1 system by releasing the reset of the CPU and peripheral circuits 107 connected to the power supply circuit 110 and supplying a clock signal.

[0031] When the operating mode is set to standby mode, the control circuit 108 stops supplying power from the power supply circuit 110 to the CPUs 101 and 102 by switching switches SW11 and SW12 from on to off. The control circuit 108 then maintains switches SW11 and SW12 in the off state until a specific recovery event is triggered.

[0032] In this disclosure, the maximum operating frequency of CPU 101 is 800MHz, and the maximum operating frequency of CPU 102 is 400MHz. Therefore, when 800MHz is set as the frequency setting information in MRAM 105, the control circuit 108 controls switch SW11 to ON and switch SW12 to OFF. In other words, the power connection section consisting of switches SW11 and SW12 selects CPU 101 as the connection destination for the power supply circuit 110. As a result, power voltage is supplied from the power supply circuit 110 to CPU 101. At this time, selector SEL11 selects the signal from CPU 101, which has been selected as the connection destination for the power supply circuit 110, from among the signals from CPU 101 to bus B1 and signals from CPU 102 to bus B1, and outputs it to bus B1. Selector SEL12 also selects the signal from CPU 101, which has been selected as the connection destination for the power supply circuit 110, from among the signals from CPU 101 to cache SRAM 106 and signals from CPU 102 to cache SRAM 106, and outputs it to cache SRAM 106.

[0033] In contrast, when 400MHz is set as the frequency setting information in MRAM105, the control circuit 108 controls switch SW11 to turn off and switch SW12 to turn on. In other words, the power connection section consisting of switches SW11 and SW12 selects CPU102 as the connection destination for the power supply circuit 110. As a result, power voltage is supplied from the power supply circuit 110 to CPU102. At this time, selector SEL11 selects the signal from CPU102, which was selected as the connection destination for the power supply circuit 110, from among the signals from CPU101 to bus B1 and the signals from CPU102 to bus B1, and outputs it to bus B1. Selector SEL12 also selects the signal from CPU102, which was selected as the connection destination for the power supply circuit 110, from among the signals from CPU101 to cache SRAM106 and the signals from CPU102 to cache SRAM106, and outputs it to cache SRAM106.

[0034] (How to replace logical cells) Using Figures 3 and 4, we will explain how to form the logical structure of CPU 102 by replacing some of the multiple LVt cells used in CPU 101 with HVt cells, starting from the logical structure of CPU 101. Figure 3 is a flowchart of the method for replacing logical cells. Figure 4 is a diagram illustrating the method for replacing logical cells.

[0035] First, prepare CPU 101 (step S101). Preparing CPU 101 means, for example, preparing the logical structure of CPU 101 in the logical design environment.

[0036] The upper diagram of Figure 4 shows flip-flops 301 and 302, and logic cells 401 to 404, which are LVt cells, as part of the CPU 101 circuit. Logic cell 401 is a logical AND circuit, logic cell 402 is a logical OR circuit, logic cell 403 is a buffer circuit, and logic cell 404 is a logical AND circuit.

[0037] Furthermore, the upper part of Figure 4 shows the results of a timing analysis when the CPU 101 is operated at its maximum operating frequency of 800MHz. In the example shown in the upper part of Figure 4, the signal propagation time from flip-flop 301 to flip-flop 302 via logic cells 401 to 404 must be 1.25ns (=1 / 800MHz) or less. However, for the sake of simplicity, wiring delays, setup time constraints, and hold time constraints are not considered. In the example shown in the upper part of Figure 4, the delay time of logic cell 401 is 0.3ns, the delay time of logic cell 402 is 0.2ns, the delay time of logic cell 403 is 0.4ns, and the delay time of logic cell 404 is 0.3ns. The signal propagation time is 1.2ns, which is less than or equal to 1.25ns, so the timing constraint is satisfied.

[0038] Subsequently, all LVt cells used in CPU 101 are replaced with HVt cells (step S102). Hereafter, CPU 101 in which all LVt cells have been replaced with HVt cells will be referred to as CPU 101a.

[0039] The middle diagram in Figure 4 shows flip-flops 301 and 302, and logic cells 411 to 414, which are HVt cells, as part of the CPU 101a circuit. In other words, in the example in the middle diagram of Figure 4, the logic cells 401 to 404, which are LVt cells, are replaced with logic cells 411 to 414, which are HVt cells, in the circuit shown in the upper diagram of Figure 4.

[0040] Subsequently, a timing analysis is performed when CPU 101a is operated at 400MHz, which is the maximum operating frequency of CPU 102 (step S103).

[0041] If the timing analysis reveals that there are paths that do not satisfy the timing constraints (YES in step S104), the paths that do not satisfy the timing constraints are extracted (step S105), and some of the HVt cells located on the extracted paths are replaced with LVt cells (step S106). In some cases, all HVt cells located on the extracted paths may be replaced with LVt cells in order to satisfy the timing constraints. However, it is preferable to minimize the replacement of HVt cells with LVt cells as much as possible while still satisfying the timing constraints.

[0042] The middle diagram in Figure 4 shows the results of a timing analysis when CPU 101a is operated at the maximum operating frequency of CPU 102, which is 400 MHz. In the example in the middle diagram of Figure 4, the signal propagation time from flip-flop 301 to flip-flop 302 via logic cells 411 to 414 must be 2.5 ns (= 1 / 400 MHz) or less. However, for the sake of simplicity, wiring delays, setup time constraints, and hold time constraints are not considered. In the example in the middle diagram of Figure 4, the delay time of logic cell 411 is 0.7 ns, the delay time of logic cell 412 is 0.5 ns, the delay time of logic cell 413 is 0.8 ns, and the delay time of logic cell 414 is 0.7 ns. The signal propagation time is 2.7 ns, which is greater than 2.5 ns, so the timing constraint is not met.

[0043] Therefore, in order to satisfy the timing constraints, some of the HVt cells used in CPU 101a are replaced with LVt cells (steps S105 to S106). Hereafter, CPU 101a in which some HVt cells have been replaced with LVt cells will be referred to as CPU 101b.

[0044] The lower diagram of Figure 4 shows flip-flops 301 and 302, and logic cells 411 (HVt cell), 402 (LVt cell), 413 (HVt cell), and 414 (HVt cell) as part of the CPU 101b circuit. In other words, in the example shown in the lower diagram of Figure 4, logic cell 412 (HVt cell) is replaced with logic cell 402 (LVt cell) in the circuit shown in the middle diagram of Figure 4.

[0045] Subsequently, a timing analysis is performed when CPU 101b is operated at 400MHz, which is the maximum operating frequency of CPU 102 (step S103).

[0046] If the timing analysis reveals that there are paths that do not satisfy the timing constraints (YES in step S104), the paths that do not satisfy the timing constraints are extracted (step S105), and some of the HVt cells located on the extracted paths are replaced with LVt cells (step S106). If all paths satisfy the timing constraints (NO in step S104), the logical cell replacement is completed.

[0047] The lower part of Figure 4 shows the results of a timing analysis when CPU 101b is operated at the maximum operating frequency of CPU 102, which is 400 MHz. In the example shown in the lower part of Figure 4, the signal propagation time from flip-flop 301 to flip-flop 302 via logic cells 411, 402, 413, and 414 must be 2.5 ns or less. However, for the sake of simplicity, wiring delays, setup time constraints, and hold time constraints are not considered. In this example, the delay time of logic cell 411 is 0.7 ns, the delay time of logic cell 402 is 0.2 ns, the delay time of logic cell 413 is 0.8 ns, and the delay time of logic cell 414 is 0.7 ns. The signal propagation time is 2.4 ns, which is less than or equal to 2.5 ns, thus satisfying the timing constraint.

[0048] A CPU101b that satisfies all timing constraints will be used as CPU102. In other words, the logical structure of a CPU101b that satisfies all timing constraints will be used as the logical structure of CPU102.

[0049] In this way, CPU 102 is formed by replacing as many LVt cells as possible used in CPU 101 with HVt cells.

[0050] (Method for dynamic switching between CPUs 101 and 102) The semiconductor device 1 is configured to dynamically switch between the CPUs 101 and 102 that are in operation.

[0051] For example, if the power supply circuit 110 is connected to the CPU 101, and the temperature sensor 109 detects that the temperature of the CPU 101 is above a predetermined temperature, the leakage current of the CPU 101, which uses many LVt cells, may increase. Therefore, the semiconductor device 1 switches the CPU it operates from CPU 101 to CPU 102, which uses many HVt cells.

[0052] First, the CPU 101 updates the frequency setting information stored in the MRAM 105 from 800MHz to 400MHz. In other words, the CPU 101 updates the frequency setting information stored in the MRAM 105 to information that instructs the power supply circuit 110 to switch the connection destination from CPU 101 to CPU 102.

[0053] Subsequently, the control circuit 108 resets the CPU 102 and peripheral circuits 107 based on instructions from the CPU 101, then initializes the peripheral circuits 107 based on trimming information read from the MRAM 105, and connects the power supply circuit 110 to either the CPU 101 or 102 based on frequency setting information read from the MRAM 105. Specifically, the control circuit 108 switches the connection destination of the power supply circuit 110 from the CPU 101 to the CPU 102 based on the frequency setting information read from the MRAM 105. After that, the control circuit 108 releases the reset of the CPU 102 and peripheral circuits 107 and supplies a clock signal to operate the semiconductor device 1 system.

[0054] Furthermore, for example, if the power supply circuit 110 is connected to the CPU 102, and the temperature sensor 109 detects that the temperature of the CPU 101 is below a predetermined temperature, the leakage current of the CPU 101, which uses many LVt cells, will decrease. Therefore, if the semiconductor device 1 wants to increase the operating speed, for example, it will switch the CPU being operated from CPU 102 to CPU 101.

[0055] First, CPU 102 updates the frequency setting information stored in MRAM 105 to information instructing the power supply circuit 110 to switch the connection destination from CPU 102 to CPU 101. Specifically, CPU 102 updates the frequency setting information stored in MRAM 105 from 400MHz to 800MHz.

[0056] Subsequently, the control circuit 108 resets the CPU 101 and peripheral circuits 107 based on instructions from the CPU 102, then initializes the peripheral circuits 107 based on trimming information read from the MRAM 105, and connects the power supply circuit 110 to either the CPU 101 or 102 based on frequency setting information read from the MRAM 105. Specifically, the control circuit 108 switches the connection destination of the power supply circuit 110 from the CPU 102 to the CPU 101 based on the frequency setting information read from the MRAM 105. After that, the control circuit 108 releases the reset of the CPU 101 and peripheral circuits 107 and supplies a clock signal to operate the semiconductor device 1 system.

[0057] Thus, the semiconductor device 1 according to this disclosure can achieve high-speed operation at low temperatures while reducing leakage current, especially at high temperatures, by switching between a CPU 101 that uses many LVt cells and a CPU 102 that uses many HVt cells. In other words, the semiconductor device 1 according to this disclosure can achieve high-speed operation while reducing leakage current. The design of the semiconductor device 1 according to this disclosure is simple, requiring only the addition of a CPU 102, selectors SEL11 and SEL12, and a switch SW12 to the configuration of the semiconductor device 50. Program designers can easily design the semiconductor device 1 without being aware that there are two CPUs.

[0058] Furthermore, multiple semiconductor devices with different maximum operating frequencies may be shipped as products from multiple semiconductor devices 1. For example, from multiple semiconductor devices 1, a semiconductor device 1a with a maximum operating frequency of 800 MHz and a semiconductor device 1b with a maximum operating frequency of 400 MHz may be shipped as separate products.

[0059] In this case, the MRAM105 further stores a permission flag in a hidden memory area indicating whether or not to allow updating the frequency setting information (power connection information). For example, if the permission flag is "1" (active), updating the frequency setting information is permitted, and if the permission flag is "0" (inactive), updating the frequency setting information is not permitted.

[0060] For example, when semiconductor device 1a with a maximum operating frequency of 800MHz is shipped as a product, "800MHz" is written to MRAM105 as frequency setting information, and the enable flag is set to "1" to indicate update permission. Similarly, when semiconductor device 1b with a maximum operating frequency of 400MHz is shipped as a product, "400MHz" is written to MRAM105 as frequency setting information, and the enable flag is set to "0" to indicate update permission.

[0061] <Conceptual semiconductor device 60 before reaching Embodiment 2> Figure 5 is a block diagram showing an example configuration of a semiconductor device 60 in the conceptual stage. The semiconductor device 60 is, for example, an MCU equipped with a communication circuit.

[0062] Specifically, the semiconductor device 60 includes a communication circuit 201, a CPU 203, an SRAM 204, an MRAM 205, a control circuit 208, a temperature sensor 209, a power supply circuit 210, a bus B2, and a switch SW21. The temperature sensor 209 detects the temperature of the semiconductor device 60. More specifically, the temperature sensor 209 detects the temperature of the communication circuit 201.

[0063] The CPU 203 is connected to the SRAM 204, MRAM 205, control circuit 208, temperature sensor 209, and communication circuit 201 via bus B2. Switch SW21 is located between the power supply circuit 210 and the communication circuit 201. The communication circuit 201 is used for communication with the outside world.

[0064] When the CPU 203 and communication circuit 201 transmit data to the outside of the semiconductor device 60, they perform the following operations. First, the CPU 203 sets the communication speed and initializes the address of the transmit buffer, etc., for the communication circuit 201. Then, the CPU 203 writes the data for the transmission unit to the transmit buffer of the communication circuit 201 and then sets the register for the transmission start instruction of the communication circuit 201. As a result, the communication circuit 201 transmits the written data to the outside of the semiconductor device 60. After that, the CPU 203 monitors the transmission completion flag of the communication circuit 201 and waits for the transmission to be completed.

[0065] The control circuit 208 controls the on / off state of switch SW21 based on setting information read from a predetermined register. When switch SW21 is turned on, power is supplied from the power supply circuit 210 to the communication circuit 201, making the communication circuit 201 operational. On the other hand, when switch SW21 is turned off, the power supply from the power supply circuit 210 to the communication circuit 201 is cut off, reducing the leakage current of the communication circuit 201.

[0066] Here, the communication circuit 201 is configured using more LVt cells than HVt cells to achieve high-speed operation. In other words, the communication circuit 201 is configured using more MOS transistors with a threshold voltage of LVt than MOS transistors with a threshold voltage of HVt. Therefore, the communication circuit 201 has a high operating speed (i.e., a high maximum operating frequency), but the leakage current is large. In particular, with the miniaturization of processes in recent years, the leakage current increases significantly as the temperature rises. However, in the communication circuit 201, which is dominated by LVt cells, even if the operating frequency is lowered at a high temperature, only the dynamic current associated with switching is reduced, and the significantly increased leakage current is not reduced. Therefore, the communication circuit 201 is suitable for high-speed operation under low-temperature conditions, but may not be suitable for low-current-consumption operation under high-temperature conditions. In this disclosure, the case where the maximum operating frequency of the communication circuit 201 is 800 MHz will be explained as an example.

[0067] Thus, while the conceptual semiconductor device 60 can achieve high-speed operation under low-temperature conditions, it has the problem of increasing leakage current, especially under high-temperature conditions. Therefore, a semiconductor device 2 according to this disclosure has been found that solves this problem and can achieve high-speed operation under low-temperature conditions while reducing leakage current, especially under high-temperature conditions.

[0068] <Embodiment 2> Figure 6 is a block diagram showing an example configuration of the semiconductor device 2 according to Embodiment 2. The semiconductor device 2 is, for example, an MCU equipped with a communication circuit.

[0069] Compared to semiconductor device 60, semiconductor device 2 further includes a communication circuit 202, a selector SEL21, and a switch SW22. Specifically, semiconductor device 2 includes a communication circuit (first electronic circuit) 201, a communication circuit (second electronic circuit) 202, a CPU 203, an SRAM 204, an MRAM 205, a control circuit 208, a temperature sensor 209, a power supply circuit (power supply) 210, a bus B2, a selector SEL21, and switches SW21 and SW22.

[0070] Communication circuit 202 has the same logic configuration as communication circuit 201. Like communication circuit 201, communication circuit 202 is composed of multiple LVt cells and multiple HVt cells. However, the proportion of HVt cells among the multiple logic cells used in communication circuit 202 is larger than that of communication circuit 201. Therefore, the operating speed of communication circuit 202 is slower than that of communication circuit 201 (i.e., the maximum operating frequency of communication circuit 202 is lower than that of communication circuit 201), but the leakage current is lower than that of communication circuit 201. As a result, the increase in leakage current, which was particularly pronounced at high temperatures, is suppressed in communication circuit 202. In this disclosure, the case where the maximum operating frequency of communication circuit 202 is 400 MHz will be explained as an example.

[0071] Switch SW21 is located between the power supply circuit 210 and the communication circuit 201 and switches on and off based on a control signal from the control circuit 208. Switch SW22 is located between the power supply circuit 210 and the communication circuit 202 and switches on and off based on a control signal from the control circuit 208. Switches SW21 and SW22 constitute the power supply connection section and, when the operating mode is normal operating mode, switch on and off complementaryly based on a control signal from the control circuit 208, and when the operating mode is standby mode, both are turned off based on a control signal from the control circuit 208.

[0072] Selector SEL21 selects either a signal from communication circuit 201 to bus B2 or a signal from communication circuit 202 to bus B2 and outputs it to bus B1. The signal from bus B1 is input to either communication circuit 201 or 202.

[0073] The MRAM205 stores frequency setting information. Here, frequency setting information refers to the information of the maximum operating frequency required for the communication circuit. The frequency setting information can also be described as power connection information that determines which communication circuit among the communication circuits 201 and 202 the power supply circuit 210 is connected to.

[0074] The control circuit 208, for example, receives instructions from the CPU 203 and connects the power supply circuit 210 to one of the communication circuits 201 or 202 based on the frequency setting information read from the MRAM 205. Specifically, the control circuit 208 outputs control signals corresponding to the frequency setting information read from the MRAM 205 to switches SW21, SW22 and selector SEL21. As a result, switches SW21 and SW22 connect the power supply circuit 210 to the communication circuit corresponding to the frequency setting information among the communication circuits 201 and 202. Selector SEL21 connects the signal line between the communication circuit connected to the power supply circuit 210 and bus B2. After that, the control circuit 208 resets the communication circuit connected to the power supply circuit 210 and then activates the communication function of the semiconductor device 2 by supplying a clock signal.

[0075] In this disclosure, the maximum operating frequency of communication circuit 201 is 800 MHz, and the maximum operating frequency of communication circuit 202 is 400 MHz. Therefore, when 800 MHz is set as the frequency setting information in MRAM 205, the control circuit 208 controls switch SW21 to turn ON and switch SW22 to turn OFF. In other words, the power connection section consisting of switches SW21 and SW22 selects communication circuit 201 as the connection destination for power supply circuit 210. As a result, power voltage is supplied from power supply circuit 210 to communication circuit 201. At this time, selector SEL21 selects the signal from communication circuit 201, which is selected as the connection destination for power supply circuit 210, from among the signals from communication circuit 201 to bus B2 and signals from communication circuit 202 to bus B2, and outputs it to bus B2.

[0076] In contrast, when 400MHz is set as the frequency setting information in MRAM205, the control circuit 208 controls switch SW21 to turn off and switch SW22 to turn on. In other words, the power connection section consisting of switches SW21 and SW22 selects the communication circuit 202 as the connection destination for the power supply circuit 210. As a result, power voltage is supplied from the power supply circuit 210 to the communication circuit 202. At this time, the selector SEL21 selects the signal from the communication circuit 202, which was selected as the connection destination for the power supply circuit 210, from among the signals from the communication circuit 201 toward bus B2 and the signals from the communication circuit 202 toward bus B2, and outputs it to bus B2.

[0077] (Method for dynamic switching of communication circuits 201 and 202) The semiconductor device 2 is configured to dynamically switch which of the communication circuits 201 and 202 is activated.

[0078] For example, if the power supply circuit 210 is connected to the communication circuit 201, and the temperature sensor 209 detects that the temperature of the communication circuit 201 is above a predetermined temperature, the leakage current of the communication circuit 201, which uses many LVt cells, may increase. Therefore, the semiconductor device 2 switches the communication circuit it operates from the communication circuit 201 to the communication circuit 202, which uses many HVt cells. This will be explained in detail below.

[0079] If the temperature sensor 209 detects that the temperature of the communication circuit 201 is above a predetermined temperature, the CPU 203 first waits for the transmission completion flag of the communication circuit 201 to become active and for the transmission of the data to be completed. Then, the CPU 203 updates the frequency setting information stored in the MRAM 205 from 800MHz to 400MHz. That is, the CPU 203 updates the frequency setting information stored in the MRAM 205 to information that instructs the power supply circuit 210 to switch its connection destination from the communication circuit 201 to the communication circuit 202.

[0080] Subsequently, the control circuit 208, upon receiving instructions from the CPU 203, connects the power supply circuit 210 to either the communication circuit 201 or 202 based on the frequency setting information read from the MRAM 205. Specifically, the control circuit 208 switches the connection destination of the power supply circuit 210 from the communication circuit 201 to the communication circuit 202 based on the frequency setting information read from the MRAM 205. After that, the control circuit 208 resets the communication circuit 202 and then starts the communication operation by the communication circuit 202.

[0081] Furthermore, for example, if the power supply circuit 210 is connected to the communication circuit 202, and the temperature sensor 209 detects that the temperature of the communication circuit 201 is below a predetermined temperature, the leakage current of the communication circuit 201, which uses many LVt cells, will decrease. Therefore, if the semiconductor device 2 wants to increase the operating speed, for example, it switches the communication circuit being operated from communication circuit 202 to communication circuit 201. This will be explained in detail below.

[0082] If the temperature sensor 209 detects that the temperature of the communication circuit 201 is below a predetermined temperature, the CPU 203 first waits for the transmission completion flag of the communication circuit 201 to become active and for the transmission of the data to be completed. Then, the CPU 203 updates the frequency setting information stored in the MRAM 205 from 400MHz to 800MHz. That is, the CPU 203 updates the frequency setting information stored in the MRAM 205 to information that instructs the power supply circuit 210 to switch its connection destination from the communication circuit 202 to the communication circuit 201.

[0083] Subsequently, the control circuit 208, upon receiving instructions from the CPU 203, connects the power supply circuit 210 to either the communication circuit 201 or 202 based on the frequency setting information read from the MRAM 205. Specifically, the control circuit 208 switches the connection destination of the power supply circuit 210 from the communication circuit 202 to the communication circuit 201 based on the frequency setting information read from the MRAM 205. After that, the control circuit 208 resets the communication circuit 201 and then starts the communication operation by the communication circuit 201.

[0084] Thus, the semiconductor device 2 according to this disclosure can achieve high-speed operation under low-temperature conditions while reducing leakage current, especially under high-temperature conditions, by switching between a communication circuit 201 that uses many LVt cells and a communication circuit 202 that uses many HVt cells. In other words, the semiconductor device 2 according to this disclosure can achieve high-speed operation while reducing leakage current. The design of the semiconductor device 2 according to this disclosure is simple, requiring only the addition of a communication circuit 202, a selector SEL21, and a switch SW22 to the configuration of the semiconductor device 60. Furthermore, since the address spaces of communication circuits 201 and 202 are the same, the programmer can easily design the semiconductor device 2 without being aware that there are two communication circuits.

[0085] This disclosure describes, but is not limited to, cases in which a semiconductor device dynamically switches between operating a CPU 101 that uses many LVt cells and a CPU 102 that uses many HVt cells, or a communication circuit 201 that uses many LVt cells and a communication circuit 202 that uses many HVt cells. The semiconductor device may also include circuits other than the CPU and communication circuits that use many LVt cells and circuits that use many HVt cells, and operate them by dynamically switching between them. Furthermore, the configurations of CPUs 101 and 102 and the configurations of communication circuits 201 and 202 may be used in combination. Moreover, dynamic switching is not limited to cases where it is performed based on the detection result of a temperature sensor, but may also be performed based on other factors.

[0086] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention.

[0087] This disclosure can be realized by having a CPU execute a computer program to perform some or all of the processing of each semiconductor device 1, 2.

[0088] The program described above includes, when loaded into a computer, a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored in a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive), or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray® disc, or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically, or otherwise propagating signals. [Explanation of symbols]

[0089] 1 Semiconductor device 1a Semiconductor device 1b Semiconductor equipment 2 Semiconductor devices 50 Semiconductor Equipment 60 Semiconductor Devices 101 CPU 101a CPU 101b CPU 102 CPU 104 SRAM 105 MRAM 106 cache SRAM 107 Peripheral Circuits 108 Control circuits 109 Temperature Sensor 110 Power supply circuit 201 Communication Circuit 202 Communication Circuit 203 CPU 204 SRAM 205 MRAM 208 Control circuits 209 Temperature Sensor 210 Power supply circuit 301 Flip-flops (FF) 302 Flip-flops (FF) 401-404 Logical Cells 411-414 Logical Cells B1 Bus B2 Bus SEL11 Selector SEL12 Selector SEL21 Selector SW11 Switch SW12 Switch SW21 Switch SW22 Switch

Claims

1. A first electronic circuit comprising a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage, A second electronic circuit having the same logic configuration as the first electronic circuit, and in which the proportion of the second semiconductor element group among the first semiconductor element group and the second semiconductor element group is greater than that of the first electronic circuit, A power supply connection section that connects either the first electronic circuit or the second electronic circuit to a power supply, A storage unit that stores power connection information, A control circuit controls the power supply connection unit to connect either the first electronic circuit or the second electronic circuit selected based on the power supply connection information read from the storage unit to the power supply, A semiconductor device equipped with [the necessary components].

2. The first electronic circuit is further provided with a temperature sensor for detecting the temperature of the first electronic circuit. When the power supply is connected to the first electronic circuit, and the temperature sensor detects that the temperature of the first electronic circuit is above a predetermined temperature, the control circuit controls the power supply connection unit to switch the power supply connection destination from the first electronic circuit to the second electronic circuit based on the power supply connection information read from the storage unit. The semiconductor device according to claim 1.

3. When the power supply is connected to the first electronic circuit, and the temperature sensor detects that the temperature of the first electronic circuit is above a predetermined temperature, the first electronic circuit updates the power supply connection information stored in the storage unit to information instructing the power supply to be switched from the first electronic circuit to the second electronic circuit. The semiconductor device according to claim 2.

4. When the power supply is connected to the second electronic circuit, and the temperature sensor detects that the temperature of the first electronic circuit is below a predetermined temperature, the control circuit controls the power supply connection unit to switch the power supply connection destination from the second electronic circuit to the first electronic circuit based on the power supply connection information read from the storage unit. The semiconductor device according to claim 3.

5. When the power supply is connected to the second electronic circuit, and the temperature sensor detects that the temperature of the first electronic circuit is below a predetermined temperature, the second electronic circuit updates the power supply connection information stored in the storage unit to information instructing the power supply to be switched from the second electronic circuit to the first electronic circuit. The semiconductor device according to claim 4.

6. Both the first electronic circuit and the second electronic circuit are arithmetic processing circuits that execute program instructions. The semiconductor device according to claim 1.

7. The storage unit further stores a permission flag indicating whether or not to allow the updating of the power connection information. The aforementioned power connection information is configured to be updatable only when the permission flag is active. The semiconductor device according to claim 1.

8. Both the first electronic circuit and the second electronic circuit are communication circuits that communicate with the outside world. The semiconductor device according to claim 1.

9. The first electronic circuit is configured to operate at a higher maximum operating frequency than the second electronic circuit. The semiconductor device according to claim 1.

10. The power connection information includes information on the maximum operating frequency. The semiconductor device according to claim 9.

11. The aforementioned storage unit is a non-volatile memory. The semiconductor device according to claim 1.

12. When the operating mode is the normal operating mode, the control circuit controls the power supply connection unit to connect the power supply to either the first electronic circuit or the second electronic circuit selected based on the power supply connection information read from the storage unit. When the operating mode is standby mode, the control circuit controls the power supply connection section to disconnect the connection between the first electronic circuit and the second electronic circuit and the power supply. The semiconductor device according to claim 1.

13. A first electronic circuit comprising a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage, A second electronic circuit having the same logic configuration as the first electronic circuit, and in which the proportion of the second semiconductor element group among the first semiconductor element group and the second semiconductor element group is greater than that of the first electronic circuit, A control method for a semiconductor device, comprising: The power connection information stored in the memory unit is read out. Connect the power supply to either the first electronic circuit or the second electronic circuit selected based on the power supply connection information read out. A method for controlling a semiconductor device.

14. When the power supply is connected to the first electronic circuit, and the temperature sensor detects that the temperature of the first electronic circuit is above a predetermined temperature, the power supply is switched from the first electronic circuit to the second electronic circuit based on the power supply connection information read out. A method for controlling a semiconductor device according to claim 13.

15. A first electronic circuit comprising a first group of semiconductor elements having a first threshold voltage and a second group of semiconductor elements having a second threshold voltage higher than the first threshold voltage, A second electronic circuit having the same logic configuration as the first electronic circuit, and in which the proportion of the second semiconductor element group among the first semiconductor element group and the second semiconductor element group is greater than that of the first electronic circuit, A control program that causes a computer to perform control processing for a semiconductor device, comprising: The process of reading power connection information stored in the memory unit, A process of connecting either the first electronic circuit or the second electronic circuit selected based on the power supply connection information read out, to a power supply, A control program that instructs a computer to execute a command.

16. In the process of connecting either the first electronic circuit or the second electronic circuit to the power supply, if the power supply is connected to the first electronic circuit, and the temperature sensor detects that the temperature of the first electronic circuit is above a predetermined temperature, the power supply is switched from the first electronic circuit to the second electronic circuit based on the power supply connection information read out. The control program according to claim 15.

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