Memory system

Abstract

This system aims to suppress the degradation of access performance to non-volatile memory. [Solution] According to the embodiment, the memory system comprises a plurality of memory chips, each containing a plurality of first blocks, and a controller. The controller controls a plurality of parallel access units to which a plurality of second blocks, which are sets of at least one block allocated from a plurality of first blocks contained in each of the plurality of memory chips, belong. The controller manages conversion information for each memory chip, which is defined so that the number of initial bad blocks belonging to each of the plurality of parallel access units is less than or equal to an acceptable number. The controller generates management information indicating whether the number of bad blocks belonging to a plurality of third blocks, to which a plurality of second blocks belonging to a parallel access unit belong, are less than or equal to an acceptable number, based on the conversion information for each memory chip.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system including a non-volatile memory.

Background Art

[0002] In recent years, memory systems including non-volatile memories have been widely spread. As one of such memory systems, a solid state drive (SSD) including a NAND type flash memory is known. The SSD is used as data storage for various computing devices and information processing systems.

[0003] A memory system including a non-volatile memory includes, for example, a plurality of non-volatile memory chips. In the memory system, in order to improve access performance (that is, read performance and write performance), for example, a technique of accessing a plurality of non-volatile memory chips in parallel is used. Specifically, a technique of accessing in parallel a plurality of physical blocks included in each of the plurality of non-volatile memory chips is used. A parallel access unit, which is a set of a plurality of physical blocks that can be accessed in parallel, is also referred to as a super block.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a memory system including a plurality of non-volatile memory chips, there may be unusable defective blocks (bad blocks) in the plurality of non-volatile memory chips. If there is a defective block in a non-volatile memory chip that constitutes a part of a super block, which is a parallel access unit, it may hinder the improvement of access performance.

[0006] The problem that this invention aims to solve is to provide a memory system that suppresses a decrease in access performance even if bad blocks exist in the non-volatile memory chips within the superblock. [Means for solving the problem]

[0007] According to the embodiment, the memory system comprises a plurality of non-volatile memory chips and a controller. Each of the plurality of non-volatile memory chips includes a plurality of first blocks. The controller is electrically connected to the plurality of non-volatile memory chips. The controller is capable of parallel access to the plurality of non-volatile memory chips. The controller assigns a plurality of first block addresses to each of the plurality of first blocks in a specific order. The controller controls parallel access to the plurality of non-volatile memory chips in a plurality of parallel access units. Each of the plurality of parallel access units includes a plurality of second blocks, which are sets of at least one block assigned from the plurality of first blocks contained in each of the plurality of non-volatile memory chips. One or more of the plurality of non-volatile memory chips include one or more initial fault blocks. The controller manages a plurality of conversion pieces corresponding to each of the plurality of non-volatile memory chips, which are defined so that the number of initial fault blocks belonging to each of the plurality of parallel access units is less than or equal to an allowable number. The controller converts each of the plurality of second blocks belonging to the parallel access unit into a plurality of third blocks based on the conversion information, and reconfigures the plurality of third blocks into a parallel access unit. The controller generates a plurality of management information, each indicating whether the number of bad blocks belonging to the reconfigured parallel access unit is less than or equal to the allowable number. When access to one of the plurality of first blocks, the controller requests a fourth block, it obtains first management information from the plurality of management information corresponding to the first parallel access unit to which the fourth block belongs among the plurality of parallel access units. If the first management information indicates that the number of bad blocks belonging to the reconfigured parallel access unit is less than or equal to the allowable number, the controller obtains first conversion information from the plurality of conversion information corresponding to the first non-volatile memory chip containing the fourth block among the plurality of non-volatile memory chips. The controller converts the first block address assigned to the fourth block to a second block address based on the first conversion information.The controller instructs the first non-volatile memory chip to access the block to which the second block address has been assigned. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing an example configuration of an information processing system including a memory system according to the embodiment. [Figure 2] A block diagram showing an example configuration of NAND flash memory in a memory system according to the embodiment. [Figure 3] A block diagram showing an example of the configuration of a memory chip in a memory system according to this embodiment. [Figure 4] A diagram showing an example of the configuration of a superblock used in a memory system according to this embodiment. [Figure 5] This figure shows (a) an example of the bad block occurrence pattern in multiple memory chips (before superblock reconstruction) and (b) an example of the bad block pattern in each memory chip (after superblock reconstruction) in which bad blocks have been replaced with physical blocks other than bad blocks. [Figure 6] A diagram showing (a) an example of the bad block occurrence pattern in multiple memory chips (before superblock reconstruction) and (b) an example of the bad block pattern in each memory chip (after superblock reconstruction) in which bad blocks have been replaced with physical blocks other than bad blocks. [Figure 7] A diagram showing an example of a memory system according to the embodiment, in which (a) multiple superblocks are formed by converting the physical block number of each physical block belonging to each memory chip, thereby equalizing the number of initial defective blocks, and (b) conversion information used for the conversion. [Figure 8] A figure showing an example of the physical block number before conversion (a) and a first example (b), a second example (c), and a third example (d) of the physical block number after conversion by the conversion information 52 in a single memory chip within the memory system according to the embodiment. [Figure 9] A diagram showing an example of a management table used in the memory system according to the embodiment. [Figure 10] A diagram showing another example of a management table used in the memory system according to the embodiment. [Figure 11] A diagram showing an example of the configuration of a superblock specified based on a subtable in the memory system according to the embodiment. [Figure 12] A flowchart showing an example of the procedure of conversion information generation processing executed in a host device connected to the memory system according to the embodiment. [Figure 13] A flowchart showing an example of the procedure of conversion and management information setting processing executed in the memory system according to the embodiment. [Figure 14] A flowchart showing an example of the procedure of defective block management processing executed in the memory system according to the embodiment. [Figure 15] A flowchart showing an example of the procedure of access control processing executed in the memory system according to the embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] First, referring to FIG. 1, a configuration example of an information processing system including a memory system according to the embodiment will be described. The information processing system 1 includes, for example, a host device 2 and a memory system 3.

[0011] The host device 2 may be a storage server that stores a large amount and diverse data in the memory system 3, or may be a personal computer. Hereinafter, the host device 2 will also be referred to as the host 2.

[0012] The memory system 3 is a storage device configured to write data to and read data from a non-volatile memory. The memory system 3 is also referred to as a storage device. The non-volatile memory is, for example, a NAND flash memory 4. The memory system 3 is realized as, for example, a solid state drive (SSD) including the NAND flash memory 4.

[0013] The memory system 3 can be used as the storage of the host 2. The memory system 3 may be built into the host 2 or may be connected to the host 2 via a cable or a network.

[0014] The interface for connecting the host 2 and the memory system 3 complies with a standard such as, for example, PCI Express TM (PCIe TM )、Ethernet TM 、Fibre channel, or NVM Express TM (NVMe TM ).

[0015] The memory system 3 includes, for example, a NAND flash memory 4, a dynamic random access memory (DRAM) 5, and a controller 6.

[0016] Referring to FIGS. 2 and 3, the configuration of the NAND flash memory 4 will be described.

[0017] FIG. 2 is a block diagram showing a configuration example of the NAND flash memory 4.

[0018] The NAND flash memory 4 includes, for example, a plurality of NAND memory chips 41. The NAND memory chips 41 are non-volatile memory chips. Hereinafter, the NAND memory chips 41 will also be simply referred to as memory chips 41. Each of the plurality of memory chips 41 can operate independently. That is, each of the plurality of memory chips 41 functions as a parallel-operating unit. The plurality of memory chips 41 may be, for example, 32 memory chips #0 to #31. Each of the plurality of memory chips is connected to the controller 6 via, for example, one of a plurality of channels CH. The plurality of channels CH may be, for example, eight channels CH1 to CH8. The plurality of memory chips 41 may constitute a plurality of banks. A bank is a unit that operates at least two of the plurality of memory chips 41 in parallel through interleaved operation. The plurality of banks may be, for example, four banks BNK1, BNK2, BNK3, and BNK4. Each of the four banks, BNK1, BNK2, BNK3, and BNK4, consists of, for example, eight memory chips.

[0019] Controller 6 is electrically connected to multiple memory chips 41 via multiple channels. Controller 6 is provided with a NAND interface (NAND I / F) 13. The NAND I / F 13 is a memory control circuit configured to control the NAND flash memory 4. The NAND I / F 13 comprises, for example, multiple NAND controllers 131, the same number as the number of channels. The multiple NAND controllers 131 are, for example, eight NAND controllers 131-1, 131-2, ..., and 131-8 (hereinafter referred to as NAND controllers 131-1 to 131-8). The eight NAND controllers 131-1 to 131-8 are each connected to eight channels CH1 to CH8. Each of the NAND controllers 131-1 to 131-8 may be connected to multiple memory chips 41 in the NAND flash memory 4 via the connected channel. By driving multiple memory chips 41 in parallel, it becomes possible to increase the access bandwidth between the controller 6 and the NAND flash memory 4.

[0020] In the example shown in Figure 2, memory chips #0, #8, #16, and #24 are connected to NAND controller 131-1 via channel CH1. Memory chips #1, #9, #17, and #25 are connected to NAND controller 131-2 via channel CH2. Memory chips #7, #15, #23, and #31 are connected to NAND controller 131-8 via channel CH8. Additionally, memory chips #0 to #7 constitute bank BNK1. Memory chips #8 to #15 constitute bank BNK2. Memory chips #16 to #23 constitute bank BNK3. Memory chips #24 to #31 constitute bank BNK4.

[0021] In the following, any unspecified memory chip among the multiple memory chips 41 will also be referred to as memory chip 41.

[0022] Figure 3 shows an example configuration of a memory chip 41. The memory chip 41 includes, for example, L planes 42, where L is, for example, an integer greater than or equal to 1. Each of the L planes 42 is a unit that performs data writing and data reading operations. The number of planes 42 included in the memory chip 41 is arbitrary. Figure 3 illustrates the case where the memory chip 41 includes a first plane 42-1, ..., and the Lth plane 42-L. Hereafter, any unspecified plane among the L planes 42 will also be referred to as plane 42.

[0023] The plane 42 includes a memory cell array 421. The memory cell array 421 includes multiple physical blocks PB0, PB1, PB2, ..., and PBm-1, each containing multiple memory cells arranged in a matrix. Each of the multiple physical blocks PB0, PB1, PB2, ..., and PBm-1 can function as a unit for data erasure operations. A physical block is also called an erase block. Each of the multiple physical blocks PB0, PB1, PB2, ..., and PBm-1 includes multiple physical pages PP0, ..., and PPn-1. Each of the multiple physical pages PP0, ..., and PPn-1 contains multiple memory cells connected to a single word line. Each of the multiple physical pages PP0, ..., and PPn-1 functions as a unit for data write operations and data read operations. A word line may also function as a unit for data write operations and data read operations. In general, the access performance of a non-volatile memory chip includes read performance and write performance. The read performance of a non-volatile memory chip refers to its ability to read data stored in a physical block or physical page within the non-volatile memory chip (e.g., read time). Conversely, the write performance of a non-volatile memory chip refers to its ability to write data to a physical block or physical page within the non-volatile memory chip (e.g., write time). In this embodiment, access performance primarily refers to write performance.

[0024] Multiple physical blocks PB0, PB1, PB2, ..., PBm-1 are each assigned multiple physical block numbers in a specific order by, for example, the controller 6. Specifically, multiple physical blocks PB0, PB1, PB2, ..., PBm-1, which are arranged according to the physical coordinates in the memory cell array 421, are each assigned ascending numbers, for example, 0, 1, 2, ..., m-1. Alternatively, multiple physical blocks PB0, PB1, PB2, ..., PBm-1 may each be assigned descending numbers, for example, m-1, ..., 2, 1, 0. Furthermore, physical block numbers may be assigned to each plane 42, or they may be assigned across multiple planes 42 within a single memory chip 41. Physical block numbers are also called block addresses. Physical block numbers are not limited to numbers and can be any form of information that uniquely identifies the corresponding physical block.

[0025] Each of the multiple physical blocks PB0, PB1, PB2, ..., PBm-1 has an upper limit on the number of program / erase cycles (P / E cycles) it can tolerate, which is called the maximum P / E cycle count. One P / E cycle for a physical block includes a data erasure operation to erase all memory cells in that physical block, and a program operation to write data to each physical page of that physical block.

[0026] Furthermore, in memory system 3, multiple superblocks may be configured. Multiple superblocks are sets of physical blocks, each containing at least one selected from each of multiple parallel-operating memory chips 41. In other words, multiple superblocks are multiple parallel access units controlled by controller 6. Controller 6 controls multiple superblocks, each containing multiple physical blocks belonging to each of the multiple memory chips 41 (or multiple planes 42). A superblock is also called a logical block or block group. Additionally, a set of physical pages, each containing one physical block, that make up a superblock is called a superpage or logical page.

[0027] Figure 4 shows an example of a superblock configuration. Here, we describe a case where there are 8 channels and 4 banks, and one physical block is selected from each of multiple parallel-operating memory chips. The 8-channel x 4-bank configuration corresponds to 32 memory chips #0 to #31. In this case, one superblock contains a total of 32 physical blocks, one from each of the 32 memory chips #0 to #31.

[0028] Figure 4 illustrates a superblock SBx containing 32 physical blocks PBx. Here, the superblock SBx is composed of the x-th physical block PBx contained in each of the memory chips #0 to #31. Figure 4 also illustrates a superpage SPy containing the physical pages PPy of each of the 32 physical blocks PBx. Controller 6 can perform data write operations in parallel for the 32 physical pages PPy that make up the superpage SPy. Controller 6 can also perform data read operations in parallel for the 32 physical pages PPy that make up the superpage SPy.

[0029] Furthermore, if the memory chip 41 includes multiple planes 42 (i.e., a multi-plane configuration), each plane 42 includes multiple physical blocks. For example, if each of the memory chips #0 to #31 includes two planes, one superblock SBx includes a total of 64 physical blocks PBx, one selected from each of the 64 planes 42 corresponding to the NAND flash memory chips #0 to #31. In this case, one superpage SPy includes the physical page PPy of each of these 64 physical blocks PBx. The controller 6 can execute data write operations in parallel for the 64 physical pages PPy that constitute the superpage SPy. The controller 6 can also execute data read operations in parallel for the 64 physical pages PPy that constitute the superpage SPy. In the following, physical blocks and superblocks may be collectively referred to simply as blocks.

[0030] Return to Figure 1.

[0031] DRAM5 is volatile memory. The memory area of ​​DRAM5 is allocated, for example, as a cache area for a logical-physical address translation table 51, multiple translation information 52, multiple management tables 53, and one or more subtables 54. The memory area of ​​DRAM5 may be further allocated as a storage area for firmware (FW) and a buffer area for temporarily storing user data 4U. FW is a program for controlling the operation of controller 6. FW is loaded, for example, from NAND flash memory 4 into DRAM5. User data 4U is data requested to be written by host 2.

[0032] The logical-physical address translation table 51 is a table for managing the mapping between each logical address and each physical address of the NAND flash memory 4. A logical address is an address used by the host 2 to address the storage area of ​​the memory system 3. A logical address is, for example, a logical block address (LBA).

[0033] The multiple conversion information 52 corresponds to, for example, multiple memory chips 41. The multiple conversion information 52 is pre-generated outside the memory system 3 (for example, on the host 2) based on, for example, test results for each memory chip 41 and the configuration of the memory chips 41 in the NAND flash memory 4. The test results for each memory chip 41 include, for example, information about initial defective blocks contained in the memory chip 41. A defective block is a physical block that cannot be read and written to properly. Initial defective blocks are defective blocks that occurred during the manufacturing process of the NAND flash memory 4.

[0034] Each of the multiple conversion information pieces 52 is information indicating the rules of operation for converting the physical block number of a physical block in the corresponding memory chip 41 to the physical block number of another physical block. The multiple rules of operation indicated by each of the multiple conversion information pieces 52 are specified to equalize the number of initial bad blocks belonging to each of the multiple superblocks (parallel access units) without bias. Equalizing the number of initial bad blocks belonging to each of the multiple superblocks means, for example, minimizing the difference in the number of initial bad blocks belonging to each of the multiple superblocks. The difference in the number of blocks is ideally 0 or 1, but may be set to 1 or more. Specifically, as equalization by the multiple rules of operation, for example, it is specified that the number of initial bad blocks belonging to each of the multiple superblocks is less than or equal to an allowable number. The allowable number is the upper limit of the number of bad blocks that are allowed to belong to each superblock, and can be appropriately determined by the specifications of the memory system.

[0035] The multiple block numbers assigned to each of the multiple physical blocks belonging to the superblock are converted to multiple physical block numbers based on multiple conversion information 52 (i.e., conversion information 52 for each memory chip 41). The superblock to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple physical blocks to which the multiple conversion information 52 to which are to which are to which are to which are to which the conversion of physical block numbers based on the multiple conversion information 52 to which the multiple physical blocks to which are to which are to which the multiple superblocks are each converted. In the following, the reconstructed superblock to which the superblocks are reconstructed based on the multiple conversion information 52 will also be simply referred to as the reconstructed superblock corresponding to the superblock. The structure of the conversion information 52 and specific examples of the conversion of physical block numbers based on the conversion information 52 will be described later with reference to Figures 7 and 8.

[0036] Multiple management tables 53 correspond to multiple superblocks. Each management table 53 contains information (management information) indicating whether the number of defective blocks in a reconfigured superblock, which is formed by reconfiguring multiple physical blocks belonging to the corresponding superblock, is below an acceptable number. Specific examples of the configuration of management tables 53 will be described later with reference to Figures 9 and 10.

[0037] One or more subtables 54 are associated with one or more of the management tables 53. Each subtable 54 indicates the multiple physical blocks that actually belong to a reconfigured superblock (i.e., to the superblock corresponding to that reconfigured superblock) when the number of bad blocks belonging to that reconfigured superblock exceeds the allowable number. Subtables 54 are secondary information generated in response to the number of bad blocks belonging to a reconfigured superblock exceeding the allowable number. In other words, when the number of bad blocks belonging to a reconfigured superblock exceeds the allowable number, the multiple physical blocks that actually belong to the corresponding superblock are identified using the subtable 54 associated with the management table 53 corresponding to that superblock. Therefore, by using subtables 54, the physical blocks belonging to a superblock can be changed. This reduces performance variations between superblocks due to the occurrence of later bad blocks and extends the lifespan of the memory system 3. A specific example of the configuration of subtables 54 will be described later with reference to Figure 11.

[0038] The controller 6 may be comprised of a circuit such as a System-on-a-Chip (SoC). The controller 6 may also be comprised of multiple semiconductor chips. The controller 6 is electrically connected to the NAND flash memory 4 and configured to control the NAND flash memory 4. The functions of each part within the controller 6 may be implemented by dedicated hardware within the controller 6 or by a processor running the firmware.

[0039] The controller 6 may function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 4. The data management performed by this FTL includes (1) managing mapping information that shows the correspondence between each logical address and each physical address of the NAND flash memory 4, and (2) processing to conceal the difference between page-level data read / write operations and block-level data erase operations. Block management includes bad block management, wear-leveling, and garbage collection (GC).

[0040] The management of mapping information between each logical address and each physical address is performed, for example, using a logical-physical address translation table 51. The controller 6 uses the logical-physical address translation table 51 to manage the mapping between each logical address and each physical address in units of a specific management size. The physical address corresponding to a given logical address indicates the physical storage location in the NAND flash memory 4 where the data for that logical address is written. The controller 6 uses the logical-physical address translation table 51 to manage multiple storage areas that are logically divided from the storage area of ​​the NAND flash memory 4. The size of each of these multiple storage areas is the management size described above. Each of these multiple storage areas corresponds to a multiple logical address. In other words, each of these multiple storage areas is identified by a single logical address. The logical-physical address translation table 51 may be loaded from the NAND flash memory 4 into the DRAM 5 when the memory system 3 is started.

[0041] Data can only be written to a single memory cell once per P / E cycle. Therefore, the controller 6 writes the update data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous data corresponding to that logical address is stored. The controller 6 then invalidates the previous data by updating the logical-physical address translation table 51 to associate this logical address with this different physical memory location. Data referenced by the logical-physical address translation table 51 (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address is called invalid data. Valid data is data that may be read by the host 2 later. Invalid data is data that can no longer be read by the host 2.

[0042] Blocks within NAND flash memory 4 are broadly classified into active blocks and free blocks. Active blocks are blocks that store valid data and cannot have new data written to them. Free blocks do not store valid data and can be used to write new data after a data erasure operation. In other words, free blocks are used as new write destination blocks after a data erasure operation. Write destination blocks can store valid data. Each active block is managed by a list called the active block pool. Each free block is managed by a list called the free block pool.

[0043] Furthermore, the data stored in the NAND flash memory 4 is broadly divided into management data 4M and user data 4U.

[0044] Management data 4M consists of various pieces of information for managing the state of memory system 3 and controlling its operation. Management data 4M includes, for example, a logical-physical address translation table 51, multiple translation information 52, multiple management tables 53, and one or more subtables 54. At least one of the logical-physical address translation table 51, multiple translation information 52, multiple management tables 53, and one or more subtables 54 may be stored in non-volatile memory within memory system 3 other than NAND flash memory 4.

[0045] User data 4U is the data that host 2 requested to be written, as mentioned above.

[0046] Garbage collection is a process that increases the number of free blocks in the NAND flash memory 4. Specifically, garbage collection is a process that copies valid data from several active blocks containing a mixture of valid and invalid data to other blocks. Blocks that now only store invalid data after the valid data has been copied to other blocks are freed as free blocks. Therefore, garbage collection can increase the number of free blocks in the NAND flash memory 4.

[0047] The controller 6 includes, for example, a host interface circuit (host I / F) 11, a DRAM interface circuit (DRAM I / F) 12, a NAND interface circuit (NAND I / F) 13, and a CPU 14. These host I / F 11, DRAM I / F 12, NAND I / F 13, and CPU 14 are connected, for example, via a bus 10. The controller 6 may further include a static random access memory (SRAM) 15. The SRAM 15 is a volatile memory. The SRAM 15 is connected to various parts of the controller 6, for example, via the bus 10. The SRAM 15 can store at least a portion of the data (information) stored in the aforementioned DRAM 5.

[0048] The host interface 11 is a circuit configured to receive various commands (e.g., input / output (I / O) commands and control commands) and data from host 2, and to send responses to commands and data to host 2. I / O commands are access commands such as write commands or read commands. A write command is a command that requests the writing of user data to a specified logical address. A read command is a command that requests the reading of user data from a specified logical address. Control commands include, for example, unmap commands (trim commands). An unmap command is a command that requests the invalidation of data corresponding to a specified logical address.

[0049] DRAM I / F12 is a DRAM control circuit configured to control access to DRAM5.

[0050] As mentioned above, the NAND I / F 13 is a memory control circuit configured to control the NAND flash memory 4. Each of the multiple NAND controllers 131 within the NAND I / F 13 includes, for example, a block number conversion circuit 31.

[0051] When access to a physical block (hereinafter also referred to as a target physical block) is requested, the block number conversion circuit 31 uses conversion information 52 for each memory chip 41, a management table 53 for each superblock, and a subtable 54 associated with any of the management tables 53 to determine which physical block should actually be accessed.

[0052] Specifically, the block number conversion circuit 31 receives, for example, information that can identify the target physical block. This information includes, for example, the chip number of the memory chip 41 (hereinafter also referred to as memory chip A) containing the target physical block, and the physical block number of the target physical block. The block number conversion circuit 31 uses the conversion information 52 corresponding to memory chip A to convert the physical block number of the target physical block belonging to the superblock to the physical block of the reconfigured superblock corresponding to that superblock (hereinafter referred to as physical block number A). The block number conversion circuit 31 also uses the management table 53 of the superblock to which the target physical block belongs to determine whether the number of defective blocks belonging to the corresponding reconfigured superblock is below the allowable number.

[0053] If the number of bad blocks belonging to the reconfigured superblock is less than or equal to the allowable number, the block number conversion circuit 31 sends the physical block number A obtained by conversion using the conversion information 52 to the memory chip A. In other words, the block number conversion circuit 31 determines that the physical block to which physical block number A is assigned is the physical block to be actually accessed. The block number conversion circuit 31 instructs the target memory chip 41 to access the physical block to which physical block number A is assigned.

[0054] If the number of bad blocks belonging to the reconfigured superblock exceeds the allowable number, the block number conversion circuit 31 uses a subtable 54 associated with the management table 53 of the corresponding superblock to obtain information indicating the physical blocks that actually constitute the superblock (hereinafter also referred to as block information). The block information indicates, for example, the chip number of the memory chip 41 containing the corresponding physical block and the physical block number assigned to that physical block. The block information may further include the channel number of the channel to which the memory chip 41 containing the corresponding physical block is connected and the plane number of the plane 42 within the memory chip 41 containing the physical block. The block number conversion circuit 31 determines the physical block identified based on the obtained block information as the physical block that should actually be accessed. The block number conversion circuit 31 instructs the memory chip 41 identified based on the block information to access the physical block identified based on the block information.

[0055] The block number conversion circuit 31 may be located inside the controller 6, rather than inside the NAND controller 131.

[0056] The CPU 14 is a processor configured to control the host I / F 11, DRAM I / F 12, and NAND I / F 13. The CPU 14 performs various processes by executing firmware (FW) loaded from the NAND flash memory 4 into the DRAM 5. The FW is a control program containing a set of instructions that causes the CPU 14 to perform various processes. The CPU 14 can perform command processing to handle various commands from the host 2. The operation of the CPU 14 is controlled by the FW executed by the CPU 14.

[0057] The CPU 14 functions, for example, as a block management unit 141, a write control unit 142, and a read control unit 143. The CPU 14 functions by, for example, executing firmware. Note that some or all of each of the block management unit 141, the write control unit 142, and the read control unit 143 may be implemented by dedicated hardware within the controller 6. The block management unit 141, the write control unit 142, and the read control unit 143 work in conjunction with the NAND I / F 13 to control multiple superblocks.

[0058] The block management unit 141 manages multiple physical blocks contained in each of the multiple memory chips 41 within the NAND flash memory 4.

[0059] Specifically, the block management unit 141 manages the active blocks and free blocks contained in the NAND flash memory 4. Active blocks include, for example, active physical blocks and active superblocks. Free blocks include, for example, free physical blocks and free superblocks. The block management unit 141 manages active blocks using, for example, an active block pool. The block management unit 141 manages free blocks using, for example, a free block pool.

[0060] The block management unit 141 assigns multiple physical block numbers (block addresses) to multiple physical blocks contained in each memory chip 41 in a specific order. The block management unit 141 manages multiple superblocks (parallel access units) and the multiple physical blocks that constitute each of those superblocks.

[0061] The block management unit 141 receives conversion information 52 for each memory chip 41 from the host 2 via the host I / F 11, for example. The timing of receiving the conversion information 52 is, for example, any timing during the manufacturing process of the memory system 3. The block management unit 141 stores the received conversion information 52 as management data 4M in the NAND flash memory 4 (i.e., records it non-volatilely). The block management unit 141 then sets the conversion information 52 in the block number conversion circuit 31 within each NAND controller 131. Specifically, the block management unit 141 sets the conversion information 52 in the block number conversion circuit 31 by storing the conversion information 52 in the memory area of ​​the block number conversion circuit 31, or by storing the conversion information 52 in a memory area accessible by the block number conversion circuit 31 (e.g., DRAM 5). Note that the block number conversion circuit 31 may have conversion information 52 corresponding to each of the multiple memory chips 41 to which the NAND controller 131 containing the block number conversion circuit 31 is connected via the channel CH.

[0062] The block management unit 141 manages whether the number of defective blocks belonging to the reconfigured superblock is below an acceptable number. Specifically, the block management unit 141 generates a management table 53 for each superblock and stores it, for example, as management data 4M in the NAND flash memory 4. When a subsequent defective block occurs, the block management unit 141 identifies the reconfigured superblock to which the subsequent defective block belongs. Then, the block management unit 141 updates the management table 53 (target management table 53) of the superblock corresponding to the identified reconfigured superblock according to the subsequent defective block that occurred. A subsequent defective block is a defective block that occurred after the memory system 3 was shipped.

[0063] The block management unit 141 generates a subtable 54 when the number of defective blocks belonging to the reconfigured superblock exceeds the allowable number due to the occurrence of subsequent defective blocks. The block management unit 141 associates the generated subtable 54 with the target management table 53. The block management unit 141 also replaces the defective blocks belonging to the reconfigured superblock with one free physical block selected from one or more free physical blocks shown in the free block pool. The block management unit 141 sets block information in the generated subtable 54 that indicates the physical blocks that actually constitute the superblock, including the free physical block that replaced the defective block. Specific examples of the operations for managing subsequent defective blocks, the management table 53, and the subtable 54 will be described later with reference to Figures 9 to 11.

[0064] The write control unit 142 controls the writing of data to the NAND flash memory 4 via the NAND I / F 13. Specifically, the write control unit 142 selects, for example, one free superblock from one or more free superblocks shown in the free block pool. The write control unit 142 assigns the selected free superblock as the destination superblock to which user data received from the host 2 should be written.

[0065] The write control unit 142 requests the NAND I / F 13 to perform the process of writing the user data received from host 2 along with the write command to multiple physical blocks contained in the destination superblock in parallel. Specifically, the write control unit 142 requests the NAND I / F 13 to write the user data received from host 2 to an available physical storage location in the destination superblock, in response to the write command received from host 2. The write control unit 142 then updates the logical-physical address translation table 51 so that the logical address specified in the write command is mapped to the physical address indicating the physical storage location where the user data has been written. If the entire destination superblock is filled with data, this destination superblock is managed by the active block pool. A new destination superblock is also allocated using the free block pool.

[0066] The read control unit 143 controls the reading of data from the NAND flash memory 4 via the NAND I / F 13. When the read control unit 143 receives a read command from the host 2, it requests the NAND I / F 13 to read the user data corresponding to the logical address specified in the read command from the physical storage location in the superblock where this user data is stored. Specifically, when the read control unit 143 receives a read command from the host 2, it obtains the physical address mapped to the logical address specified in the read command by referring to the logical-physical address translation table 51. The read control unit 143 requests the NAND I / F 13 to read the user data from this physical address. Then, the read control unit 143 transmits the read user data to the host 2.

[0067] With the above configuration, the controller 6 manages multiple superblocks using conversion information 52 for each memory chip 41. The controller 6 uses a management table 53 for each superblock to manage whether the number of bad blocks belonging to the corresponding reconfigured superblock is below the allowable number. Furthermore, if the number of bad blocks belonging to the reconfigured superblock exceeds the allowable number, the controller 6 uses a subtable 54 to manage the physical blocks that actually constitute the superblock. By using such conversion information 52, management table 53, and subtable 54, the controller 6 can control access to each superblock at low cost. In addition, access control using conversion information 52 makes it possible to prevent bias in access performance between superblocks. Therefore, the memory system 3 can suppress a decrease in access performance to the NAND flash memory 4.

[0068] Here, we will describe the configuration of the superblock in the memory system relating to the comparative example, taking into account the initial defective blocks in the NAND flash memory.

[0069] Figure 5 shows examples of (a) the occurrence pattern of bad blocks in multiple memory chips (before superblock reconstruction) and (b) the pattern of bad blocks in each memory chip in which bad blocks have been replaced with physical blocks other than bad blocks (after superblock reconstruction) in the memory system of the comparative example.

[0070] Here, we assume that the NAND flash memory 4 contains eight memory chips CHIP#0 to #7. Each of the eight memory chips CHIP#0 to CHIP#7 contains 32 physical blocks PB#0 to PB#31. Of the 32 physical blocks PB#0 to PB#31 contained in each of the eight memory chips CHIP#0 to CHIP#7, the eight physical blocks belonging to the same physical block number PB# each belong to one superblock. The physical block number of each physical block belonging to a superblock is determined based on the superblock number that identifies this superblock and a mathematical rule. The superblock number is also called the superblock address. The mathematical rule is, for example, any rule that can uniquely determine a combination of physical block numbers using the superblock number.

[0071] By using a method that uniquely determines the combination of physical block numbers of multiple physical blocks belonging to a superblock based on such superblock numbers and mathematical rules, it becomes unnecessary to create a dedicated management table for each superblock that shows the physical block numbers of the multiple physical blocks belonging to that superblock. Furthermore, this method makes it easy to identify the combination of physical block numbers of multiple physical blocks belonging to a superblock based on the superblock number of that superblock.

[0072] Figure 5 shows 32 superblocks SB#0 to SB#31. Here, for the sake of illustration and understanding, an example is shown where a superblock belongs to a set of physical blocks whose physical block numbers have the same value as the superblock number of that superblock (i.e., superblock number = physical block number).

[0073] Specifically, superblock SB#0 contains eight physical blocks PB#0, each belonging to memory chips CHIP#0 to CHIP#7. Superblock SB#1 contains eight physical blocks #PB1, each belonging to memory chips CHIP#0 to CHIP#7. Superblock SB#2 contains eight physical blocks #PB2, each belonging to memory chips CHIP#0 to CHIP#7. The same applies to the other superblocks SB#3 to SB#31.

[0074] In Figure 5(a), blocks indicated by cross-hatching are bad blocks. Memory chip CHIP#0 contains 8 bad blocks. Memory chip CHIP#1 contains 2 bad blocks. Memory chip CHIP#2 contains 1 bad block. Memory chip CHIP#3 contains 1 bad block. Memory chip CHIP#4 contains 5 bad blocks. Memory chip CHIP#5 contains 1 bad block. Memory chip CHIP#6 contains 1 bad block. Memory chip CHIP#7 contains 1 bad block.

[0075] If a policy is applied that superblocks SB# (physical block PB#, indicated by a single hatch pointing diagonally downwards to the right) containing two or more bad blocks are not treated as unusable blocks, then superblocks with zero bad blocks, or superblocks SB# (physical block PB#, indicated by a single hatch pointing diagonally downwards to the left) containing only one bad block, will be treated as usable normal blocks. However, if the condition is that superblocks containing two or more bad blocks are also used, then superblocks containing two or more bad blocks will have lower access performance than superblocks containing one bad block. Furthermore, if there is a bias in the number of bad blocks belonging to each superblock, the performance differences between superblocks will vary greatly. Therefore, whether a superblock containing bad blocks is treated as a usable normal block or an unusable block is determined by considering the above factors.

[0076] Figure 5(b) shows the reconfigured superblock. Here, it is reconfigured to secure more available superblocks with fewer bad blocks (in this example, zero bad blocks). In other words, more available superblocks are secured by replacing bad blocks with specific physical blocks limited to each memory chip (in this example, PB#0 to PB#26 are available healthy blocks).

[0077] For example, in memory chip CHIP#0, physical blocks #PB3, #PB8, #PB13, #PB16, #PB19, and #PB21, each being a bad block, are replaced by physical blocks #PB25, #PB26, #PB28, #PB29, #PB30, and #PB31, respectively, which are included in memory chip CHIP#0. Similarly, in memory chip CHIP#1, physical blocks #PB10 and #PB21, each being a bad block, are replaced by physical blocks #PB30 and #PB31, respectively, which are included in memory chip CHIP#1. The same applies to the other memory chips CHIP#2 through CHIP#7.

[0078] In this way, by replacing the bad blocks in each memory chip with certain physical blocks, the first 24 physical blocks PB#0 to PB#23 of each memory chip become usable superblocks SB#0 to SB#23. However, the remaining physical blocks #PB24 to #PB31 of each memory chip become unusable superblocks SB#24 to SB#31. In the comparative example, the number of unusable superblocks after reconstruction is the same as the number of bad blocks in the memory chip with the most bad blocks. Therefore, the number of usable superblocks reconstructed in the comparative memory system is limited to 24, which is the number of normal blocks in memory chip CHIP#0, which has the most bad blocks (8).

[0079] In contrast, in the memory system 3 according to this embodiment, the conversion information 52 for each memory chip 41 is predetermined so that the number of bad blocks contained in each of the superblocks #SB0 to #SB31 is less than or equal to an acceptable number. When the controller 6 of the memory system 3 receives a request to access a physical block contained in a certain memory chip 41, it may perform a block number change operation to convert the physical block number assigned to that physical block based on the conversion information 52 corresponding to that memory chip 41. The controller 6 instructs the memory chip 41 to access the physical block to which the physical block number obtained by this conversion is assigned. In other words, the controller 6 sends the physical block number obtained by this conversion to the memory chip 41.

[0080] Figure 6 shows examples of (a) bad block occurrence patterns in multiple memory chips 41 within the memory system 3 (before superblock reconstruction) and (b) bad block patterns in each memory chip 41 in which bad blocks have been replaced with non-bad physical blocks (after superblock reconstruction).

[0081] The example of the defective block occurrence pattern shown in Figure 6(a) is the same as the example of the defective block occurrence pattern described above, with reference to Figure 5(a). Note that in the examples in Figures 5(a) and 6(a), the number of initial defective blocks belonging to each superblock SB#0 to SB#31 is not uniform across the entire superblock and varies. For example, there are 16 superblocks with 0 defective blocks, 14 superblocks with 1 defective block, 1 superblock with 2 defective blocks, and 1 superblock with 4 defective blocks.

[0082] Figure 6(b) shows an example of reconstructed superblocks SB#0 to SB#31 (reconstructed superblocks SB#0 to SB#31) that were reconstructed based on the conversion information 52 for each memory chip 41, as shown in Figure 6(a). Multiple block numbers assigned to each of the multiple physical blocks belonging to a superblock are converted to multiple physical block numbers based on the conversion information 52 for each memory chip 41. The reconstructed superblocks corresponding to a superblock belong to multiple physical blocks, each to which the multiple physical block numbers obtained through this conversion are assigned. The number of initial defective blocks belonging to the multiple reconstructed superblocks SB#0 to SB#31, which are each reconstructed based on the multiple conversion information 52 of the multiple superblocks, is equalized. In other words, there are 12 superblocks with 0 defective blocks and 20 superblocks with 1 defective block, and each superblock is reconstructed so that it has either 0 or 1 defective block.

[0083] In the example shown in Figure 6(b), physical blocks were replaced for each memory chip 41 so that the allowable number of bad blocks in each reconfigured superblock #SB0 to #SB31 was 1 or less. However, the allowable number is not limited to 1. The allowable number can be set to an integer less than or equal to the average number of bad blocks in each of the multiple memory chips 41. Here, the total number of bad blocks is 20 and the number of memory chips 41 is 8, so the allowable number is, for example, an integer less than or equal to 2.5 (=20 / 8). This allows the number of available physical blocks to be increased compared to the reconfiguration of physical blocks belonging to the superblocks in the comparative example shown in Figure 5(b), while limiting the difference in the number of bad blocks in each reconfigured superblock #SB0 to #SB31 to a certain range.

[0084] The frequency of bad blocks in memory chips 41 tends to increase with increasing storage capacity and the complexity and difficulty of the manufacturing process. Furthermore, the number of bad blocks per memory chip 41 varies from chip to chip. The difference (variation) in the number of bad blocks between memory chips 41 tends to increase as the number of manufacturing steps for these memory chips 41 increases. For example, three-dimensional flash memory, manufactured by stacking multiple layers, is complex and requires many manufacturing steps, so the difference (variation) in the number of bad blocks among the manufactured memory chips 41 tends to be relatively large. Even in ordinary memory chips, which have fewer manufacturing steps compared to three-dimensional flash memory, there are very rare cases where only some chips contain a large number of bad blocks.

[0085] Referring to Figure 5(b), in the reconfigured superblocks SB#0 to SB#31 described above, the number of available physical blocks within each memory chip is limited to the number of healthy blocks in the memory chip with the most bad blocks, CHIP#0. In the example in Figure 5(b), the number of available physical blocks (superblocks) is 24.

[0086] In contrast, in the reconfigured superblocks SB#0 to SB#31 shown in Figure 6(b), the number of usable physical blocks within each memory chip 41 is not limited to the number of normal blocks in memory chip CHIP#0, which has the most bad blocks. In the example in Figure 6(b), all 32 physical blocks (superblock count) can be made available. Therefore, as long as the total number of bad blocks across all memory chips 41 is not extremely large, the difference in the number of bad blocks between the reconfigured superblocks SB#0 to SB#31 can be limited to a certain range. Consequently, the differences in read / write performance between these reconfigured superblocks SB#0 to SB#31 can be kept within an acceptable range. For example, because data is written to a reconfigured superblock with an equalized number of bad blocks, performance differences are less likely to occur when reading data. In other words, in cases where data is read in parallel, the number of physical blocks that can be read in parallel will be roughly the same across the reconfigured superblocks.

[0087] Furthermore, if a method were used to manage the relationship between each reconstructed superblock and the set of physical blocks belonging to each of these reconstructed superblocks using table-formatted management information, a large amount of memory resources would be consumed to store this management information. For example, the data size of this management information would be [total number of physical blocks in all memory chips] × [data length of chip number + data length of block number]. For example, one memory chip 41 contains approximately 1000 to 2000 physical blocks. Also, [data length of chip number + data length of block number] is approximately 2 bytes. Therefore, the data size of the management information would become very large. This would increase the resource consumption for processing and storing the management information, and referencing the management information each time a superblock is constructed could degrade the performance of the memory system.

[0088] In the memory system 3 of this embodiment, the block number of a physical block is converted in each memory chip 41 by a block number conversion operation (arithmetic logic operations such as addition, subtraction, order reversal, etc.) based on conversion information 52 that indicates mathematical rules, thereby reconstructing the physical blocks belonging to the superblock. One piece of conversion information 52 specifies, for example, one of several available operations and the parameters used in this operation. Therefore, the data size of one piece of conversion information 52 is only a few bits. In this case, the total data size of the conversion information 52 for each memory chip 41 is [total number of chips (or total number of planes)] × [a few bits]. Thus, the memory system 3 can control multiple superblocks at low cost.

[0089] Figure 7 shows the distribution of bad block counts in multiple superblocks SB#0 to SB#7, and the bad block patterns of each memory chip 41 (CHP#0 to CHP#3) belonging to the superblock, before (configuration 81, left side of Figure 7(a)) and after (configuration 82, right side of Figure 7(a)) conversion using conversion information 52. An example of the conversion information 52 used for the conversion is shown in Figure 7(b). By performing this conversion on each memory chip 41, it becomes possible to equalize the number of bad blocks, which were scattered locally, across the entire block. This point will be described in more detail below.

[0090] First, we will illustrate the case where four memory chips, CHIP#0 to CHIP#3, each containing eight physical blocks, comprise eight superblocks, SB#0 to SB#7. Memory chip CHIP#0 contains three initial defective blocks, PB#0, PB#2, and PB#3. Memory chip CHIP#1 contains two initial defective blocks, PB#2 and PB#4. Memory chip CHIP#2 contains three initial defective blocks, PB#1, PB#2, and PB#3. Memory chip CHIP#4 contains no initial defective blocks. As in Figures 5 and 6, blocks indicated by cross-hatching are defective blocks.

[0091] (Configuration 81 before conversion based on conversion information 52) On the left side of Figure 7(a), the configuration 81 of superblocks SB#0 to SB#7 before the physical block numbers are converted using conversion information 52 is shown. Specifically, the configuration 81 of superblocks SB#0 to SB#7 is determined using a method that uniquely determines the combination of physical block numbers of the multiple physical blocks belonging to the superblock, based on the superblock number and mathematical rules.

[0092] Here, each superblock is defined as containing a set of physical blocks whose physical block numbers are the same as the superblock number of that superblock. For example, superblock SB#0 contains physical block PB#0 of memory chip CHIP#0, physical block PB#0 of memory chip CHIP#1, physical block PB#0 of memory chip CHIP#2, and physical block PB#0 of memory chip CHIP#3. Similarly, superblock SB#1 contains physical block PB#1 of memory chip CHIP#0, physical block PB#1 of memory chip CHIP#1, physical block PB#1 of memory chip CHIP#2, and physical block PB#1 of memory chip CHIP#3. The same applies to the other superblocks SB#2 to SB#7.

[0093] In this configuration 81 of superblocks SB#0 to SB#7, for example, if an access request specifying physical block number "0" of memory chip CHIP#1 is made, the NAND I / F 13 (more specifically, the NAND controller 131) sends physical block number "0" to memory chip CHIP#1. This instructs memory chip CHIP#1 to access physical block PB#0. Similarly, if an access request specifying superblock number "5" is made, the NAND I / F 13 sends physical block number "5" to each of memory chips CHIP#0 to CHIP#3. This instructs each of memory chips CHIP#0 to CHIP#3 to access physical block PB#5.

[0094] In this configuration 81, the number of initial defective blocks is not equalized across each superblock. In other words, the initial defective blocks are locally scattered across each superblock. Specifically, superblock SB#0 contains one initial defective block (physical block PB#0 of memory chip CHIP#0). Superblock SB#1 contains one initial defective block (physical block PB#1 of memory chip CHIP#2). Superblock SB#2 contains three initial defective blocks (physical block PB#2 of memory chip CHIP#0, physical block PB#2 of memory chip CHIP#1, and physical block PB#2 of memory chip CHIP#2). Superblock SB#3 contains two initial defective blocks (physical block PB#3 of memory chip CHIP#0, and physical block PB#3 of memory chip CHIP#2). Superblock SB#4 contains one initial defective block (physical block PB#4 of memory chip CHIP#1). None of the Super Blocks SB#5 through SB#7 contain any blocks with initial defects.

[0095] Thus, in the configuration 81 of superblocks SB#0 to SB#7 before the physical block numbers are converted using the conversion information 52, the number of initial defective blocks is not equalized. Therefore, in the memory system 3, the conversion information 52 for each memory chip 41 is used so that superblocks SB#0 to SB#7 are configured (reconfigured) in which the number of initial defective blocks is equalized across all physical blocks of SB#0 to SB#7.

[0096] The conversion information 52 corresponding to a single memory chip 41 indicates, for example, at least one of the following: (1) an operation to shift each of the multiple physical block numbers (block addresses) assigned to each of the multiple physical blocks contained in the memory chip 41 by an arbitrary integer (shift operation); and (2) an operation to reverse the order of those multiple physical block numbers (reverse operation). The shift operation is, for example, an operation to add an arbitrary integer to each of the multiple physical block numbers (block addresses) assigned to each of the multiple physical blocks contained in the memory chip 41 (addition), or an operation to subtract an arbitrary integer from each of those multiple physical block numbers (subtraction). The reverse operation is, for example, an operation to rearrange multiple physical block numbers arranged in ascending order to descending order, or an operation to rearrange multiple physical block numbers arranged in descending order to ascending order. Note that the conversion information 52 may indicate any arithmetic operation, not limited to shift operations and reverse operations. The following examples illustrate cases in which the conversion information 52 indicates shift operations, reverse operations, and combinations thereof.

[0097] The conversion information 52 is represented, for example, by the parameters used in the shift operation and reverse operation for each physical block number in the corresponding memory chip 41.

[0098] The shift operation parameter indicates the amount (i.e., offset) to shift multiple physical block numbers in the corresponding memory chip 41. If the parameter is 0, the physical block numbers are not shifted. If the parameter is a positive integer, the physical block numbers are increased by that integer. If the parameter is a negative integer, the physical block numbers are decreased by that integer. Note that multiple physical block numbers are treated cyclically. For example, if each memory chip 41 contains 8 physical blocks and the corresponding 8 physical block numbers "0" to "7" are shifted by "+1", physical block number "7" is converted to physical block number "0". Also, for example, if the 8 physical block numbers "0" to "7" are shifted by "-1", physical block number "0" is converted to physical block number "7".

[0099] The reverse operation parameter indicates whether or not to reverse the order of multiple physical block numbers in the corresponding memory chip 41. If the order of these multiple physical block numbers is to be reversed, the reverse operation parameter is set to, for example, 1. If the order of these multiple physical block numbers is not to be reversed, the reverse operation parameter is set to, for example, 0. The reverse operation parameter can be set to any value indicating whether or not to reverse the order of multiple physical block numbers. The reverse operation parameter may also indicate whether the order of the multiple physical block numbers in the corresponding memory chip 41 should be ascending or descending.

[0100] (Converted structure based on conversion information 82) Figure 7(b) shows four conversion information sets 52-0, 52-1, 52-2, and 52-3, corresponding to memory chips CHIP#0 to CHIP#3, respectively. Each of the conversion information sets 52-0, 52-1, 52-2, and 52-3 is represented by parameters used for shift operations and reverse operations, respectively.

[0101] Specifically, conversion information 52-0 indicates that a shift operation of "-1" is performed on each physical block number in memory chip CHIP#0, and no reverse operation is performed ("0"). Conversion information 52-1 indicates that a shift operation of "-6" is performed on each physical block number in memory chip CHIP#1, and no reverse operation is performed. Conversion information 52-2 indicates that a shift operation of "+1" is performed on each physical block number in memory chip CHIP#2, and a reverse operation is performed ("1"). Conversion information 52-2 indicates that neither a shift operation nor a reverse operation is performed on each physical block number in memory chip CHIP#3.

[0102] On the right side of Figure 7(a), a configuration 82 is shown in which the number of bad blocks (more specifically, the number of initial bad blocks) is leveled across the entire superblock SB#0 to SB#7 by converting the physical block numbers using the conversion information 52 shown in Figure 7(b).

[0103] Specifically, in memory chip CHIP#0, each of the eight physical block numbers is converted to a different physical block number by shifting it by "-1" based on conversion information 52-0. In memory chip CHIP#1, each of the eight physical block numbers is converted to a different physical block number by shifting it by "-6" based on conversion information 52-1. In memory chip CHIP#2, each of the eight physical block numbers is converted to a different physical block number by shifting it by "+1" and reversing its order based on conversion information 52-2. In memory chip CHIP#3, each of the eight physical block numbers is neither shifted nor reversed based on conversion information 52-3, so the physical block number remains the same after conversion.

[0104] In this case, for example, if an access request is made specifying physical block number "0" of memory chip CHIP#0, the NAND I / F13 converts physical block number "0" to physical block number "7" based on the conversion information 52-0 corresponding to memory chip CHIP#0. Then, the NAND I / F13 sends physical block number "7" to memory chip CHIP#0. This instructs memory chip CHIP#0 to access physical block PB#7.

[0105] For example, if an access request specifying superblock number "0" is made, NAND I / F13 converts physical block number "0" to physical block number "7" based on conversion information 52-0 corresponding to memory chip CHIP#0. NAND I / F13 converts physical block number "0" to physical block number "2" based on conversion information 52-1 corresponding to memory chip CHIP#1. NAND I / F13 converts physical block number "0" to physical block number "0" based on conversion information 52-2 corresponding to memory chip CHIP#2. NAND I / F13 leaves physical block number "0" as physical block number "0" based on conversion information 52-3 corresponding to memory chip CHIP#3. Then, NAND I / F13 sends physical block number "7" to memory chip CHIP#0, physical block number "2" to memory chip CHIP#1, physical block number "0" to memory chip CHIP#2, and physical block number "0" to memory chip CHIP#3. As a result, memory chip CHIP#0 is instructed to access physical block PB#7, memory chip CHIP#1 is instructed to access physical block PB#2, memory chip CHIP#2 is instructed to access physical block PB#0, and memory chip CHIP#3 is instructed to access physical block PB#0. Note that physical block PB#2 in memory chip CHIP#1 is a bad block, so NAND I / F13 does not need to send physical block number "2" to memory chip CHIP#1.

[0106] In configuration 82 of superblocks SB#0 to SB#7, the number of bad blocks is equalized among the superblocks. Here, each of the superblocks SB#0 to SB#7 has one initial bad block. In this way, by converting the physical block numbers of memory chips CHIP#0 to CHIP#3 using the corresponding conversion information 52-0, 52-1, 52-2, and 52-3, the superblocks SB#0 to SB#7 with an equalized number of initial bad blocks can be reconstructed. In other words, the superblocks SB#0 to SB#7 included in configuration 82 are reconstructed superblocks SB#0 to SB#7 with an equalized number of initial bad blocks based on the conversion information 52-0, 52-1, 52-2, and 52-3.

[0107] Referring to Figure 8, an example of converting physical block numbers using conversion information 52 will be further explained.

[0108] Figure 8 shows an example of the physical block number before conversion (a) and the first example (b), second example (c), and third example (d) of the physical block number after conversion by the conversion information 52 for a single memory chip 41. Here, the memory chip 41 whose physical block number is to be converted is assumed to be memory chip CHIP#0. Memory chip CHIP#0 contains eight physical blocks PB#0 to PB#7. Of these eight physical blocks PB#0 to PB#7, the three physical blocks PB#0, PB#2, and PB#3, indicated by cross-hatching, are bad blocks.

[0109] Figure 8(a) shows the physical block number in memory chip CHIP#0 that has not been converted using conversion information 52 (the physical block number before conversion). When the physical block number before conversion is used, for example, when an access request specifying any physical block number within memory chip CHIP#0 is made, the NAND I / F13 sends that physical block number to memory chip CHIP#0. This instructs memory chip CHIP#0 to access the physical block to which that physical block number is assigned. Note that the physical block number before conversion is the same as the physical block number after conversion using conversion information 52, where the shift operation parameter is 0 and the reverse operation parameter is 0.

[0110] Figure 8(b) shows the physical block number (converted physical block number) converted using the first conversion information 52 in the memory chip CHIP#0. The first conversion information 52 indicates an operation to shift the physical block number by "-1". Specifically, the first conversion information 52 specifies "-1" as the parameter for the shift operation and "0" as the parameter for the reverse operation.

[0111] When the first conversion information 52 is used, for example, in response to a request for access specifying any physical block number within memory chip CHIP#0, the NAND I / F 13 obtains a different block number by subtracting 1 from that physical block number. The NAND I / F 13 sends this different physical block number to memory chip CHIP#0. This instructs memory chip CHIP#0 to access the physical block to which the different physical block number is assigned.

[0112] More specifically, for example, if an access request is made specifying physical block number "1" of memory chip CHIP#0, the NAND I / F13 obtains physical block number "0" by subtracting 1 from physical block number "1". Similarly, if access requests are made specifying physical block numbers "2" to "7", the NAND I / F13 obtains physical block numbers "1" to "6". Note that if an access request is made specifying physical block number "0" of memory chip CHIP#0, the NAND I / F13 calculates that physical block number "-1" by subtracting 1 from physical block number "0". However, since physical blocks "0" to "7" are treated cyclically, physical block number "-1" means physical block number "7". Therefore, in this case, as a result of the shift operation, the NAND I / F13 obtains the largest physical block number "7", which corresponds to the physical block number immediately preceding the smallest physical block number "0".

[0113] Thus, when the first conversion information 52 is used, the physical block numbers "0" and "1" to "7" within the memory chip CHIP#0 specified in the access request are converted to physical block numbers "7" and "0" to "6", respectively.

[0114] Figure 8(c) shows the physical block numbers in memory chip CHIP#0 after conversion using the second conversion information 52. The second conversion information 52 indicates an operation to reverse the order of the physical block numbers. Specifically, the second conversion information 52 specifies "0" as the parameter for the shift operation and "1" as the parameter for the reverse operation.

[0115] When the second conversion information 52 is used, for example, in response to a request for access specifying any physical block number within memory chip CHIP#0, the NAND I / F 13 obtains a different block number by performing a conversion that reverses the order of the physical block numbers. The NAND I / F 13 sends this different physical block number to memory chip CHIP#0. This instructs memory chip CHIP#0 to access the physical block to which the different physical block number is assigned.

[0116] More specifically, for example, if an access request is made specifying physical block number "0" of memory chip CHIP#0, the NAND I / F13 obtains physical block number "7" by reversing the order of physical block number "0" in the sequence of physical block numbers "0" to "7". In other words, the first physical block number "0" is converted to the last physical block number "7" by reversing the order.

[0117] Thus, when the second conversion information 52 is used, the physical block numbers "0" to "7" within the memory chip CHIP#0 specified in the access request are converted to physical block numbers "7" to "0", respectively.

[0118] Figure 8(d) shows the physical block numbers in memory chip CHIP#0 after conversion using the third conversion information 52. The third conversion information 52 indicates an operation that reverses the order of the physical block numbers and shifts them by "-1". Specifically, the third conversion information 52 specifies "-1" as the parameter for the shift operation and "1" as the parameter for the reverse operation.

[0119] When the third conversion information 52 is used, for example, in response to a request for access specifying any physical block number within the memory chip CHIP#0, the NAND I / F 13 reverses the order of the physical block numbers and obtains another block number by subtracting 1 from the physical block number obtained by the order reversal. The NAND I / F 13 sends this other physical block number to the memory chip CHIP#0. This instructs the memory chip CHIP#0 to access the physical block to which the other physical block number is assigned.

[0120] More specifically, for example, if an access request is made specifying physical block number "0" of memory chip CHIP#0, the NAND I / F13 obtains physical block number "7" by reversing the order of physical block number "0" in physical block numbers "0" to "7". Then, the NAND I / F13 obtains physical block number "6" by subtracting 1 from this physical block number "7".

[0121] For example, if an access request is made specifying physical block number "7" of memory chip CHIP#0, the NAND I / F13 obtains physical block number "0" by performing a conversion that reverses the order of physical block number "7" in physical block numbers "0" to "7". Then, the NAND I / F13 obtains -1 by performing a conversion that subtracts 1 from this physical block number "0". Since physical blocks "0" to "7" are treated cyclically, if the NAND I / F13 obtains -1 as the result of the calculation, it obtains the largest physical block number "7", which corresponds to the physical block number immediately preceding the smallest physical block number "0".

[0122] Thus, when the third conversion information 52 is used, the physical block numbers "0" to "7" within the memory chip CHIP#0 specified in the access request are converted to physical block numbers "6" to "0" and "7", respectively.

[0123] By setting conversion information 52, which indicates various combinations of such shift and reverse operations, for each memory chip 41, the controller 6 of the memory system 3 can manage the configuration 82 of superblocks SB#0 to SB#7 (i.e., reconfigured superblocks SB#0 to SB#7) in which the number of initial defective blocks is leveled, as shown in Figure 7(a), for example.

[0124] Controller 6 is also configured to manage later-developing defective blocks. Specifically, Controller 6 (more precisely, Block Management Unit 141) manages defective blocks, including initial defective blocks and later-developing defective blocks, using, for example, a management table 53 and a subtable 54.

[0125] Referring to Figures 9 to 11, the management of bad blocks using management table 53 and subtable 54 will be explained. Here, the NAND flash memory 4 is assumed to contain N memory chips CHIP#0 to CHIP#N-1. Each of the N memory chips CHIP#0 to CHIP#N-1 contains M physical blocks PB#0 to PB#M-1.

[0126] Figure 9 shows an example of a management table 53. Here, we assume that the allowable number is 2. One management table 53 corresponds to one superblock. The management table 53 indicates whether the number of bad blocks included in the multiple physical blocks after conversion is less than or equal to the allowable number, when multiple physical blocks belonging to the corresponding superblock are converted into multiple physical blocks based on the conversion information 52 for each memory chip 41. In other words, the management table 53 indicates whether the number of bad blocks belonging to the reconstructed superblock, into which the corresponding superblock has been reconstructed, is less than or equal to the allowable number.

[0127] The management table 53 contains, for example, the same number of fields as the allowable number (in this case, 2). The size of each field corresponds to, for example, the size of the information that can uniquely identify one bad block belonging to the reconstructed superblock. This size is, for example, 8 bits. The management table 53 is set with information (values) according to the number of bad blocks belonging to the reconstructed superblock. Specifically, the management table 53 is set with information according to each of the following cases, for example, (A) when there are no bad blocks in the reconstructed superblock, (B) when there is one bad block in the reconstructed superblock, (C) when there are two bad blocks in the reconstructed superblock, and (D) when there are three or more bad blocks in the reconstructed superblock. Examples of the management table 53 for each of cases (A) to (D) are described below.

[0128] (A) If there are no bad blocks in the reconstructed superblock The reconstructed superblock 600 contains no bad blocks. In other words, the N physical blocks belonging to the reconstructed superblock 600 are all normal blocks. These N physical blocks are contained within N memory chips CHIP#0 to CHIP#N-1, respectively.

[0129] In this case, all fields (two fields in this case) in the management table 53A are set with a special key. The special key is a value that indicates that the reconfigured superblock 600 is in a specific state, for example, "0xff". The management table 53A, with special keys set in all fields, indicates that the corresponding superblock has been reconfigured and there are no bad blocks in the reconfigured superblock 600.

[0130] Therefore, the controller 6 can determine, based on the management table 53A corresponding to a certain superblock, that there are no bad blocks in the reconfigured superblock 600 corresponding to that superblock. Furthermore, the controller 6 can determine, based on the management table 53A, that the number of bad blocks belonging to the reconfigured superblock 600 is less than or equal to the allowable number.

[0131] (B) When one bad block is included in the reconstructed superblock The reconfigured superblock 601 contains one bad block. In the example shown in Figure 9, of the N physical blocks belonging to the reconfigured superblock 601, one physical block in memory chip CHIP#0 is a bad block, while the (N-1) physical blocks contained in the other memory chips CHIP#1 to CHIP#N-1 are normal blocks.

[0132] In this case, in the management table 53B, for example, a special key is set in the first field, and the value "0x00" indicating the chip number of memory chip CHIP#0 containing the bad blocks is set in the second field. The number of chip numbers set in the management table 53B corresponds to the number of bad blocks belonging to the reconfigured superblock 601 in which the corresponding superblock has been reconfigured.

[0133] Therefore, based on the management table 53B corresponding to a certain superblock, the controller 6 can determine that one bad block belongs to the reconfigured superblock 601 corresponding to that superblock, and that this bad block is included in memory chip CHIP#0. Furthermore, based on the management table 53B, the controller 6 can determine that the number of bad blocks belonging to the reconfigured superblock 601 is less than or equal to the allowable number.

[0134] (C) When two bad blocks belong to the reconstructed superblock The reconfigured superblock 602 contains two bad blocks. In the example shown in Figure 9, of the N physical blocks belonging to the reconfigured superblock 602, the two physical blocks contained in memory chips CHIP#1 and CHIP#N-1 are bad blocks, while the (N-2) physical blocks contained in the other memory chips CHIP#0 and CHIP#2 to CHIP#N-2 are normal blocks.

[0135] In this case, two fields in the management table 53C are set to the value "0x01" which indicates the chip number of memory chip CHIP#1 containing the bad block, and the value "0x0N-1" which indicates the chip number of memory chip CHIP#N-1 containing the bad block. The two values ​​"0x01" and "0x0N-1" representing the two chip numbers are set in the two fields in the management table 53C in a specific order, for example. The specific order is, for example, ascending order of the two values. In this case, in the management table 53C, the value "0x01" is set in the first field and the value "0x0N-1" is set in the second field. The number of chip numbers set in the management table 53C corresponds to the number of bad blocks belonging to the reconfigured superblock 602 in which the corresponding superblock has been reconfigured.

[0136] Therefore, based on the management table 53C corresponding to a certain superblock, the controller 6 can determine that two bad blocks belong to the reconfigured superblock 602 corresponding to that superblock, and that these two bad blocks are contained in the two memory chips CHIP#1 and CHIP#N-1, respectively. Furthermore, based on the management table 53C, the controller 6 can determine that the number of bad blocks belonging to the reconfigured superblock 602 is less than or equal to the allowable number.

[0137] (D) If the reconstructed superblock contains three or more defective blocks The reconfigured superblock 603 contains three or more bad blocks. In the example shown in Figure 9, of the N physical blocks belonging to the reconfigured superblock 603, the three physical blocks contained in memory chips CHIP#2, CHIP#N-2, and CHIP#N-1 are bad blocks, while the (N-3) physical blocks contained in the other memory chips CHIP#0, CHIP#1, and CHIP#3 to CHIP#N-3 are normal blocks.

[0138] In this case, in the management table 53D, the first field is set to the subtable 54 number, and the second field is set to the special key. The subtable 54 number and the special key are not limited to this order, but are set in the two fields in a predetermined order. The subtable 54 number set in management table 53B is information that uniquely identifies the subtable 54 associated with management table 53D. The subtable 54 associated with management table 53D contains information (block information) that indicates the physical blocks that actually constitute the superblock corresponding to management table 53D.

[0139] Therefore, since the management table 53D corresponding to a certain superblock contains the number in the subtable 54, the controller 6 can determine that the reconfigured superblock 603 corresponding to that superblock has three or more bad blocks. In other words, based on the management table 53D, the controller 6 can determine that the number of bad blocks belonging to the reconfigured superblock 601 exceeds the allowable number.

[0140] Thus, the management table 53 indicates whether the number of bad blocks belonging to the reconfigured superblock in which the corresponding superblock was reconfigured is less than or equal to the allowable number. Therefore, the controller 6 can determine whether the number of bad blocks belonging to the reconfigured superblock in which the corresponding superblock was reconfigured is less than or equal to the allowable number, based on the information contained in the management table 53.

[0141] Next, we will explain the management table 53 when the allowed number is 1.

[0142] Figure 10 shows an example of a control table 53 when the allowable number is 1. The control table 53 includes, for example, a 1-bit field and a 7-bit field. In other words, this control table 53 is an 8-bit data sequence.

[0143] Each field is set with information (values) corresponding to the number of bad blocks belonging to the reconstructed superblock. Specifically, each field is set with information corresponding to the following cases: (E) when there are no bad blocks in the reconstructed superblock or when there is one bad block, and (F) when there are two or more bad blocks in the reconstructed superblock. Examples of the management table 53 for each of cases (E) and (F) are described below.

[0144] (E) If the reconstructed superblock does not contain any bad blocks, or contains one bad block. The reconstructed superblock 610 contains no bad blocks. In the example shown in Figure 10, all N physical blocks belonging to the reconstructed superblock 610 are normal blocks.

[0145] In this case, the first field (bit 0) in the management table 53E is set to a value ("0" in Figure 10) indicating that the number of bad blocks belonging to the reconstructed superblock 610 is less than or equal to the allowable number. The second field (bits 1 to 7) is set to a special key, for example.

[0146] If a reconfigured superblock 610 contains one bad block, the second field in the management table 53E will be set to, for example, the chip number of the memory chip 41 containing this bad block.

[0147] Therefore, the controller 6 can determine, based on the management table 53E corresponding to a certain superblock, that the number of bad blocks belonging to the reconfigured superblock 610 corresponding to that superblock is less than or equal to the allowable number.

[0148] (F) If the reconstructed superblock contains two or more bad blocks The reconfigured superblock 611 contains two bad blocks. In the example shown in Figure 10, of the N physical blocks belonging to the reconfigured superblock 611, the two physical blocks contained in memory chips CHIP#0 and CHIP#N-1 are bad blocks, while the (N-2) physical blocks contained in the other memory chips CHIP#1 to CHIP#N-2 are normal blocks.

[0149] In this case, in the management table 53F, the first field is set to a value ("1" in Figure 10) indicating that the number of bad blocks belonging to the reconfigured superblock 610 exceeds the allowable number. The second field is set to the subtable 54 number. The subtable 54 number set in the management table 53F is information that uniquely identifies the subtable 54 associated with the management table 53F. The subtable 54 associated with the management table 53F contains information (block information) indicating the physical blocks that actually constitute the superblock corresponding to the management table 53F.

[0150] Therefore, since the management table 53F corresponding to a certain superblock contains the number in the subtable 54, the controller 6 can determine that the reconfigured superblock 611 corresponding to that superblock contains two or more bad blocks. In other words, based on the management table 53F, the controller 6 can determine that the number of bad blocks belonging to the reconfigured superblock 611 exceeds the allowable number.

[0151] Figure 11 shows an example of the configuration of a superblock identified based on subtable 54. Figure 11 illustrates M reconfigured superblocks SB#0 to SB#M-1, where each of the N memory chips CHIP#0 to CHIP#N-1 contains M physical blocks PB#0 to PB#M-1. Each of the reconfigured superblocks SB#0 to SB#M-1 corresponds to a set of physical blocks whose physical block numbers have the same value as the superblock number. The physical block numbers (PB#) shown in Figure 11 represent the physical block numbers before conversion based on conversion information 52. Here, the allowable number is 2, and the configuration of the management table 53 described above (i.e., a configuration containing 2 fields) is used, as shown in Figure 9.

[0152] Each of the multiple management tables 53 corresponds to each of the multiple superblocks SB#0 to SB#M-1. In other words, each of the multiple management tables 53 corresponds to each of the multiple reconfigured superblocks SB#0 to SB#M-1.

[0153] The reconfigured superblock SB#0 contains one bad block. This bad block is a physical block within the memory chip CHIP#0. Therefore, in the management table 53-0 corresponding to the reconfigured superblock SB#0 (superblock SB#0), a special key is set in the first field, and the value "0x00", which indicates the chip number of the memory chip CHIP#0, is set in the second field.

[0154] Reconstructed superblock SB#1 does not contain any bad blocks. Therefore, in the management table 53-1 corresponding to reconstructed superblock SB#1 (superblock SB#1), all fields are set to special keys.

[0155] The reconfigured superblock SB#2 contains two bad blocks. These two bad blocks are a physical block within memory chip CHIP#1 and a physical block within memory chip CHIP#N-1. Therefore, in the management table 53-2 corresponding to the reconfigured superblock SB#2 (superblock SB#2), the first field is set to the value "0x01" which indicates the chip number of memory chip CHIP#1, and the second field is set to the value "0x0N-1" which indicates the chip number of memory chip CHIP#N-1.

[0156] The reconfigured superblock SB#M-2 contains three bad blocks, i.e., three bad blocks exceeding the allowable number. These three bad blocks are physical block 902 in memory chip CHIP#2, physical block 906 in memory chip CHIP#N-2, and physical block 907 in memory chip CHIP#N-1. Therefore, in the management table 53-(M-2) corresponding to the reconfigured superblock SB#M-2 (superblock SB#M-2), the first field is set to the value "1" which indicates the subtable number 54-1 (subtable number), and the second field is set to a special key. Note that the subtable number is not limited to a number, but can be any format of information that uniquely identifies the corresponding subtable 54.

[0157] The reconfigured superblock SB#M-1 does not contain any bad blocks. Therefore, in the management table 53-(M-1) corresponding to the reconfigured superblock SB#M-1 (superblock SB#M-1), special keys are set for all fields.

[0158] Here, we will explain the block information set in subtable 54-1. Subtable 54-1 is associated with management table 53-(M-2), which corresponds to the reconfigured superblock SB#M-2 (superblock SB#M-2).

[0159] Before shipment, the reconfigured superblock SB#M-2 is configured to contain fewer than or equal to the allowable number of initial defective blocks, based on the conversion information 52. Therefore, of the three defective blocks belonging to the reconfigured superblock SB#M-2, one or more are later-developed defective blocks. For example, in the reconfigured superblock SB#M-2, physical block 902 in memory chip CHIP#2 is a later-developed defective block, while physical block 906 in memory chip CHIP#N-2 and physical block 907 in memory chip CHIP#N-1 are initial defective blocks.

[0160] In response to the occurrence of subsequent defective blocks causing the number of defective blocks belonging to the reconfigured superblock SB#M-2 to exceed the allowable number, the block management unit 141 of the controller 6 creates a subtable 54-1 associated with the management table 53-(M-2). The block management unit 141 sets the subtable number "1" of subtable 54-1 in the first field of the management table 53-(M-2). Then, the block management unit 141 replaces the defective blocks belonging to the reconfigured superblock SB#M-2 with one free physical block 71 selected using the free block pool 7. In the example shown in Figure 11, defective block 907 in the memory chip CHIP#N-1, which belongs to the reconfigured superblock SB#M-2, is replaced with the free physical block 71.

[0161] The free physical blocks managed by the free block pool 7 are, for example, free physical blocks among one or more physical blocks obtained by excluding the multiple physical blocks belonging to each of the multiple reconfigured superblocks from the multiple physical blocks contained in the multiple memory chips 41. In other words, the free physical blocks managed by the free block pool 7 are unused physical blocks (i.e., physical blocks in which no valid data is stored), such as surplus physical blocks in the NAND flash memory 4.

[0162] Alternatively, unused physical blocks belonging to a reconfigured superblock with a surplus relative to its allowance may be used as free physical blocks, or unused physical blocks belonging to a reconfigured superblock whose allowance has been freed up by performing garbage collection. A reconfigured superblock with a surplus relative to its allowance (or whose allowance has been freed up) is a reconfigured superblock whose value obtained by subtracting the number of bad blocks belonging to it from the allowance is equal to or greater than a threshold.

[0163] The block management unit 141 sets information (block information) in the subtable 54-1 indicating the N physical blocks that actually constitute the corresponding superblock SB#M-1 (reconstructed superblock SB#M-1). The subtable 54-1 includes, for example, N fields 910 to 917. Each of the N fields 910 to 917 may contain N block information. Each of the N block information indicates the N physical blocks that actually constitute the superblock SB#M-1. The block information indicates, for example, the chip number of the memory chip 41 containing the corresponding physical block and the physical block number assigned to that physical block. The block information may further include the channel number of the channel to which the memory chip 41 containing the corresponding physical block is connected and the plane number of the plane 42 within the memory chip 41 containing that physical block.

[0164] In the example shown in Figure 11, the block management unit 141 sets block information for each of the physical blocks 900 to 906 belonging to the reconfigured superblock SB#M-2 in fields 910 to 916 of subtable 54-1. Then, the block management unit 141 sets block information for the free physical block 71 that replaced physical block 907 belonging to the reconfigured superblock SB#M-2 in field 917 of subtable 54-1. The block information for the free physical block 71 includes, for example, the chip number of the memory chip 41 containing the free physical block 71, the channel number of the channel to which the memory chip 41 is connected, the plane number of the plane 42 within the memory chip 41 containing the free physical block 71, and the physical block number assigned to the free physical block 71.

[0165] Furthermore, the block management unit 141 does not need to set block information indicating a defective block 902 in field 912. Similarly, the block management unit 141 does not need to set block information indicating a defective block 906 in field 916.

[0166] In this way, if the number of defective blocks belonging to a reconfigured superblock exceeds the allowable number due to subsequent defective blocks, the controller 6 replaces the defective blocks with free physical blocks. This allows the controller 6 to maintain the number of defective blocks belonging to each reconfigured superblock below the allowable number. Furthermore, the controller 6 can manage the physical blocks that actually constitute the reconfigured superblock, including the free physical blocks that replaced the defective blocks, using subtable 54-1.

[0167] For example, if further defective blocks occur in a reconfigured superblock based on subtable 54-1, the block management unit 141 replaces the defective blocks belonging to that reconfigured superblock with one free physical block selected using the free block pool 7. The block management unit 141 then updates subtable 54-1 to change the physical block information indicating the replaced defective block to physical block information indicating the free physical block that replaced the defective block.

[0168] Next, referring to Figures 12 to 15, the processes executed in the information processing system 1 will be described.

[0169] Figure 12 is a flowchart illustrating an example of the procedure for the conversion information generation process performed on host 2. The conversion information generation process generates conversion information 52 to equalize the number of initial defective blocks in each of the multiple superblocks, taking into account the initial defective blocks that may be contained in each of the multiple memory chips 41. The CPU 21 of host 2 performs the conversion information generation process on the memory system 3 before it is shipped. Host 2, which performs the conversion information generation process, is, for example, a manufacturing device for the memory system 3.

[0170] In memory system 3, multiple physical blocks contained in each memory chip 41 are assigned multiple block numbers (block addresses) in a specific order. Furthermore, in memory system 3, multiple superblocks are configured according to a specific rule using the assigned block numbers. Each superblock is a set of at least one physical block allocated (selected) from each of the multiple memory chips 41.

[0171] First, the CPU 21 obtains information indicating the initial defective blocks contained in each memory chip 41 (defective block information) from, for example, the memory system 3 (step S11). The defective block information is obtained, for example, during the manufacturing process of the memory system 3 and stored as management data 4M. Using the defective block information, the CPU 21 generates conversion information 52 for each memory chip 41 to equalize the number of defective blocks among multiple superblocks (step S12). Specifically, the CPU 21 generates conversion information 52 for each memory chip 41 to ensure that the number of defective blocks in any of the multiple superblocks is below the allowable number.

[0172] Then, the CPU 21 sends the conversion information 52 for each generated memory chip 41 to the memory system 3 (step S13), and terminates the conversion information generation process. The CPU 21 sends the conversion information 52 to the memory system 3 at any time during the manufacturing process of the memory system 3.

[0173] Through the above conversion information generation process, the CPU 21 can generate conversion information 52 to equalize the number of initial defective blocks contained in each of the multiple superblocks, taking into account the initial defective blocks that may be contained in each of the multiple memory chips 41.

[0174] The conversion information generation process may be performed in the memory system 3. In other words, the function for realizing the conversion information generation process may be provided in the memory system 3. This function may be provided, for example, in the block management unit 141 of the CPU 14. In this case, the block management unit 141 can not only generate conversion information 52 for equalizing the number of initial defective blocks among superblocks in the memory system 3 before shipment, but can also generate conversion information 52 for equalizing the number of defective blocks among superblocks in, for example, a used or refurbished memory system 3. A used or refurbished memory system 3 is, for example, a reset memory system 3, a memory system 3 from which all user data has been erased, or a memory system 3 in which at least one of performance degradation and capacity shortage has occurred due to wear and tear of the NAND flash memory 4.

[0175] The block management unit 141 generates conversion information 52 for each memory chip 41 using bad block information indicating bad blocks in the NAND flash memory 4, in response to a request (signal) from an external device such as a host 2. The block management unit 141 then sets the generated conversion information 52 for each memory chip 41 in the corresponding block number conversion circuit 31. If the range in which data can be erased within the NAND flash memory 4 is limited, the block number conversion circuit 31 may be configured to convert only the physical block numbers of physical blocks included within that limited range. Alternatively, the block management unit 141 may generate conversion information 52 for converting only the physical block numbers of physical blocks included within that limited range.

[0176] By generating conversion information 52 for used or refurbished memory systems 3, for example, it may be possible to equalize the degree of wear between blocks, improve performance variability between superblocks through reconfiguration, and recover usable storage capacity.

[0177] Figure 13 is a flowchart showing an example of the procedure for the conversion and management information setting process performed in the memory system 3. The conversion and management information setting process is the process of setting conversion information 52 for each memory chip and a management table 53 for each superblock in the memory system 3. The CPU 14 of the memory system 3 executes the conversion and management information setting process, for example, when it receives conversion information 52 from the host 2 via the host I / F 11.

[0178] First, the CPU 14 writes the conversion information 52 received from the host 2 to the NAND flash memory 4 as part of the management data 4M (step S201).

[0179] Then, the CPU 14 sets the conversion information 52 in the block number conversion circuit 31 (step S202). Specifically, the CPU 21 reads the conversion information 52 from the NAND flash memory 4, for example, and stores the read conversion information 52 in a memory area provided in the block number conversion circuit 31. Alternatively, the CPU 21 may read the conversion information 52 from the NAND flash memory 4 and store the read conversion information 52 in the DRAM 5. In this case, the block number conversion circuit 31 refers to the conversion information 52 stored in the DRAM 5.

[0180] Next, the CPU 14 sets the variable i to 0 (step S203). The variable i is used to identify one of the M superblocks managed in the memory system 3. M is the total number of superblocks managed in the memory system 3. M is, for example, an integer greater than or equal to 2. The variable i is, for example, any integer from 0 to (M-1).

[0181] The CPU 14 creates a management table 53 corresponding to the i-th superblock (SB#i) (step S204). The management table 53 contains, for example, the same number of fields as the allowable number. The CPU 14 sets a special key (for example, "0xff") in all fields of the created management table 53 (step S205).

[0182] The CPU 14 obtains the number of bad blocks belonging to the i-th superblock (i.e., the i-th reconfigured superblock (reconfigured SB#i)) that is constructed based on the conversion information 52 (step S206). The CPU 14 determines whether the number of bad blocks belonging to the i-th reconfigured superblock is greater than 0 (step S207). In other words, the CPU 14 determines whether or not the i-th reconfigured superblock contains bad blocks.

[0183] If the number of bad blocks in the i-th reconfigured superblock is greater than 0 (Yes in step S207), the CPU 14 sets the chip numbers of the memory chips 41 containing the bad blocks in a specific order in the field of the management table 53 corresponding to the i-th superblock, and the processing by the CPU 14 proceeds to step S209. The specific order is, for example, ascending order of chip numbers.

[0184] If the number of bad blocks in the i-th reconfigured superblock is 0 (No. in step S207), the CPU 14 proceeds to step S209.

[0185] Next, CPU 14 adds 1 to variable i (step S209). CPU 14 determines whether variable i is less than the total number of superblocks M (step S210).

[0186] If the variable i is less than the total number of superblocks M (Yes in step S210), the CPU 14 returns to step S204. That is, the CPU 14 continues the process of creating a management table 53 corresponding to another superblock based on the updated variable i.

[0187] If the variable i is greater than or equal to the total number of superblocks M (No. in step S210), the CPU 14 terminates the conversion and management information setting process.

[0188] Through the above conversion and management information setting process, the CPU 14 can set the conversion information 52 for each memory chip in the block number conversion circuit 31. The CPU 14 can create a management table 53 for each superblock. Furthermore, if a bad block is included in the reconstructed superblock configured based on the conversion information 52, the CPU 14 can set the number of the memory chip 41 containing the bad block in the management table 53 of the corresponding superblock.

[0189] In the conversion and management information setting process, the example given was the case where conversion information 52 is received from host 2. However, the conversion information 52 may have already been received from host 2 and stored in NAND flash memory 4. In that case, the CPU 14 reads the conversion information 52 from NAND flash memory 4, for example, when the memory system 3 is started, and sets the read conversion information 52 in the block number conversion circuit 31.

[0190] Figure 14 is a flowchart showing an example of the bad block management process performed in the memory system 3. The bad block management process is a process for managing bad blocks belonging to each reconfigured superblock. The CPU 14 of the memory system 3 executes the bad block management process, for example, when a new bad block (later bad block) occurs in any of the M reconfigured superblocks.

[0191] First, the CPU 14 identifies the reconfigured superblock to which the newly defective physical block (i.e., the later defective block) belongs from among the M reconfigured superblocks configured based on the conversion information 52 (step S301). The reconfigured superblock to which the later defective block belongs is also called the target reconfigured superblock (target reconfigured SB). The CPU 14 obtains the superblock management table 53 (hereinafter referred to as the target management table 53) corresponding to the target reconfigured superblock (step S302).

[0192] Then, the CPU 14 uses the target management table 53 to determine whether the current number of bad blocks in the target reconfigured superblock, including the subsequently occurring bad blocks, is less than or equal to the allowable number (step S303). Specifically, for example, if special keys are set in all fields of the target management table 53, or if special keys and chip numbers are set in multiple fields of the target management table 53, the CPU 14 determines that the current number of bad blocks in the target reconfigured superblock is less than or equal to the allowable number. Also, if chip numbers are set in all fields of the target management table 53, or if subtable 54 numbers and special keys are set in multiple fields of the target management table 53, the CPU 14 determines that the current number of bad blocks in the target reconfigured superblock exceeds the allowable number.

[0193] If the current number of bad blocks in the target reconfigured superblock is less than or equal to the allowable number (Yes in step S303), the CPU 14 sets the numbers of the memory chips 41 containing the later-developing bad blocks in a specific order in the fields of the target management table 53 (step S304). If the number of the memory chip 41 containing the bad blocks is already set in any field in the management table 53, the CPU 14 sets the already set memory chip 41 numbers and the numbers of the memory chips 41 containing the later-developing bad blocks in multiple fields in the management table 53, for example, in ascending order. Then, the CPU 14 terminates the bad block management process.

[0194] If the current number of bad blocks in the target reconfigured superblock exceeds the allowable number (No. in step S303), the CPU 14 determines whether the current number of bad blocks in the target reconfigured superblock is equal to the allowable number plus 1 (step S305). In other words, the CPU 14 determines whether the number of bad blocks in the target reconfigured superblock exceeds the allowable number in response to the occurrence of subsequent bad blocks.

[0195] If the current number of bad blocks in the target reconfiguration superblock is equal to the allowable number plus 1 (Yes in step S305), the CPU 14 creates a subtable 54 (step S306). The CPU 14 sets the number of the created subtable 54 and a special key in the target management table 53 (step S307). The CPU 14 replaces one bad block belonging to the target reconfiguration superblock with one free physical block selected from the free block pool 7 (step S308). The bad block replaced by the free physical block may be a later-developing bad block or an initial bad block. The CPU 14 sets block information indicating the physical block belonging to the target reconfiguration superblock in the subtable 54 (step S309). By using this subtable 54, the CPU 14 can identify the physical block belonging to the target reconfiguration superblock without using the conversion information 52. Then, the CPU 14 terminates the bad block management process.

[0196] If the current number of bad blocks in the target reconfiguration superblock exceeds the allowable number plus 1 (No. in step S305), the CPU 14 obtains the number of the subtable 54 set in the target management table 53 (step S310). The CPU 14 uses the subtable 54 of the obtained number (hereinafter referred to as the target subtable 54) to replace one bad block belonging to the target reconfiguration superblock with one free physical block selected from the free block pool 7 (step S311). The CPU 14 updates the target subtable 54 to indicate that this free physical block belongs to the target reconfiguration superblock (step S312). Specifically, in the target subtable 54, the CPU 14 sets block information that identifies the free physical block in the field corresponding to the bad block that was replaced with a free physical block. The block information that identifies the free physical block includes, for example, the chip number of the memory chip 41 containing the free physical block and the physical block number of the free physical block. The information that allows for the identification of a free physical block may further include the channel number of the channel to which the memory chip 41 containing the free physical block is connected, and the plane number of the plane within the memory chip 41 containing the free physical block. Then, the CPU 14 terminates the bad block management process.

[0197] Through the bad block management process described above, the CPU 14 can manage the bad blocks belonging to each reconfigured superblock using the management table 53 and the subtable 54. Specifically, the CPU 14 can use the management table 53 to manage the relationship between the number of bad blocks belonging to each reconfigured superblock and the allowable number. Furthermore, if the number of bad blocks belonging to a reconfigured superblock exceeds the allowable number, the CPU 14 can replace the bad blocks with free physical blocks and manage the physical blocks that actually constitute the corresponding superblock (reconfigured superblock) using the subtable 54.

[0198] Figure 15 is a flowchart illustrating an example of the access control process performed in the memory system 3. The access control process controls access to the NAND flash memory 4 via the NAND I / F 13. The NAND I / F 13 (more specifically, the NAND controller 131) executes the access control process, for example, in response to an access request from the CPU 14. An access request from the CPU 14 is, for example, an access request in response to an access command received from the host 2 (e.g., a read command or a write command), or an access request in internal processing such as wear leveling and garbage collection. Here, it is assumed that the physical block to be accessed (e.g., chip number and physical block number) is specified in the access request.

[0199] First, the NAND I / F 13 obtains a management table 53 corresponding to the superblock to which the physical block to be accessed (hereinafter referred to as the target physical block) belongs, based on the chip number and physical block number specified in the access request (step S401). The superblock to which the target physical block belongs is also referred to as the target superblock. The NAND I / F 13 determines whether or not the obtained management table 53 contains a subtable number (step S402). This determination is equivalent to determining whether or not the N physical blocks belonging to the reconfigured superblock corresponding to the target superblock contain more bad blocks than the allowable number.

[0200] If the management table 53 does not contain a subtable number (No. in step S402), that is, if the N physical blocks belonging to the reconstructed superblock do not contain more bad blocks than the allowable number, the NAND I / F 13 obtains conversion information 52 corresponding to the memory chip containing the target physical block (hereinafter referred to as memory chip A) (step S403). The NAND I / F 13 obtains physical block number A by converting the physical block number of the target physical block using the obtained conversion information 52 (step S404). The physical block to which physical block number A is assigned is a physical block belonging to the reconstructed superblock. The NAND I / F 13 instructs memory chip A to access the physical block to which physical block number A is assigned (step S405), and terminates the access control process. Specifically, the NAND I / F 13 sends, for example, at least physical block number A to memory chip A.

[0201] If the management table 53 contains a subtable number (Yes in step S402), that is, if the N physical blocks belonging to the reconfigured superblock contain more bad blocks than the allowable number, the NAND I / F 13 obtains the subtable 54 corresponding to the target superblock based on the subtable number in the management table 53 (step S406). From the obtained subtable 54, the NAND I / F 13 obtains the physical block information corresponding to the chip number of memory chip A (step S407). For example, if the chip number of memory chip A is "1", the NAND I / F 13 obtains the information for the first physical block in the subtable 54. From the obtained physical block information, the NAND I / F 13 obtains the chip number B and the physical block number B (step S408). The memory chip B to which the chip number B is assigned is either the same memory chip as memory chip A or a different memory chip from memory chip A. The physical block in memory chip B to which physical block number B is assigned is a physical block belonging to the reconstructed superblock, or a physical block in which a bad block belonging to the reconstructed superblock has been replaced. NAND I / F13 instructs memory chip B to access the physical block to which physical block number B is assigned (step S409), and terminates the access control process. Specifically, NAND I / F13 sends, for example, at least physical block number B to memory chip B.

[0202] Through the access control process described above, the NAND I / F13 can control access to the NAND flash memory 4 in response to access requests. Specifically, when access to a physical block is requested, the NAND I / F13 controls which physical block is actually accessed depending on whether or not a subtable 54 corresponding to the superblock to which that physical block (target physical block) belongs has been created. In other words, the NAND I / F13 controls which physical block is actually accessed depending on whether or not the corresponding reconfigured superblock contains more bad blocks than the allowed number.

[0203] If subtable 54 is not created, NAND I / F 13 instructs memory chip A to access the physical block determined based on the conversion information 52 of memory chip A containing the target physical block. On the other hand, if subtable 54 is created, NAND I / F 13 uses the physical block information in subtable 54 corresponding to the chip number of memory chip A to instruct memory chip B, specified by that physical block information, to access physical block B, specified by that physical block information.

[0204] In this way, the NAND I / F 13 can control access to the NAND flash memory 4 in response to access requests using the conversion information 52, the management table 53, and the subtable 54. Furthermore, access control using the conversion information 52 makes it possible to prevent bias in access performance between superblocks.

[0205] As described above, according to this embodiment, it is possible to suppress the decrease in access performance to non-volatile memory.

[0206] The multiple memory chips 41 contained in the NAND flash memory 4 each contain multiple first blocks. The controller 6 can access the multiple memory chips 41 in parallel via the NAND I / F 13. The block management unit 141 assigns multiple first block addresses to each of the multiple first blocks in a specific order. The block management unit 141, the write control unit 142, the read control unit 143, and the NAND I / F 13 control multiple superblocks (parallel access units). Each of the multiple superblocks contains multiple second blocks, which are sets of at least one block assigned from the multiple first blocks contained in each of the multiple memory chips 41. Each of the one or more memory chips 41 contains one or more initial defective blocks. The block management unit 141 manages multiple conversion information 52 corresponding to each of the multiple memory chips 41, which is defined so that the number of initial defective blocks belonging to each of the multiple superblocks is less than or equal to an allowable number. The block management unit 141 generates multiple management tables 53, each corresponding to a plurality of superblocks, and each management table 53 indicates whether the number of bad blocks belonging to a reconfigured superblock (reconfigured parallel access unit) to which a plurality of third blocks, each converted based on a plurality of conversion information 52, belong is less than or equal to an allowable number. When access to the fourth block among a plurality of first blocks is requested, the NAND I / F 13 (more specifically, the block number conversion circuit 31) obtains the first management table 53 from the plurality of management tables 53 that corresponds to the first superblock to which the fourth block among the plurality of superblocks belongs. If the first management table 53 indicates that the number of bad blocks belonging to the reconfigured superblock is less than or equal to an allowable number, the NAND I / F 13 obtains the first conversion information 52 from the plurality of conversion information 52 that corresponds to the first memory chip 41 containing the fourth block among the plurality of memory chips 41. The NAND I / F13 translates the first block address assigned to the fourth block to the second block address based on the first translation information 52.The NAND I / F13 instructs the first memory chip 41 to access the block to which the second block address has been assigned.

[0207] In this way, the memory system 3 manages multiple superblocks (reconstructed superblocks) using conversion information 52 for each memory chip 41. The memory system 3 also generates a management table 53 for each superblock that indicates whether the number of bad blocks belonging to the corresponding reconstructed superblock is below an acceptable number. By using the conversion information 52 and the management table 53, the memory system 3 can control access to each superblock at a lower cost compared to, for example, a method of managing the set of physical blocks belonging to each of all reconstructed superblocks using table-formatted information (chip number, physical block number, etc.). Furthermore, access control using the conversion information 52 makes it possible to prevent bias in access performance between superblocks. Therefore, the memory system 3 can suppress a decrease in access performance to the NAND flash memory 4.

[0208] Each of the various functions described in this embodiment may be implemented by a circuit (processing circuit). Examples of processing circuits include a programmed processor, such as a central processing unit (CPU). This processor performs each of the described functions by executing computer programs (sets of instructions) stored in memory. This processor may be a microprocessor including electrical circuits. Examples of processing circuits also include digital signal processors (DSPs), application-specific integrated circuits (ASICs), microcontrollers, controllers, and other electrical circuit components. Each of the components other than the CPU described in this embodiment may also be implemented by a processing circuit.

[0209] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0210] 1... Information processing system, 2... Host, 3... Memory system, 4... NAND flash memory, 5... DRAM, 6... Controller, 11... Host I / F, 12... DRAM I / F, 13... NAND I / F, 14... CPU, 131... NAND controller, 141... Block management unit, 142... Write control unit, 143... Read control unit, 41... Memory chip, 42... Plane, 51... Logical-physical address translation table, 52... Translation information, 53... Management table, 54... Subtable, 4M... Management data, 4U... User data.

Claims

1. Each of the multiple non-volatile memory chips includes multiple first blocks, The plurality of non-volatile memory chips are electrically connected, The aforementioned multiple non-volatile memory chips can be accessed in parallel, A plurality of first block addresses are assigned to each of the plurality of first blocks in a specific order. The system comprises a controller configured to control parallel access to multiple non-volatile memory chips in units of multiple parallel accesses, Each of the aforementioned multiple parallel access units comprises a plurality of second blocks, which are a set of at least one block allocated from each of the plurality of first blocks contained in each of the plurality of non-volatile memory chips. One or more of the aforementioned non-volatile memory chips include one or more initial defective blocks. The aforementioned controller, The system manages multiple conversion pieces of information corresponding to each of the multiple non-volatile memory chips, such that the number of initial bad blocks belonging to each of the multiple parallel access units is less than or equal to an acceptable number. Each of the plurality of second blocks belonging to the parallel access unit is converted into a plurality of third blocks based on the conversion information, and the plurality of third blocks are reconfigured into a parallel access unit to which they belong. In the reconfigured parallel access unit, multiple pieces of management information are generated, each indicating whether the number of bad blocks belonging to it is less than or equal to the allowable number. When access to one of the plurality of first blocks, specifically the fourth block, is requested, the first management information corresponding to the first parallel access unit to which the fourth block belongs is obtained from the plurality of management information. In the first management information, if the number of bad blocks belonging to the reconfigured parallel access unit is less than or equal to the allowable number, From the plurality of conversion information, first conversion information corresponding to the first non-volatile memory chip, including the fourth block, among the plurality of non-volatile memory chips is obtained. The first block address assigned to the fourth block is converted to a second block address based on the first conversion information. The configuration is configured to instruct the first non-volatile memory chip to access the block to which the second block address has been assigned. Memory system.

2. The controller is further configured to generate one or more secondary pieces of information associated with one or more of the management information among the plurality of management information, The one or more sub-informations include a first sub-information associated with a second management information among the one or more management informations, The second management information corresponds to the second parallel access unit among the plurality of parallel access units, The controller is further configured such that, when a plurality of third block addresses assigned to each of the plurality of second blocks belonging to the second parallel access unit are converted to a plurality of fourth block addresses based on the plurality of conversion information, the controller replaces a fifth block, which is a faulty block in the plurality of third blocks, with a sixth block, and generates the first secondary information including information indicating the sixth block, in accordance with the number of bad blocks included in the plurality of third blocks to which the plurality of fourth block addresses are assigned, if the number of bad blocks exceeds the allowable number. The memory system according to claim 1.

3. The fifth block is included in the second non-volatile memory chip among the plurality of non-volatile memory chips, The fifth block address among the plurality of third block addresses is a block address assigned to the seventh block belonging to the second parallel access unit. The sixth block address among the plurality of fourth block addresses is a block address converted from the fifth block address based on the second conversion information corresponding to the second non-volatile memory chip among the plurality of conversion information, and is a block address assigned to the fifth block. The controller further, when access to the seventh block is requested, From the aforementioned multiple pieces of management information, the second management information corresponding to the second parallel access unit to which the seventh block belongs is obtained, The first secondary information associated with the second management information is obtained, Based on the first secondary information, the system is configured to instruct the second non-volatile memory chip to access the sixth block. The memory system according to claim 2.

4. The controller is further configured to update the second management information in response to the generation of the first secondary information, so as to include information that can identify the first secondary information and information indicating a first value. The memory system according to claim 2.

5. The second management information is, If the reconfigured parallel access unit corresponding to the second parallel access unit has one or more bad blocks, and the number of bad blocks is less than or equal to the allowable number, then the information includes information that can identify the non-volatile memory chip containing each of the one or more bad blocks, and the number of bad blocks is less than or equal to the allowable number. If the reconfigured parallel access unit corresponding to the second parallel access unit has more bad blocks than the allowable number, the information includes the first secondary information and the information including the first value. If no bad blocks belong to the reconfigured parallel access unit corresponding to the second parallel access unit, the following information is included, each indicating the first value: The memory system according to claim 2.

6. The first secondary information further includes information indicating the plurality of third blocks, other than the fifth block, to which each of the plurality of fourth block addresses is assigned. The memory system according to claim 2.

7. The sixth block is a free block among one or more blocks obtained by excluding the plurality of third blocks from the plurality of first blocks. The memory system according to claim 2.

8. The sixth block is an unused block belonging to the reconfigured parallel access unit whose number of bad blocks to which it belongs is equal to or greater than the threshold value obtained by subtracting the allowable number from the number of bad blocks to which it belongs. The memory system according to claim 2.

9. The first conversion information includes at least one of the following: (1) a shift operation that shifts each of the plurality of first block addresses assigned to each of the plurality of first blocks contained in the first non-volatile memory chip by an arbitrary integer; and (2) a reverse operation that reverses the order of the plurality of first block addresses assigned to each of the plurality of first blocks contained in the first non-volatile memory chip. The memory system according to claim 1.

10. The shift operation is either an operation to add an arbitrary integer to each of the plurality of first block addresses assigned to each of the plurality of first blocks included in the first non-volatile memory chip, or an operation to subtract an arbitrary integer from each of the plurality of first block addresses assigned to each of the plurality of first blocks included in the first non-volatile memory chip. The memory system according to claim 9.

11. The reverse operation is either an operation to rearrange the plurality of first block addresses, each assigned in ascending order to the plurality of first blocks contained in the first non-volatile memory chip, in descending order, or an operation to rearrange the plurality of first block addresses, each assigned in descending order to the plurality of first blocks contained in the first non-volatile memory chip, in ascending order. The memory system according to claim 9.

12. The block address assigned to each of the aforementioned plurality of second blocks is determined based on an address that identifies the corresponding parallel access unit and a mathematical rule. The memory system according to claim 1.

13. Each of the aforementioned plurality of non-volatile memory chips includes L planes, The plurality of first blocks include a plurality of blocks contained in each of the L planes, Each of the aforementioned multiple parallel access units belongs to a plurality of second blocks, which are sets of L blocks allocated per plane from the plurality of first blocks contained in each of the plurality of non-volatile memory chips. The aforementioned L is an integer of 2 or more. The memory system according to claim 1.

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