Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

To provide a semiconductor memory device with high reliability. [Solution] The semiconductor memory device comprises a laminate having conductive layers and insulating layers, wherein the conductive layers and insulating layers are alternately stacked in a first direction; a plurality of memory pillars extending in the first direction within the laminate; and a structure that divides the plurality of memory pillars and extends in the first direction within the laminate. The structure comprises a crystalline conductor extending in the first direction within the laminate; a first insulating film provided between the laminate and the crystalline conductor; a crystalline semiconductor film containing silicon provided between the crystalline conductor and the first insulating film; and a second insulating film containing silicon and oxygen provided between the crystalline semiconductor film and the side surface of the crystalline conductor. The crystalline conductor has a first crystalline region containing germanium that is in contact with the crystalline semiconductor film; and a second crystalline region provided on the first crystalline region that is in contact with the second insulating film in a second direction perpendicular to the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

Background Art

[0002] Semiconductor memory devices such as NAND flash memories in which memory cells are three-dimensionally arranged on a semiconductor wafer are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One of the problems to be solved by the invention is to provide a semiconductor memory device having high reliability.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment includes a stacked body having a conductive layer and an insulating layer, the conductive layer and the insulating layer being alternately stacked in a first direction, a plurality of memory pillars extending in the first direction within the stacked body, and a structure that divides the plurality of memory pillars and extends in the first direction within the stacked body. The structure includes a crystalline conductor extending in the first direction within the stacked body, a first insulating film provided between the stacked body and the crystalline conductor, a crystalline semiconductor film provided between the crystalline conductor and the first insulating film and containing silicon, and a second insulating film provided between the crystalline semiconductor film and the side surface of the crystalline conductor and containing silicon and oxygen. The crystalline conductor has a first crystal region containing germanium and contacting the crystalline semiconductor film, and a second crystal region provided on the first crystal region and contacting the second insulating film in a second direction perpendicular to the first direction. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing an example of a memory configuration. [Figure 2] This is a circuit diagram showing the circuit configuration of a memory cell array. [Figure 3] This is a schematic cross-sectional diagram showing an example of the structure of a semiconductor memory device. [Figure 4] This is an enlarged schematic diagram showing a portion of the cross-section of a semiconductor memory device. [Figure 5] This is a schematic plan view showing an example of a planar layout of the memory pillar MP and structure BS. [Figure 6] This is a schematic cross-sectional diagram showing an example of the structure of a memory pillar MP. [Figure 7] This is a schematic cross-sectional view showing an example of the structure of structural frame BS. [Figure 8] This figure shows an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device. [Figure 9] This figure shows an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device. [Figure 10] This figure shows an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device. [Figure 11] This figure shows an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device. [Figure 12] This figure shows an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device. [Figure 13] This figure shows an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device. [Figure 14] This is a schematic cross-sectional diagram illustrating a conventional structural example of a structural frame (BS). [Figure 15] This is a schematic cross-sectional diagram illustrating an example of the structure BS in the semiconductor memory device of this embodiment. [Figure 16] This is a schematic cross-sectional diagram illustrating the first modified example of structural frame BS. [Figure 17] This is a schematic cross-sectional diagram illustrating a second modified example of structure BS. [Figure 18]It is a cross-sectional schematic diagram for explaining a structural example of a conventional structure BS. [Figure 19] It is a cross-sectional schematic diagram for explaining a third modification example of the structure BS.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The relationship between the thickness and the planar dimensions of each component described in the drawings, the ratio of the thicknesses of each component, etc. may be different from the actual object. Also, in the embodiments, substantially the same components are denoted by the same reference numerals and the description thereof will be omitted as appropriate.

[0008] In this specification, "connect" includes not only physically connecting but also electrically connecting unless otherwise specified.

[0009] A configuration example of a semiconductor memory device will be described. FIG. 1 is a block diagram showing a configuration example of a memory. The memory includes a memory cell array 1, a command register 2, an address register 3, a sequencer 4, a driver 5, a row decoder 6, and a sense amplifier 7.

[0010] The memory cell array 1 includes a plurality of blocks BLK (BLK0 to BLK(L - 1), where L is a natural number of 2 or more). The block BLK is a set of a plurality of memory cells that store data.

[0011] The command register 2 holds a command signal CMD received from a memory controller. The command signal CMD includes, for example, instruction data for causing the sequencer 4 to execute a read operation, a write operation, and an erase operation.

[0012] Address register 3 holds the address signal ADD received from the memory controller. The address signal ADD includes, for example, the block address BA, the page address PA, and the column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select the block BLK, the word line WL, and the bit line BL, respectively.

[0013] The sequencer 4 controls the operation of the memory. The sequencer 4 controls the driver 5, the raw decoder 6, and the sense amplifier 7, etc., based on the command signal CMD held in the command register 2, for example, to perform operations such as read operations, write operations, and erase operations.

[0014] Driver 5 generates voltages used in read, write, and erase operations, etc. Driver 5 includes, for example, a DA converter. Then, driver 5 applies the generated voltage to the signal line corresponding to the selected word line WL, based on, for example, the page address PA held in the address register 3.

[0015] The raw decoder 6 selects one block BLK in the corresponding memory cell array 1 based on the block address BA held in the address register 3. Then, the raw decoder 6 transfers, for example, the voltage applied to the signal line corresponding to the selected word line WL to the selected word line WL in the selected block BLK.

[0016] During a write operation, the sense amplifier 7 applies a desired voltage to each bit line BL according to the write data DAT received from the memory controller. During a read operation, the sense amplifier 7 determines the data stored in the memory cell based on the voltage of the bit line BL and transfers the determination result to the memory controller as read data DAT.

[0017] Communication between the memory and the memory controller supports, for example, the NAND interface standard. For instance, communication between the memory and the memory controller uses the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, the ready busy signal RBn, and the input / output signal I / O.

[0018] The command latch enable signal CLE indicates that the input / output signal I / O received by memory is the command signal CMD. The address latch enable signal ALE indicates that the received signal I / O is the address signal ADD. The write enable signal WEn instructs memory to input an input / output signal I / O. The read enable signal REn instructs memory to output an input / output signal I / O.

[0019] The ready / busy signal RBn is a signal that notifies the memory controller whether the memory is in a ready state to accept instructions from the memory controller or in a busy state that does not accept instructions.

[0020] Input / output signals (I / O) are, for example, 8-bit wide signals and may include signals such as command signals (CMD), address signals (ADD), and write data signals (DAT).

[0021] The memory and memory controller described above may be combined to form a single semiconductor storage device. Examples of such semiconductor storage devices include memory cards such as SD cards and solid-state drives (SSDs).

[0022] Next, an example of the circuit configuration of memory cell array 1 will be described. Figure 2 is a circuit diagram showing the circuit configuration of memory cell array 1. Figure 2 shows block BLK0 as an example, but the configuration of the other block BLKs is the same.

[0023] Block BLK contains multiple string units SU. Each string unit SU contains multiple NAND strings NS. Figure 2 illustrates three string units SU (SU0 to SU2), but the number of string units SU is not particularly limited.

[0024] Each NAND string NS is connected to one of several bit lines BL (BL0 to BL(N-1) (where N is a natural number greater than or equal to 2)). Each NAND string NS includes, for example, a memory transistor MT, a selection transistor ST1, and a selection transistor ST2. The memory transistor MT constitutes one memory cell MC. Each NAND string NS has multiple memory cells connected in series.

[0025] The memory transistor MT includes a control gate and a charge storage layer, and is capable of non-volatile data storage. The memory transistor MT may be a MONOS type with an insulating film in the charge storage layer, or an FG type with a conductive layer in the charge storage layer. In the following embodiments, the MONOS type will be described as an example.

[0026] The control gate of a memory transistor MT is connected to the corresponding word line WL. One source and drain of one of the multiple memory transistors MT is connected to the other source and drain of another of the multiple memory transistors MT. Figure 2 illustrates multiple memory transistors MT (MT0 to MT(M-1) (where M is a natural number greater than or equal to 2)), but the number of memory transistors MT is not particularly limited.

[0027] The selection transistor ST1 is used to select the string unit SU during various operations. The number of selection transistors ST1 is not particularly limited.

[0028] The selection transistor ST2 is used to select the string unit SU during various operations. The number of selection transistors ST2 is not particularly limited.

[0029] In each NAND string NS, the drain of the selection transistor ST1 is connected to the corresponding bit line BL. The source of the selection transistor ST1 is connected to one end of the series-connected memory transistor MT. The other end of the series-connected memory transistor MT is connected to the drain of the selection transistor ST2.

[0030] In the same block BLK, the source of selection transistor ST2 is connected to source line SL. The gate of selection transistor ST1 in each string unit SU is connected to the corresponding selection gate line SGD. The gate of memory transistor MT is connected to the corresponding word line WL. The gate of selection transistor ST2 is connected to the corresponding selection gate line SGS.

[0031] Multiple NAND strings NS assigned the same column address CA are connected to the same bit line BL across multiple block BLKs. Source lines SL are connected across multiple block BLKs.

[0032] Figure 3 is a schematic cross-sectional view showing an example of the structure of a semiconductor memory device according to the embodiment. Figure 4 is an enlarged schematic view showing a part of the cross-section of the semiconductor memory device according to the embodiment. Figures 3 and 4 show the X-axis direction which is substantially parallel to the surface of the semiconductor substrate 11, the Y-axis direction which is substantially perpendicular to the X-axis along the surface, and the Z-axis direction which intersects the surface substantially perpendicularly. "Substantially parallel" may include not only the parallel direction but also, for example, a direction shifted by ±10 degrees from the parallel direction. "Substantially perpendicular" may include not only the perpendicular direction but also, for example, a direction shifted by ±10 degrees from the perpendicular direction. The Z-axis direction is, for example, the thickness direction of the semiconductor substrate 11.

[0033] The semiconductor memory device has a circuit area 10 and an array area 20. The circuit area 10 includes peripheral circuits such as a command register 2, an address register 3, a sequencer 4, a driver 5, a raw decoder 6, and a sense amplifier 7. The peripheral circuits can be composed of, for example, CMOS circuits. The array area 20 includes a memory cell array 1.

[0034] A semiconductor memory device is formed, for example, by bonding a circuit wafer W1 containing a circuit region 10 and an array wafer W2 containing an array region 20. Figure 3 shows the bonding surface B between the circuit region 10 and the array region 20.

[0035] The circuit region 10 includes a semiconductor substrate 11, a transistor 12, an interlayer insulating film 13, a contact plug 14, a wiring layer 15 containing multiple wires, a via plug 16, and a metal pad 17.

[0036] The array region 20 includes an interlayer insulating film 21, a metal pad 22, a via plug 23, a wiring layer 24 containing multiple wirings, a contact plug 25, a laminate 26, a memory pillar MP, a structure BS, a source layer 28, and an insulating film 29. Figure 3 shows one of the contact plugs 25.

[0037] The semiconductor substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The transistor 12 is provided on the semiconductor substrate 11 and includes a gate insulating film 12a and a gate electrode 12b. The transistor 12 constitutes, for example, the CMOS circuit described above. The interlayer insulating film 13 is provided on the semiconductor substrate 11 so as to cover the transistor 12. The interlayer insulating film 13 is, for example, an SiO2 film (silicon oxide film), or a multilayer film including an SiO2 film and other insulating films.

[0038] The contact plug 14, wiring layer 15, via plug 16, and metal pad 17 are formed within the interlayer insulating film 13. Specifically, the contact plug 14 is located on the semiconductor substrate 11 or on the gate electrode 12b of the transistor 12. In Figure 3, the contact plug 14 on the semiconductor substrate 11 is located on the source region and drain region (not shown) of the transistor 12. The wiring layer 15 is located on the contact plug 14. The via plug 16 is located on the wiring layer 15. The metal pad 17 is located above the semiconductor substrate 11 and on the via plug 16. The metal pad 17 is, for example, a Cu (copper) layer.

[0039] The interlayer insulating film 21 is formed on the interlayer insulating film 13. The interlayer insulating film 21 is, for example, an SiO2 film, or a laminated film including an SiO2 film and other insulating films.

[0040] The metal pad 22, via plug 23, wiring layer 24, and contact plug 25 are formed within the interlayer insulating film 21. Specifically, the metal pad 22 is located on the metal pad 17 above the semiconductor substrate 11. The metal pad 22 is, for example, a Cu layer. The via plug 23 is located on the metal pad 22. The wiring layer 24 is located on the via plug 23. Figure 3 shows one of several wirings within the wiring layer 24, which functions, for example, as a bit line BL. The contact plug 25 is located on the wiring layer 24.

[0041] The laminate 26 is provided on an interlayer insulating film 21 and includes a plurality of conductive layers 31 and a plurality of insulating layers 32 that are alternately stacked in a direction substantially parallel to the Z-axis direction. The conductive layer 31 is, for example, a metal layer including a tungsten (W) layer and functions as a word line WL. The insulating layer 32 is, for example, an SiO2 film. In this embodiment, the plurality of conductive layers 31 have the same thickness, and the plurality of insulating layers 32 have the same thickness. However, the thickness of the uppermost insulating layer 32 among these insulating layers 32 may be greater than the thickness of the other insulating layers 32.

[0042] The source layer 28 includes a semiconductor layer 37 and a metal layer 38 formed sequentially on the laminate 26, memory pillar MP, and structure BS, and functions as a source line SL. The metal layer 38 is formed directly on the semiconductor layer 37. The semiconductor layer 37 is, for example, a polycrystalline semiconductor layer such as a polysilicon layer. The metal layer 38 includes, for example, a W layer, a Cu layer, or an Al (aluminum) layer. The semiconductor layer 37 may contain P (phosphorus) atoms and H (hydrogen) atoms as impurity atoms.

[0043] The insulating film 29 is formed on the source layer 28. The insulating film 29 is, for example, an SiO2 film.

[0044] The circuit region 10 further includes a wiring layer 15a containing multiple wires and a wiring layer 15b containing multiple wires, as shown in Figure 3. In Figure 3, wiring layer 15a is provided on wiring layer 15, wiring layer 15b is provided on wiring layer 15a, and via plug 16 is provided on wiring layer 15b. In Figure 3, the circuit region 10 has three wiring layers 15, 15a, and 15b, but the number of wiring layers in the circuit region 10 may be other than three.

[0045] The array region 20 further has a wiring layer 24a containing multiple wirings, as shown in Figure 3. In Figure 3, the wiring layer 24a is provided on the via plug 23, and the wiring layer 24 is provided on the wiring layer 24a. In Figure 3, the array region 20 has two wiring layers 24 and 24a, but the number of wiring layers in the array region 20 may be other than two.

[0046] The array region 20 further includes a memory cell array 1 provided beneath the insulating film 29 within an interlayer insulating film 21. The memory cell array 1 includes a stack 26, memory pillars MP, a structure BS, a source layer 28, and the like. Each conductive layer 31 within the stack 26 functions as a word line WL, and the source layer 28 functions as a source line SL.

[0047] The memory cell array 1 includes a stepped structure 42. Each word line WL is electrically connected to the word wiring layer 44 via a contact plug 43. Meanwhile, each memory pillar MP is electrically connected to the bit line BL via a contact plug 25 and also electrically connected to the source line SL. In this embodiment, the word wiring layer 44 and the bit line BL are contained within the wiring layer 24.

[0048] The array region 20 further includes a plurality of via plugs 45 provided on the wiring layer 24, metal pads 46 provided on these via plugs 45 and the insulating film 29, and a passivation film 47 provided on the metal pads 46 and the insulating film 29.

[0049] The metal pad 46 is, for example, a Cu layer or an Al layer, and functions as an external connection pad (bonding pad) for the semiconductor memory device of this embodiment. The passivation film 47 is, for example, an insulating film such as an SiO2 film, and has an opening P that exposes the upper surface of the metal pad 46. The metal pad 46 can be electrically connected to a mounting substrate or other device through this opening P by bonding wires, solder balls, metal bumps, etc.

[0050] The memory pillar MP extends within the stack 26 in a direction substantially parallel to the Z-axis. The stack 26 and the multiple memory pillar MP form a memory cell array 1.

[0051] Multiple memory pillars MP are divided into multiple groups by a structure BS. The structure BS may be, for example, a contact embedded in the laminate 26. The structure BS may penetrate the laminate 26 in a direction substantially parallel to the Z axis and be connected to the source layer 28.

[0052] Figure 5 is a schematic plan view showing an example of a planar layout of memory pillars MP and structures BS. Figure 5 shows multiple memory pillars MP and multiple structures BS. The multiple structures BS are arranged, for example, along a direction substantially parallel to the Y-axis of the semiconductor substrate 11 and extend along a direction substantially parallel to the X-axis. The multiple memory pillars MP are arranged between the multiple structures BS. Note that the number of memory pillars MP is not limited to the number shown in Figure 5.

[0053] Figure 6 is a schematic cross-sectional view showing an example of the structure of a memory pillar MP. For convenience, Figure 6 shows the memory pillar MP with its top and bottom reversed compared to the memory pillar MP shown in Figures 3 and 4. The memory pillar MP is divided into multiple tiers, including a first tier T1 and a second tier T2 provided above the first tier T1. In both the first tier T1 and the second tier T2, the memory pillar MP extends toward the semiconductor layer 37 such that its width in the Y-axis direction narrows. The number of multiple tiers may be other than two.

[0054] The memory pillar MP comprises a block insulating film 201, a charge storage film 202, a tunnel insulating film 203, a semiconductor layer 204, a core insulating layer 205, and a cap layer 206. The block insulating film 201, the charge storage film 202, the tunnel insulating film 203, the semiconductor layer 204, and the core insulating layer 205 extend along a direction substantially parallel to the Z-axis. One memory pillar corresponds to one NAND string NS. The memory pillar MP has a memory layer. The memory layer comprises the block insulating film 201, the charge storage film 202, and the tunnel insulating film 203. The memory layer penetrates the laminate 26 in a direction substantially parallel to the Z-axis. A portion of the memory layer may extend within the semiconductor layer 37 in a direction substantially parallel to the Z-axis.

[0055] The block insulating film 201 and the core insulating layer 205 contain, for example, oxygen and silicon. The charge storage film 202 contains, for example, nitrogen and silicon. The tunnel insulating film 203 contains, for example, oxygen and silicon. The block insulating film 201 and the tunnel insulating film 203 may further contain, for example, nitrogen.

[0056] More specifically, holes corresponding to memory pillars MP are formed by penetrating multiple conductive layers 31. Block insulating films 201, charge storage films 202, and tunnel insulating films 203 are sequentially stacked on the sides of the holes. Then, a semiconductor layer 204 is formed so that its sides are in contact with the tunnel insulating film 203.

[0057] The semiconductor layer 204 extends within the laminate 26 in a direction substantially parallel to the Z-axis in both the first tier T1 and the second tier T2. The semiconductor layer 204 has channel-forming regions for the selection transistor ST1, the selection transistor ST2, and the memory transistor MT. Thus, the semiconductor layer 204 functions as a signal line connecting the current paths of the selection transistor ST1, the selection transistor ST2, and the memory transistor MT.

[0058] The semiconductor layer 204 is in contact with the surface of the tunnel insulating film 203 in each of the first tier T1 and the second tier T2. The semiconductor layer 204 includes, for example, a polycrystalline semiconductor layer such as polysilicon. The semiconductor layer 204 may also be formed, for example, by crystallizing an amorphous silicon film. The semiconductor layer 204 further extends into the interior of the semiconductor layer 37 and is in contact with the semiconductor layer 37. That is, the semiconductor layer 204 is exposed from the tunnel insulating film 203, the semiconductor layer 37 is in direct contact with the semiconductor layer 204, and the source layer 28 is electrically connected to the channel formation region of each memory pillar MP. A portion of the semiconductor layer 204 may extend within the semiconductor layer 37 in a direction substantially parallel to the Z axis.

[0059] The core insulating layer 205 is provided inside the semiconductor layer 204 in both the first tier T1 and the second tier T2. The core insulating layer 205 extends within the laminate 26 in a direction substantially parallel to the Z axis. In the XY plane, the core insulating layer 205 is surrounded by the semiconductor layer 204.

[0060] The cap layer 206 is provided on the core insulating layer 205 and is in contact with the semiconductor layer 204. The cap layer 206 contains, for example, oxygen and silicon, or polysilicon containing N-type impurity elements. For example, if the cap layer 206 contains oxygen and silicon, the diffusion of impurity elements can be suppressed. If the cap layer 206 is an insulating layer, N-type impurity elements such as phosphorus or arsenic may be implanted into the surface of the cap layer 206. The cap layer 206 is connected to the contact plug 25.

[0061] Figure 7 is a schematic cross-sectional view showing an example of the structure of structure BS. For convenience, in Figure 7, the top and bottom of structure BS are shown inverted compared to structure BS shown in Figures 3 and 4. Structure BS is divided into multiple tiers, including a first tier T1 and a second tier T2 provided above the first tier T1. In both the first tier T1 and the second tier T2, structure BS extends toward the semiconductor layer 37 such that its width in the Y-axis direction narrows. The number of multiple tiers may be other than two.

[0062] The structure BS comprises a crystalline conductor 301, an insulating film 302, a crystalline semiconductor film 303, and an insulating film 304.

[0063] The crystalline conductor 301 narrows in width in the direction substantially parallel to the Y axis toward the semiconductor layer 37 in each of the first tier T1 and the second tier T2, and extends within the laminate 26 tapering in the direction substantially parallel to the Z axis. The crystalline conductor 301 contains germanium. The crystalline conductor 301 may also contain at least one metallic element of tungsten and molybdenum. It is preferable that the crystalline conductor 301 does not contain silicon. If silicon is not included, a gas that does not contain fluorine atoms can be used as a raw material for forming the crystalline conductor 301, as will be described later. An example of the crystalline conductor 301 includes a conductive layer mainly composed of germanium. Here, the main component is the component with the highest concentration among the constituent elements. However, it is not limited to this, and the crystalline conductor 301 may be, for example, a laminate of a conductive layer mainly composed of germanium and a conductive layer mainly composed of a metallic element.

[0064] The insulating film 302 is provided between the laminate 26 and the crystalline conductor 301. The insulating film 302 prevents the multiple conductive layers 31 from being electrically connected to the crystalline conductor 301. The insulating film 302 includes, for example, silicon and oxygen. An example of the insulating film 302 is a silicon oxide film.

[0065] The crystalline semiconductor film 303 is provided between the insulating film 302 and the crystalline conductor 301. The crystalline semiconductor film 303 is provided so as to overlap with the inner bottom surface BT of the slit ST, which will be described later, in the Z-axis direction. The crystalline semiconductor film 303 contains silicon. An example of the crystalline semiconductor film 303 is a polysilicon film.

[0066] The insulating film 304 is provided between the crystalline semiconductor film 303 and the side surface of the crystalline conductor 301. The insulating film 304 is in contact with the side surface of the crystalline semiconductor film 303 in a direction substantially parallel to the Y axis. The insulating film 304 is not provided between the crystalline semiconductor film 303 and the crystalline conductor 301 in the Z axis direction. Furthermore, in this embodiment, the insulating film 304 is not provided between the crystalline semiconductor film 303 and the crystalline conductor 301 in a direction substantially parallel to the Y axis of the first tier T1, except for, for example, the tapering portion of the second tier T2. The insulating film 304 contains silicon and oxygen. An example of the insulating film 304 is a silicon oxide film.

[0067] Furthermore, the crystalline conductor 301 has a crystalline region 301A and a crystalline region 301B.

[0068] The crystalline region 301A contains germanium. Preferably, the crystalline region 301A is mainly composed of germanium. The crystalline region 301A does not contact the insulating film 304 in a direction substantially parallel to the Y-axis, but contacts the crystalline semiconductor film 303 in a direction substantially parallel to the Z-axis. The crystalline region 301A may also contact the crystalline semiconductor film 303 in directions substantially parallel to the X-axis and substantially parallel to the Y-axis. The crystalline region 301A may be, for example, polycrystalline.

[0069] The crystalline region 301B is located above the crystalline region 301A and contacts the insulating film 304 in a direction substantially parallel to the Y-axis. The crystalline region 301B contains germanium or at least one metallic element. The at least one metallic element is selected from, for example, tungsten and molybdenum. Preferably, the crystalline region 301B is mainly composed of germanium or at least one metallic element. The crystalline region 301B may be, for example, polycrystalline.

[0070] The crystalline region 301B may contain at least one element consisting of silicon, oxygen, carbon, and nitrogen. The concentration of at least one element is 1 × 10⁻⁶. 20 / cm 3 The above 1 x 10 22 / cm 3The following is preferable. This improves Young's modulus and increases flexural strength. The concentration of each element can be measured, for example, by energy-dispersive X-ray spectroscopy (EDX). If the crystalline region 301B contains silicon, it is preferable that the silicon concentration in the crystalline conductor 301 is lower than the germanium concentration in the crystalline region 301A.

[0071] The interface between crystalline region 301A and crystalline region 301B may not be visible. In this case, crystalline region 301A and crystalline region 301B can be distinguished, for example, by differences in composition determined by elemental analysis. However, this is not limited to this, and for example, the portion in contact with the crystalline semiconductor film 303 in a direction substantially parallel to the Y axis may be designated as crystalline region 301A, and the portion in contact with the insulating film 304 in a direction substantially parallel to the Y axis may be designated as crystalline region 301B.

[0072] Next, an example of a semiconductor memory device manufacturing method shown in Figure 3 will be described. Here, in particular, a series of manufacturing steps related to the formation of the structure BS will be described, and the cross-sectional structure of the array wafer W2 during manufacturing is shown in Figures 8, 9, 10, 11, 12, and 13. Figures 8 to 13 are schematic cross-sectional diagrams illustrating an example of a semiconductor memory device manufacturing method. Note that the semiconductor substrate 11, the laminate 26, the interlayer insulating film 21, and other parts of the circuit region 10 and array region 20 such as the memory pillar MP can be formed by known methods, so their explanation is omitted here.

[0073] As shown in Figure 8, a slit ST is formed. The slit ST extends within the laminate 26 containing the memory pillars MP in a direction substantially parallel to the Z-axis and penetrates the laminate 26. The slit ST divides the multiple memory pillars MP that extend within the laminate 26 in a tapering manner along the Z-axis. The slit ST has an inner bottom surface BT and an inner wall surface SW. The slit ST can be formed, for example, by partially etching the laminate 26 multiple times in a direction substantially parallel to the Z-axis using etching such as reactive ion etching (RIE).

[0074] Next, an insulating film 302 is formed as shown in Figure 9. The insulating film 302 is formed on the inner bottom surface BT and the inner wall surface SW of the slit ST. The insulating film 302 can be formed, for example, by depositing a silicon oxide film using low-pressure chemical vapor deposition (LP-CVD).

[0075] Next, as shown in Figure 10, a crystalline semiconductor film 303 is formed. The crystalline semiconductor film 303 is formed on the inner bottom surface BT and the inner wall surface SW, with the insulating film 302 in between. The crystalline semiconductor film 303 can be formed, for example, by depositing a silicon film using LP-CVD.

[0076] Next, as shown in Figure 11, an insulating film 304 is formed. The insulating film 304 is formed on the crystalline semiconductor film 303 such that it covers at least a portion of the first portion of the crystalline semiconductor film 303 that overlaps with the inner wall surface SW in directions substantially parallel to the X axis and substantially parallel to the Y axis, and exposes the second portion of the crystalline semiconductor film 303 that overlaps with the inner bottom surface BT in a direction substantially parallel to the Z axis. A portion of the first portion of the crystalline semiconductor film 303 adjacent to the inner bottom surface BT may be exposed from the insulating film 304. In this embodiment, for example, the crystalline semiconductor film 303 on the side and bottom surfaces of the first tier T1 is exposed from the insulating film 304. Also, the crystalline semiconductor film 303 on the side surface of the second tier T2 is covered by the insulating film 304. The insulating film 304 can be formed, for example, by depositing a silicon oxide film using ALD. The insulating film 304 can be made to cover at least a portion of the first portion of the crystalline semiconductor film 303 while exposing the second portion of the crystalline semiconductor film 303 from the insulating film 304, for example, by adjusting conditions such as pressure, temperature, and time during film formation.

[0077] Next, as shown in Figure 12, an amorphous body 301a is formed on the second portion of the crystalline semiconductor film 303. The amorphous body 301a is in contact with the crystalline semiconductor film 303 in a direction substantially parallel to the Z axis. The amorphous body 301a may also be in contact with the crystalline semiconductor film 303 in directions substantially parallel to the X axis and substantially parallel to the Y axis. The amorphous body 301a contains germanium. The amorphous body 301a can be formed, for example, by depositing germanium using CVD. The amorphous body 301a may be composed of, for example, a plurality of grains.

[0078] The amorphous material 301a containing germanium is not formed on the surface of the insulating film 304, which is a silicon oxide film, but only on the surface of the crystalline semiconductor film 303. This is thought to be because the oxygen atoms present on the surface of the silicon oxide film are bonded to silicon atoms, preventing them from bonding with germanium atoms.

[0079] The amorphous material 301a is preferably formed at a temperature of 300°C to 900°C. This suppresses, for example, the degradation of the insulating film and word lines of the memory cell.

[0080] The amorphous material 301a may be formed by LP-CVD using GeH4 and an amino compound as raw materials. This allows for film formation at temperatures below 900°C, for example.

[0081] The amorphous body 301a is preferably formed in a hydrogen-containing atmosphere. This can improve, for example, the embedding properties of the amorphous body 301a.

[0082] Next, as shown in Figure 13, an electrical conductor 301b is formed above the amorphous body 301a, and the amorphous body 301a is crystallized to form a crystalline body 301a1. By performing crystal growth (epitaxial growth), a crystalline conductor having the crystalline region 301A and crystalline region 301B shown in the figure is formed. The amorphous body 301a is crystallized, for example, under the conditions used to form the electrical conductor 301b.

[0083] The electrical conductor 301b is a semiconductor or conductor. The electrical conductor 301b contains germanium or at least one metallic element. The electrical conductor 301b may also be a metallic layer containing, for example, tungsten, tungsten carbide, or molybdenum as the main component. The electrical conductor 301b can be formed, for example, by depositing raw materials using CVD.

[0084] When the electrical conductor 301b contains silicon, it is preferable that the electrical conductor 301b be formed by LP-CVD using, for example, at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and a second compound selected from the group consisting of Si2H6, SiH4, SiH2Cl2, SiHCl3, Si2Cl6, SiCl4, and amino compounds containing Si as raw materials. This makes it possible to form a film with good coverage (step coverage), for example.

[0085] If the electrical conductor 301b contains oxygen, it is preferable that the electrical conductor 301b be formed by LP-CVD using at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and at least one third compound selected from the group consisting of O2, O3, N2O, NO, and CO as raw materials. This allows for the addition of oxygen without the matrix forming an oxide film, for example.

[0086] When the electrical conductor 301b contains nitrogen, it is preferable that the electrical conductor 301b be formed by LP-CVD using at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and at least one fourth compound selected from the group consisting of NH3, N2O, and NO as raw materials. This allows nitrogen to be added without the base material becoming a nitride, for example.

[0087] Subsequently, chemical dry etching is performed along a direction substantially parallel to the Z-axis until, for example, the surface of the insulating layer 32 is exposed, as shown in Figure 7. Through these steps, the structure BS can be formed.

[0088] As described above, the semiconductor memory device manufacturing method of this embodiment involves forming an amorphous body 301a on a silicon-containing crystalline semiconductor film 303 at the bottom of the slit ST, forming an electrical conductor 301b above the amorphous body 301a, and crystallizing the amorphous body 301a to form a crystalline body 301a1, and then performing crystal growth (epitaxial growth) to form a crystalline conductor 301 having a crystalline region 301A and a crystalline region 301B as shown in Figure 7. This makes it possible to suppress a decrease in the reliability of the semiconductor memory device.

[0089] The semiconductor memory device structure of this embodiment is suitable, for example, when a structure BS is formed in a slit ST having a high aspect ratio.

[0090] Figure 14 is a schematic cross-sectional diagram illustrating a conventional structural example of a structural frame BS. As shown in Figure 14, when the structural frame BS is divided into a first tier T1 and a second tier T2, and a lower slit LST corresponding to the first tier T1 and an upper slit UST corresponding to the second tier T2 are formed, the structural frame BS is formed by forming an insulating film 302 on the inner wall surfaces of both the lower slit LST and the upper slit UST, and embedding a crystalline conductor 301 such as silicon on top of the insulating film 302. The structural frame BS has a bowing shape, for example, with a narrower width in the direction substantially parallel to the X-axis or Y-axis at both ends in the Z-axis direction. The structural frame BS does not have a crystalline semiconductor film 303 or an insulating film 304. In this case, since the width of the lower slit LST and the upper slit UST may narrow in the direction substantially parallel to the Y-axis as the depth increases, voids S are likely to occur in the crystalline semiconductor film 303 formed in the lower slit LST. This is because the crystalline semiconductor film 301 is formed from the sidewall surface of the lower slit LST, making it easy for voids to form near the center of the lower slit LST. Furthermore, the width in a direction approximately parallel to the Y-axis narrows near the entrances of the lower slit LST and the upper slit UST, and at the joint between the lower slit LST and the upper slit UST. This can cause the area near the entrance of the lower slit LST to become blocked before the area near the center of the lower slit LST is filled with the crystalline conductor 301. If the continuous length of the void S increases, the flexural strength of the crystalline conductor 301 may decrease. For example, if the continuous length of the void S is 2 μm or more, the flexural strength decreases by more than 20% compared to the case where the continuous length of the void S is 0 μm or more and less than 1 μm. This can lead to a decrease in the reliability of semiconductor memory devices.

[0091] Furthermore, in conventional semiconductor memory devices, crystalline conductors 301 are generally formed by depositing silicon using CVD, but fluorine atoms contained in the raw materials tend to remain in the voids S. In this case, the fluorine atoms diffuse above or below the structure BS, making the semiconductor layer 37 below the structure BS or the interlayer insulating film 21 above the structure BS susceptible to damage. This leads to a decrease in the reliability of the semiconductor memory device.

[0092] In contrast, Figure 15 is a schematic cross-sectional diagram illustrating an example of the structure BS in the semiconductor memory device of this embodiment. As shown in Figure 15, when forming the lower slit LST and the upper slit UST in the laminate 26, first a crystalline semiconductor film 303 is formed on the side and bottom surfaces of the insulating film 302 in the first tier T1 and on the side surfaces of the insulating film 302 in the second tier T2. In addition, an insulating film 304 is formed on the side surface of the insulating film 303 in the second tier T2. As a result, amorphous material 301a is formed not on the insulating film 304, but on the first tier T1 where the silicon-containing crystalline semiconductor film 303 is exposed. For example, it is formed on the inner bottom surface BT of slit ST. Then, the amorphous material 301a in contact with the crystalline semiconductor film 303 is crystallized to form crystalline material 301a1, and by crystal growth, crystalline regions 301A and 301B are formed from the lower slit LST to the upper slit UST of slit ST. This reduces the size of the void S in the lower slit LST, and can even reduce or eliminate the void S, thereby improving the embedding properties of the crystalline conductor 301. This suppresses a decrease in flexural strength. Therefore, it suppresses a decrease in the reliability of the semiconductor memory device.

[0093] Furthermore, by growing an amorphous material 301a, which is mainly composed of germanium, instead of silicon to form a crystalline conductor 301, it is possible to select a raw material gas that contains germanium but does not contain fluorine, thereby preventing damage to the source layer 28 and the interlayer insulating film 21 by fluorine atoms. Thus, a decrease in the reliability of the semiconductor memory device can be suppressed.

[0094] (First variant of structure BS) In the above embodiment, an example was described in which the crystalline regions 301A and 301B contain germanium, but the structure BS may have another crystalline region containing at least one metallic element on top of the germanium-containing crystalline region.

[0095] Figure 16 is an enlarged schematic diagram showing a cross-section of the first modified structure BS. Similar to the structure BS shown in Figure 7, the structure BS is divided into multiple tiers, including a first tier T1 and a second tier T2 located above the first tier T1. The following description will focus on the differences from the structure BS shown in Figure 7; for other parts, the description of the structure BS shown in Figure 7 can be appropriately referenced.

[0096] The structure BS shown in Figure 16 differs from the structure BS shown in Figure 7 in that the crystalline conductor 301 has crystalline regions 301A1, 301B1, and 301C1, and the insulating film 304 is in contact with the side surface of the crystalline semiconductor film 303 at the first tier T1 and the second tier T2.

[0097] The crystalline region 301A1 contains germanium. Preferably, the crystalline region 301A1 is mainly composed of germanium. The crystalline region 301A1 does not contact the insulating film 304 in a direction substantially parallel to the Y-axis, but contacts the crystalline semiconductor film 303 in a direction substantially parallel to the Z-axis. The crystalline region 301A1 may also contact the crystalline semiconductor film 303 in directions substantially parallel to the X-axis and substantially parallel to the Y-axis. The crystalline region 301A1 may be, for example, polycrystalline. Further descriptions of the crystalline region 301A1 can be appropriately referenced from the description of the crystalline region 301A.

[0098] The crystalline region 301B1 is located above the crystalline region 301A1 in the first tier T1 and is in contact with the insulating film 304 in a direction substantially parallel to the Y-axis. The crystalline region 301B contains at least one metallic element. The at least one metallic element is selected from, for example, tungsten and molybdenum. Preferably, the crystalline region 301B1 is mainly composed of at least one metallic element. The crystalline region 301B1 may be, for example, polycrystalline.

[0099] The crystalline region 301C1 is located above the crystalline region 301B1 in the second tier T2 and is in contact with the insulating film 304 in a direction substantially parallel to the Y axis. The crystalline region 301C1 contains at least one metallic element. The at least one metallic element is selected from, for example, tungsten and molybdenum. Preferably, the crystalline region 301C1 is mainly composed of at least one metallic element. The crystalline region 301C1 may be polycrystalline, for example. The crystalline region 301C1 may have the same metallic elements as the crystalline region 301B1.

[0100] Crystalline regions 301A1, 301B1, and 301C1 can be formed, for example, by forming an amorphous body 301a mainly composed of germanium on a silicon-containing crystalline semiconductor film 303, similar to the embodiment described above, forming an electrical conductor 301b mainly composed of at least one of the metal elements above the amorphous body 301a, and then crystallizing the amorphous body 301a to form a crystalline body 301a1, which is then grown (epitaxially).

[0101] As described above, the second modification of structure BS has a crystalline region 301B1 containing a metal element and a crystalline region 301C1 on top of the crystalline region 301A1, which makes it possible to reduce the electrical resistance of the crystalline conductor 301, for example.

[0102] Furthermore, in the first tier T1 and the second tier T2, the insulating film 304 is in contact with the side surface of the crystalline semiconductor film 303. As a result, in the portion of the crystalline semiconductor film 303 that overlaps with the insulating film 304 in a direction substantially parallel to the Y-axis, the amorphous material 301a, which is mainly composed of germanium, is not deposited on the insulating film 304. Therefore, when the amorphous material 301a is crystallized to form a crystalline material 301a1 and then subjected to crystal growth (epitaxial growth), crystal growth does not proceed in the portion of the crystalline semiconductor film 303 that overlaps with the insulating film 304 in a direction substantially parallel to the Y-axis, making it easier to grow crystals from the crystalline material 301a1.

[0103] (Second variation of structure BS) Figure 17 is an enlarged schematic diagram showing a cross-section of a second modified example of structure BS. In the second modified example of structure BS, the insulating film 304 differs in that it has a gap G at the joint between the first tier T1 and the second tier. In the gap G, the insulating film 304 is not formed, and the crystalline semiconductor film 303 is in contact with the crystalline conductor 301. The following explanation will focus on the differences from structure BS shown in Figure 7, and for other parts, the explanation of structure BS shown in Figure 7 can be appropriately referenced.

[0104] The gap G is provided, for example, near the entrance of the first tier T1. For example, at the joint between the first tier T1 and the second tier, the width of the slit ST in the second tier T2 in the direction substantially parallel to the Y axis is narrower than the width of the slit ST in the first tier T1 in the direction substantially parallel to the Y axis, making it difficult to form the insulating film 304, and thus a gap G may be formed. However, even if a gap G is formed, at the joint between the first tier T1 and the second tier, the width of the slit ST in the second tier T2 in the direction substantially parallel to the Y axis is narrower than the width of the slit ST in the first tier T1 in the direction substantially parallel to the Y axis, making it difficult to form amorphous material 301a on the crystalline semiconductor film 303 facing the gap G. Therefore, in the second modification of structure BS, when the amorphous material 301a is crystallized into a crystalline material 301a1 by the insulating film 304 contacting a part of the side surface of the crystalline semiconductor film 303 at the second tier T2, and crystal growth (epitaxial growth) is performed, crystal growth does not proceed in the part of the crystalline semiconductor film 303 that overlaps with the insulating film 304 in a direction substantially parallel to the Y axis, making it easier to grow crystals from the crystalline material 301a1.

[0105] (Third variation of structure BS) In the above embodiment, an example was described in which the structure BS is divided into multiple tiers, including a first tier T1 and a second tier T2. However, the structure BS does not necessarily have to have multiple tiers.

[0106] Figure 18 is a schematic cross-sectional diagram illustrating a conventional structural example of a structural body BS. As shown in Figure 18, when the structural body BS does not have multiple tiers, it is formed by forming an insulating film 302 on the inner wall surface of a slit ST and embedding a crystalline conductor 301 such as silicon on top of the insulating film 302. The structural body BS does not have a crystalline semiconductor film 303 or an insulating film 304. In this case, the width of the slit ST may narrow in a direction substantially parallel to the Y axis as it progresses in the depth direction, making it easy for voids S to occur within the crystalline semiconductor film 303 formed in the slit ST. This is because the crystalline semiconductor film 303 is formed from the side wall surface of the slit ST, making it easy for voids to form near the center of the slit ST, and because the width narrows near the entrance of the slit ST, the area near the entrance may be blocked before the area near the center of the slit ST is filled.

[0107] Furthermore, in conventional semiconductor memory devices, crystalline conductors 301 are generally formed by depositing silicon using CVD, but fluorine atoms contained in the raw materials tend to remain in the voids S. In this case, the fluorine atoms diffuse above or below the structure BS, making the source layer 28 below the structure BS or the interlayer insulating film 21 above the structure BS susceptible to damage. This leads to a decrease in the reliability of the semiconductor memory device.

[0108] In contrast, Figure 19 is a schematic cross-sectional diagram illustrating an example of the structure BS in the semiconductor memory device of this embodiment. As shown in Figure 19, in the slit ST, similar to the structure BS shown in Figure 7, a crystalline semiconductor film 303 is formed in contact with the side surface of the insulating film 302, an insulating film 304 is formed in contact with the crystalline semiconductor film 303 in a direction substantially parallel to the Y axis, an amorphous body 301a is formed in contact with the crystalline semiconductor film 303 in the Z axis direction, an electrical conductor 301b is formed above the amorphous body 301a, and crystallization is performed to form a crystalline body 301a1, and by crystal growth (epitaxial growth), a crystalline region 301A and a crystalline region 301B are formed. As a result, a crystalline semiconductor film 303 is formed on the inner bottom surface of the slit ST, and the amorphous material 301a in contact with the crystalline semiconductor film 303 is crystallized to form a crystalline material 301a1, which can then be grown. This reduces the size of the voids S, and can be reduced or eliminated, thereby improving the embedding of the crystalline conductor 301 in the slit ST. This suppresses a decrease in flexural strength. Therefore, it is possible to suppress a decrease in the reliability of the semiconductor memory device.

[0109] Furthermore, by crystallizing an amorphous material 301a, which mainly consists of germanium instead of silicon, to form a crystalline material 301a1, and then growing the crystal to form a crystalline conductor 301, it is possible to select a raw material gas that does not contain fluorine, thereby preventing damage to the source layer 28 and the interlayer insulating film 21 by fluorine atoms. Thus, a decrease in the reliability of the semiconductor memory device can be suppressed. Further descriptions of the third modification of structure BS can be appropriately based on the descriptions of the embodiments described above.

[0110] Furthermore, the first, second, and third variations can be combined as appropriate.

[0111] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0112] 1...Memory cell array, 2...Command register, 3...Address register, 4...Programmable logic controller, 5...Driver, 6...Raw decoder, 7...Sense amplifier, 10...Circuit region, 11...Semiconductor substrate, 12...Transistor, 12a...Gate insulating film, 12b...Gate electrode, 13...Interlayer insulating film, 14...Contact plug, 15...Wiring layer, 15a...Wiring layer, 15b...Wiring layer, 16...Via plug, 17...Metal pad, 20...Array region, 21...Interlayer insulating film, 22...Metal pad, 23...Via plug, 24...Wiring layer, 24a...Wiring layer, 25 ...Contact plug, 26...Laminate, 28...Source layer, 29...Insulating film, 31...Conductive layer, 32...Insulating layer, 37...Semiconductor layer, 38...Metal layer, 42...Stepped structure, 43...Contact plug, 44...Word wiring layer, 45...Via plug, 46...Metal pad, 47...Passivation film, 201...Block insulating film, 202...Charge storage film, 203...Tunnel insulating film, 204...Semiconductor layer, 205...Core insulating layer, 206...Cap layer, 301...Crystalline conductor, 301A...Crystalline region, 301A1...Crystalline region, 301B...Crystalline region, 30 1B1...Crystal region, 301C1...Crystal region, 301a...Amorphous material, 301a1...Crystalous material, 301b...Electrical conductor, 302...Insulating film, 303...Crystalline semiconductor film, 304...Insulating film, BS...Structure, BT...Inner bottom surface, CA...Column address, CLE...Command latch enable signal, CMD...Command signal, DAT...Write data, DAT...Read data, DAT...Write data signal, G...Gap, I / O...Input / output signal, I / O...Signal, LST...Lower slit, MC...Memory cell, MP...Memory pillar, MT...Memory Molybdenum transistor, NS...NAND string, P...aperture, PA...page address, RBn...ready busy signal, REn...read enable signal, S...void, SGD...selection gate line, SGS...selection gate line, SL...source line, ST...slit, ST1...selection transistor, ST2...selection transistor, SU...string unit, SW...inner wall surface, T1...first tier, T2...second tier, UST...upper slit, W1...circuit wafer, W2...array wafer, WEn...write enable signal, WL...word line.

Claims

1. A laminate having a conductive layer and an insulating layer, wherein the conductive layer and the insulating layer are alternately stacked in a first direction, A plurality of memory pillars extending in the first direction within the laminate, The plurality of memory pillars are divided, and a structure extends within the laminate in the first direction, It is equipped with, The aforementioned structure is A crystalline conductor extending in the first direction within the laminate, A first insulating film is provided between the laminate and the crystalline conductor, A crystalline semiconductor film containing silicon is provided between the crystalline conductor and the first insulating film, A second insulating film containing silicon and oxygen is provided between the crystalline semiconductor film and the side surface of the crystalline conductor, It has, The crystalline conductor is A first crystalline region containing germanium is in contact with the crystalline semiconductor film, A second crystal region is provided on the first crystal region and is in contact with the second insulating film in a second direction perpendicular to the first direction, Having, Semiconductor memory device.

2. The structure is divided into multiple tiers, including a first tier and a second tier provided on top of the first tier. The crystalline semiconductor film is provided between the crystalline conductor and the first insulating film in the first tier and the second tier. The first crystalline region is in contact with the crystalline semiconductor film in the first tier. The semiconductor memory device according to claim 1.

3. The second insulating film is not provided between the crystalline semiconductor film and the crystalline conductor in the first direction. The semiconductor memory device according to claim 1.

4. The second crystalline region contains germanium, The semiconductor memory device according to claim 1.

5. The second crystalline region contains at least one metallic element selected from the group consisting of tungsten and molybdenum. The semiconductor memory device according to claim 1.

6. The second crystalline region contains at least one element consisting of silicon, oxygen, carbon, and nitrogen. The concentration of at least one element in the second crystalline region is 1 × 10⁻⁶ ２０ / cm ３ The above 1 x 10 ２２ / cm ３ The following is: The semiconductor memory device according to claim 1.

7. The silicon concentration in the crystalline conductor is lower than the germanium concentration in the first crystalline region. The semiconductor memory device according to claim 1.

8. A plurality of memory pillars extending in the first direction within a laminate having a conductive layer and an insulating layer, wherein the conductive layer and the insulating layer are alternately stacked in the first direction, are divided, and a slit is formed within the laminate extending in the first direction, having an inner bottom surface and an inner wall surface. A first insulating film is formed on the inner bottom surface and the inner wall surface. A crystalline semiconductor film containing silicon is formed on the first insulating film, A second insulating film containing silicon and oxygen is formed on the crystalline semiconductor film such that it covers at least a portion of the first portion of the crystalline semiconductor film that overlaps with the inner wall surface in a second direction perpendicular to the first direction, and exposes the second portion of the crystalline semiconductor film that overlaps with the inner bottom surface in the first direction. An amorphous body containing germanium is formed on the inner bottom surface in contact with the crystalline semiconductor film. An electrical conductor containing germanium or a metallic element is formed above the amorphous body in the slit, the amorphous body is crystallized to form a crystalline body, and the crystalline body is grown to form a crystalline conductor having a first crystalline region containing germanium and a second crystalline region provided on the first crystalline region and in contact with the second insulating film in the second direction. A method for manufacturing semiconductor memory devices.

9. The amorphous body is formed at a temperature of 300°C to 900°C. The method for manufacturing a semiconductor memory device according to claim 8.

10. The amorphous material is GeH ４ It is formed by a low-pressure chemical vapor deposition method using amino compounds and as raw materials. The method for manufacturing a semiconductor memory device according to claim 8.

11. The amorphous body is formed under a hydrogen-containing atmosphere. The method for manufacturing a semiconductor memory device according to claim 8.

12. The electrical conductor contains the germanium, The method for manufacturing a semiconductor memory device according to claim 8.

13. The electrical conductor contains at least one element consisting of silicon, oxygen, carbon, and nitrogen. The concentration of the at least one element in the electrical conductor is 1×10 ２０ / cm ３ or more and 1×10 ２２ / cm ３ or less, The method for manufacturing a semiconductor memory device according to claim 8.

14. The aforementioned electrical conductor contains silicon, The aforementioned electrical conductor is GeH ４ and at least one first compound selected from the group consisting of amino compounds containing Ge, and Si ２ H ６ SiH ４ SiH ２ Cl ２ SiHCl ３ Si ２ Cl ６ SiCl ４ A second compound selected from the group consisting of , and an amino compound containing Si, is formed by a low-pressure chemical vapor deposition method using as a raw material. The method for manufacturing a semiconductor memory device according to claim 8.

15. The aforementioned electrical conductor contains oxygen, The aforementioned electrical conductor is GeH ４ and at least one first compound selected from the group consisting of amino compounds containing Ge, and O ２ , O ３ , N ２ Formed by low-pressure chemical vapor deposition using at least one third compound selected from the group consisting of O, NO, and CO as a raw material. The method for manufacturing a semiconductor memory device according to claim 8.

16. The aforementioned electrical conductor contains nitrogen, The aforementioned electrical conductor is GeH ４ and at least one first compound selected from the group consisting of amino compounds containing Ge, and NH ３ , N ２ Formed by low-pressure chemical vapor deposition using at least one fourth compound selected from the group consisting of O and NO as raw materials, The method for manufacturing a semiconductor memory device according to claim 8.

17. The aforementioned electrical conductor contains tungsten, tungsten carbide, or molybdenum. The method for manufacturing a semiconductor memory device according to claim 8.

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