Signal processing circuit and method for adjusting the signal processing circuit

Abstract

To flatten the temperature characteristics of the offset of the output signal of a signal processing circuit. [Solution] The signal processing circuit includes a first current amplification circuit that outputs a first amplified current obtained by amplifying the photocurrent generated by a first photodetector, a second current amplification circuit that outputs a second amplified current obtained by amplifying the photocurrent generated by a second photodetector, and an IV conversion circuit that converts the difference current, which is the difference between the first amplified current and the second amplified current, into a voltage and outputs it. The first current amplification circuit includes a first output transistor that outputs a first amplified current, and a first bias circuit that applies a variable first bias voltage to the source of the first output transistor. The second current amplification circuit includes a second output transistor that outputs a second amplified current, and a second bias circuit that applies a variable second bias voltage to the source of the second output transistor.

Description

Technical Field

[0001] The disclosed technology relates to a signal processing circuit and a method for adjusting a signal processing circuit.

Background Art

[0002] As technologies related to a signal processing circuit of an optical encoder, the following technologies are known. For example, Patent Document 1 describes a signal processing circuit that determines that a position is a Z-phase position representing a predetermined reference position when a differential signal between a current signal generated by light reception at a first position and a current signal generated by light reception at a second position exceeds a threshold value.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An optical encoder is a sensor that detects the amount of movement of an object and includes a light emitting element, a light receiving element array, and a signal processing circuit. The signal processing circuit outputs a voltage signal corresponding to the difference in photocurrent generated at each of two light receiving elements having a specific positional relationship among the plurality of light receiving elements constituting the light receiving element array.

[0005] The threshold voltage V of a plurality of transistors constituting the signal processing circuit TH varies due to manufacturing variations. When the threshold voltage V TH varies individually and the balance between circuit blocks is lost, the offset of the output signal of the signal processing circuit varies according to changes in ambient temperature. That is, the temperature characteristic of the offset becomes non-flat. In this case, the detection accuracy in the optical encoder decreases. Therefore, it is preferable that the temperature characteristic of the offset of the output signal is flat.

[0006] The disclosed technology aims to flatten the temperature characteristics of the offset of the output signal of a signal processing circuit. [Means for solving the problem]

[0007] The signal processing circuit relating to the disclosed technology includes: a first current amplification circuit that outputs a first amplified current obtained by amplifying the photocurrent generated by a first photodetector; a second current amplification circuit that outputs a second amplified current obtained by amplifying the photocurrent generated by a second photodetector; and an IV conversion circuit that converts a differential current, which is the difference between the first amplified current and the second amplified current, into a voltage and outputs it. The first current amplification circuit includes: a first output transistor that outputs the first amplified current; and a first bias circuit that applies a variable first bias voltage to the source of the first output transistor. The second current amplification circuit includes: a second output transistor that outputs the second amplified current; and a second bias circuit that applies a variable second bias voltage to the source of the second output transistor.

[0008] The first bias circuit may have a first voltage divider circuit having a plurality of resistive elements, including at least one variable resistor, that divide a constant voltage. The second bias circuit may have a second voltage divider circuit having a plurality of resistive elements, including at least one variable resistor, that divide a constant voltage. The voltage divided by the first voltage divider circuit may be supplied to the source of the first output transistor, and the voltage divided by the second voltage divider circuit may be supplied to the source of the second output transistor.

[0009] The first bias circuit may have a first variable voltage source connected to the source of the first output transistor, having a variable output voltage. The second bias circuit may have a second variable voltage source connected to the source of the second output transistor, having a variable output voltage.

[0010] A method for adjusting a signal processing circuit according to the disclosed technology includes adjusting the first bias voltage and the second bias voltage so that the temperature characteristics of the offset of the output signal of the IV conversion circuit become flat. [Effects of the Invention]

[0011] According to the disclosed technology, it is possible to flatten the temperature characteristics of the offset of the output signal of a signal processing circuit. [Brief explanation of the drawing]

[0012] [Figure 1] This is a circuit diagram showing an example of the configuration of a signal processing circuit according to the disclosed technical embodiment. [Figure 2] This graph shows an example of the temperature characteristics of the offset. [Figure 3] This graph shows an example of the temperature characteristics of the offset. [Figure 4] This is a circuit diagram showing an example of the configuration of a signal processing circuit according to another embodiment of the disclosed technology. [Figure 5] Figure 5 is a circuit block diagram showing an example of the configuration of an optical encoder according to an embodiment of the disclosed technology. [Modes for carrying out the invention]

[0013] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, identical or equivalent components and parts will be given the same reference numerals, and redundant descriptions will be omitted.

[0014] [First Embodiment] Figure 1 is a circuit diagram showing an example of the configuration of a signal processing circuit 10 according to a first embodiment of the disclosed technology. The signal processing circuit 10 includes a first current amplifier circuit 20, a second current amplifier circuit 30, and an IV conversion circuit 50.

[0015] The first current amplification circuit 20 amplifies the current generated by the first photodetector 81 to produce a first amplified current I A1The first light-receiving element 81 generates a photocurrent corresponding to the intensity of the irradiated light. The first light-receiving element 81 may be, for example, a photodiode or a phototransistor.

[0016] The first current amplifier circuit 20 includes a current source 28, current mirror circuits 200 and 201, transistors 23, 24, and 27, and a first bias circuit 60. Current mirror circuit 200 includes transistors 21 and 22, and current mirror circuit 201 includes transistors 25 and 26. Transistors 21, 22, and 24 are p-channel type MOSFETs, and transistors 23, 25, 26, and 27 are n-channel type MOSFETs.

[0017] Transistor 21 has its source connected to power line 11, its drain connected to the drain of transistor 23, and its gate connected to its own drain and the gate of transistor 22. Transistor 22 has its source connected to power line 11, and its drain connected to the source of transistor 24.

[0018] Transistor 23 has its source connected to the cathode of the first photodetector 81 and the current source 28, and a constant voltage is applied to its gate. Transistor 24 has its drain connected to the drain of transistor 25, and a constant voltage is applied to its gate. The anode of the first photodetector 81 is connected to the ground line.

[0019] Transistor 25 has its drain connected to the drain of transistor 24, its source connected to the ground line, and its gate connected to its own drain and the gate of transistor 26. Transistor 26 has its drain connected to the source of transistor 27, and its source connected to the first bias circuit 60. Transistor 27 has its drain connected to node n1, and a constant voltage is applied to its gate.

[0020] Transistor 26 controls the first amplified current I, which is the output current of the first current amplifier circuit 20. A1This is the first output transistor that outputs [the specified signal]. The first bias circuit 60 applies a variable bias voltage to the source of the transistor 26.

[0021] The first bias circuit 60 includes a constant voltage source 61 and resistors 62 and 63. Resistor 63 is a variable resistor with a variable resistance value. The constant voltage source 61 has its negative terminal connected to the ground line and its positive terminal connected to one end of resistor 63. The other end of resistor 63 is connected to one end of resistor 62. The other end of resistor 62 is connected to the ground line. In the first bias circuit 60, a first voltage divider circuit is configured to divide the output voltage of the constant voltage source 61 by resistors 62 and 63.

[0022] The second current amplification circuit 30 amplifies the current generated by the second photodetector 82 to produce a second amplified current I A2 The output is generated. The second light-receiving element 82 generates a photocurrent corresponding to the intensity of the irradiated light. The second light-receiving element 82 is, for example, a photodiode or a phototransistor.

[0023] The second current amplifier circuit 30 includes a current source 42, current mirror circuits 300, 301, 302, transistors 33, 34, 37, 40, and a second bias circuit 70. Current mirror circuit 300 includes transistors 31 and 32, current mirror circuit 301 includes transistors 35 and 36, and current mirror circuit 302 includes transistors 38 and 39. Transistors 31, 32, 34, 38, 39, and 40 are p-channel type MOSFETs, and transistors 33, 35, 36, and 37 are n-channel type MOSFETs.

[0024] Transistor 31 has its source connected to power line 11, its drain connected to the drain of transistor 33, and its gate connected to its own drain and the gate of transistor 32. Transistor 32 has its source connected to power line 11, and its drain connected to the source of transistor 34.

[0025] Transistor 33 has its source connected to the cathode of the second photodetector 82 and the current source 42, and a constant voltage is applied to its gate. Transistor 34 has its drain connected to the drain of transistor 35, and a constant voltage is applied to its gate. The anode of the second photodetector 82 is connected to the ground line.

[0026] Transistor 35 has its drain connected to the drain of transistor 34, its source connected to the ground line, and its gate connected to its own drain and the gate of transistor 36. Transistor 36 has its drain connected to the source of transistor 37, and its source connected to the second bias circuit 70. Transistor 37 has its drain connected to the drain of transistor 38.

[0027] Transistor 38 has its source connected to power line 11, its drain connected to the drain of transistor 37, and its gate connected to its own drain and the gate of transistor 39. Transistor 39 has its source connected to power line 11, and its drain connected to the source of transistor 40. Transistor 40 has its drain connected to node n1, and a constant voltage is applied to its gate.

[0028] Transistor 36 controls the second amplified current I, which is the output current of the second current amplifier circuit 30. A2 This is a second output transistor that outputs [the specified voltage]. The second bias circuit 70 applies a variable bias voltage to the source of transistor 36.

[0029] The second bias circuit 70 includes a constant voltage source 71 and resistors 72 and 73. The resistor 73 is a variable resistor with a variable resistance value. The constant voltage source 71 has its negative terminal connected to the ground line and its positive terminal connected to one end of the resistor 73. The other end of the resistor 73 is connected to one end of the resistor 72. The other end of the resistor 72 is connected to the ground line. In the second bias circuit 70, a second voltage divider circuit is configured to divide the output voltage of the constant voltage source 71 by the resistors 72 and 73.

[0030] The I-V conversion circuit 50 converts a differential current, which is the difference between the first amplified current I A1 and the second amplified current I A2 , into a voltage and outputs it. The I-V conversion circuit 50 includes a differential amplifier 51, a resistor element 52, and a constant voltage source 53. The inverted input terminal of the differential amplifier 51 is connected to the node n1. A reference voltage V ref output from the constant voltage source 53 is applied to the non-inverted input terminal of the differential amplifier 51. One end of the resistor element 52 is connected to the node n1, and the other end is connected to the output terminal of the differential amplifier 51.

[0031] Hereinafter, the operation of the signal processing circuit 10 will be described. The photocurrent generated by the first light receiving element 81 is amplified at a magnification corresponding to the mirror ratio of the current mirror circuit 200. The amplified photocurrent is further amplified at a magnification corresponding to the mirror ratio of the current mirror circuit 201, and is output as the first amplified current I A1 from the transistor 26. The first amplified current I A1 flows in the direction of drawing current from the node n1. The current source 28 is used for the purpose of supplying an idling current to the first current amplification circuit 20. Thereby, the response performance of the first current amplification circuit 20 is improved.

[0032] The photocurrent generated by the second light receiving element 82 is amplified at a magnification corresponding to the mirror ratio of the current mirror circuit 300. The amplified photocurrent is further amplified at a magnification corresponding to the mirror ratio of the current mirror circuit 301, and is output as the second amplified current I A2 from the transistor 36. The second amplified current I A2 is folded back by the current mirror circuit 302 having a mirror ratio of 1. The folded-back current may be substantially different from the second amplified current I A2 due to variations in the mirror ratio, but can be regarded as substantially the same as the second amplified current I A2 . The folded-back second amplified current I A2The current flows in the direction of flowing into node n1. The current source 42 is used to supply idling current to the second current amplifier circuit 30. This improves the response performance of the second current amplifier circuit 30.

[0033] The IV conversion circuit 50 receives the first amplification current I A1 and the second amplification current I A2 The difference current, which is the difference between the two, is input. The IV conversion circuit 50 outputs a voltage V by converting the above difference current into a voltage. OUT Outputs.

[0034] Output signal V OUT Offset V offset The following can be superimposed. Output signal V OUT Offset V offset This is expressed by equation (1) below. In equation (1), V0 is the output signal V when there is no optical input to the first photodetector 81 and the second photodetector 82. OUT That is the case. V offset =V0-V ref ...(1)

[0035] The threshold voltage V of the transistors constituting the signal processing circuit 10 TH This value varies from the standard value due to manufacturing variations. Threshold voltage V TH These vary individually, disrupting the balance between the first current amplification circuit 20 and the second current amplification circuit 30, and causing the first amplified current I A1 and the second amplification current I A2 The temperature characteristics become mismatched, resulting in an offset V in the signal processing circuit 10. offset This fluctuates in response to changes in ambient temperature. That is, offset V offset The temperature characteristics become non-flat. TH If it deviates from the standard value, offset V offset The level itself fluctuates, but this can be eliminated in the subsequent circuit, so we won't consider it a problem here.

[0036] Figure 2 shows the offset V offsetThis graph shows an example of the temperature characteristics. Figure 2 shows the threshold voltages V of transistors 26 and 36. TH This is the standard value, and when there is a balance between the first current amplification circuit 20 and the second current amplification circuit 30, the threshold voltage V of transistors 26 and 36 TH When the values ​​vary individually and the balance between the first current amplifier circuit 20 and the second current amplifier circuit 30 is disrupted, the offset V in each case is as follows: offset The temperature characteristics are shown. In the graph in Figure 2, the vertical axis represents the offset V at an ambient temperature of -40°C. offset Offset V when set to the reference value offset This is the amount of change, and the horizontal axis is ambient temperature. As shown in Figure 2, when the balance is maintained between the first current amplifier circuit 20 and the second current amplifier circuit 30, the offset V offset The temperature characteristics are flat. On the other hand, if the balance between the first current amplifier circuit 20 and the second current amplifier circuit 30 is disrupted, the offset V offset The temperature characteristics are not flat. When the signal processing circuit 10 is applied to the optical encoder, the offset V offset If the temperature characteristics are not flat, the detection accuracy in the optical encoder decreases. Therefore, offset V offset The temperature characteristics are preferably flat.

[0037] The first bias circuit 60 adjusts the first bias voltage applied to the source of transistor 26, and the second bias circuit 70 adjusts the second bias voltage applied to the source of transistor 36, thereby reducing the offset V offset It is possible to flatten the non-flat temperature characteristics.

[0038] Drain current I of transistors 26 and 36 D This is expressed by equation (2) below. In equation (2), W and L are the gate width and gate length of transistors 26 and 36, respectively, and V GS This is the gate-source voltage of transistors 26 and 36, V TH This is the threshold voltage of transistors 26 and 36, and has a temperature characteristic.ox μ is the capacitance per unit area of ​​transistors 26 and 36, and μ is the carrier mobility, which has a temperature characteristic.

number

[0039] The gate-source voltage V of transistor 26 is adjusted by adjusting the first bias voltage applied to the source of transistor 26 by the first bias circuit 60. GS It is possible to adjust the gate-source voltage V of transistor 36 by adjusting the second bias voltage applied to the source of transistor 36 by the second bias circuit 70. GS It is possible to adjust this. For example, by increasing the resistance value of the variable resistor element 63, the first bias voltage applied to the source of transistor 26 becomes smaller, and the gate-source voltage V of transistor 26 becomes smaller. GS The threshold voltage V will increase for transistors 26 and 36 due to manufacturing variations. TH The deviation from the standard value of the gate-source voltage V GS By adjusting this, the drain current I D The discrepancy is corrected, the imbalance between the first current amplifier circuit 20 and the second current amplifier circuit 30 is eliminated, and consequently the offset V offset The temperature characteristics can be made flat.

[0040] In other words, the method for adjusting the signal processing circuit 10 is the output signal V of the IV conversion circuit 50. OUT This includes adjusting the first bias voltage in the first bias circuit 60 and the second bias voltage in the second bias circuit 70 so that the temperature characteristics of the offset become flat. The adjustment of the first bias voltage and the second bias voltage is performed, for example, by changing the combination of resistance values ​​of the resistor elements 63 and 73 while adjusting the offset V offset The process of obtaining the offset V is performed at multiple temperatures, including the upper and lower limits of the operating temperature range. offsetThis can also be done by searching for a combination of resistance values ​​for the resistor elements 63 and 73 that results in a flat temperature characteristic.

[0041] Figure 3 shows the threshold voltage V of transistors 26 and 36. TH When the values ​​vary individually and the balance between the first current amplifier circuit 20 and the second current amplifier circuit 30 is disrupted, the offset V is calculated for both cases: with and without correction performed by the first bias circuit 60 and the second bias circuit 70. offset This graph shows an example of the temperature characteristics. As shown in Figure 3, the offset V is due to the imbalance between the first current amplifier circuit 20 and the second current amplifier circuit 30. offset The non-flat temperature characteristics are achieved by adjusting the first and second bias voltages applied to the sources of transistors 26 and 36, thereby reducing the threshold voltage V TH It is possible to approximate a flat temperature characteristic, similar to that of a system without any deviations.

[0042] As described above, according to the signal processing circuit 10 of the disclosed technology, the output signal V OUT Offset V offset It is possible to flatten the temperature characteristics.

[0043] [Second Embodiment] Figure 4 is a circuit diagram showing an example of the configuration of a signal processing circuit 10A according to a second embodiment of the disclosed technology. The configuration of the first and second bias circuits in the signal processing circuit 10A according to the second embodiment differs from that of the signal processing circuit 10 according to the first embodiment (see Figure 1).

[0044] In the signal processing circuit 10A, the first bias circuit 60A has a first variable voltage source 64. The first variable voltage source 64 includes a voltage output circuit with a variable output voltage and applies a variable first bias voltage to the source of transistor 26. The second bias circuit 70A has a second variable voltage source 74. The second variable voltage source 74 includes a voltage output circuit with a variable output voltage and applies a variable second bias voltage to the source of transistor 36.

[0045] According to the signal processing circuit 10A of the second embodiment, similar to the signal processing circuit 10 of the first embodiment, the output signal V OUT Offset V offset It is possible to flatten the temperature characteristics.

[0046] [Third Embodiment] Figure 5 is a circuit block diagram showing an example of the configuration of an optical encoder 100 according to a third embodiment of the disclosed technology. The optical encoder 100 is a reflective incremental encoder IC that integrates a light-emitting element 101 and an OEIC (Opto Electronic Integrated Circuit) 102 into a single package. The light-emitting element 101 is an LED (Light Emitting Diode). The OEIC 102 includes an LED driver 103 for driving the light-emitting element 101, a plurality of light-receiving elements 104, and a signal processing circuit 105. The plurality of light-receiving elements 104 are arrayed photodiodes or phototransistors, and include a first light-receiving element 81 and a second light-receiving element 82 according to the first embodiment. The signal processing circuit 105 includes a signal processing circuit 10 according to the first embodiment or a signal processing circuit 10A according to the second embodiment.

[0047] The optical encoder 100 is used in conjunction with a scale 110 attached to an object (not shown). The scale 110 moves linearly with the object. The scale 110 has a pattern in which a plurality of reflective portions 112 with relatively high reflectivity are arranged at a constant pitch on the surface of a substrate 111 with relatively low reflectivity.

[0048] The optical encoder 100 detects the relative movement between the optical encoder 100 and the scale 110 (object) by irradiating light from the light-emitting element 101 toward the scale 110 and receiving the diffraction image of the reflected light with the photodetector element 104.

[0049] The signal processing circuit 105 incorporates either the signal processing circuit 10 according to the first embodiment or the signal processing circuit 10A according to the second embodiment. The signal processing circuit 105 processes the output signal V of the IV conversion circuit 50. OUT By processing the A-phase analog signal V A and B-phase analog signal V B Outputs the A-phase analog signal V. A and B-phase analog signal V B From this, it is possible to derive the relative movement amount between the optical encoder 100 and the scale 110 (object).

[0050] According to the optical encoder 100 of this embodiment, the internal signal offset V offset Since the temperature characteristics can be made flat, it is possible to improve the detection accuracy of the relative movement between the optical encoder 100 and the scale 110 (object). [Explanation of symbols]

[0051] 10, 10A signal processing circuit 20 First current amplifier circuit 28 Current source 30. Second current amplifier circuit 42 Current source 50 IV conversion circuit 51 Differential Amplifier 52 Resistor elements 53 Constant voltage source 60, 60A First bias circuit 61 Constant voltage source 62, 63 Resistor elements 64 Variable voltage source 70, 70A Second bias circuit 71 Constant voltage source 72, 73 Resistor elements 74 Variable voltage source 81 First light-receiving element 82 Second light-receiving element 100 Optical Encoders 101 Light-emitting element 103 LED Driver 104 Photodetector 105 Signal Processing Circuit 1 / 110 scale 111 circuit board 112 Reflector 200, 201, 300, 301, 302, Current mirror circuit 201 Current Mirror Circuit 300 Current Mirror Circuit 301 Current Mirror Circuit 302 Current Mirror Circuit

Claims

1. A first current amplification circuit that outputs a first amplified current obtained by amplifying the photocurrent generated by the first photodetector, A second current amplification circuit outputs a second amplified current, which is obtained by amplifying the photocurrent generated by the second photodetector, An I-V conversion circuit that converts the difference current, which is the difference between the first amplification current and the second amplification current, into a voltage and outputs it, Includes, The first current amplification circuit is, A first output transistor that outputs the first amplified current, A first bias circuit that applies a variable first bias voltage to the source of the first output transistor, Includes, The second current amplification circuit described above is: A second output transistor that outputs the second amplified current, A second bias circuit that applies a variable second bias voltage to the source of the second output transistor, including Signal processing circuit.

2. The first bias circuit has a first voltage divider circuit having a plurality of resistive elements, including at least one variable resistor element, which divides a constant voltage. The second bias circuit has a second voltage divider circuit having a plurality of resistive elements, including at least one variable resistor element, which divides a constant voltage. The voltage divided by the first voltage divider circuit is supplied to the source of the first output transistor. The voltage divided by the second voltage divider circuit is supplied to the source of the second output transistor. The signal processing circuit according to claim 1.

3. The first bias circuit has a first variable voltage source connected to the source of the first output transistor, the first variable voltage source having a variable output voltage, The second bias circuit has a second variable voltage source, which has a variable output voltage, connected to the source of the second output transistor. The signal processing circuit according to claim 1.

4. The first bias voltage and the second bias voltage are adjusted so that the temperature characteristics of the offset of the output signal of the I-V conversion circuit become flat. A method for adjusting a signal processing circuit according to any one of claims 1 to 3.

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