A phased array device and communication apparatus
By combining transconductance stage circuits and quadrature mixer circuits, the area of the phased array device is reduced, solving the problem of excessive size of the phased array device in the prior art, and making it suitable for the field of high-frequency millimeter-wave communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2021-03-24
- Publication Date
- 2026-06-30
AI Technical Summary
The existing phased array devices have a large area, resulting in large communication equipment that is difficult to meet the miniaturization requirements.
By combining transconductance stage circuits and quadrature mixer circuits, voltage signals are converted into current signals through transconductance unit arrays, and phase shifting and combining of signals are achieved in the quadrature mixer circuit, reducing the dependence on passive phase shifters and power divider/combiner networks.
This effectively reduces the area of the phased array device and the size of the communication equipment.
Smart Images
Figure CN116670936B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a phased array device and communication equipment. Background Technology
[0002] Phased array technology is widely used in 5G communication, microwave backhaul and indoor short-range communication.
[0003] In existing technologies, phased arrays can include multiple channels, each of which includes multiple passive devices, resulting in a large area of the phased array. Therefore, how to reduce the area of the phased array, and thus reduce the size of communication equipment using phased arrays, is a technical problem that urgently needs to be solved. Summary of the Invention
[0004] This application provides a phased array device and communication equipment, which can be used to reduce the area of the phased array.
[0005] To achieve the above objectives, this application adopts the following technical solution:
[0006] In a first aspect, a phased array device is provided, comprising: a plurality of receiving channels coupled to a plurality of antenna elements in an antenna array, each receiving channel including a transconductance stage circuit, the transconductance stage circuit including a first transconductance element array and a second transconductance element array, wherein the input terminals of the first transconductance element array and the second transconductance element array of each receiving channel are coupled to the antenna element corresponding to the receiving channel; a quadrature mixer circuit, the non-inverting input terminal and the quadrature input terminal of the quadrature mixer circuit being coupled to the output terminals of the first transconductance element array and the second transconductance element array of the plurality of receiving channels, respectively; and a signal processing circuit, the input terminal of the signal processing circuit being coupled to the output terminal of the quadrature mixer circuit, for amplifying, filtering, and other processing of the coupled currents of the plurality of receiving channels output by the quadrature mixer circuit.
[0007] In the above technical solution, each of the multiple receiving channels includes a transconductance stage circuit. The first and second transconductance unit arrays in the transconductance stage circuit can be used to convert one signal received by the corresponding coupled antenna unit into two signals. After the two signals are orthogonally mixed by the orthogonal mixer circuit, the phase shift of the signal transmitted in the receiving channel can be achieved. Moreover, the two transconductance unit arrays of different receiving channels are coupled to the orthogonal mixer circuit, thereby achieving signal combining at the orthogonal mixer circuit. Therefore, compared with the prior art, this application does not require the independent setting of passive phase shifters and power divider / combiner networks for different receiving channels, thus reducing the area of the phased array device.
[0008] In one possible implementation of the first aspect, the first transconductance element array and the second transconductance element array in each of the plurality of receiving channels have a phase-shifting function. In the above possible implementation, the first transconductance element array and the second transconductance element array in the same receiving channel can be used to convert a voltage signal received by a correspondingly coupled antenna element into two current signals. After the two current signals are orthogonally mixed by the orthogonal mixing circuit, the phase shift of the signal transmitted in the receiving channel can be achieved. Thus, by adjusting the amplitude of the two current signals, different phase shifts can be achieved after the orthogonal mixing process. Therefore, there is no need to set up an independent passive phase shifter for the receiving channel, thereby reducing the area of the phased array device.
[0009] In one possible implementation of the first aspect, both the first transconductance unit array and the second transconductance unit array include multiple transconductance stages, and the number of conducting transconductance stages is adjustable. In the above possible implementation, for each of the multiple receiving channels, by adjusting the number of conducting transconductance stages included in the two transconductance unit arrays in the receiving channel, the signal transmitted in the receiving channel can be phase-shifted at different angles, thereby reducing the area of the phased array device.
[0010] In one possible implementation of the first aspect, each of the multiple transconductance stages in each of the first and second transconductance unit arrays is provided with a corresponding bias control circuit. This bias control circuit can be used to control the conduction or disconnection of the transconductance stage. For example, the bias control circuit can output a bias voltage to control the conduction or disconnection of the transconductance stage. Thus, the number of transconductance stages in the transconductance unit array that are on or off can be controlled by the multiple bias control circuits corresponding to the multiple transconductance stages. In the above possible implementation, the number of conducting transconductance stages can be effectively controlled by the bias control circuit corresponding to each of the multiple transconductance stages. Therefore, by adjusting the number of conducting transconductance stages in the two transconductance unit arrays, the signal transmitted in the receiving channel can be phase-shifted at different angles.
[0011] In one possible implementation of the first aspect, the first transconductance unit array and the second transconductance unit array are respectively provided with a first control circuit and a second control circuit, used to control the number of transconductance stages in the first transconductance unit array and the second transconductance unit array that are turned on or off, respectively. In the above possible implementation, the number of transconductance stages in the first transconductance unit array and the second transconductance unit array that are turned on can be adjusted by the first control circuit and the second control circuit, thereby performing phase shifting of the signal transmitted in the receiving channel at different angles.
[0012] In one possible implementation of the first aspect, each of the first and second control circuits includes a switching stage circuit coupled one-to-one with the transconductance stage, the switching stage circuit being used to control the on or off state of the corresponding transconductance stage. The above possible implementations provide a simple and effective switching stage circuit for controlling the on or off state of the corresponding transconductance stage.
[0013] In one possible implementation of the first aspect, the transconductance stage in the first and second transconductance unit arrays includes: a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor, with the gate of the first MOS transistor and the gate of the second MOS transistor serving as the input terminal of the transconductance stage, the source of the first MOS transistor and the source of the second MOS transistor coupled to a first node, and the drain of the first MOS transistor and the drain of the second MOS transistor serving as the output terminal of the transconductance stage. Optionally, the transconductance stage further includes: a tail current transistor coupled between the first node and a ground terminal. The above possible implementations provide a structure of an active transconductance stage in a transconductance unit array, which can be used to convert differential voltage signals into differential current signals. Since the transconductance stage is implemented based on multiple MOS transistors, the area of the phased array device can be reduced.
[0014] In one possible implementation of the first aspect, the switching stage circuit includes a first signal generator and a second signal generator, which are respectively used to generate switching signals to turn the switching stage circuit on and off. The above possible implementations provide a simple and effective way to control the switching stage circuit to turn on or off.
[0015] In one possible implementation of the first aspect, the switching stage circuit includes: a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; wherein the gates of the third MOSFET and the sixth MOSFET are used to receive positive-phase switching signals, and the gates of the fourth MOSFET and the fifth MOSFET are used to receive negative-phase switching signals; the sources of the third MOSFET and the fourth MOSFET are coupled to a second node, and the sources of the fifth MOSFET and the sixth MOSFET are coupled to a third node, with the second and third nodes serving as the input terminals of the switching stage circuit; the drains of the third MOSFET and the fifth MOSFET are coupled to a fourth node, and the drains of the fourth MOSFET and the sixth MOSFET are coupled to a fifth node, with the fourth and fifth nodes serving as the output terminals of the switching stage circuit. The above possible implementation provides a structure for an active switching stage circuit based on multiple MOSFETs, thereby reducing the area of the phased array device.
[0016] In one possible implementation of the first aspect, the quadrature mixer circuit includes: a first quadrature mixer having a first in-phase input and a first quadrature input; a second quadrature mixer having a second in-phase input and a second quadrature input; and a local oscillator signal generator having a in-phase output and a quadrature output. The first in-phase input serves as the in-phase input of the quadrature mixer circuit and is coupled to the output of a first transconductance unit array in the plurality of receiving channels. The second quadrature input serves as the quadrature input of the quadrature mixer circuit and is coupled to the output of a second transconductance unit array in the plurality of receiving channels. The first quadrature input is coupled to the quadrature output of the local oscillator signal generator, and the second in-phase input is coupled to the in-phase output of the local oscillator signal generator. In the above possible implementation, the quadrature mixer circuit can be used to perform quadrature mixing processing on current signals output from different transconductance unit arrays in the same receiving channel. Current signals from different receiving channels can be combined, thereby achieving signal combining processing in different receiving channels.
[0017] In one possible implementation of the first aspect, each of the first and second quadrature mixers includes a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, and a tenth MOSFET; wherein the gates of the seventh and tenth MOSFETs are used to receive a positive-phase local oscillator signal, and the gates of the eighth and ninth MOSFETs are used to receive a negative-phase local oscillator signal; the sources of the seventh and eighth MOSFETs are coupled to a sixth node, and the sources of the ninth and tenth MOSFETs are coupled to a sixth node. The circuit has seven nodes; the drains of the seventh and ninth MOSFETs are coupled to the eighth node, and the drains of the eighth and tenth MOSFETs are coupled to the ninth node; the sixth and seventh nodes of the first quadrature mixer are coupled to the sixth and seventh nodes of the second quadrature mixer, respectively, serving as the output terminals of the quadrature mixer circuit; when the quadrature mixer is the first quadrature mixer, the sixth and seventh nodes serve as the first non-inverting input terminals; when the quadrature mixer is the second quadrature mixer, the sixth and seventh nodes serve as the second quadrature input terminals. Among the above possible implementations, an active quadrature mixer structure is provided, which can perform quadrature mixing processing on different differential current signals. This quadrature mixer is implemented based on multiple MOSFETs, thereby reducing the area of the phased array device.
[0018] In one possible implementation of the first aspect, each of the plurality of receiving channels further includes a low-noise amplifier, the input of which is coupled to the antenna element corresponding to the receiving channel, and the output of which is coupled to the inputs of the first transconductance element array and the second transconductance element, respectively. In the above possible implementation, the power of the voltage signal received by the receiving channel can be amplified by the low-noise amplifier in each receiving channel.
[0019] In one possible implementation of the first aspect, the signal processing circuit includes one or more of a transformer, a capacitor, a drive amplifier, a low-pass filter, and an analog-to-digital converter coupled to the output of the quadrature mixer circuit. The above-described possible implementations provide a possible structure for a signal processing circuit used to process signals.
[0020] In a second aspect, a chip module is provided, comprising: a chip and a packaging substrate, the chip being fixed to the packaging substrate, the chip comprising any phased array device provided by the first aspect or any possible implementation thereof, and the packaging substrate comprising an antenna array having a plurality of antenna elements coupled to a plurality of receiving channels.
[0021] Thirdly, a communication device is provided, which includes a phased array apparatus as provided in the first aspect or any possible implementation thereof.
[0022] Understandably, any of the chip modules and communication devices provided above include all the contents of the phased array device provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the phased array device provided above, and will not be repeated here. Attached Figure Description
[0023] Figure 1 A schematic diagram of a phased array architecture provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram of the structure of a phased array device provided in an embodiment of this application;
[0025] Figure 3 This is a schematic diagram of the structure of a receiving channel provided in an embodiment of this application;
[0026] Figure 4 This is a schematic diagram of another phased array device provided in an embodiment of this application;
[0027] Figure 5 A schematic diagram of another phased array device provided in the embodiments of this application;
[0028] Figure 6This is a schematic diagram of the structure of an orthogonal mixer circuit provided in an embodiment of this application;
[0029] Figure 7 This is a schematic diagram of another phased array device provided in an embodiment of this application;
[0030] Figure 8 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation
[0031] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.
[0032] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.
[0033] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.
[0034] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple.
[0035] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.
[0036] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0037] The technical solution provided in this application can be applied to high-frequency millimeter-wave communication. High-frequency millimeter waves have abundant spectrum resources and high bandwidth, making them suitable for application scenarios with large bandwidth and large data rates. They are widely used in 5G communication, microwave backhaul, indoor short-range communication, and other fields.
[0038] High-frequency millimeter waves have greater spatial loss in the channel and their transmission characteristics are closer to direct light. Since phased array technology can achieve more concentrated energy transmission and better signal directionality, it is often used to realize high-frequency millimeter wave communication.
[0039] In this application, the communication equipment employing phased array technology can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; the communication equipment can also be deployed on water (such as ships), and in the air (such as airplanes, balloons, and satellites). For example, the communication equipment can be a terminal or a base station. For example, the terminal includes, but is not limited to: mobile phone, tablet computer, laptop computer, handheld computer, mobile internet device (MID), wearable device (such as smartwatch, smart bracelet, pedometer, etc.), in-vehicle device (such as car, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, smart home device (such as refrigerator, television, air conditioner, electricity meter, etc.), smart robot, workshop equipment, terminal in self-driving, terminal in remote medical surgery, terminal in smart grid, terminal in transportation safety, terminal in smart city, or terminal in smart home, and flying device (such as smart robot, hot air balloon, drone, airplane, etc.).
[0040] Figure 1 This is a schematic diagram of a phased array architecture, which includes at least two phased array channels. Figure 1 (Taking two phased array channels as an example for illustration), each phased array channel can support the transmission and reception of signals in two frequency bands (i.e., B1 and B2). Each phased array channel includes an antenna (ANT), a switch (SW), front-end circuits for the two frequency bands coupled sequentially to the switch SW, and a phase shifter (PS). The PSs of the same frequency band in different phased array channels are coupled through a power splitter / combiner network, and after coupling, they are connected to the mixer amplifier circuit of their respective frequency bands. Figure 1 The front-end circuitry includes a power amplifier (PA) and a switch coupled in sequence, and a low noise amplifier (LNA) and a switch coupled in sequence; the mixer amplifier circuitry includes a switch, a mixer (MIX), and a drive amplifier (DA) coupled in sequence.
[0041] The above Figure 1 In the phased array architecture shown, phase shifting of each phased array channel is achieved by phase shifting radio frequency signals of different frequency bands. Furthermore, one or more phase shifters of the corresponding frequency band are required for radio frequency signals of different frequency bands, resulting in a large area of the phased array.
[0042] Figure 2 This is a schematic diagram of a phased array device provided in an embodiment of this application. The phased array device can be a communication device or a module applied within a communication device. Figure 2 As shown, the phased array device may include: multiple receiving channels 2 coupled to the antenna array 1, an orthogonal mixing circuit 3, and a signal processing circuit 4.
[0043] The antenna array 1 includes multiple antenna elements 11, which may include two or more antenna elements 11. Each antenna element 11 can be used to receive radio frequency signals in a first frequency band. The radio frequency signal may be a voltage signal, which may be a single-ended voltage signal or a differential voltage signal. The first frequency band may be a millimeter wave band.
[0044] The plurality of receiving channels 2 are coupled to the plurality of antenna elements 11. For example, each of the plurality of receiving channels 2 can be coupled to one of the antenna elements 11. Each of the plurality of receiving channels 2 includes a transconductance stage circuit 21, which includes a first transconductance element array 211 and a second transconductance element array 212. The input terminals of the first transconductance element array 211 and the second transconductance element array 212 of each receiving channel 2 are coupled to the antenna element 1 corresponding to that receiving channel 2. The first transconductance element array 211 and the second transconductance element array 212 are used to convert the voltage signal received by the antenna element 1 into a current signal. That is, the transconductance stage circuit 21 can be used to convert one voltage signal into two current signals.
[0045] The quadrature mixer circuit 3 includes a non-inverting input terminal P1 and a quadrature input terminal P2. The non-inverting input terminal P1 is coupled to the output terminal of the first transconductance unit array 211 in the plurality of receiving channels 2, and the quadrature input terminal P2 is coupled to the output terminal of the second transconductance unit array 212 in the plurality of receiving channels 2. The quadrature mixer circuit 3 can be used to perform quadrature mixing processing on the current signals output from the first transconductance unit array 211 and the current signals output from the second transconductance unit array 212 in the plurality of receiving channels 2. The current signals of different receiving channels 2 can be combined at the quadrature mixer circuit 3.
[0046] The signal processing circuit 4 includes an input terminal, which is coupled to the output terminal of the quadrature mixer circuit 3. The signal processing circuit 4 can be used to perform a series of signal processing functions such as amplification, filtering, and analog-to-digital conversion on the current signal output by the quadrature mixer circuit 3.
[0047] In this embodiment, each of the plurality of receiving channels 2 includes a transconductance stage circuit 21. The first transconductance element array 211 and the second transconductance element array 212 in the transconductance stage circuit 21 can be used to convert one voltage signal received by the antenna element 1 into two current signals. After the two current signals are orthogonally mixed by the orthogonal mixer circuit 3, the phase shift of the signal transmitted in the receiving channel and the combining of the signals transmitted in the plurality of receiving channels 2 can be achieved. Therefore, compared with the prior art, this application does not require the independent setting of passive phase shifters and power divider / combiner networks for different receiving channels, thereby reducing the area of the phased array.
[0048] Furthermore, both the first transconductance unit array 211 and the second transconductance unit array 212 include multiple transconductance stages, and the number of conducting transconductance stages is adjustable. Thus, for each receiving channel 2, by adjusting the number of conducting transconductance stages in the two transconductance unit arrays in the receiving channel 2, the signal transmitted in the receiving channel 2 can be phase-shifted at different angles.
[0049] For example, assuming that the voltage signal corresponding to the radio frequency signal received by the antenna unit 1 of a certain receiving channel 2 is as shown in formula (1), that is, the voltage signals received by the first transconductance unit array 211 and the second transconductance unit array 212 in the receiving channel 2 are both as shown in formula (1), then the two current signals output by the first transconductance unit array 211 and the second transconductance unit array 212 can be as shown in formula (2) and formula (3) respectively. The circuit signals after the orthogonal mixing circuit 3 performs orthogonal mixing processing on these two current signals can be as shown in formula (4) and formula (5), and the current signal output after accumulating the current signals after mixing processing can be as shown in formula (6).
[0050] Vin_I=Acos(wt) (1)
[0051] Iout_I=Acos(wt)×g m ×M (2)
[0052] Iout_Q=Acos(wt)×g m ×N (3)
[0053] Iout_mixer_I = G mixer ×Acos(ww lo )t×g m ×M(4)
[0054] Iout_mixer_Q = G mixer ×Asin(ww lo )t×g m ×N(5)
[0055]
[0056] In the formula, M is the number of transconductance stages in the first transconductance unit array 211 that are turned on, N is the number of transconductance stages in the second transconductance unit array 212 that are turned on, and g m G represents the transconductance coefficients of the first transconductance element array 211 and the second transconductance element array 212. mixer Let w be the mixing coefficient of the quadrature mixer circuit 3. lo This is the angular frequency of the local oscillator signal used for quadrature mixing.
[0057] Combining formulas (1) to (6) above, it can be seen that the phase of the signal transmitted in receiving channel 2 can be achieved as follows: The adjustment, and The value of is related to M and N. By adjusting the number of multiple transconductance stages included in the first transconductance unit array 211 and the second transconductance unit array 212 in the receiving channel 2, the signal transmitted in the receiving channel 2 can be phase-shifted at different angles.
[0058] Furthermore, the adjustment of the number of conducting transconductance stages in the first transconductance unit array 211 and the second transconductance unit array 212 can be achieved in the following two ways, as described in detail below.
[0059] In the first method, each of the multiple transconductance stages in each of the first transconductance unit array 211 and the second transconductance unit array 212 is provided with a bias control circuit. The bias control circuit can be used to control the conduction or disconnection of the transconductance stage. For example, the bias control circuit can be used to output a bias voltage to control the conduction or disconnection of the transconductance stage. Thus, the number of transconductance stages in the transconductance unit array that are turned on or off can be controlled by the multiple bias control circuits corresponding to the multiple transconductance stages.
[0060] The second method, such as Figure 3 As shown, the first transconductance unit array 211 and the second transconductance unit array 212 in the same receiving channel 2 are respectively provided with a first control circuit 213 and a second control circuit 214, which are used to control the number of transconductance stages in the first transconductance unit array 211 and the second transconductance unit array 212 to be turned on or off respectively.
[0061] For example, each control circuit in the first control circuit 213 and the second control circuit 214 may include multiple switching stage circuits. These multiple switching stage circuits are coupled one-to-one with multiple transconductance stages in the corresponding transconductance unit array. A switching stage circuit coupled to a transconductance stage can be used to control the conduction or disconnection of that transconductance stage. Optionally, each switching stage circuit may be equipped with a first signal generator and a second signal generator. The first signal generator and the second signal generator can be used to generate switching signals to turn the switching stage circuit on and off, respectively, thereby controlling the opening or closing of the switching stage circuit through the first signal generator and the second signal generator.
[0062] Both of the above implementation methods can be applied to scenarios where the corresponding antenna element 11 is used to receive single-ended voltage signals and differential voltage signals. When the voltage signals received by the antenna element 11 are different, the structures of the transconductance stages in the first transconductance element array 211 and the second transconductance element array 212, the bias control circuit corresponding to each transconductance stage, and the switching stage circuit corresponding to each transconductance stage will also differ. The following mainly uses the second method of the antenna element 11 receiving single-ended voltage signals and receiving differential voltage signals as examples to describe in detail the structure of the transconductance stage and the switching stage circuit.
[0063] When the antenna element 11 is used to receive a single-ended voltage signal, such as Figure 4 As shown, the transconductance stage may include: a first metal-oxide-semiconductor (MOS) transistor M11, the gate of the first MOS transistor M11 serving as the input terminal of the transconductance stage and used to receive the single-ended voltage signal VIN, the source of the first MOS transistor M11 coupled to ground, and the drain of the first MOS transistor M11 serving as the output terminal of the transconductance stage for outputting a single-ended current signal. Correspondingly, as... Figure 4 As shown, the switching stage circuit may include: a second MOS transistor M12, the source of the second MOS transistor M12 being coupled to the output terminal of the corresponding transconductance stage, the drain of the second MOS transistor M12 serving as the output terminal of the switching stage circuit, and the gate of the third MOS transistor M13 being used to receive the switching signal S.
[0064] Specifically, after receiving a single-ended voltage signal through the gate of the first MOSFET M11, the transconductance stage converts the single-ended voltage signal into a single-ended current signal and outputs it from the drain of the first MOSFET M11, i.e., from the output terminal of the transconductance stage. When the second MOSFET M12 in the switching stage circuit is turned on, the switching stage circuit is in the on state, thereby transmitting the single-ended current signal output by the transconductance stage to the quadrature mixer circuit 3. When the second MOSFET M12 in the switching stage circuit is turned off, the switching stage circuit is in the off state, and the corresponding transconductance stage is in the off state.
[0065] When the antenna element 11 is used to receive differential voltage signals, such as Figure 5 As shown, the transconductance stage may include: a first MOSFET M21 and a second MOSFET M22. The gates of the first MOSFET M21 and the second MOSFET M22 serve as the differential input terminals of the transconductance stage and are used to receive the differential voltage signal VIN. The sources of the first MOSFET M11 and the second MOSFET M22 are coupled to the first node. The drains of the first MOSFET M11 and the second MOSFET M22 serve as the differential output terminals of the transconductance stage and are used for differential current signals. Optionally, the transconductance stage may further include: a tail current transistor M0 coupled between the first node and the ground terminal. The tail current transistor M0 may be a MOSFET, for example, the MOSFET is coupled to the first node and the ground terminal through its source and drain respectively, and the gate of the MOSFET is used to receive a bias voltage signal.
[0066] Correspondingly, such as Figure 5 As shown, the switching stage circuit may include: a third MOSFET M23, a fourth MOSFET M24, a fifth MOSFET M25, and a sixth MOSFET M26. In this circuit, the gates of the third MOSFET M23 and the sixth MOSFET M26 are used to receive the positive phase switching signal S+, and the gates of the fourth MOSFET M24 and the fifth MOSFET M25 are used to receive the negative phase switching signal S-. The positive phase switching signal S+ and the negative phase switching signal S- constitute the differential switching signal used to turn the switching stage circuit on or off. The sources of the third MOSFET M23 and the fourth MOSFET M24 are coupled to the second node, and the sources of the fifth MOSFET M25 and the sixth MOSFET are coupled to the third node. The second and third nodes are the input terminals of this switching stage circuit and can be used to receive the differential current signal output by the corresponding transconductance stage. The drains of the third MOSFET M23 and the fifth MOSFET M25 are coupled to the fourth node, and the drains of the fourth MOSFET M24 and the sixth MOSFET M26 are coupled to the fifth node. The fourth and fifth nodes are the differential output terminals of this switching stage circuit, and these differential output terminals can be used to output the differential current signal.
[0067] Specifically, after receiving a differential voltage signal through the gate of the first MOSFET M21 and the gate of the second MOSFET M22, the transconductance stage converts the differential voltage signal into a differential current signal and outputs it from the drain of the first MOSFET M21 and the drain of the second MOSFET M22, i.e., from the differential output terminal of the transconductance stage. When the third MOSFET M23, the fourth MOSFET M24, the fifth MOSFET M25, and the sixth MOSFET M26 in the switching stage circuit are all turned on, the switching stage circuit is in the on state, thereby transmitting the differential current signal output by the transconductance stage to the quadrature mixer circuit 3. When the third MOSFET M23, the fourth MOSFET M24, the fifth MOSFET M25, and the sixth MOSFET M26 in the switching stage circuit are all turned off, the switching stage circuit is in the off state, and the corresponding transconductance stage is also in the off state.
[0068] It should be noted that the MOSFETs in the above transconductance stage and switching stage circuits can be either NMOS or PMOS transistors. Figure 4 and Figure 5 This explanation uses only a PMOS transistor as an example. Figure 4 and Figure 5 The structure of the transconductance stage and switching stage circuits in this application does not constitute a limitation on the embodiments thereof.
[0069] Furthermore, the quadrature mixer circuit 3 may include a first quadrature mixer 31 having a first in-phase input and a first quadrature input, a second quadrature mixer 32 having a second in-phase input and a second quadrature input, and a local oscillator signal generator 33 having an in-phase output and a quadrature output. Specifically, the first in-phase input serves as the in-phase input P1 of the quadrature mixer circuit 3 and is coupled to the output of the first transconductance unit array 211 in the plurality of receiving channels 2; the second quadrature input serves as the quadrature input P2 of the quadrature mixer circuit 3 and is coupled to the output of the second transconductance unit array 212 in the plurality of receiving channels 2; the first quadrature input is coupled to the quadrature output of the local oscillator signal generator 33; and the second in-phase input is coupled to the in-phase output of the local oscillator signal generator 33.
[0070] For example, such as Figure 6As shown, taking one of the multiple receiving channels 2 as an example, the output terminal of the first transconductance unit array 211 in the receiving channel 2 can be coupled to the first non-inverting input terminal of the first quadrature mixer 31, the output terminal of the second transconductance unit array 212 can be coupled to the second quadrature input terminal of the second quadrature mixer 32, the first quadrature input terminal of the first quadrature mixer 31 can be coupled to the quadrature output terminal of the local oscillator signal generator 33, and the second non-inverting input terminal of the second quadrature mixer 32 can be coupled to the non-inverting output terminal of the local oscillator signal generator 33. The output terminal of the first quadrature mixer 31 and the output terminal of the second quadrature mixer 32 are coupled together as the output terminal of the quadrature mixing circuit 3.
[0071] The above Figure 6 The quadrature mixer circuit shown is also applicable to the scenarios where the corresponding antenna unit 11 is used to receive single-ended voltage signals and to receive differential voltage signals. The specific structures of the first quadrature mixer 31 and the second quadrature mixer 33 in these two cases will be described in detail below.
[0072] When the antenna element 11 is used to receive a single-ended voltage signal, such as Figure 4 As shown, each quadrature mixer in the first quadrature mixer 31 and the second quadrature mixer 33 may include: a third MOSFET M13, the source of the third MOSFET M13 serving as the input terminal of the quadrature mixer, the drain of the third MOSFET M13 serving as the output terminal of the quadrature mixer, and the gate of the third MOSFET M13 used to receive the local oscillator signal. Specifically, the gate of the third MOSFET M13 in the first quadrature mixer 31 can be used to receive a local oscillator signal with a phase of 0°, and the gate of the third MOSFET M13 in the second quadrature mixer 32 can be used to receive a local oscillator signal with a phase of 90°. The drain of the third MOSFET M13 in the first quadrature mixer 31 is coupled to the drain of the third MOSFET M13 in the second quadrature mixer 32, serving as the output terminal of the quadrature mixer circuit 3.
[0073] When the antenna element 11 is used to receive differential voltage signals, such as Figure 5As shown, each quadrature mixer in the first quadrature mixer 31 and the second quadrature mixer 33 may include: a seventh MOSFET M27, an eighth MOSFET M28, a ninth MOSFET M29, and a tenth MOSFET M30. The gates of the seventh MOSFET M27 and the tenth MOSFET are used to receive positive-phase local oscillator signals, while the gates of the eighth MOSFET M28 and the ninth MOSFET M29 are used to receive negative-phase local oscillator signals. The sources of the seventh MOSFET M27 and the eighth MOSFET M28 are coupled to the sixth node, and the sources of the ninth MOSFET M29 and the tenth MOSFET M30 are coupled to the seventh node. The drains of the seventh MOSFET M27 and the ninth MOSFET M29 are coupled to the eighth node, and the drains of the eighth MOSFET M28 and the tenth MOSFET M30 are coupled to the ninth node. In addition, the sixth and seventh nodes in the first quadrature mixer 31 are coupled to the sixth and seventh nodes in the second quadrature mixer 32, respectively, as the differential output terminals of the quadrature mixer circuit 3. The phase of the positive phase local oscillator signal received in the first quadrature mixer 31 can be 180° and the phase of the negative phase local oscillator signal can be 0°. The phase of the positive phase local oscillator signal received in the second quadrature mixer 32 can be 90° and the phase of the negative phase local oscillator signal can be 270°.
[0074] It should be noted that the MOSFETs in the aforementioned quadrature mixer can be either NMOS or PMOS transistors. Figure 4 and Figure 5 This explanation uses only a PMOS transistor as an example. Figure 4 and Figure 5 The structure of the quadrature mixer in the present application does not constitute a limitation on the embodiments thereof.
[0075] Furthermore, such as Figure 7 As shown, each of the plurality of receiving channels 2 further includes a low noise amplifier (LNA), the input of which is coupled to the antenna element 1 corresponding to the receiving channel 2, and the output of which is coupled to the input of the first transconductance element array 211 and the input of the second transconductance element 212, respectively.
[0076] In addition, the signal processing circuit 4 may include one or more of the following coupled to the output of the quadrature mixer circuit 3: a transformer T, a capacitor C, a drive amplifier (DA), a low-pass filter (LPF), and an analog-to-digital converter (ADC). Figure 7 The following description uses only the signal processing circuit 4, which includes a transformer T and a capacitor C, as an example.
[0077] In the phased array device provided in this application embodiment, each of the plurality of receiving channels 2 includes a transconductance stage circuit 21. The first transconductance unit array 211 and the second transconductance unit array 212 in the transconductance stage circuit 21 can be used to convert the voltage signal received by the antenna unit 1 into a current signal. Then, by accumulating the current signals of different receiving channels, the signal combining processing in different receiving channels can be realized. In addition, the first transconductance unit array 211 and the second transconductance unit array 212 in each of the plurality of receiving channels 2 can be used to convert one received voltage signal into two current signals. After the two current signals are orthogonally mixed by the orthogonal mixing circuit 3, the phase shift of the signal transmitted in the receiving channel 2 can be realized. Therefore, compared with the prior art, this application does not require the independent setting of passive phase shifters and power divider / combiner networks for different receiving channels, thereby reducing the area of the phased array.
[0078] In another embodiment of this application, a chip module is also provided, which includes a chip and a packaging substrate. The chip includes a phased array device, which can be any of the phased array devices provided above. The packaging substrate can include the antenna array provided above.
[0079] like Figure 8 As shown in the figure, this application embodiment also provides a communication device, which includes a memory 101, a processor 102, and the phased array device 103 provided above.
[0080] It should be understood that the communication device can specifically be a smartphone, computer, smartwatch, or other terminal device. When the terminal device is a smartphone, the phased array device 103 can also be referred to as a communication circuit, and the terminal device may also include an input / output device 104. The processor 102 is mainly used to process communication protocols and communication data, control the entire smartphone, execute software programs, and process software program data. The memory 101 is mainly used to store software programs and data. The phased array device 103 is mainly used for the conversion between baseband signals and radio frequency signals, the processing of radio frequency signals, and the transmission and reception of radio frequency signals in the form of electromagnetic waves. The input / output device, such as a touch screen, display screen, or keyboard, is mainly used to receive user input data and output data to the user.
[0081] When the smartphone is powered on, the processor 102 can read the software program in the memory 101, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 102 performs baseband processing on the data to be transmitted and outputs a baseband signal to the phased array device 103. The phased array device 103 performs radio frequency processing on the baseband signal and transmits the radio frequency signal outward in the form of electromagnetic waves through the antenna. When data is sent to the smartphone, the phased array device 103 receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 102. The processor 102 converts the baseband signal into data and processes the data.
[0082] Those skilled in the art will understand that, for ease of explanation, Figure 8 Only one memory and one processor are shown. In actual terminal devices, multiple processors and multiple memories may exist. Memory can also be called storage medium or storage device, etc. It should be noted that the type of memory is not limited in the embodiments of this application.
[0083] It should be understood that the Xth frequency band mentioned in the embodiments of this application, such as the first frequency band, refers to a fixed frequency range defined by a standards organization or used commercially, including but not limited to the 5G millimeter wave frequency bands defined by 3GPP in the embodiments of this application, such as n257 (26.5GHz-29.500GHz), n260 (37GHz-40GHz), n258 (24.25GHz-27.5GHz), and n261 (27.5GHz-28.35GHz).
[0084] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A phased array device, characterized in that, The device includes: Multiple receiving channels are coupled to multiple antenna elements in an antenna array. Each receiving channel includes a transconductance stage circuit, which includes a first transconductance element array and a second transconductance element array. The input terminals of the first transconductance element array and the second transconductance element array of each receiving channel are coupled to the antenna element corresponding to the receiving channel. A quadrature mixer circuit, wherein the non-inverting input terminal and the quadrature input terminal of the quadrature mixer circuit are respectively coupled to the output terminal of the first transconductance unit array in the plurality of receiving channels and the output terminal of the second transconductance unit array in the plurality of receiving channels; A signal processing circuit, wherein the input terminal of the signal processing circuit is coupled to the output terminal of the quadrature mixer circuit; The quadrature mixer circuit includes: a first quadrature mixer having a first in-phase input terminal and a first quadrature input terminal, a second quadrature mixer having a second in-phase input terminal and a second quadrature input terminal, and a local oscillator signal generator having an in-phase output terminal and a quadrature output terminal; Wherein, the first non-inverting input terminal serves as the non-inverting input terminal of the quadrature mixer circuit and is coupled to the output terminal of the first transconductance unit array in the plurality of receiving channels; the second quadrature input terminal serves as the quadrature input terminal of the quadrature mixer circuit and is coupled to the output terminal of the second transconductance unit array in the plurality of receiving channels; the first quadrature input terminal is coupled to the quadrature output terminal of the local oscillator signal generator; and the second non-inverting input terminal is coupled to the non-inverting output terminal of the local oscillator signal generator. Each of the first quadrature mixer and the second quadrature mixer includes: a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, and a tenth MOSFET; In this configuration, the gates of the seventh and tenth MOS transistors are used to receive positive-phase local oscillator signals, and the gates of the eighth and ninth MOS transistors are used to receive negative-phase local oscillator signals. The sources of the seventh and eighth MOS transistors are coupled to a sixth node, and the sources of the ninth and tenth MOS transistors are coupled to a seventh node. The drains of the seventh and ninth MOS transistors are coupled to an eighth node, and the drains of the eighth and tenth MOS transistors are coupled to a ninth node. The sixth and seventh nodes in the first quadrature mixer are coupled to the sixth and seventh nodes in the second quadrature mixer, respectively, serving as the output terminals of the quadrature mixer circuit. When the quadrature mixer is the first quadrature mixer, the sixth and seventh nodes serve as the first non-inverting input terminals. When the quadrature mixer is the second quadrature mixer, the sixth and seventh nodes serve as the second quadrature input terminals.
2. The apparatus according to claim 1, characterized in that, The first transconductance unit array and the second transconductance unit array in each of the plurality of receiving channels have phase shifting functions.
3. The apparatus according to claim 1, characterized in that, Both the first transconductance unit array and the second transconductance unit array include multiple transconductance stages, and the number of conducting stages is adjustable.
4. The apparatus according to claim 1, characterized in that, The first transconductance unit array and the second transconductance unit array are respectively provided with a first control circuit and a second control circuit, which are used to control the number of transconductance stages in the first transconductance unit array and the second transconductance unit array that are turned on or off respectively.
5. The apparatus according to claim 4, characterized in that, Each of the first and second control circuits includes a switching stage circuit coupled to each of the transconductance stages in a one-to-one correspondence. The switching stage circuit is used to control the conduction or disconnection of the corresponding transconductance stage.
6. The apparatus according to claim 1, characterized in that, The transconductance stage in the first transconductance unit array and the second transconductance unit array includes: a first MOS transistor and a second MOS transistor, the gate of the first MOS transistor and the gate of the second MOS transistor serve as the input terminal of the transconductance stage, the source of the first MOS transistor and the source of the second MOS transistor are coupled to a first node, and the drain of the first MOS transistor and the drain of the second MOS transistor serve as the output terminal of the transconductance stage.
7. The apparatus according to claim 6, characterized in that, The transconductance stage further includes a tail current tube coupled between the first node and the ground terminal.
8. The apparatus according to claim 5, characterized in that, The switching stage circuit is provided with a first signal generator and a second signal generator, which are used to generate switching signals to turn the switching stage circuit on and off, respectively.
9. The apparatus according to claim 5, characterized in that, The switching stage circuit includes: a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; In this circuit, the gates of the third and sixth MOS transistors are used to receive positive-phase switching signals, and the gates of the fourth and fifth MOS transistors are used to receive negative-phase switching signals. The sources of the third and fourth MOS transistors are coupled to a second node, and the sources of the fifth and sixth MOS transistors are coupled to a third node. The second and third nodes are the input terminals of the switching stage circuit. The drains of the third and fifth MOS transistors are coupled to a fourth node, and the drains of the fourth and sixth MOS transistors are coupled to a fifth node. The fourth and fifth nodes are the output terminals of the switching stage circuit.
10. The apparatus according to claim 1, characterized in that, Each of the plurality of receiving channels further includes: A low-noise amplifier, wherein the input terminal of the low-noise amplifier is coupled to the antenna element corresponding to the receiving channel, and the output terminal of the low-noise amplifier is coupled to the input terminals of the first transconductance element array and the second transconductance element, respectively.
11. The apparatus according to any one of claims 1-10, characterized in that, The signal processing circuit includes: One or more of a transformer, capacitor, drive amplifier, low-pass filter, and analog-to-digital converter coupled to the output of the quadrature mixer circuit.
12. A chip module, characterized in that, include: A chip and a packaging substrate, the chip being fixed to the packaging substrate, the chip including a phased array device as described in any one of claims 1-11, and the packaging substrate including an antenna array having a plurality of antenna elements.
13. A communication device, characterized in that, The communication device includes the phased array device as described in any one of claims 1-11.