Data bus inversion circuit and memory

Abstract

The embodiment of the present disclosure provides a data bus inversion circuit and a memory, wherein the data bus inversion circuit comprises: a preprocessing circuit configured to receive a comparison result of current data and previous data, and to preprocess the comparison result to output a preprocessing signal; a first comparison circuit configured to receive the preprocessing signal and output a first comparison signal based on the preprocessing signal; the first comparison signal is used to determine whether a number of preset values in the comparison result is greater than or equal to a first value, wherein the preset value represents that corresponding bit data of the current data and the previous data is different; a second comparison circuit configured to receive the preprocessing signal and output a second comparison signal based on the preprocessing signal; the second comparison signal is used to determine whether the number of preset values is greater than or equal to a second value; and a signal processing circuit configured to receive the first comparison signal, the second comparison signal and a data inversion signal corresponding to the previous data, and output a data inversion signal of the current data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and to, but is not limited to, a data bus switching circuit and a memory. Background Technology

[0002] Starting with the fourth generation of Double Data Rate Four Synchronous Dynamic Random Access Memory (DDR4 SDRAM), a Data Bus Inversion (DBI) operation was added to Dynamic Random Access Memory (DRAM) to reduce frequent data flipping and thus reduce dynamic power consumption.

[0003] In traditional Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), it's only necessary to determine if the number of 0 or 1 bits in the current byte exceeds a certain value. For example, in DDR4, if the number of 0s in a byte is greater than 4, the data toggle signal dbi_n is pulled low, and all data is toggled. In High Bandwidth Memory Third Generation (HBM3), the data toggle signal needs to be combined with the previous data entry to calculate the number of bits that need to be toggled in the current data, and it also needs to be combined with the previous data toggle signal to determine whether the current data needs to be toggled. However, current data bus toggle circuits are relatively complex and consume significant power. Summary of the Invention

[0004] This disclosure provides a data bus switching circuit and a memory.

[0005] In a first aspect, embodiments of this disclosure provide a data bus switching circuit, the circuit comprising:

[0006] A preprocessing circuit is used to receive the comparison result between the current data and the previous data, preprocess the comparison result, and output a preprocessed signal. The comparison result contains multiple sub-results, and each sub-result is used to characterize the comparison result between the current data and the previous data at the corresponding bit.

[0007] A first comparison circuit is configured to receive the preprocessing signal and output a first comparison signal based on the preprocessing signal; the first comparison signal is configured to determine whether the number of preset values ​​in the comparison result is greater than or equal to a first value, wherein the preset value indicates that the corresponding bit data of the current data is different from that of the previous data.

[0008] The second comparison circuit is used to receive the preprocessed signal and output the second comparison signal based on the preprocessed signal; the second comparison signal is used to determine whether the number of the preset values ​​is greater than or equal to a second value.

[0009] The signal processing circuit is used to receive the first comparison signal, the second comparison signal, and the data flip signal corresponding to the previous data, and output the data flip signal of the current data.

[0010] In some embodiments, the data bus switching circuit further includes: an output circuit;

[0011] The output circuit is used to receive the data flip signal of the current data and determine the data transmitted on the current data line based on the data flip signal of the current data.

[0012] In some embodiments, the first value is greater than the second value, and the second value is equal to half the amount of data transmitted by the data line at the same time; the first comparison signal indicates a second state when the number of preset values ​​is greater than or equal to the first value; the first comparison signal indicates a first state when the number of preset values ​​is less than the first value.

[0013] The second comparison signal indicates the first state when the number of preset values ​​is greater than or equal to the second value; the second comparison signal indicates the second state when the number of preset values ​​is less than the second value.

[0014] The signal processing circuit is used to output the data flip signal of the previous data as the data flip signal of the current data when both the second comparison signal and the first comparison signal indicate the first state.

[0015] The signal processing circuit is used to output a first data flip signal as the data flip signal of the current data when the second comparison signal outputs the first state and the first comparison signal outputs the second state, wherein the first data flip signal indicates that the current data needs to be flipped;

[0016] The signal processing circuit is configured to output a second data flip signal as the data flip signal of the current data when the second comparison signal outputs the second state and the first comparison signal outputs the first state, wherein the second data flip signal indicates that the current data does not need to be flipped.

[0017] In some embodiments, the comparison result includes 2n sub-results, wherein the first n sub-results form a first set of data signals, and the last n sub-results form a second set of data signals; the preprocessing circuit includes: a first preprocessing circuit and a second preprocessing circuit;

[0018] The first preprocessing circuit includes a first module and a second module; the first module is used to receive the first set of data signals and output a first output signal based on the first set of data signals.

[0019] The second module is used to receive the first output signal and output a second output signal based on the first output signal;

[0020] The second preprocessing circuit includes a third module and a fourth module; the third module is used to receive the second set of data signals and output a third output signal based on the second set of data signals;

[0021] The fourth module is used to receive the third output signal and output a fourth output signal based on the third output signal.

[0022] In some embodiments, the first comparison circuit is configured to receive the second output signal and the fourth output signal, and output the first comparison signal based on the second output signal and the fourth output signal;

[0023] The second comparison circuit is used to receive the second output signal and the fourth output signal, and output the second comparison signal based on the second output signal and the fourth output signal.

[0024] In some embodiments, both the first module and the third module include n / 2 logical components;

[0025] In this configuration, every two non-repeating data signals in the first group of data signals serve as input terminals for n / 2 logic components in the first module; and every two non-repeating data signals in the second group of data signals serve as input terminals for n / 2 logic components in the third module.

[0026] In some embodiments, n equals 4, the first module includes a first logic component and a second logic component; the first group of data signals includes a first data signal, a second data signal, a third data signal and a fourth data signal;

[0027] The first logic component includes a first NAND gate and a first NOR gate. The first NAND gate receives the first data signal and the second data signal, and performs a NAND operation on the first data signal and the second data signal to obtain a first result. The first NOR gate receives the first data signal and the second data signal, and performs a NOR operation on the first data signal and the second data signal to obtain a second result.

[0028] The second logic component includes a second NAND gate and a second NOR gate. The second NAND gate receives the third data signal and the fourth data signal, and performs a NAND operation on the third data signal and the fourth data signal to obtain a third result. The second NOR gate receives the third data signal and the fourth data signal, and performs a NOR operation on the third data signal and the fourth data signal to obtain a fourth result.

[0029] The first result, the second result, the third result, and the fourth result constitute the first output signal.

[0030] In some embodiments, the third module includes a third logic component and a fourth logic component; the second set of data signals includes a fifth data signal, a sixth data signal, a seventh data signal, and an eighth data signal;

[0031] The third logic component includes a third NAND gate and a third NOR gate. The third NAND gate receives the fifth data signal and the sixth data signal, and performs a NAND operation on the fifth data signal and the sixth data signal to obtain a fifth result. The third NOR gate receives the fifth data signal and the sixth data signal, and performs a NOR operation on the fifth data signal and the sixth data signal to obtain a sixth result.

[0032] The fourth logic component includes a fourth NAND gate and a fourth NOR gate. The fourth NAND gate receives the seventh data signal and the eighth data signal, and performs a NAND operation on the seventh data signal and the eighth data signal to obtain a seventh result. The fourth NOR gate receives the seventh data signal and the eighth data signal, and performs a NOR operation on the seventh data signal and the eighth data signal to obtain an eighth result.

[0033] The fifth result, the sixth result, the seventh result, and the eighth result constitute the third output signal.

[0034] In some embodiments, the second module includes a fifth NOR gate, a first OR gate, a second OR gate, a fifth NAND gate, a sixth NAND gate, a sixth NOR gate, and a seventh NAND gate;

[0035] The fifth NOR gate receives the first result and the third result, and performs an NOR gate operation on the first result and the third result to obtain the ninth result;

[0036] The first OR gate receives the first result and the fourth result, the second OR gate receives the second result and the third result, and the output terminals of the first OR gate and the second OR gate are both connected to the fifth NAND gate. The fifth NAND gate is used to perform a NAND operation on the output results of the first OR gate and the second OR gate to obtain the tenth result.

[0037] The sixth NAND gate receives the first result and the third result, and performs a NAND gate operation on the first result and the third result to obtain the eleventh result;

[0038] The sixth NOR gate receives the second result and the fourth result, and performs an NOR gate operation on the second result and the fourth result to obtain the twelfth result;

[0039] The seventh NAND gate receives the second result and the fourth result, and performs a NAND gate operation on the second result and the fourth result to obtain the thirteenth result;

[0040] The ninth result, the tenth result, the eleventh result, the twelfth result, and the thirteenth result constitute the second output signal.

[0041] In some embodiments, the fourth module includes a seventh NOR gate, a third OR gate, a fourth OR gate, an eighth NAND gate, a ninth NAND gate, an eighth NOR gate, and a tenth NAND gate;

[0042] The seventh NOR gate receives the fifth result and the seventh result, and performs an NOR gate operation on the fifth result and the seventh result to obtain the fourteenth result;

[0043] The third OR gate receives the fifth result and the eighth result, the fourth OR gate receives the sixth result and the seventh result, and the output terminals of the third OR gate and the fourth OR gate are both connected to the eighth NAND gate. The eighth NAND gate is used to perform a NAND operation on the output results of the third OR gate and the fourth OR gate to obtain the fifteenth result.

[0044] The ninth NAND gate receives the fifth result and the seventh result, and performs a NAND gate operation on the fifth result and the seventh result to obtain the sixteenth result;

[0045] The eighth NOR gate receives the sixth result and the eighth result, and performs an NOR gate operation on the sixth result and the eighth result to obtain the seventeenth result;

[0046] The tenth NAND gate receives the sixth result and the eighth result, and performs a NAND gate operation on the sixth result and the eighth result to obtain the eighteenth result;

[0047] The fourteenth result, the fifteenth result, the sixteenth result, the seventeenth result, and the eighteenth result constitute the fourth output signal;

[0048] The second output signal and the fourth output signal constitute the preprocessed signal.

[0049] In some embodiments, the first comparison circuit includes a fifth logic component, a sixth logic component, a seventh logic component, and a third AND gate;

[0050] The fifth logic component includes a first AND gate, a second AND gate, and a ninth NOR gate; the first AND gate receives the ninth result and the eighteenth result, the second AND gate receives the thirteenth result and the fourteenth result, and the ninth NOR gate is connected to the output terminals of the first AND gate and the second AND gate, and the ninth NOR gate is used to perform NOR operation on the output results of the first AND gate and the second AND gate to obtain the nineteenth result;

[0051] The sixth logic component includes a fifth OR gate and an eleventh NAND gate; the fifth OR gate receives the eleventh result and the twelfth result, the eleventh NAND gate is connected to the output of the fifth OR gate and receives the fifteenth result, and the eleventh NAND gate is used to perform a NAND operation on the output of the fifth OR gate and the fifteenth result to obtain the twentieth result;

[0052] The seventh logic component includes a sixth OR gate and a twelfth NAND gate; the sixth OR gate receives the sixteenth result and the seventeenth result, the twelfth NAND gate is connected to the output of the sixth OR gate and receives the tenth result, and the twelfth NAND gate is used to perform a NAND operation on the output of the sixth OR gate and the tenth result to obtain the twenty-first result;

[0053] The third AND gate receives the nineteenth result, the twentieth result, and the twenty-first result, and performs an AND operation on the nineteenth result, the twentieth result, and the twenty-first result to obtain the first comparison signal.

[0054] In some embodiments, the second comparison circuit includes a tenth NOR gate, an eighth logic component, a ninth logic component, and a fourteenth NAND gate;

[0055] The tenth NOR gate receives the ninth result and the fourteenth result, and performs a NOR operation on the ninth result and the fourteenth result to obtain the twenty-second result;

[0056] The eighth logic component includes a fourth AND gate, a fifth AND gate, and an eleventh NOR gate; the fourth AND gate receives the tenth result and the eighteenth result, the fifth AND gate receives the fifteenth result and the thirteenth result, and the eleventh NOR gate is connected to the output terminals of the fourth AND gate and the fifth AND gate. The eleventh NOR gate is used to perform a NOR operation on the output results of the fourth AND gate and the fifth AND gate to obtain the twenty-third result.

[0057] The ninth logic component includes a seventh OR gate, an eighth OR gate, and a thirteenth NAND gate; the seventh OR gate receives the eleventh and twelfth results, the eighth OR gate receives the sixteenth and seventeenth results, and the thirteenth NAND gate is connected to the outputs of the seventh and eighth OR gates. The thirteenth NAND gate is used to perform a NAND operation on the outputs of the seventh and eighth OR gates to obtain the twenty-fourth result.

[0058] The fourteenth NAND gate receives the second twelfth result, the second thirteenth result, and the second fourteenth result, and performs an NAND operation on the second twelfth result, the second thirteenth result, and the second fourteenth result to obtain the second comparison signal.

[0059] In some embodiments, the signal processing circuit includes a fifteenth NAND gate and a sixteenth NAND gate;

[0060] The fifteenth NAND gate receives the second comparison signal and the data inversion signal of the previous data, and performs NAND processing on the second comparison signal and the data inversion signal of the previous data to obtain the twenty-fifth result;

[0061] The sixteenth NAND gate receives the twenty-fifth result and the first comparison signal, and performs NAND processing on the twenty-fifth result and the first comparison signal to output the twenty-sixth result; the twenty-sixth result includes any one of the data flip signal of the current data, the first data flip signal and the second data flip signal.

[0062] Secondly, embodiments of this disclosure provide a memory that includes at least the data bus switching circuit described in any of the above embodiments.

[0063] In this embodiment, since the range of the number of bits that need to be flipped in the current data can be determined using two simple comparison circuits, this embodiment provides a relatively simple data bus flipping circuit, which not only shortens the calculation time of the data flipping signal but also reduces circuit power consumption. Furthermore, because this embodiment dynamically compares the current data with the previous data and its flipping signal when determining the current data flipping signal, it can more accurately determine whether the current data needs to be flipped and also reduce the power consumption of data flipping. Attached Figure Description

[0064] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0065] Figure 1 A schematic diagram of the composition structure of a data bus switching circuit provided in an embodiment of this disclosure;

[0066] Figure 2 A schematic diagram of the preprocessing circuit provided in an embodiment of this disclosure;

[0067] Figure 3 This is a schematic diagram of the first module structure provided in an embodiment of the present disclosure;

[0068] Figure 4 This is a schematic diagram of the third module structure provided in an embodiment of the present disclosure;

[0069] Figure 5 This is a schematic diagram of the second module structure provided in an embodiment of the present disclosure;

[0070] Figure 6 This is a schematic diagram of the fourth module structure provided in an embodiment of the present disclosure;

[0071] Figure 7 This is a schematic diagram of the structure of the first comparison circuit provided in an embodiment of the present disclosure;

[0072] Figure 8 This is a schematic diagram of the structure of the second comparison circuit provided in an embodiment of the present disclosure;

[0073] Figure 9 This is a schematic diagram of the signal processing circuit provided in an embodiment of the present disclosure;

[0074] Figure 10 This is a schematic diagram of the output circuit provided in an embodiment of the present disclosure;

[0075] Figure 11 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0076] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0077] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0078] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0079] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0081] This disclosure provides a data bus switching circuit. Figure 1 This is a schematic diagram of the composition structure of a data bus switching circuit provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the data bus flip circuit 100 includes: a preprocessing circuit 10, a first comparison circuit 20, a second comparison circuit 30, and a signal processing circuit 40.

[0082] The preprocessing circuit 10 is used to receive the comparison result between the current data and the previous data, preprocess the comparison result, and output a preprocessed signal. The comparison result contains multiple sub-results, and each sub-result is used to characterize the comparison result between the current data and the previous data of the corresponding bit.

[0083] In this embodiment of the disclosure, the current data is the data currently being written to the storage unit or the data currently being read from the storage unit. The previous data refers to the data previously transmitted on the data line; that is, the previous data can be data that has not been flipped or data that has been flipped.

[0084] In some embodiments, the number of bits in the data signal included in the current data and the previous data can be 8n, where n can be 1, 2, 4, or 8. For example, the number of bits in the data signal included in the current data and the previous data can be 8 bits, 16 bits, 32 bits, 64 bits, etc., and this disclosure embodiment is not limited thereto. In addition, for convenience, this disclosure embodiment uses an example where the comparison result includes an 8-bit data signal for explanation and description.

[0085] The comparison result refers to the result obtained by comparing the data signals with the same bits of the current data and the previous data. The comparison result of the current data and the previous data can reflect the difference between the current data and the previous data. The number of bits in the sub-result of the comparison result is the same as the number of bits of the current data and the previous data. For example, when the current data and the previous data are both 8 bits, the sub-result in the comparison result is also 8 bits.

[0086] In some embodiments, the comparison result between the current data and the previous data can be the XOR result of the two. When the data signals at the same bits in the current data and the previous data are the same, the comparison result is 0; when the data signals at the same bits in the current data and the previous data are different, the comparison result is 1.

[0087] The first comparison circuit 20 is used to receive the preprocessing signal and output the first comparison signal based on the preprocessing signal; the first comparison signal is used to determine whether the number of preset values ​​in the comparison result is greater than or equal to the first value, the preset value indicates that the corresponding bit data of the current data is different from that of the previous data.

[0088] The second comparison circuit 30 is used to receive the preprocessed signal and output a second comparison signal based on the preprocessed signal; the second comparison signal is used to determine whether the number of preset values ​​is greater than or equal to the second value.

[0089] In this embodiment of the disclosure, the preset value is "1". The first comparison signal and the second comparison signal are used to determine whether the number of "1"s in the comparison result is greater than the first value or the second value. The first value and the second value should be different; for example, the first value is greater than the second value.

[0090] The first comparison signal outputs a state when the number of "1"s in the comparison result is greater than or equal to a first value, and outputs a different state when the number of "1"s in the comparison result is less than the first value. The second comparison signal outputs a state when the number of "1"s in the comparison result is greater than a second value, and outputs a different state when the number of "1"s in the comparison result is less than or equal to the second value. By combining the different states of the first and second comparison signals, the range of the number of bits that need to be flipped in the current data can be determined. For example, when the first value is greater than the second value, it can be determined that the number of bits that need to be flipped in the current data is greater than or equal to the first value, equal to the second value, or less than the second value.

[0091] The signal processing circuit 40 is used to receive the first comparison signal, the second comparison signal and the data flip signal corresponding to the previous data, and output the data flip signal of the current data.

[0092] The signal processing circuit 40 is used to determine whether the current data needs to be flipped based on the range of the number of bits that need to be flipped in the current data determined by the first comparison signal and the second comparison signal, that is, to determine the data flipping signal of the current data.

[0093] Specifically, if the number of bits to be flipped in the current data is greater than half of the total number of bits in the current data, then the current data needs to be flipped; if the number of bits to be flipped in the current data is less than half of the total number of bits in the current data, then the current data does not need to be flipped; if the number of bits to be flipped in the current data is equal to half of the total number of bits in the current data, then the current data can be flipped or not. In this case, the data flipping signal of the previous data is followed. When the previous data flipping signal indicates flipping, the current data is also flipped; when the previous data flipping signal indicates not to flip, the current data is not flipped.

[0094] In some embodiments, the data toggle signal can be either a high level "1" or a low level "0". When the data toggle signal is "1", the current data can be toggled, thereby reducing power consumption during data transmission. Here, toggling the current data can be understood as changing "0" in the current data to "1", or changing "1" in the current data to "0".

[0095] The data bus flipping circuit provided in this embodiment includes a preprocessing circuit, a first comparison circuit, a second comparison circuit, and a signal processing circuit. Both the first and second comparison circuits receive the preprocessing result of the comparison between the current data and the previous data from the preprocessing circuit, and output a first comparison signal and a second comparison signal based on the preprocessing result. The first and second comparison signals determine the range of the number of bits in the current data that need to be flipped. Based on the range of the number of bits in the current data that need to be flipped determined by the first and second comparison signals, the signal processing circuit determines the data flipping signal for the current data. Since this embodiment can determine the range of the number of bits in the current data that need to be flipped using only two simple comparison circuits, it provides a relatively simple data bus flipping circuit that not only shortens the calculation time for the data flipping signal but also reduces circuit power consumption. Furthermore, because this embodiment dynamically compares the current data with the previous data and its data flipping signal when determining the data flipping signal, it can more accurately determine whether the current data needs to be flipped and also reduce the power consumption of data flipping.

[0096] In some embodiments, the data bus switching circuit further includes an output circuit, which is used to receive a data switching signal of the current data and determine the data transmitted on the current data line based on the data switching signal of the current data.

[0097] The current data flip signal indicates whether the current data needs to be flipped. For example, when the current data flip signal is "1", it means that the current data needs to be flipped. At this time, the signal transmitted by the current data line output by the output circuit is the data after flipping the current data. When the current data flip signal is "0", it means that the current data does not need to be flipped. At this time, the signal transmitted by the current data line output by the output circuit is the current data without flipping.

[0098] In this embodiment of the disclosure, by dynamically acquiring the toggle signal of the current data, the current data line can transmit data with the minimum power consumption, thereby reducing the power consumption of the entire circuit.

[0099] In some embodiments, the first value is greater than the second value, and the second value is equal to half the amount of data transmitted by the data line at the same time. For example, when the number of bits transmitted for the current data and the previous data is 8 bits, the amount of data transmitted by the data line at the same time is 8. In this case, the second value is equal to 4, and the first value can be 5.

[0100] The first comparison signal indicates the second state when the number of preset values ​​is greater than or equal to the first value; the first comparison signal indicates the first state when the number of preset values ​​is less than the first value; the second comparison signal indicates the first state when the number of preset values ​​is greater than or equal to the second value; and the second comparison signal indicates the second state when the number of preset values ​​is less than the second value.

[0101] In this embodiment of the disclosure, the first state can be a high-level state, such as "1"; the second state can be a low-level state, such as "0".

[0102] The signal processing circuit 40 is configured to output the data flip signal of the previous data as the data flip signal of the current data when both the second comparison signal and the first comparison signal indicate the first state. In other words, in this embodiment, when both the second comparison signal and the first comparison signal output a high level, the signal processing circuit 40 indicates that the number of bits to be flipped in the current data is equal to the second value (i.e., half the amount of data transmitted on the data line at the same time), meaning that the current data can be flipped or not. In this case, the data flip signal of the previous data is executed, and therefore the data flip signal of the previous data is output as the data flip signal of the current data.

[0103] The signal processing circuit 40 is further configured to output a first data flip signal as the data flip signal of the current data when the second comparison signal outputs a first state and the first comparison signal outputs a second state, wherein the first data flip signal indicates that the current data needs to be flipped. That is, in this embodiment of the present disclosure, the signal processing circuit 40 is configured to indicate that the number of bits that need to be flipped in the current data is greater than a first value (i.e., greater than half of the amount of data transmitted on the data line at the same time) when the second comparison signal outputs a high level state and the first comparison signal outputs a low level state, indicating that the current data needs to be flipped, and therefore outputs a first data flip signal.

[0104] The signal processing circuit 40 is further configured to output a second data toggle signal as the data toggle signal for the current data when the second comparison signal outputs a second state and the first comparison signal outputs a first state, wherein the second data toggle signal indicates that the current data does not need to be toggleed. That is, in this embodiment of the present disclosure, the signal processing circuit 40 is configured to indicate that the number of bits that need to be toggleed in the current data is less than a second value (i.e., less than half the amount of data transmitted on the data line at the same time) when the second comparison signal outputs a low level state and the first comparison signal outputs a high level state, indicating that the current data does not need to be toggleed, and therefore outputs a second data toggle signal.

[0105] In this embodiment of the present disclosure, the signal processing circuit can quickly determine the data flip signal of the current data based on the first comparison signal and the second comparison signal output by the two comparison circuits, thereby shortening the calculation time of the data flip signal.

[0106] In some embodiments, the comparison result includes 2n sub-results, wherein the first n sub-results form a first set of data signals and the last n sub-results form a second set of data signals.

[0107] For example, the comparison result includes 8 sub-results, namely D<7:0>. The first 4 data signals form the first group of data signals D<3:0>, and the last 4 data signals form the second group of data signals D<7:4>.

[0108] Figure 2 A schematic diagram of a preprocessing circuit provided in an embodiment of this disclosure is shown below. Figure 2 As shown, the preprocessing circuit 10 includes: a first preprocessing circuit 11 and a second preprocessing circuit 12; the first preprocessing circuit includes a first module 111 and a second module 112; the first module 111 is used to receive a first set of data signals D<3:0> and output a first output signal based on the first set of data signals D<3:0>; the second module 112 is used to receive the first output signal and output a second output signal based on the first output signal.

[0109] The second preprocessing circuit 12 includes a third module 121 and a fourth module 122; the third module 121 is used to receive the second set of data signals D<7:4> and output a third output signal based on the second set of data signals D<7:4>; the fourth module 122 is used to receive the third output signal and output a fourth output signal based on the third output signal.

[0110] In some embodiments, both the first module 111 and the third module 121 include n / 2 logic components; wherein, every two non-repeating data signals in the first group of data signals D<3:0> serve as the input terminals of the n / 2 logic components in the first module 111; and every two non-repeating data signals in the second group of data signals D<7:4> serve as the input terminals of the n / 2 logic components in the third module 121.

[0111] For example, when n is 4, both the first module 111 and the third module 121 contain two logic components. In the first group of data signals D<3:0>, every two non-repeating data signals include D... <0> and D <1> D <2> and D <3> D <0> and D <1> D <2> and D <3> These serve as the input terminals for two logic components in the first module 111, respectively. In the second set of data signals D<7:3>, each pair of non-repeating data signals includes D... <4> and D <5> D <6> and D <7> D <4> and D <5> D <6> and D <7> They can be used as input terminals for two logic components in the third module 121, respectively.

[0112] Here, a logic component refers to a combination of one, two, or more logic devices, which can be AND gates, OR gates, NOT gates, NAND gates, or NOR gates. Logic components are used to implement specific logical operations.

[0113] Figure 3 This is a schematic diagram of the first module structure provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the first module 111 includes a first logic component 111a and a second logic component 111b; the first group of data signals D<3:0> includes the first data signal D <0> Second data signal D <1> Third data signal D <2> and the fourth data signal D <3> The first logic component 111a includes a first NAND gate 501 and a first NOR gate 601. The first NAND gate 501 receives the first data signal D. <0> Second data signal D <1> and the first data signal D <0> Second data signal D <1> Perform a NAND operation to obtain the first result G. <0> The first NOR gate 601 receives the first data signal D. <0> Second data signal D <1> and the first data signal D <0> Second data signal D <1> Perform a NOR operation to obtain the second result P. <0> .

[0114] The second logic component 111b includes a second NAND gate 502 and a second NOR gate 602, wherein the second NAND gate 502 receives a third data signal D. <2> and the fourth data signal D <3> and the third data signal D <2> and the fourth data signal D <3> Perform a NAND operation to obtain the third result G. <1> The second NOR gate 602 receives the third data signal D. <2> and the fourth data signal D <3> and the third data signal D <2> and the fourth data signal D <3> Perform a NOR operation to obtain the fourth result P. <1> .

[0115] First result G <0> Second result P <0> Third result G <1> and the fourth result P <1> This constitutes the first output signal.

[0116] Figure 4 This is a schematic diagram of the third module structure provided in an embodiment of the present disclosure, such as... Figure 4 As shown, the third module 121 includes a third logic component 121a and a fourth logic component 121b; the second group of data signals D<7:4> includes a fifth data signal D <4> The sixth data signal D <5> The seventh data signal D <6> and the eighth data signal D <7> The third logic component 121a includes a third NAND gate 503 and a third NOR gate 603. The third NAND gate 503 receives the fifth data signal D. <4> and the sixth data signal D <5> And for the fifth data signal D <4> and the sixth data signal D <5> Perform a NAND operation to obtain the fifth result G. <2> The third NOR gate 603 receives the fifth data signal D. <4> and the sixth data signal D <5> And for the fifth data signal D <4> and the sixth data signal D <5> Perform a NOR operation to obtain the sixth result P. <2> .

[0117] The fourth logic component 121b includes a fourth NAND gate 504 and a fourth NOR gate 604. The fourth NAND gate 504 receives the seventh data signal D. <6> and the eighth data signal D <7> And for the seventh data signal D <6> and the eighth data signal D <7> Performing a NAND operation yields the seventh result, G. <3> The fourth NOR gate 604 receives the seventh data signal D. <6> and the eighth data signal D <7> And for the seventh data signal D <6> and the eighth data signal D <7> Perform a NOR operation to obtain the eighth result P. <3> .

[0118] Fifth result G <2> Sixth result P <2> Result G (Seventh) <3> And the eighth result P <3> This constitutes the third output signal.

[0119] Figure 5 This is a schematic diagram of the second module structure provided in an embodiment of the present disclosure, as shown below. Figure 5As shown, the second module 112 includes a fifth NOR gate 605, a first OR gate 701, a second OR gate 702, a fifth NAND gate 505, a sixth NAND gate 506, a sixth NOR gate 606, and a seventh NAND gate 507.

[0120] The fifth NOR gate 605 receives the first result G. <0> and the third result G <1> And for the first result G <0> and the third result G <1> Perform an NOR gate operation to obtain the ninth result, Four. <0> The first OR gate 701 receives the first result G. <0> and the fourth result P <1> The second OR gate 702 receives the second result P. <0> and the third result G <1> The outputs of the first OR gate 701 and the second OR gate 702 are both connected to the input of the fifth NAND gate 505. The fifth NAND gate 505 is used to perform a NAND operation on the output of the first OR gate 701 and the output of the second OR gate 702 to obtain the tenth result, Three. <0> The sixth NAND gate 506 receives the first result G. <0> and the third result G <1> And for the first result G <0> and the third result G <1> Performing a NAND gate operation yields the eleventh result, Two1. <0> The sixth NOR gate 606 receives the second result P. <0> and the fourth result P <1> And for the second result P <0> and the fourth result P <1> Performing an NOR gate operation yields the twelfth result, Two2. <0> The seventh NAND gate 507 receives the second result P. <0> and the fourth result P <1> And for the second result P <0> and the fourth result P <1> Performing a NAND gate operation yields the thirteenth result, One. <0> .

[0121] Ninth result Four <0> 10th Result Three <0> 11th Result Two1 <0> 12th Result Two2 <0> And the thirteenth result One <0> This constitutes the second output signal.

[0122] Figure 6 This is a schematic diagram of the fourth module structure provided in an embodiment of the present disclosure, as shown below. Figure 6 As shown, the fourth module 122 includes a seventh NOR gate 607, a third OR gate 703, a fourth OR gate 704, an eighth NAND gate 508, a ninth NAND gate 509, an eighth NOR gate 608, and a tenth NAND gate 510.

[0123] The seventh NOR gate 607 receives the fifth result G. <2> And the seventh result G <3> And for the fifth result G <2> And the seventh result G <3> Perform an NOR gate operation to obtain the fourteenth result. <1> The third OR gate 703 receives the fifth result G. <2> And the eighth result P <3> The fourth OR gate 704 receives the sixth result P. <2> And the seventh result G <3> The outputs of the third OR gate 703 and the fourth OR gate 704 are both connected to the input of the eighth NAND gate 508. The eighth NAND gate 508 is used to perform a NAND operation on the outputs of the third OR gate 703 and the fourth OR gate 704 to obtain the fifteenth result, Three. <1> The ninth NAND gate 509 receives the fifth result G. <2> And the seventh result G <3> And for the fifth result G <2> And the seventh result G <3> Performing a NAND gate operation yields the sixteenth result, Two1. <1> The eighth NOR gate 608 receives the sixth result P. <2> And the eighth result P <3> And for the sixth result P <2> And the eighth result P <3> Performing an NOR gate operation yields the seventeenth result, Two2. <1> The tenth NAND gate 510 receives the sixth result P. <2> And the eighth result P <3> And for the sixth result P <2> And the eighth result P <3> Performing a NAND gate operation yields the eighteenth result, One. <1> .

[0124] Fourteenth Result <1> The fifteenth result is Three. <1> Sixteenth Result Two1 <1> Result Two2 (17th) <1> And the eighteenth result One <1> The fourth output signal is formed, and the second and fourth output signals together constitute the preprocessed signal.

[0125] Figure 7 A schematic diagram of the structure of the first comparison circuit provided in an embodiment of this disclosure is shown below. Figure 7 As shown, the first comparison circuit 20 includes a fifth logic component 201, a sixth logic component 202, a seventh logic component 203, and a third AND gate 803.

[0126] The fifth logic component 201 includes a first AND gate 801, a second AND gate 802, and a ninth NOR gate 609; the first AND gate 801 receives the ninth result, Four. <0> And the eighteenth result One <1> The second AND gate 802 receives the thirteenth result, One. <0> And the fourteenth result. <1> The ninth NOR gate 609 is connected to the output of the first AND gate 801 and the output of the second AND gate 802. The ninth NOR gate 609 is used to perform NOR operation on the output of the first AND gate 801 and the output of the second AND gate 802 to obtain the nineteenth result.

[0127] The sixth logic component 202 includes a fifth OR gate 705 and an eleventh NAND gate 511; the fifth OR gate 705 receives the eleventh result Two1. <0> And the twelfth result Two2 <0> The eleventh NAND gate 511 is connected to the output of the fifth OR gate 705, and receives the fifteenth result Three. <1> The eleventh NAND gate 511 is used to output the result of the fifth OR gate 705 and the fifteenth result. <1> Perform a NAND operation to obtain the twentieth result.

[0128] The seventh logic component 203 includes a sixth OR gate 706 and a twelfth NAND gate 512; the sixth OR gate 706 receives the sixteenth result Two1. <1> And the seventeenth result Two2 <1> The output of the twelfth NAND gate 512 is connected to the output of the sixth OR gate 706, and receives the tenth result Three. <0> The twelfth NAND gate 512 is used to process the output of the sixth OR gate 706 and the tenth result Three. <0> Perform a NAND operation to obtain the twenty-first result.

[0129] The third AND gate 803 receives the nineteenth, twentieth, and twenty-first results, and performs an AND operation on the nineteenth, twentieth, and twenty-first results to obtain the first comparison signal A.

[0130] Figure 8 This is a schematic diagram of the structure of the second comparison circuit provided in an embodiment of this disclosure, as shown below. Figure 8 As shown, the second comparison circuit 30 includes a tenth NOR gate 610, an eighth logic component 301, a ninth logic component 302, and a fourteenth NAND gate 514.

[0131] The tenth NOR gate 610 receives the ninth result. <0> And the fourteenth result. <1> And for the ninth result, Four <0> And the fourteenth result. <1> Perform an NOR operation to obtain the twenty-second result; the eighth logic component 301 includes a fourth AND gate 804, a fifth AND gate 805, and an eleventh NOR gate 611; the fourth AND gate 804 receives the tenth result, Three. <0> And the eighteenth result One <1> The fifth AND gate 805 receives the fifteenth result. <1> And the thirteenth result One <0> The eleventh NOR gate 611 is connected to the outputs of the fourth AND gate 804 and the fifth AND gate 805. The eleventh NOR gate 611 is used to perform a NOR operation on the outputs of the fourth AND gate 804 and the fifth AND gate 805 to obtain the twenty-third result. The ninth logic component 302 includes a seventh OR gate 707, an eighth OR gate 708, and a thirteenth NAND gate 513. The seventh OR gate 707 receives the eleventh result Two1. <0> And the twelfth result Two2 <0> The eighth OR gate 708 receives the sixteenth result, Two1. <1> And the seventeenth result Two2 <1> The thirteenth NAND gate 513 is connected to the output of the seventh OR gate 707 and the output of the eighth OR gate 708. The thirteenth NAND gate 513 is used to perform NAND operation on the output of the seventh OR gate 707 and the output of the eighth OR gate 708 to obtain the twenty-fourth result.

[0132] The fourteenth NAND gate 514 receives the twenty-second, twenty-third, and twenty-fourth results, and performs NAND operations on the twenty-second, twenty-third, and twenty-fourth results to obtain the second comparison signal B.

[0133] Figure 9 This is a schematic diagram of the signal processing circuit provided in the embodiments of this disclosure, such as... Figure 9 As shown, the signal processing circuit 40 includes a fifteenth NAND gate 515 and a sixteenth NAND gate 516; the fifteenth NAND gate 515 receives the second comparison signal B and the data inversion signal DbiBefore of the previous data, and performs NAND processing on the second comparison signal B and the data inversion signal DbiBefore of the previous data to obtain the twenty-fifth result.

[0134] The sixteenth NAND gate 516 receives the twenty-fifth result and the first comparison signal A, performs NAND processing on the twenty-fifth result and the first comparison signal A, and outputs the twenty-sixth result Dbi; the twenty-sixth result Dbi can be any one of the current data flip signal, the first data flip signal, and the second data flip signal.

[0135] Since the data flip signal of the previous data is needed when calculating the data flip signal of the current data, the fewer circuits the data flip signal passes through, the better. The signal processing circuit provided in this embodiment of the present disclosure enables the data flip signal of the current data to be obtained by passing through only two NAND gates each time the data flip signal of the previous data is calculated, which shortens the path of the data flip signal and thus reduces the power consumption of the data flip circuit.

[0136] The following example will be based on the case where the XOR result is Xor<7:0> (i.e., the comparison result is 11001110), the first comparison circuit 20 is a hamming weight 5 comparator, the second comparison circuit 30 is a hamming weight 4 comparator, and it is assumed that power saving is achieved when transmitting "0". Figures 2 to 9 This disclosure describes the detailed process of determining the data flip signal for the current data in this embodiment.

[0137] The first set of data signals in comparison result 11001110 includes the first data signal D. <0> =0, Second data signal D <1> =1, Third data signal D <2> =1 and the fourth data signal D <3> =1; The second group of data signals includes the fifth data signal D. <4> =0, Sixth data signal D <5> =0, Seventh data signal D <6> =1 and the eighth data signal D <7> =1. The first logic component 111a receives the first data signal D. <0> =0 and the second data signal D <1> =1, and output the first result G. <0> =1 and the second result P <0> =0, the second logic component 111b receives the third data signal D <2> =1 and the fourth data signal D <3> =1, and output the third result G. <1> =0 and the fourth result P <1> =0. First result G <0> =1, Second result P <0> =0, Third result G <1> =0 and the fourth result P <1> =0 constitutes the first output signal. The second module receives the first output signal and outputs the ninth result, Four. <0> =0, the tenth result Three <0> =1, Eleventh Result Two1 <0> =1, the twelfth result Two2 <0> =1 and the thirteenth result One <0> The second output signal is composed of 1.

[0138] The third logic component 121a receives the fifth data signal D. <4> =0 and the sixth data signal D <5> =0, and output the fifth result G. <2> =1 and the sixth result P <2> =1, the fourth logic component 121b receives the seventh data signal D <6> =1 and the eighth data signal D <7> =1, and output the seventh result G. <3> =0 and the eighth result P <3> =0. Fifth result G <2> =1, Sixth result P <2> =1, Seventh Result G <3> =0 and the eighth result P <3> =0 constitutes the third output signal. The fourth module receives the third output signal and outputs the fourteenth result. <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =1, Seventeenth Result Two2 <1> =0 and the eighteenth result One <1> The fourth output signal is composed of 1.

[0139] The first comparator circuit 20 (i.e., the hamming weight 5 comparator) receives the ninth result, Four. <0> =0, the tenth result Three <0> =1, Eleventh Result Two1 <0> =1, the twelfth result Two2 <0> =1, the thirteenth result One <0> =1, Fourteenth Result <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =1, Seventeenth Result Two2 <1> =0 and the eighteenth result One <1> =1, outputting the first comparison signal A in a low-level state, i.e., A is "0".

[0140] The second comparator circuit 30 (i.e., the Hamming weight 4 comparator) receives the ninth result, Four. <0> =0, the tenth result Three <0> =1, Eleventh Result Two1 <0> =1, the twelfth result Two2 <0> =1, the thirteenth result One <0> =1, Fourteenth Result <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =1, Seventeenth Result Two2 <1> =0 and the eighteenth result One <1> =1, outputting the second comparison signal B in a high-level state, that is, B is "1".

[0141] The signal processing circuit 40 receives the second comparison signal "1", the data flip signal DbiBefore of the previous data and the first comparison signal "0", and outputs the data flip signal "1" of the current data, indicating that when the comparison result D<7:0> is 11001110, the current data needs to be flipped in order to reduce power consumption.

[0142] The following example uses the XOR result Xor<7:0> (i.e., the comparison result) as 10101000, the first comparison circuit 20 as a hamming weight 5 comparator, the second comparison circuit 30 as a hamming weight 4 comparator, and assumes that power saving is achieved when transmitting "0". This will be combined with... Figures 2 to 9 This disclosure describes the detailed process of determining the data flip signal for the current data in this embodiment.

[0143] The first set of data signals in the comparison result 10101000 includes the first data signal D. <0> =0, Second data signal D <1> =0, Third data signal D <2> =0 and the fourth data signal D <3> =1; The second group of data signals includes the fifth data signal D. <4> =0, Sixth data signal D <5> =1, Seventh data signal D <6> =0 and the eighth data signal D <7> =1. The first logic component 111a receives the first data signal D. <0> =0 and the second data signal D <1> =0, and output the first result G. <0> =1 and the second result P <0> =1, the second logic component 111b receives the third data signal D <2> =0 and the fourth data signal D <3> =1, and output the third result G. <1> =1 and the fourth result P <1> =0. First result G <0> =1, Second result P <0> =1, Third result G <1> =1 and the fourth result P <1> =0 constitutes the first output signal. The second module 112 receives the first output signal and outputs the ninth result, Four. <0> =0, the tenth result Three <0> =0, Eleventh Result Two1 <0> =0, the twelfth result Two2 <0> =0 and the thirteenth result One <0> The second output signal is composed of 1.

[0144] The third logic component 121a receives the fifth data signal D. <4> =0 and the sixth data signal D <5> =1, and output the fifth result G. <2> =1 and the sixth result P <2> =0, the fourth logic component 121b receives the seven data signals D. <6> =0 and the eighth data signal D <7> =1, and output the seventh result G. <3> =1 and the eighth result P <3> =0. Fifth result G <2> =1, Sixth result P <2> =0, Seventh Result G <3> =1 and the eighth result P <3> =0 constitutes the third output signal. The fourth module 122 receives the third output signal and outputs the fourteenth result. <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =0, Seventeenth Result Two2 <1> =1 and the eighteenth result One <1> The fourth output signal is composed of 1.

[0145] The first comparator circuit 20 (i.e., the hamming weight 5 comparator) receives the ninth result, Four. <0> =0, the tenth result Three <0> =0, Eleventh Result Two1 <0> =0, the twelfth result Two2 <0> =0, Thirteenth Result One <0> =1, Fourteenth Result <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =0, Seventeenth Result Two2 <1> =1 and the eighteenth result One <1> =1, outputting the first comparison signal A in a high-level state, i.e., A is "1".

[0146] The second comparator circuit 30 (i.e., the Hamming weight 4 comparator) receives the ninth result, Four. <0> =0, the tenth result Three <0> =0, Eleventh Result Two1 <0> =0, the twelfth result Two2 <0> =0, Thirteenth Result One <0> =1, Fourteenth Result <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =0, Seventeenth Result Two2 <1> =1 and the eighteenth result One <1> =1, outputting the second comparison signal B in a low-level state, i.e., B is "0".

[0147] The signal processing circuit 40 receives the second comparison signal "0", the data flip signal DbiBefore of the previous data and the first comparison signal "1", and outputs the data flip signal "0" of the current data, indicating that when the comparison result D<7:0> is 10101000, in order to reduce power consumption, it is not necessary to flip the current data.

[0148] The following example will be based on the case where the XOR result Xor<7:0> (i.e., the comparison result) is 10101010, the first comparison circuit 20 is a hamming weight 5 comparator, the second comparison circuit 30 is a hamming weight 4 comparator, and it is assumed that the comparison is power-saving when transmitting "0".

[0149] The first group of data signals in the comparison result 10101010 includes the first data signal D. <0> =0, Second data signal D <1> =1, Third data signal D <2> =0 and the fourth data signal D <3> =1; The second group of data signals includes the fifth data signal D. <4> =0, Sixth data signal D <5> =1, Seventh data signal D <6> =0 and the eighth data signal D <7> =1. The first logic component 111a receives the first data signal D. <0> =0 and the second data signal D <1> =1, and output the first result G. <0> =1 and the second result P <0> =0, the second logic component 111b receives the third data signal D <2> =0 and the fourth data signal D <3> =1, and output the third result G. <1> =1 and the fourth result P <1> =0. First result G <0> =1, Second result P <0> =0, Third result G <1> =1 and the fourth result P <1> =0 constitutes the first output signal. The second module 112 receives the first output signal and outputs the ninth result, Four. <0> =0, the tenth result Three <0> =0, Eleventh Result Two1 <0> =0, the twelfth result Two2 <0> =1 and the thirteenth result One <0> The second output signal is composed of 1.

[0150] The third logic component 121a receives the fifth data signal D. <4> =0 and the sixth data signal D <5> =1, and output the fifth result G. <2> =1 and the sixth result P <2> =0, the fourth logic component 121b receives the seventh data signal D <6> =0 and the eighth data signal D <7> =1, and output the seventh result G. <3> =1 and the eighth result P <3> =0. Fifth result G <2> =1, Sixth result P <2> =0, Seventh Result G <3> =1 and the eighth result P <3> =0 constitutes the third output signal. The fourth module 122 receives the third output signal and outputs the fourteenth result. <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =0, Seventeenth Result Two2 <1> =1 and the eighteenth result One <1> The fourth output signal is composed of 1.

[0151] The first comparator circuit 20 (i.e., the hamming weight 5 comparator) receives the ninth result, Four. <0> =0, the tenth result Three <0> =0, Eleventh Result Two1 <0> =0, the twelfth result Two2 <0> =1, the thirteenth result One <0> =1, Fourteenth Result <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =0, Seventeenth Result Two2 <1> =1 and the eighteenth result One <1> =1, outputting the first comparison signal A in a high-level state, i.e., A is "1".

[0152] The second comparator circuit 30 (i.e., the Hamming weight 4 comparator) receives the ninth result, Four. <0> =0, the tenth result Three <0> =0, Eleventh Result Two1 <0> =0, the twelfth result Two2 <0> =1, the thirteenth result One <0> =1, Fourteenth Result <1> =0, Fifteenth Result Three <1> =0, Sixteenth Result Two1 <1> =0, Seventeenth Result Two2 <1> =1 and the eighteenth result One <1> =1, outputting the second comparison signal B in a low-level state, that is, B is "1".

[0153] The signal processing circuit 40 receives the second comparison signal "1", the data inversion signal DbiBefore of the previous data and the first comparison signal "1", and outputs the data inversion signal DbiBefore of the previous data as the data inversion signal of the current data. This means that when the comparison result D<7:0> is 10101010, in order to reduce power consumption, the operation is performed according to the data inversion signal of the previous data.

[0154] In some embodiments, the hamming weight after Xor<7:0> is the number of bits to be toggled in this operation, and the hamming weight is the number of 1 bits in Xor<7:0>. A comparator with a hamming weight of 5 outputs a low level when the hamming weight is greater than or equal to 5, and a comparator with a hamming weight of 4 outputs a high level when the hamming weight is greater than or equal to 4.

[0155] Figure 10 This is a schematic diagram of the output circuit provided in an embodiment of the present disclosure, such as... Figure 10 As shown, the output circuit 200 includes a first XOR gate 517. The first XOR gate 517 receives the twenty-sixth result (i.e., the data toggle signal of the current data) Dbi and the data DaNext<7:0> transmitted on the current data line, and performs a toggle operation on the data DaNext<7:0> transmitted on the current data line according to the data toggle signal Dbi, and finally outputs the data Da<7:0> transmitted on the current data line.

[0156] In addition, embodiments of this disclosure also provide a memory. Figure 11 This is a schematic diagram of the structure of the memory provided in the embodiments of this disclosure, such as... Figure 11 As shown, the memory 300 includes at least the data bus switching circuit 100 in any of the above embodiments.

[0157] In some embodiments, the memory 300 further includes a storage unit 310, a latch 320, a sixth AND gate 806, and a second XOR gate 807. When data is read from the memory 300, the current data (taking an 8-bit data signal as an example) is XORed with the previous data in the latch to obtain a comparison result. Then, the data bus toggle circuit 100 preprocesses and compares the comparison result, outputs a first comparison signal and a second comparison signal, determines the number of bits that need to be toggled in the current data based on the first comparison signal and the second comparison signal, and determines the data toggle signal Dbi_next corresponding to the current data based on the number of bits that need to be toggled in the current data and the data toggle signal corresponding to the previous data. Then, the sixth AND gate 806 performs an AND operation on the enable signal of the mode register and the data toggle signal Dbi_next corresponding to the current data. When Dbi_next is high and the enable signal is enabled, the sixth AND gate 806 outputs the data toggle signal Dbi_next corresponding to the current data and latches Dbi_next into latch 320 for use when determining whether the next data needs to be toggled. At the same time, the second XOR gate 807 performs an XOR operation on the data toggle signal Dbi_next corresponding to the current data and the current data, outputs the current data that has not been toggled or the toggled data DQ, and latches the above data signal into latch for use when determining whether the next data needs to be toggled.

[0158] It should be noted that, Figure 11 The data signal latched into the latch has 9 bits, including 8 bits of the current data signal and 1 bit of the current data corresponding to the data toggle signal Dbi_next.

[0159] When writing data to memory cell 310 in memory 300, the sixth AND gate 806 performs an AND operation on the enable signal in the mode register and the data toggle signal Dbi_next corresponding to the current data. Then, the second XOR gate 807 performs an XOR operation on the result of the AND operation and the current data. When Dbi_next is high and the enable signal is enabled, the current data is toggled, thereby writing data to memory cell 310.

[0160] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0161] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0162] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0163] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A data bus switching circuit, characterized in that, include: A preprocessing circuit is used to receive the comparison result between the current data and the previous data, preprocess the comparison result, and output a preprocessed signal. The comparison result contains multiple sub-results, and each sub-result is used to characterize the comparison result between the current data and the previous data at the corresponding bit. A first comparison circuit is configured to receive the preprocessed signal and output a first comparison signal based on the preprocessed signal; The first comparison signal is used to determine whether the number of preset values ​​in the comparison result is greater than or equal to a first value, wherein the preset value indicates that the corresponding bit data of the current data is different from that of the previous data. The second comparison circuit is used to receive the preprocessed signal and output the second comparison signal based on the preprocessed signal; the second comparison signal is used to determine whether the number of the preset values ​​is greater than or equal to a second value. The signal processing circuit is used to receive the first comparison signal, the second comparison signal and the data flip signal corresponding to the previous data, and output the data flip signal of the current data; The data bus flip circuit also includes: an output circuit; The output circuit is used to receive the data flip signal of the current data, and determine the data transmitted on the current data line based on the data flip signal of the current data; The first value is greater than the second value, and the second value is equal to half the amount of data transmitted by the data line at the same time; the first comparison signal indicates a second state when the number of preset values ​​is greater than or equal to the first value; the first comparison signal indicates a first state when the number of preset values ​​is less than the first value. The second comparison signal indicates the first state when the number of preset values ​​is greater than or equal to the second value; the second comparison signal indicates the second state when the number of preset values ​​is less than the second value. The signal processing circuit is used to output the data flip signal of the previous data as the data flip signal of the current data when both the second comparison signal and the first comparison signal indicate the first state. The signal processing circuit is used to output a first data flip signal as the data flip signal of the current data when the second comparison signal outputs the first state and the first comparison signal outputs the second state, wherein the first data flip signal indicates that the current data needs to be flipped; The signal processing circuit is configured to output a second data flip signal as the data flip signal of the current data when the second comparison signal outputs the second state and the first comparison signal outputs the first state, wherein the second data flip signal indicates that the current data does not need to be flipped.

2. The circuit according to claim 1, characterized in that, The comparison result includes 2n sub-results, wherein the first n sub-results form a first set of data signals, and the last n sub-results form a second set of data signals; the preprocessing circuit includes: a first preprocessing circuit and a second preprocessing circuit; The first preprocessing circuit includes a first module and a second module; the first module is used to receive the first set of data signals and output a first output signal based on the first set of data signals. The second module is used to receive the first output signal and output a second output signal based on the first output signal; The second preprocessing circuit includes a third module and a fourth module; the third module is used to receive the second set of data signals and output a third output signal based on the second set of data signals; The fourth module is used to receive the third output signal and output a fourth output signal based on the third output signal.

3. The circuit according to claim 2, characterized in that, The first comparison circuit is used to receive the second output signal and the fourth output signal, and output the first comparison signal based on the second output signal and the fourth output signal; The second comparison circuit is used to receive the second output signal and the fourth output signal, and output the second comparison signal based on the second output signal and the fourth output signal.

4. The circuit according to claim 3, characterized in that, Both the first module and the third module include n / 2 logical components; In this configuration, every two non-repeating data signals in the first group of data signals serve as input terminals for n / 2 logic components in the first module; and every two non-repeating data signals in the second group of data signals serve as input terminals for n / 2 logic components in the third module.

5. The circuit according to claim 4, characterized in that, n equals 4, the first module includes a first logic component and a second logic component; the first group of data signals includes a first data signal, a second data signal, a third data signal and a fourth data signal; The first logic component includes a first NAND gate and a first NOR gate. The first NAND gate receives the first data signal and the second data signal, and performs a NAND operation on the first data signal and the second data signal to obtain a first result. The first NOR gate receives the first data signal and the second data signal, and performs a NOR operation on the first data signal and the second data signal to obtain a second result. The second logic component includes a second NAND gate and a second NOR gate. The second NAND gate receives the third data signal and the fourth data signal, and performs a NAND operation on the third data signal and the fourth data signal to obtain a third result. The second NOR gate receives the third data signal and the fourth data signal, and performs a NOR operation on the third data signal and the fourth data signal to obtain a fourth result. The first result, the second result, the third result, and the fourth result constitute the first output signal.

6. The circuit according to claim 5, characterized in that, The third module includes a third logic component and a fourth logic component; the second group of data signals includes a fifth data signal, a sixth data signal, a seventh data signal, and an eighth data signal; The third logic component includes a third NAND gate and a third NOR gate. The third NAND gate receives the fifth data signal and the sixth data signal, and performs a NAND operation on the fifth data signal and the sixth data signal to obtain a fifth result. The third NOR gate receives the fifth data signal and the sixth data signal, and performs a NOR operation on the fifth data signal and the sixth data signal to obtain a sixth result. The fourth logic component includes a fourth NAND gate and a fourth NOR gate. The fourth NAND gate receives the seventh data signal and the eighth data signal, and performs a NAND operation on the seventh data signal and the eighth data signal to obtain a seventh result. The fourth NOR gate receives the seventh data signal and the eighth data signal, and performs a NOR operation on the seventh data signal and the eighth data signal to obtain an eighth result. The fifth result, the sixth result, the seventh result, and the eighth result constitute the third output signal.

7. The circuit according to claim 6, characterized in that, The second module includes a fifth NOR gate, a first OR gate, a second OR gate, a fifth NAND gate, a sixth NAND gate, a sixth NOR gate, and a seventh NAND gate; The fifth NOR gate receives the first result and the third result, and performs an NOR gate operation on the first result and the third result to obtain the ninth result; The first OR gate receives the first result and the fourth result, the second OR gate receives the second result and the third result, and the output terminals of the first OR gate and the second OR gate are both connected to the fifth NAND gate. The fifth NAND gate is used to perform a NAND operation on the output results of the first OR gate and the second OR gate to obtain the tenth result. The sixth NAND gate receives the first result and the third result, and performs a NAND gate operation on the first result and the third result to obtain the eleventh result; The sixth NOR gate receives the second result and the fourth result, and performs an NOR gate operation on the second result and the fourth result to obtain the twelfth result; The seventh NAND gate receives the second result and the fourth result, and performs a NAND gate operation on the second result and the fourth result to obtain the thirteenth result; The ninth result, the tenth result, the eleventh result, the twelfth result, and the thirteenth result constitute the second output signal.

8. The circuit according to claim 7, characterized in that, The fourth module includes a seventh NOR gate, a third OR gate, a fourth OR gate, an eighth NAND gate, a ninth NAND gate, an eighth NOR gate, and a tenth NAND gate; The seventh NOR gate receives the fifth result and the seventh result, and performs an NOR gate operation on the fifth result and the seventh result to obtain the fourteenth result; The third OR gate receives the fifth result and the eighth result, the fourth OR gate receives the sixth result and the seventh result, and the output terminals of the third OR gate and the fourth OR gate are both connected to the eighth NAND gate. The eighth NAND gate is used to perform a NAND operation on the output results of the third OR gate and the fourth OR gate to obtain the fifteenth result. The ninth NAND gate receives the fifth result and the seventh result, and performs a NAND gate operation on the fifth result and the seventh result to obtain the sixteenth result; The eighth NOR gate receives the sixth result and the eighth result, and performs an NOR gate operation on the sixth result and the eighth result to obtain the seventeenth result; The tenth NAND gate receives the sixth result and the eighth result, and performs a NAND gate operation on the sixth result and the eighth result to obtain the eighteenth result; The fourteenth result, the fifteenth result, the sixteenth result, the seventeenth result, and the eighteenth result constitute the fourth output signal; The second output signal and the fourth output signal constitute the preprocessed signal.

9. The circuit according to claim 8, characterized in that, The first comparison circuit includes a fifth logic component, a sixth logic component, a seventh logic component, and a third AND gate; The fifth logic component includes a first AND gate, a second AND gate, and a ninth NOR gate; the first AND gate receives the ninth result and the eighteenth result, the second AND gate receives the thirteenth result and the fourteenth result, and the ninth NOR gate is connected to the output terminals of the first AND gate and the second AND gate, and the ninth NOR gate is used to perform NOR operation on the output results of the first AND gate and the second AND gate to obtain the nineteenth result; The sixth logic component includes a fifth OR gate and an eleventh NAND gate; the fifth OR gate receives the eleventh result and the twelfth result, the eleventh NAND gate is connected to the output of the fifth OR gate and receives the fifteenth result, and the eleventh NAND gate is used to perform a NAND operation on the output of the fifth OR gate and the fifteenth result to obtain the twentieth result; The seventh logic component includes a sixth OR gate and a twelfth NAND gate; the sixth OR gate receives the sixteenth result and the seventeenth result, the twelfth NAND gate is connected to the output of the sixth OR gate and receives the tenth result, and the twelfth NAND gate is used to perform a NAND operation on the output of the sixth OR gate and the tenth result to obtain the twenty-first result; The third AND gate receives the nineteenth result, the twentieth result, and the twenty-first result, and performs an AND operation on the nineteenth result, the twentieth result, and the twenty-first result to obtain the first comparison signal.

10. The circuit according to claim 9, characterized in that, The second comparison circuit includes a tenth NOR gate, an eighth logic component, a ninth logic component, and a fourteenth NAND gate; The tenth NOR gate receives the ninth result and the fourteenth result, and performs a NOR operation on the ninth result and the fourteenth result to obtain the twenty-second result; The eighth logic component includes a fourth AND gate, a fifth AND gate, and an eleventh NOR gate; the fourth AND gate receives the tenth result and the eighteenth result, the fifth AND gate receives the fifteenth result and the thirteenth result, and the eleventh NOR gate is connected to the output terminals of the fourth AND gate and the fifth AND gate. The eleventh NOR gate is used to perform a NOR operation on the output results of the fourth AND gate and the fifth AND gate to obtain the twenty-third result. The ninth logic component includes a seventh OR gate, an eighth OR gate, and a thirteenth NAND gate; the seventh OR gate receives the eleventh and twelfth results, the eighth OR gate receives the sixteenth and seventeenth results, and the thirteenth NAND gate is connected to the outputs of the seventh and eighth OR gates. The thirteenth NAND gate is used to perform a NAND operation on the outputs of the seventh and eighth OR gates to obtain the twenty-fourth result. The fourteenth NAND gate receives the second twelfth result, the second thirteenth result, and the second fourteenth result, and performs an NAND operation on the second twelfth result, the second thirteenth result, and the second fourteenth result to obtain the second comparison signal.

11. The circuit according to claim 1, characterized in that, The signal processing circuit includes a fifteenth NAND gate and a sixteenth NAND gate; The fifteenth NAND gate receives the second comparison signal and the data inversion signal of the previous data, and performs NAND processing on the second comparison signal and the data inversion signal of the previous data to obtain the twenty-fifth result; The sixteenth NAND gate receives the twenty-fifth result and the first comparison signal, performs NAND processing on the twenty-fifth result and the first comparison signal, and outputs the twenty-sixth result; The 26th result includes any one of the following: the data flip signal of the current data, the first data flip signal, and the second data flip signal.

12. A memory, characterized in that, include: The memory cell and the data bus switching circuit as described in any one of claims 1 to 11.

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