substrate structure

The substrate structure addresses warpage and reliability issues by using dielectric layers with lower thermal expansion coefficients, forming compressive stress to enhance structural integrity and enable high-density vias and circuits.

JP2026116656APending Publication Date: 2026-07-10UNIMICRON TECH CORP

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
UNIMICRON TECH CORP
Filing Date
2025-05-15
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

High-end integrated circuit (IC) substrates face issues with warpage and reduced manufacturing yield due to increased size and thickness, leading to decreased structural reliability, especially when using glass substrates, which crack and have low hole filling yield and vias with large diameters.

Method used

A substrate structure with a dielectric core plate and build-up layers, where the dielectric layers have a smaller thermal expansion coefficient than the core, incorporating conductive vias and bonding layers to form compressive stress, enhancing structural reliability.

Benefits of technology

The structure suppresses warping and improves reliability by forming compressive stress, allowing for high-density vias and circuits, suitable for high-end products.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 2026116656000001_ABST
    Figure 2026116656000001_ABST
Patent Text Reader

Abstract

To provide a substrate structure with excellent structural reliability. [Solution] The substrate structure includes a base and at least one build-up structural layer. The base includes a dielectric core substrate and at least one first conductive via penetrating the dielectric core substrate. The at least one build-up structural layer is located on the base and includes a dielectric layer and at least one second conductive via penetrating the dielectric layer. The thermal expansion coefficient of the dielectric layer is smaller than that of the dielectric core substrate. At least one second conductive via is electrically connected to at least one first conductive via.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to a substrate structure, and more particularly to a substrate structure having excellent structural reliability.

Background Art

[0002] High-end integrated circuit (IC) substrates and circuit boards are increasing in size and thickness, resulting in a decrease in manufacturing yield and warpage of the substrates becoming a problem. To solve the problem of substrate warpage, it is necessary to thicken the inner core substrate to increase the support strength. However, in the above method, the diameter and interval of the conductive vias become large, the density of the conductive vias is not high, and it is not suitable for application to high-end products. Further, when a glass substrate is used as the core layer, the thickness of the core substrate is usually more than 0.5 mm, while the diameter of the conductive via is less than 0.1 mm, and the hole filling yield of electroplating becomes low. Also, in the build-up structure of the core layer, since the coefficient of thermal expansion is larger than that of the core layer, tensile stress is generated after a heating process (such as curing), and the core layer using a glass material is likely to crack from the center, reducing the structural reliability of the product.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a substrate structure having excellent structural reliability.

Means for Solving the Problems

[0004] The substrate structure of the present invention includes a base and at least one build-up structure layer. The base includes a dielectric core plate and at least one first conductive via penetrating the dielectric core plate. At least one build-up structure layer is disposed on the base and includes a dielectric layer and at least one second conductive via penetrating the dielectric layer. The coefficient of thermal expansion of the dielectric layer is smaller than that of the dielectric core plate. At least one second conductive via is electrically connected to at least one first conductive via.

[0005] In one embodiment of the present invention, the substrate structure further includes at least one bonding layer and at least one third conductive via. The at least one bonding layer is located between the base and at least one build-up structure layer. The at least one third conductive via penetrates the at least one bonding layer and is electrically connected to at least one first conductive via and at least one second conductive via.

[0006] In one embodiment of the present invention, the material of the at least one third conductive via includes a conductive paste, a metal paste, or a nanowire.

[0007] In one embodiment of the present invention, the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via have the same diameter when viewed in cross-section.

[0008] In one embodiment of the present invention, the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via are aligned with each other when viewed in cross-section.

[0009] In one embodiment of the present invention, the material of the dielectric core substrate of the base includes an organic material, an inorganic material, or a non-conductive composite material.

[0010] In one embodiment of the present invention, the material of the dielectric layer of the at least one build-up structure layer includes an organic material, an inorganic material, or a non-conductive composite material.

[0011] In one embodiment of the present invention, the material of the base dielectric core substrate is the same as the material of the dielectric layer of at least one build-up structure layer.

[0012] In one embodiment of the present invention, the Young's modulus of at least one of the build-up structural layers is greater than the Young's modulus of the base.

[0013] In one embodiment of the present invention, the thickness of the base is 80 to 800 μm.

[0014] In one embodiment of the present invention, the thickness of at least one of the build-up structural layers is 80 to 800 μm.

[0015] In one embodiment of the present invention, the base further includes at least one first circuit pattern, and at least one build-up structural layer further includes at least one second circuit pattern. The at least one first circuit pattern is electrically connected to at least one first conductive via. The at least one second circuit pattern is electrically connected to at least one second conductive via. [Effects of the Invention]

[0016] As described above, in the substrate structure of the present invention, since the thermal expansion coefficient of the dielectric layer of the build-up structure layer is smaller than that of the base dielectric core substrate, compressive stress is formed, warping of the substrate structure can be suppressed, and the substrate structure of the present invention can have excellent structural reliability. [Brief explanation of the drawing]

[0017] [Figure 1] This is a schematic cross-sectional view of a substrate structure according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view of a substrate structure according to another embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view of a substrate structure according to another embodiment of the present invention. [Modes for carrying out the invention]

[0018] Embodiments of the present invention can be understood in conjunction with the drawings, and the drawings of the present invention are also considered part of the disclosure. Please understand that the drawings of the present invention are not drawn to scale, and the sizes of the components may be arbitrarily enlarged or reduced in practice to clearly illustrate the features of the present invention.

[0019] Figure 1 is a schematic cross-sectional view of a substrate structure according to one embodiment of the present invention. Referring to Figure 1, in this embodiment, the substrate structure 100a includes a base 110 and at least one build-up structure layer (one build-up structure layer 120 is schematically shown). The base 110 includes a dielectric core substrate 112 and at least one first conductive via (a plurality of first conductive vias 114 are schematically shown) penetrating the dielectric core substrate 112. The build-up structure layer 120 is located on the base 110 and includes a dielectric layer 122 and at least one second conductive via (a plurality of second conductive vias 124 are schematically shown) penetrating the dielectric layer 122. The thermal expansion coefficient of the dielectric layer 122 is smaller than that of the dielectric core substrate 112. The second conductive vias 124 are electrically connected to the first conductive vias 114.

[0020] In detail, in this embodiment, the dielectric core substrate 112 of the base 110 has a first surface 111 and a second surface 113 opposite to the first surface 111. The first conductive via 114 penetrates the dielectric core substrate 112, i.e., the periphery of the first conductive via 114 is covered by the dielectric core substrate 112. In one embodiment, the opposing first ends 114a and second ends 114b of the first conductive via 114 may be aligned with the first surface 111 and second surface 113 of the dielectric core substrate 112, respectively. In one embodiment, the opposing first ends 114a and second ends 114b of the first conductive via 114 may be slightly higher than the first surface 111 and second surface 113 of the dielectric core substrate 112, respectively. In one embodiment, the thickness T1 of the base 110 is, for example, 80 to 800 μm. In one embodiment, the material of the dielectric core substrate 112 of the base 110 is, for example, an organic material, an inorganic material, or a non-conductive composite material. In one embodiment, the organic material is, for example, a glass fiber resin (e.g., FR4), a prepreg (PP), or an inorganic filler mixed with a photoresist resin, but is not limited thereto. In one embodiment, the inorganic material is, for example, glass, ceramic, or glass ceramic. In one embodiment, the first conductive via 114 can be formed on the dielectric core substrate 112 by methods such as electroplating, electroplating plus filling with a metal paste, or electroplating plus filling with a non-conductive resin, but is not limited thereto.

[0021] Referring again to Figure 1, in this embodiment, the dielectric layer 122 of the build-up structure layer 120 has an outer surface 121 and an inner surface 123 opposite to the outer surface 121, with the inner surface 123 located between the outer surface 121 and the base 110. The second conductive via 124 penetrates the dielectric layer 122, i.e., the periphery of the second conductive via 124 is covered by the dielectric layer 122. In one embodiment, the opposing first ends 124a and second ends 124b of the second conductive via 124 may be aligned with the outer surface 121 and inner surface 123 of the build-up structure layer 120, respectively. In one embodiment, the opposing first ends 124a and second ends 124b of the second conductive via 124 may be slightly higher than the outer surface 121 and inner surface 123 of the dielectric layer 122, respectively. In one embodiment, the thickness T2 of the build-up structure layer 120 is, for example, 80 to 800 μm. In one embodiment, the material of the dielectric layer 122 of the build-up structure layer 120 is, for example, an organic material, an inorganic material, or a non-conductive composite material. In one embodiment, the organic material is, for example, a glass fiber resin (e.g., FR4), a prepreg (Prepreg, PP), or an inorganic filler mixed with a photoresist resin, but is not limited thereto. In one embodiment, the inorganic material is, for example, glass, ceramic, or glass ceramic. In one embodiment, the second conductive via 124 can be formed in the dielectric layer 122 by methods such as electroplating, electroplating plus filling with metal paste, or electroplating plus filling with a non-conductive resin, but is not limited thereto.

[0022] In one embodiment, the Young's modulus of the build-up structure layer 120 may be greater than the Young's modulus of the base 110. That is, the build-up structure layer 120 has the lowest coefficient of thermal expansion and the highest Young's modulus compared to the base 110. In one embodiment, the material of the dielectric core substrate 112 of the base 110 may be the same as the material of the dielectric layer 122 of the build-up structure layer 120. For example, both may be organic materials. In one embodiment, the material of the dielectric core substrate 112 of the base 110 may be the same as the material of the dielectric layer 122 of the build-up structure layer 120. For example, both may be inorganic materials. In one embodiment, the material of the dielectric core substrate 112 of the base 110 may be an organic material, and the material of the dielectric layer 122 of the build-up structure layer 120 may be an inorganic material. In one embodiment, the material of the dielectric core substrate 112 of the base 110 may be an inorganic material, and the material of the dielectric layer 122 of the build-up structure layer 120 may be an organic material. In one embodiment, when the dielectric core substrate 112 of the base 110 and / or the dielectric layer 122 of the build-up structure layer 120 uses a glass material, the density of the first conductive via 114 and / or the second conductive via 124 can be increased. Since the glass surface is flat, it is very suitable for forming a high-density circuit thereon.

[0023] Also, referring back to FIG. 1, the substrate structure 100a of the present embodiment further includes at least one bonding layer (schematically shown as one bonding layer 130) and at least one third conductive via (schematically shown as a plurality of third conductive vias 135). The bonding layer 130 is disposed between the base 110 and the build-up structure layer 120, and the build-up structure layer 120 is fixed to the base 110 by the bonding layer 130. The third conductive via 135 penetrates the bonding layer 130 and is electrically connected to the first conductive via 114 of the base 110 and the second conductive via 124 of the build-up structure layer 120. In one embodiment, the first conductive via 114, the second conductive via 124, and the third conductive via 135 may have the same diameter and be aligned with each other in a straight line when viewed in cross section. That is, the orthographic projections on the plane of the first conductive via 114, the second conductive via 124, and the third conductive via 135 may completely overlap.

[0024] In one embodiment, the material of the bonding layer 130 may be, for example, a thermosetting or thermoplastic polymer material. In one embodiment, the material of the bonding layer 130 is, for example, polyimide (PI), Ajinomoto build-up film (ABF), bismaleimide-triazine (BT), or other polymers. In one embodiment, the thickness T3 of the bonding layer 130 is, for example, 8 to 100 μm. In one embodiment, the bonding layer 130 has a low elastic modulus and can be used as a stress buffer layer. In one embodiment, the material of the third conductive via 135 formed in the bonding layer 130 is, for example, a conductive paste (such as TLPS), a metal paste (such as a copper paste or a silver paste), or a nanowire, but is not limited thereto.

[0025] That is, since the coefficient of thermal expansion of the dielectric layer 122 of the build-up structure layer 120 is smaller than the coefficient of thermal expansion of the dielectric core substrate 112 of the base 110, a compressive stress is formed, and the warpage of the substrate structure 100a can be suppressed. The substrate structure 100a of the present embodiment can have excellent structural reliability.

[0026] Other embodiments are listed below for illustration. Note that in the following embodiments, some of the component numbers and contents of the foregoing embodiments are incorporated, and the same numbers are used to represent the same or similar components. It should be noted that the description of the same technical content is omitted. For the description of the omitted parts, refer to the foregoing embodiments, and the overlapping descriptions are omitted in the following embodiments.

[0027] Figure 2 is a schematic cross-sectional view of a substrate structure according to another embodiment of the present invention. Referring to Figures 1 and 2 together, the substrate structure 100b of this embodiment is similar to the substrate structure 100a described above, but the main difference between the two is that in this embodiment, the substrate structure 100b further includes a build-up structure layer 140, a bonding layer 150, and a third conductive via 155. In other words, the substrate structure 100b of this embodiment consists of one base 110, two build-up structure layers 120 and 140, and two bonding layers 130 and 150.

[0028] In detail, the build-up structural layer 140 is located on the second surface 113 of the base 110. The build-up structural layer 140 includes a dielectric layer 142 and at least one second conductive via (a plurality of second conductive vias 144 are schematically shown) that penetrates the dielectric layer 142. The coefficient of thermal expansion of the dielectric layer 142 is smaller than that of the dielectric core substrate 112. In this embodiment, the dielectric layer 142 of the build-up structural layer 140 has an outer surface 141 and an inner surface 143 opposite the outer surface 141, the inner surface 143 is located between the outer surface 141 and the base 110. The second conductive via 144 penetrates the dielectric layer 142, i.e., the area around the second conductive via 144 is covered by the dielectric layer 142. In one embodiment, the opposing first ends 144a and second ends 144b of the second conductive via 144 may be aligned with the outer surface 141 and inner surface 143 of the build-up structure layer 140, respectively. In one embodiment, the opposing first ends 144a and second ends 144b of the second conductive via 144 may be slightly higher than the outer surface 141 and inner surface 143 of the dielectric layer 142, respectively. In one embodiment, the thickness T4 of the build-up structure layer 140 is, for example, 80 to 800 μm. In one embodiment, the material of the dielectric layer 142 of the build-up structure layer 140 is, for example, an organic material, an inorganic material, or a non-conductive composite material. In one embodiment, the organic material is, for example, a glass fiber resin (e.g., FR4), a prepreg (Prepreg, PP), or an inorganic filler mixed with a photoresist resin, but is not limited thereto. In one embodiment, the inorganic material is, for example, glass, ceramic, or glass ceramic. In one embodiment, the second conductive via 144 can be formed on the dielectric layer 142 by methods such as electroplating, electroplating plus filling with metal paste, or electroplating plus filling with a non-conductive resin, but is not limited thereto.

[0029] In one embodiment, the material of the dielectric layer 122 of the build-up structure layer 120, the material of the dielectric core substrate 112 of the base 110, and the material of the dielectric layer 142 of the build-up structure layer 140 may be a combination of glass, organic material, and glass (COG), in that order. In one embodiment, the material of the dielectric layer 122 of the build-up structure layer 120, the material of the dielectric core substrate 112 of the base 110, and the material of the dielectric layer 142 of the build-up structure layer 140 may be a combination of ceramic, organic material, and ceramic (COC), in that order. In one embodiment, the material of the dielectric layer 122 of the build-up structure layer 120, the material of the dielectric core substrate 112 of the base 110, and the material of the dielectric layer 142 of the build-up structure layer 140 may be a combination of ceramic, organic material, and glass (COG), in that order. In one embodiment, the substrate structure 100b can be considered a hybrid core structure.

[0030] It is noteworthy that in a structure where two glass layers (dielectric layers 122 and 142 of build-up structural layers 120 and 140) cover both sides of an organic material (such as the dielectric core substrate 112 of the base 110), the thickness of the organic material can be effectively reduced, and rigidity can be improved. Furthermore, because the thickness of the organic material can be reduced, smaller vias can be used, the pitch can be reduced, and the density of conductive vias can be increased accordingly.

[0031] Referring again to Figure 2, the bonding layer 150 is positioned between the second surface 113 of the base 110 and the build-up structure layer 140, and the build-up structure layer 140 is fixed to the base 110 by the bonding layer 150. The third conductive via 155 penetrates the bonding layer 150 and is electrically connected to the first conductive via 114 of the base 110 and the second conductive via 144 of the build-up structure layer 140. In one embodiment, the first conductive via 114, the second conductive via 124, the second conductive via 144, the third conductive via 135, and the third conductive via 155 have the same diameter when viewed in cross-section and are aligned with each other in a straight line. That is, the orthogonal projections of the first conductive via 114, the second conductive via 124, the second conductive via 144, the third conductive via 135, and the third conductive via 155 on a plane may completely overlap.

[0032] In one embodiment, the material of the bonding layer 150 may be, for example, a thermosetting or thermoplastic polymer material. In one embodiment, the material of the bonding layer 150 may be, for example, polyimide (PI), Ajinomoto build-up film (ABF), bismaleimide-triazine (BT), or other polymers. In one embodiment, the thickness T5 of the bonding layer 150 is, for example, 8 to 100 μm. In one embodiment, the bonding layer 150 has a low elastic modulus and can serve as a stress buffer layer. In one embodiment, the material of the third conductive via 155 formed in the bonding layer 150 may be, for example, a conductive paste (such as TLPS), a metal paste (such as copper paste or silver paste), or a nanowire, but is not limited thereto.

[0033] In other words, in this embodiment, the outermost build-up structural layers 120 and 140 have a smaller coefficient of thermal expansion and a larger Young's modulus than the dielectric core substrate 112 of the base 110. Because the coefficients of thermal expansion of the dielectric layers 122 and 142 of the build-up structural layers 120 and 140 are smaller than those of the dielectric core substrate 112 of the base 110, compressive stress is formed, which suppresses warping of the substrate structure 100b, and the substrate structure 100b of this embodiment can have excellent structural reliability.

[0034] Figure 3 is a schematic cross-sectional view of a substrate structure according to another embodiment of the present invention. Referring to Figures 2 and 3 together, the substrate structure 100c of this embodiment is similar to the substrate structure 100b described above, but the main difference between the two is that in this embodiment, the base 110' further includes at least one first circuit pattern 116, the build-up structure layer 120' further includes at least one second circuit pattern 126, and the build-up structure layer 140' further includes at least one second circuit pattern 146. The first circuit pattern 116 is arranged on the first surface 111 and the second surface 113 of the dielectric core substrate 112, and the first circuit pattern 116 is electrically connected to a first conductive via 114. In one embodiment, the first circuit pattern 116 may be, for example, a pad, a circuit, a conductive blind via, or a combination thereof. The second circuit pattern 126 is arranged on the outer surface 121 and the inner surface 123 of the dielectric layer 122, and the second circuit pattern 126 is electrically connected to a second conductive via 124. In one embodiment, the second circuit pattern 126 may be, for example, a pad, a circuit, a conductive blind via, or a combination thereof. The second circuit pattern 146 is arranged on the outer surface 141 and inner surface 143 of the dielectric layer 142, and the second circuit pattern 146 is electrically connected to the second conductive via 144. In one embodiment, the second circuit pattern 146 may be, for example, a pad, a circuit, a conductive blind via, or a combination thereof.

[0035] Furthermore, the build-up structure layer 120' is fixed to the first surface 111 of the base 110 by the bonding layer 130', and the bonding layer 130' contacts and covers the inner surface 123 of the build-up structure layer 120', a portion of the second circuit pattern 126, a portion of the first circuit pattern 116, and the first surface 111 of the dielectric core substrate 112. The build-up structure layer 140' is fixed to the second surface 113 of the base 110 by the bonding layer 150', and the bonding layer 150' contacts and covers the inner surface 143 of the build-up structure layer 140', a portion of the second circuit pattern 146, a portion of the first circuit pattern 116, and the second surface 113 of the dielectric core substrate 112. The second conductive via 124 is electrically connected to the first conductive via 114 by the third conductive via 135', and the second conductive via 144 is electrically connected to the first conductive via 114 by the third conductive via 155'.

[0036] Since the base 110' and the build-up structural layers 120' and 140' are joined by bonding layers 130' and 150', the joints of the base 110' and the build-up structural layers 120 and 140' are wired, respectively, which can improve the wiring density of the substrate structure 100c. In embodiments not shown, multiple substrate structures can also be combined using bonding layers, and the substrate structures can be electrically connected via conductive vias in the bonding layers.

[0037] In summary, in the substrate structure of the present invention, the thermal expansion coefficient of the dielectric layer of the build-up structure layer is smaller than that of the base dielectric core substrate, so compressive stress is formed, warping of the substrate structure can be suppressed, and the substrate structure of the present invention can have excellent structural reliability. [Industrial applicability]

[0038] The substrate structure of the present invention is suitable for application in high-end products. [Explanation of Symbols]

[0039] 100a, 100b, 100c: Substrate structure 110, 110': Bass 111: 1st surface 112: Dielectric core substrate 113:Second surface 114: First conductive via 114a: 1st end 114b: 2nd end 116: First Circuit Pattern 120, 120', 140, 140': Build-up structural layers 121, 141: Outer surface 122, 142: Dielectric layer 123, 143: Inner surface 124, 144: Second conductive via 124a, 144a: 1st end 124b, 144b: 2nd end 126, 146: Second circuit pattern 130, 130', 150, 150': Bonding layer 135, 135', 155, 155': Third conductive via T1, T2, T3, T4, T5: Thickness

Claims

1. A base comprising a dielectric core substrate and at least one first conductive via penetrating the dielectric core substrate, Displaced on the base, at least one build-up structure layer comprising a dielectric layer and at least one second conductive via penetrating the dielectric layer, Includes, A substrate structure in which the thermal expansion coefficient of the dielectric layer is smaller than that of the dielectric core substrate, and the at least one second conductive via is electrically connected to the at least one first conductive via.

2. At least one bonding layer disposed between the base and the at least one build-up structural layer, Penetrating the at least one bonding layer, and electrically connected to the at least one first conductive via and the at least one second conductive via, The substrate structure according to claim 1, further comprising:

3. The substrate structure according to claim 2, wherein the material of the at least one third conductive via includes a conductive paste, a metal paste, or a nanowire.

4. The substrate structure according to claim 2, wherein the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via have the same diameter when viewed in cross-section.

5. The substrate structure according to claim 2, wherein the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via are aligned with each other when viewed in cross-section.

6. The substrate structure according to claim 1, wherein the material of the dielectric core substrate of the base includes an organic material, an inorganic material, or a non-conductive composite material.

7. The substrate structure according to claim 1, wherein the material of the dielectric layer of the at least one build-up structure layer includes an organic material, an inorganic material, or a non-conductive composite material.

8. The substrate structure according to claim 1, wherein the material of the dielectric core substrate of the base is the same as the material of the dielectric layer of the at least one build-up structure layer.

9. The substrate structure according to claim 1, wherein the Young's modulus of at least one build-up structural layer is greater than the Young's modulus of the base.

10. The substrate structure according to claim 1, wherein the thickness of the base is 80 to 800 μm.

11. The substrate structure according to claim 1, wherein the thickness of at least one build-up structure layer is 80 to 800 μm.

12. The substrate structure according to claim 1, wherein the base further comprises at least one first circuit pattern, and the at least one build-up structural layer further comprises at least one second circuit pattern, wherein the at least one first circuit pattern is electrically connected to the at least one first conductive via, and the at least one second circuit pattern is electrically connected to the at least one second conductive via.