Light-emitting display device

Abstract

To provide a light-emitting display device with improved reliability in high-temperature and high-humidity environments. [Solution] A light-emitting display device according to one or more embodiments of this specification includes a substrate including a display area and a pad area; a sealing portion extending from the display area toward the pad area on the substrate; at least one inorganic insulating layer disposed on the sealing portion; pad electrodes disposed in the pad area on the substrate and electrically connected to each of the signal link lines; and a pad cover portion configured to cover at least a portion of the pad electrodes in the pad area, wherein the at least one inorganic insulating layer includes an extended pattern portion configured to overlap with the edge of the pad cover portion.

Description

Technical Field

[0001] This specification relates to a light-emitting display device.

Background Art

[0002] With the development of the information society, the requirements for display devices for displaying images have increased in various forms, and light-emitting display devices such as liquid crystal display devices (LCDs), organic light-emitting display devices (OLEDs), micro LED display devices (Micro LED Displays), and quantum dot display devices (QDs) are being utilized.

[0003] In a light-emitting display device, a sealing film is formed to prevent the penetration of moisture and oxygen from the outside. Such a sealing film is composed of at least one inorganic film and at least one organic film, and prevents the penetration of moisture and oxygen.

Summary of the Invention

Problems to be Solved by the Invention

[0004] A light-emitting display device may have a ToE (Touch on Encapsulation) structure in which a plurality of touch sensors and a plurality of touch sensor lines are directly formed on a sealing film in order to implement a touch function. However, in the process of forming the ToE structure provided in the light-emitting display device, the inorganic film of the sealing layer may be damaged or a crack defect may occur. Due to such a crack defect, moisture penetrates in a high-temperature / high-humidity environment, and the signal voltage line disposed in the pad region is corroded, resulting in an electrolytic corrosion defect problem.

[0005] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting display device capable of preventing moisture from penetrating through the pad region of a display panel.

[0006] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting device that can prevent damage and crack defects in the inorganic film in the pad area.

[0007] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting display device that can prevent electrolytic corrosion failure of signal voltage lines located in a pad area.

[0008] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting device with improved reliability in high-temperature / high-humidity environments.

[0009] The problems addressed by one or more embodiments of this specification are not limited to those mentioned above, and other problems not mentioned will be readily apparent to those skilled in the art from the following description. [Means for solving the problem]

[0010] A light-emitting display device according to one or more embodiments of this specification includes a substrate including a display area and a pad area; a sealing portion on the substrate extending from the display area toward the pad area; at least one inorganic insulating layer disposed on the sealing portion; pad electrodes disposed in the pad area on the substrate and electrically connected to each of the signal link lines; and a pad cover portion configured to cover at least a portion of the pad electrodes in the pad area, wherein the at least one inorganic insulating layer includes an extended pattern portion configured to overlap the edge of the pad cover portion.

[0011] Specific details, other than the solutions to the problems mentioned above, are included in the following descriptions and drawings. [Effects of the Invention]

[0012] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device that can prevent moisture from penetrating through the pad area of ​​a display panel.

[0013] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device that can prevent damage and crack defects in the inorganic film in the pad area.

[0014] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device that can prevent electrolytic corrosion failure of signal voltage lines arranged in a pad area.

[0015] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device with improved reliability in high-temperature / high-humidity environments.

[0016] The light-emitting display devices according to one or more embodiments of this specification can prevent damage and cracking of the inorganic film in the pad area of ​​the display panel and prevent moisture from penetrating through the pad area. Therefore, it is possible to prevent electrolytic corrosion failure of the signal voltage lines located in the pad area and improve reliability in high temperature / high humidity environments, thereby optimizing the manufacturing process of the light-emitting display device, saving power consumption and enabling low-power operation, extending lifespan, and reducing production energy, thus contributing to ESG (Environment / Social / Governance).

[0017] The effects described herein are not limited to those mentioned above, and any other effects not mentioned will be readily apparent to those skilled in the art from the following description.

[0018] Since the content of the invention described above—the problem to be solved, the means of solving the problem, and the effects—does not specify the essential features of the claims, the scope of rights in the claims is not limited to the matters described in the content of the invention. [Brief explanation of the drawing]

[0019] [Figure 1] This figure shows a schematic configuration of a light-emitting display device according to the embodiments described herein. [Figure 2] This figure shows a light-emitting device according to an embodiment of this specification. [Figure 3] It is a diagram showing a structure in which a touch panel is built into a display panel according to an embodiment of this specification. [Figure 4] It is a diagram showing the A region shown in FIG. 2 according to an embodiment of this specification. [Figure 5] It is a cross-sectional view of the I-I' line shown in FIG. 4 according to an embodiment of this specification. [Figure 6] It is a diagram showing the B region shown in FIG. 4 according to an embodiment of this specification. [Figure 7] It is a cross-sectional view of the II-II' line shown in FIG. 6 according to an embodiment of this specification. [Figure 8] It is a cross-sectional view of the III-III' line shown in FIG. 6 according to an embodiment of this specification. [Figure 9] It is a diagram showing the C region shown in FIG. 4 according to another embodiment of this specification. [Figure 10] It is a cross-sectional view of the IV-IV' line shown in FIG. 9 according to another embodiment of this specification.

Modes for Carrying Out the Invention

[0020] The advantages and features of this specification, and the methods for achieving them, will become clear by referring to various examples described in detail hereinafter based on the accompanying drawings. However, this specification is not limited to an example disclosed below, and can be embodied in various different forms. The embodiments of this specification complete the disclosure of this specification and are provided to fully inform those with ordinary knowledge in the technical field to which the technical idea of this specification belongs of the scope of the technical idea, and this specification is only defined by the scope of the claims.

[0021] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings illustrating the embodiments herein are illustrative only, and this specification is not limited to those depicted. The same reference numerals throughout the specification indicate the same components. Furthermore, in the description herein, if it is determined that a specific description of related known technology would unnecessarily obscure the gist of this specification, such detailed description will be omitted.

[0022] When using words such as "includes," "possesses," and "becomes" as used herein, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0023] In interpreting the constituent elements, even if there is no separate explicit mention of the margin of error, it shall be interpreted as including the margin of error.

[0024] When describing the relative positions of two parts, for example, using phrases like "on top of," "above," "below," or "next to," one or more other parts can be located between the two parts, unless "immediately" or "directly" is used.

[0025] When describing temporal relationships, for example, when describing sequential relationships using phrases like "after," "following," "next," or "before," unless "immediately" or "directly" is used, it can include situations that are not continuous.

[0026] The terms "first," "second," etc., are used to describe various components, but these components are not limited to these terms. These terms are used simply to distinguish one component from others. Therefore, the first component mentioned below may also be the second component within the technical concepts of this specification.

[0027] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component.

[0028] Where it is stated that one component is “connected,” “joined,” “attached,” or “attached” to another component, that component may be directly connected, joined, attached, or attached to the other component, but unless otherwise explicitly stated, it should be understood that other components may be interposed between each component that may be indirectly connected, joined, attached, or attached.

[0029] Where it is stated that a component or layer "contacts" or "overlaps" with another component or layer, the component or layer may directly contact or overlap with another component or layer, but unless otherwise explicitly stated, it can be understood that other components may be interposed between each component that may indirectly contact or overlap with it.

[0030] "At least one" should be understood to include all combinations of one or more related components. For example, "at least one of the first, second, and third components" can be said to include not only the first, second, or third component, but also all combinations of two or more components from the first, second, and third components.

[0031] Many of the features of the embodiments described herein can be combined or combined in part or in whole with one another, enabling a variety of technical interdependencies and drives, and each embodiment can be implemented independently of the others or together in a related manner.

[0032] The embodiments of this specification will now be described based on the attached drawings and examples. The scales of the components shown in the drawings are different from those of actual components for the sake of explanation and are not limited to the scales shown in the drawings.

[0033] Figure 1 shows a schematic configuration of a light-emitting display device according to an embodiment of this specification. Figure 2 shows a light-emitting display device according to an embodiment of this specification. Figure 3 shows a structure in which a touch panel is built into a display panel according to an embodiment of this specification.

[0034] In the following, the X-axis indicates the direction parallel to the scan line (or gate line), the Y-axis indicates the direction parallel to the data line, and the Z-axis indicates the height direction of the light-emitting display device.

[0035] The light-emitting display devices described herein will primarily be those implemented as organic light-emitting displays, but they may also be implemented as liquid crystal displays, quantum dot light-emitting diodes, or electrophoresis displays. Furthermore, the light-emitting display devices described herein can be implemented as touch displays with a built-in touch function in the display panel.

[0036] Referring to Figures 1 to 3, the light-emitting display device according to the embodiment of this specification can provide both a function for displaying images and a function for touch sensing.

[0037] The light-emitting display device according to the embodiments of this specification may include a display panel 110, a scan drive unit 120 (or gate drive unit) built into the display panel 110, a data drive unit 130 connected to the display panel 110, a timing control unit 160 that controls the scan drive unit 120 and the data drive unit 130, and a power supply circuit 170 in order to provide a video display function.

[0038] The display panel 110 may include a substrate 111 and a counter substrate 112. The counter substrate 112 may be a sealing substrate. The substrate 111 may include a plastic film or a glass substrate, but the embodiments herein are not limited thereto. For example, the substrate 111 may be composed of a semiconductor material such as a silicon wafer. The counter substrate 112 may be a plastic film, a glass substrate, or a sealing film (or protective film).

[0039] The display panel 110 may include a display area DA and a non-display area NDA that surrounds the display area DA and is located on the outer casing. The display panel 110 can display an image by providing pixels P in the display area DA. Each pixel P may include a plurality of sub-pixels SP. The structure of the sub-pixels SP can be varied in various ways depending on the type of light-emitting device. For example, depending on the structure, the sub-pixels SP may be configured in a top emission, bottom emission, or dual emission manner. A sub-pixel SP means a unit that can emit its own hue, or one in which a specific type of color filter is formed. Depending on the light emission characteristics, the sub-pixels SP may have one or more different light emission areas. For example, a plurality of sub-pixels SP may be arranged in a stripe type or a quad type, but the embodiments herein are not limited thereto, and the color type, arrangement type, arrangement order, etc. of the sub-pixels SP can be configured in various forms depending on the light emission characteristics, element lifespan, device specifications, etc.

[0040] The display panel 110 may be configured with data lines DL and scan lines (or gate lines) SL connected to sub-pixels SP. The data lines DL may be configured to intersect with the scan lines SL. Each sub-pixel SP of the display panel 110 may be connected to one of the data lines DL and one of the scan lines SL. The data lines DL can supply data voltages supplied from the data drive unit 130 to each sub-pixel SP. The scan lines SL can supply scan signals supplied from the scan drive unit 120 to each sub-pixel SP.

[0041] Each sub-pixel SP is turned on in response to the scan signal, and when the data voltage of the data line DL is supplied to the gate electrode of the drive transistor, the light-emitting element can emit light due to the current between the drain and source of the drive transistor. The scan drive unit 120 can receive a scan control signal GCS from the timing control unit 160. The scan drive unit 120 can use the scan control signal GCS to supply a scan signal or a light emission control signal to the scan line SL.

[0042] The scan drive unit 120 may be configured in a GIP (gate driver in panel) manner on the non-display area NDA outside one or both sides of the display area DA. Alternatively, the scan drive unit 120 may be manufactured as a drive chip, mounted on a flexible film, and attached to the non-display area NDA outside one or both sides of the display area DA using a TAB (tape automated bonding) method.

[0043] The data drive unit 130 can receive digital video data DATA and data control signal DCS from the timing control unit 160. Using the data control signal DCS, the data drive unit 130 can convert the digital video data DATA into analog positive / negative polarity data voltages and supply them to the data line DL.

[0044] The data drive unit 130 may include a plurality of source drive integrated circuits (source drive ICs). Each source drive IC may be mounted on the source film 140 using a COF (Chip On Film), COP (chip on plastic), FPC (Flexible Printed Circuit), or FFC (Flexible Flat Cable) method. One side of the source film 140 is electrically connected to the display panel 110, and COF wiring for electrically connecting each source drive IC to the display panel 110 may be arranged on the top of the source film 140. The source film 140 may be attached to a pad provided in the non-display area (NDA) of the display panel 110 using an anisotropic conducting film, so that each source drive IC is connected to the pad.

[0045] The display panel 110 may include a circuit board 150 for circuit connection between the data drive unit 130 and other devices. The circuit board 150 may consist of at least one, but the embodiments herein are not limited thereto.

[0046] A source film 140 may be attached to the circuit board 150. Multiple circuits embodied by the drive chip may be mounted on the circuit board 150. For example, a timing control unit 160 may be mounted on the circuit board 150. The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

[0047] The timing control unit 160 can receive digital video data DATA and timing signals from the host system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The vertical synchronization signal is a signal that defines one frame period. The horizontal synchronization signal is a signal that defines one horizontal period required to supply data voltage to a pixel of one horizontal line on the display panel 110. The data enable signal is a signal that defines the period during which valid data is input. The dot clock is a signal that repeats at a predetermined short period.

[0048] The timing control unit 160 can generate a data control signal DCS to control the operating timing of the data drive unit 130 and a scan control signal GCS to control the operating timing of the scan drive unit 120, based on the timing signal. The timing control unit 160 can output the scan control signal GCS to the scan drive unit 120 and output digital video data DATA and the data control signal DCS to the data drive unit 130.

[0049] The power supply circuit 170 can use the input voltage to generate and supply multiple drive voltages necessary for the operation of all circuit configurations of the light-emitting display device. The power supply circuit 170 can generate and supply a first power supply voltage EVDD (or drive power supply voltage), a second power supply voltage EVSS (or common power supply voltage), and a reference power supply voltage Vref (or reference voltage) to the display panel 110. The power supply circuit 170 can generate and supply various drive voltages necessary for the operation of the scan drive unit 120, the data drive unit 130, and the timing control unit 160.

[0050] The light-emitting display device according to the embodiments of this specification may further include a touch panel TSP including a plurality of touch electrodes TE to provide a touch sensing function, and a touch sensing circuit 200 that supplies a touch drive signal to the touch panel TSP, detects a touch sensing signal from the touch panel TSP, and senses whether or not a user is touching the touch panel TSP or the touch position (or touch coordinates) based on the detected touch sensing signal.

[0051] The touch sensing circuit 200 may include a touch drive circuit 210 that supplies a touch drive signal to the touch panel TSP and detects a touch sensing signal from the touch panel TSP, and a touch control unit 220 that senses whether or not a user is touching the touch panel TSP or the location of the touch based on the touch sensing signal detected by the touch drive circuit 210. The touch drive circuit 210 can supply a touch drive signal to the touch panel TSP and detect a touch sensing signal from the touch panel TSP.

[0052] The touch drive circuit 210 and the touch control unit 220 may be embodied by separate components or integrated into a single component, but the embodiments herein are not limited thereto.

[0053] For example, the scan drive unit (or gate drive unit) 120, the data drive unit 130, and the touch drive circuit 210 are each implemented by one or more integrated circuits and are implemented using COG (Chip On Glass), COF (Chip On Film), COP (chip on plastic), or TCP (Tape Carrier Package) methods in terms of electrical connection with the display panel 110, and the scan drive unit 120 can be implemented using the GIP (gate driver in panel) method.

[0054] For example, each of the circuit configurations 120, 130, and 160 for display driving and the circuit configurations 210 and 220 for touch sensing can be implemented by one or more individual components. For example, one or more of the circuit configurations 120, 130, and 160 for display driving and one or more of the circuit configurations 210 and 220 for touch sensing may be functionally integrated and implemented by one or more components.

[0055] For example, the data drive unit 130 and the touch drive circuit 210 can be implemented by integrating them into one or more integrated circuit chips. When the data drive unit 130 and the touch drive circuit 210 are implemented by integrating them into two or more integrated circuit chips, each of the two or more integrated circuit chips may have both data drive functionality and touch drive functionality.

[0056] The touch panel TSP may include a plurality of touch electrodes TE to which a touch drive signal is applied or a touch sensing signal is detected, and a plurality of touch routing lines connecting the plurality of touch electrodes TE to the touch drive circuit 210.

[0057] The touch panel TSP may be configured outside the display panel 110. In this case, the touch panel TSP and the display panel 110 may be manufactured separately and then combined. Such a touch panel TSP is called an external type or an add-on type. Alternatively, the touch panel TSP may be built into the display panel 110. In this case, when manufacturing the display panel 110, the multiple touch electrodes and multiple touch routing lines that constitute the touch panel TSP may be formed together with the multiple electrodes and signal lines for driving the display of the touch sensor structure.

[0058] The touch panel TSP according to the embodiments of this specification may have a ToE (Touch on Encapsulation) structure formed directly on the upper part of the sealing portion ENC of the display panel 110. For example, the touch panel TSP can be operated by patterning at least one inorganic insulating layer and a touch electrode TE on the upper part of the sealing portion ENC and connecting it to a signal line formed as an electrode for driving the display.

[0059] Referring to Figure 3, in the display area DA of the display panel 110, a plurality of subpixels SP are arranged on the upper part of the substrate 111, and a sealing part ENC may be placed on the upper part of the display panel 110 to prevent external moisture and oxygen from penetrating the circuit elements of the subpixels SP arranged on the display panel 110.

[0060] The touch panel TSP according to the embodiments of this specification may be positioned on top of the sealing portion ENC of the display panel 110. For example, a touch sensor structure such as a plurality of touch electrodes TE that make up the touch panel TSP may be positioned on the sealing portion ENC.

[0061] During touch sensing, a touch drive signal or a touch sensing signal may be applied to the touch electrode TE. Therefore, during touch sensing, the distance between the touch electrode TE and the cathode, which are positioned with the sealing portion ENC in between, may be designed to have a predetermined value considering the thickness of the display panel, the manufacturing process of the display panel, and the display performance. For example, the thickness of the sealing portion ENC may be designed to be at least 1 μm.

[0062] The touch panel TSP according to the embodiments of this specification uses a capacitance-based touch sensing method, and can also sense touch using a mutual-capacitance-based touch sensing method or a self-capacitance-based touch sensing method, but the embodiments of this specification are not limited to these.

[0063] In a touch sensing method based on mutual capacitance, multiple touch electrodes TE can be classified into drive touch electrodes (transmitting touch electrodes) to which a touch drive signal is applied, and sensing touch electrodes (receiving touch electrodes) to which a touch sensing signal is detected and which form a capacitance with the drive touch electrodes. For example, in a touch sensing method based on mutual capacitance, the touch sensing circuit 200 can sense the presence or absence of a touch or touch coordinates based on the change in capacitance (mutual capacitance) between the drive touch electrode and the sensing touch electrode due to the presence or absence of a pointer such as a finger or pen.

[0064] In a self-capacitance-based touch sensing method, each touch electrode TE fulfills both the roles of a driving touch electrode and a sensing touch electrode. That is, the touch sensing circuit 200 applies a touch driving signal to one or more touch electrodes TE, detects a touch sensing signal via the touch electrodes TE to which the touch driving signal is applied, and, based on the detected touch sensing signal, can sense the presence or absence of a touch or the touch coordinates by grasping the change in capacitance between a pointer such as a finger or pen and the touch electrode TE. In a self-capacitance-based touch sensing method, there is no distinction between a driving touch electrode and a sensing touch electrode.

[0065] Figure 4 is a diagram showing area A shown in Figure 2 according to an embodiment of this specification. Figure 5 is a cross-sectional view of the line I-I' shown in Figure 4 according to an embodiment of this specification.

[0066] Referring to Figures 4 and 5, the display panel 110 according to the embodiment of this specification may include a display area DA for displaying images and a non-display area NDA surrounding the display area DA. Multiple dam patterns DAM may be arranged in the non-display area NDA. The non-display area NDA may include a pad area PA and a routing area RA.

[0067] The pad area PA is located at one end of the display panel 110 and may include a plurality of pads PD to which external signals are applied. The plurality of pads PD may not be covered by an insulating layer and may be exposed to the outside and connected to the source film 140. For example, the source film 140 may have a source drive IC of the data drive unit 130 mounted on it, and COF wiring that electrically connects the source drive IC to the plurality of pads PD may be arranged on it. The source film 140 may also have COF wiring that transmits drive control signals and drive power supply voltage supplied from the circuit board 150. The source film 140 is attached to the plurality of pads PD located in the pad area PA using an anisotropic conducting film, and can electrically connect each pad PD to the COF wiring.

[0068] The multiple pads PD may include a power pad PPD to which various drive power supply voltages are applied, a display pad DPD to which various control voltage signals related to display driving are applied, and a touch pad TPD to which various touch driving signals and touch sensing signals related to touch driving are applied. For example, the power pad PPD may include a first power pad to which a first power supply voltage EVDD (or drive power supply voltage) supplied from the power supply circuit 170 is applied, a second power supply pad to which a second power supply voltage EVSS is applied, and a reference power supply pad to which a reference power supply voltage Vref is applied. The display pad DPD may also include a data signal pad to which data signals are applied and a gate drive pad to which a scan control signal for controlling the scan drive unit 120 is applied, but the embodiments described herein are not limited thereto.

[0069] The routing area RA is located between the pad area PA and the display area DA, and may include power supply voltage shorting lines DVSL, RVSL, CVSL, and various signal link lines SLL1, SLL2, TLL.

[0070] The power supply voltage shorting lines DVSL, RVSL, and CVSL are connected to the power supply pad PPD located in the pad area PA and can extend to the display area DA. The power supply voltage shorting lines DVSL, RVSL, and CVSL can extend in a first direction (or X-axis direction) and a second direction (or Y-axis direction), or can extend only in the second direction. For example, the power supply voltage shorting lines DVSL, RVSL, and CVSL may include a first power supply voltage shorting line DVSL, a second power supply voltage shorting line CVSL, and a reference voltage shorting line RVSL. For example, the first power supply voltage shorting line DVSL and the reference voltage shorting line RVSL can extend in the second direction, and the second power supply voltage shorting line CVSL can extend in the second direction and then bend and extend in the first direction, but the embodiments herein are not limited thereto.

[0071] The signal link lines (SLL1, SLL2, TLL) are connected to the display pad DPD and touch pad TPD located in the pad area PA and can extend to the display area DA. The signal link lines SLL1, SLL2, TLL can extend in a first direction, a second direction, or a third direction (or diagonal direction) between the first and second directions.

[0072] The signal link lines SLL1, SSL2, and TLL may include display drive link lines SLL1 and SLL2 connected to the data line DL and scan drive unit 120 located in the display area DA, and a touch drive link line TLL connected to the touch electrode TE and touch line TL located in the display area DA.

[0073] The display drive link lines SLL1 and SLL2 can extend in a third direction toward the right or left depending on their position connected to the pad area PA. For example, the display drive link lines SLL1 and SLL2 may include a gate control link line SLL1 and a data signal link line SLL2. The gate control link line SLL1 can be connected to the left or right side of the pad area PA in a first direction (or the X-axis direction) and can extend to the left or right edge of the display area DA where the scan drive unit 120 is located. The data signal link line SLL2 can be connected to the center of the pad area PA and can extend radially so as to be uniformly distributed across the display area DA.

[0074] The touch drive link line TLL can extend to connect to the touch electrode TE and touch line TL located in the display area DA, and may overlap with the display drive link lines SLL1 and SLL2 in the routing area RA.

[0075] The display drive link lines SLL1 and SLL2 may be arranged in the routing area RA superimposed on the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the display drive link lines SLL1 and SLL2 may be arranged to cross below the power supply voltage shorting lines DVSL, RVSL, and CVSL. Alternatively, the touch drive link line TLL may be arranged to cross above the power supply voltage shorting lines DVSL, RVSL, and CVSL.

[0076] The display panel 110 according to the embodiments herein may include a sealing portion ENC. The sealing portion ENC may be located in a display area DA and configured to cover the entire display area DA. The sealing portion ENC may extend from the display area DA toward the pad area PA. The sealing portion ENC may be located so as not to overlap with the pad area PA, such that a plurality of pads PD located in the pad area PA are exposed to the outside. For example, the sealing portion ENC may be located in the display area DA and the routing area RA.

[0077] The display drive link lines SLL1 and SLL2 in the embodiments of this specification may have one end connected to a display pad DPD and the other end connected to a data line DL located in the display area DA and a scan drive unit 120. The display drive link lines SLL1 and SLL2 may be located in the routing area RA between the pad area PA and the display area DA. In the routing area RA of the non-display area NDA, a touch drive link line TLL may be located superimposed on the display drive link lines SLL1 and SLL2.

[0078] The sealing portion ENC in the embodiments of this specification plays a role in preventing electrical interference and short circuits between the display drive link lines SLL1 and SLL2, which are formed earlier in the thin-film transistor formation process, and the touch drive link line TLL, which is formed in the subsequent ToE (Touch on Encapsulation) process. For example, the touch drive link line TLL may be positioned on top of the sealing portion ENC that covers the display drive link lines SLL1 and SLL2. Alternatively, a touch electrode TE and a touch line TL may be positioned on top of the sealing portion ENC in the display area DA.

[0079] Multiple dam patterns (DAM) may be arranged to surround the display area (DA). Multiple dam patterns (DAM) may be placed in the routing area (RA) between the pad area (PA) and the display area (DA). Multiple dam patterns (DAM) may be superimposed on the power supply voltage shorting lines (DVSL, RVSL, CVSL) and signal link lines (SLL1, SLL2, TLL). Multiple dam patterns (DAM) play a role in blocking the flow of the organic layer (PCL) that constitutes the sealing section (ENC).

[0080] Multiple dam patterns (DAM) may be composed of one or more organic materials. Multiple dam patterns (DAM) may include a first dam pattern (DM1) adjacent to the display area (DA) and composed of multiple organic materials, and a second dam pattern (DM2) adjacent to the pad area (PA) and composed of multiple organic materials. Furthermore, multiple dam patterns (DAM) may include sub-dam patterns (SDM1, SDM2) positioned between the first dam pattern (DM1) and the second dam pattern (DM2) and composed of at least one organic material.

[0081] Referring to Figure 4, the display panel 110 according to the embodiment of this specification may include a substrate 111 having a display area DA and a non-display area NDA, at least one insulating layer disposed on the substrate 111, a power supply voltage shorting line CVSL, at least one thin-film transistor TFT, a light-emitting element ED, a sealing portion ENC, a touch sealing layer (or inorganic insulating layer) S-BF and S-ILD disposed on the sealing portion ENC, and touch sensor arrays (or touch electrode arrays) TE, TL, etc.

[0082] The substrate 111 may include a transparent or opaque plastic film or a glass substrate. For example, the substrate 111 may include at least one thin-film transistor TFT and a light-emitting element ED, and may be an array substrate or a first substrate, but the embodiments herein are not limited thereto.

[0083] At least one insulating layer (buffer layer BF, gate insulating layer GI, first interlayer insulating layer ILD1, second interlayer insulating layer ILD2) may be placed on the substrate 111. For example, a buffer layer BF may be placed on the substrate 111. The buffer layer BF is placed over the entire substrate 111 and is configured to cover the light-shielding single layer LS placed on the substrate 111, and plays a role in blocking foreign matter or moisture from penetrating through the substrate 111.

[0084] A gate insulating layer GI, first and second interlayer insulating layers ILD1 and ILD2, and at least one thin-film transistor TFT may be arranged on the buffer layer BF. For example, at least one insulating layer (buffer layer BF, gate insulating layer GI, first interlayer insulating layer ILD1, second interlayer insulating layer ILD2) may be silicon oxide (SiO2). X ), silicon nitride (SiN X The examples herein may consist of a single or multilayer structure comprising a material and an inorganic insulating material such as aluminum oxide (Al2O3), but the examples herein are not limited thereto.

[0085] In the display region DA, a thin-film transistor TFT may be placed on the buffer layer BF. The thin-film transistor TFT may include an active layer ACT, a gate electrode GE, and source and drain electrodes SD1 and SD2.

[0086] The active layer ACT is located on the buffer layer BF and may contain an oxide semiconductor-based semiconductor material such as IGZO (indium-gallium-zinc-oxide) or a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon, but the examples herein are not limited thereto. The active layer ACT may include a source region, a drain region, and a channel region between the source region and the drain region.

[0087] The gate isolation layer GI may be patterned and formed only on the channel region of the active layer ACT, or it may be placed over the entire buffer layer BF containing the active layer ACT.

[0088] The gate electrode GE is positioned on the gate insulating layer GI so as to overlap with the channel region of the active layer ACT and may be patterned together with the gate insulating layer GI. The gate electrode GE may be made of the same material in the same layer as the scanline SL located in the display region DA. For example, the gate electrode GE may be made of the same material in the same layer as the display drive link lines SLL1 and SLL2 located in the non-display region NDA, but the embodiments herein are not limited thereto. For example, parts of the display drive link lines SLL1 and SLL2 may be made of the same material in the same layer as the gate electrode GE.

[0089] A first interlayer insulating layer ILD1 is disposed on the gate insulating layer GI, which includes the gate electrode GE, and an intermediate metal layer TM may be disposed on the first interlayer insulating layer ILD1. The intermediate metal layer TM may consist of a connecting pattern (or jumper pattern) that connects the gate electrode GE pattern and the source drain electrode SD pattern between the gate electrode GE and the source drain electrode SD, or a part of the electrodes included in the storage capacitor. For example, the intermediate metal layer TM may be made of the same material and in the same layer as the display drive link lines SLL1 and SLL2 located in the non-display area NDA, but the embodiments herein are not limited thereto. For example, a part of the display drive link lines SLL1 and SLL2 may be made of the same material and in the same layer as the intermediate metal layer TM. Alternatively, the display drive link lines SLL1 and SLL2 may consist of a first display drive link line made of the same material and in the same layer as the gate electrode GE, and a second display drive link line made of the same material and in the same layer as the intermediate metal layer TM, superimposed on each other to form a single signal line, but the embodiments herein are not limited thereto.

[0090] In the non-display area NDA, display drive link lines SLL1 and SLL2 may be arranged on the gate insulating layer GI and the first interlayer insulating layer ILD1. For example, the display drive link lines SLL1 and SLL2 may be arranged in the routing area RA between the display area DA and the pad area PA. The display drive link lines SLL1 and SLL2 may include a first display drive line made of the same material as the gate electrode GE on the gate insulating layer GI, and a second display drive link line made of the same material as the intermediate metal layer TM on the first interlayer insulating layer ILD1. The first and second display drive link lines may be arranged alternately or overlapping each other, but the embodiments herein are not limited thereto.

[0091] A second interlayer insulating layer ILD2 is disposed on a first interlayer insulating layer ILD1 which includes an intermediate metal layer TM, and source-drain electrodes SD1 and SD2 may be disposed on the second interlayer insulating layer ILD2. Source-drain electrodes SD1 and SD2 may include a first source-drain electrode SD1 and a second source-drain electrode SD2. For example, the first source-drain electrode SD1 may be electrically connected to a first region (source or drain region) of the active layer ACT. The first source-drain electrode SD1 may also be electrically connected to a light-shielding single layer LS on the substrate 111. The second source-drain electrode SD2 may be electrically connected to a second region (source or drain region) of the active layer ACT. For example, source-drain electrodes SD1 and SD2 may be made of the same material in the same layer as the power supply voltage shorting lines DVSL, RVSL, and CVSL located in the non-display region NDA, but the embodiments herein are not limited thereto. Also, source-drain electrodes SD1 and SD2 may be made of the same material in the same layer as the pad electrodes of a plurality of pads PD located in the pad region PA. For example, the pad electrodes placed in the pad region PA may be made of the same material in the same layer as the source and drain electrodes SD1 and SD2.

[0092] In the non-display area NDA, power supply voltage shorting lines DVSL, RVSL, and CVSL may be located on the second interlayer insulating layer ILD2. For example, the power supply voltage shorting lines DVSL, RVSL, and CVSL may be located in the routing area RA between the display area DA and the pad area PA. The power supply voltage shorting lines DVSL, RVSL, and CVSL may be made of the same material as the source drain electrodes SD1 and SD2 on the second interlayer insulating layer ILD2, but the embodiments herein are not limited thereto.

[0093] In the non-display area NDA, multiple pad electrodes PD may be arranged on the second interlayer insulating layer ILD2. For example, the pad electrodes may be arranged in the pad area PA. The pad electrodes may be made of the same material as the source and drain electrodes SD1 and SD2 on the second interlayer insulating layer ILD2, but the examples herein are not limited to this.

[0094] In the display area DA, a planarization layer PLN may be placed on the second interlayer insulating layer ILD2. The planarization layer PLN flattens steps caused by thin-film transistors TFT, scan lines SL and data lines DL placed on the substrate 111, and may be composed of an organic insulating material. For example, the planarization layer PLN may be composed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but the examples in this specification are not limited to these.

[0095] A light-emitting element ED, composed of a pixel electrode AE, an emissive layer EL, and a common electrode CE, may be arranged on the planarization layer PLN from the display area DA. Furthermore, a bank layer BA configured to define the aperture region (or emissive region) of the pixel electrode AE ​​may be further arranged on the planarization layer PLN. For example, the bank layer BA may be configured to cover the edge of the pixel electrode AE. The bank layer BA may be placed between the pixel electrode AE ​​and the emissive layer EL. On the other hand, a spacer SPC may be further arranged on the bank layer BA. The spacer SPC can maintain a gap between the light-emitting element ED and the sealing portion ENC in the display area DA and support the sealing portion ENC, but the embodiments herein are not limited to this.

[0096] A sealing section ENC may be placed on the light-emitting element ED and the bank layer BA to protect the light-emitting element ED. The sealing section ENC may be placed over the entire display area DA so as to fully cover the light-emitting element ED and may extend to at least a portion of the non-display area NDA. For example, the sealing section ENC may extend to the non-display area NDA excluding the pad area PA and may be placed superimposed on the power supply voltage shorting lines DVSL, RVSL, CVSL and display drive link lines SLL1, SLL2 located in the routing area RA of the non-display area NDA. In the routing area RA, the sealing section ENC may be configured to cover the power supply voltage shorting lines DVSL, RVSL, CVSL and display drive link lines SLL1, SLL2.

[0097] The sealing portion ENC may include a first inorganic layer EPAS1, an organic layer PCL, and a second inorganic layer EPAS2. The first inorganic layer EPAS1 is placed on the common electrode CE of the light-emitting element ED, the organic layer PCL is placed on the first inorganic layer EPAS1, and the second inorganic layer EPAS2 may be placed on the organic layer PCL or the first inorganic layer EPAS1 so as to cover the organic layer PCL.

[0098] The first inorganic layer EPAS1 may be positioned on the substrate 111 on which the common electrode CE is located, so as to be closest to the light-emitting element ED. For example, the first inorganic layer EPAS1 may be silicon nitride (SiNx ), silicon oxide (SiO x ), or inorganic insulating material capable of low-temperature deposition such as silicon oxynitride (SiON) or aluminum oxide (Al2O3), are not limited to the examples herein. Since the first inorganic layer EPAS1 is deposited in a low-temperature atmosphere, damage to the light-emitting element ED containing organic material that is sensitive to high-temperature atmospheres can be prevented during deposition.

[0099] The organic layer PCL is arranged in a smaller area than the first inorganic layer EPAS1, and the organic layer PCL may be configured to expose both ends of the first inorganic layer EPAS1. The organic layer PCL acts as a buffer to relieve stress between layers due to the bending of the light-emitting device and also plays a role in enhancing planarization performance. For example, the organic layer PCL may be composed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC), but the examples herein are not limited to these.

[0100] The second inorganic layer EPAS2 may be arranged to cover the top and side surfaces of the first inorganic layer EPAS1 and the organic layer PCL, respectively. The second inorganic layer EPAS2 plays a role in minimizing or blocking the penetration of external moisture and oxygen into the first inorganic layer EPAS1 and the organic layer PCL. For example, the second inorganic layer EPAS2 may be silicon nitride (SiN x ), silicon oxide (SiO x ), or inorganic insulating materials such as silicon oxynitride (SiON) or aluminum oxide (Al2O3), are also included, but the examples herein are not limited thereto.

[0101] Multiple dam patterns (DAMs) may be arranged in the non-display area (NDA) on the substrate 111. For example, multiple dam patterns (DAMs) may be arranged in the routing area (RA) of the non-display area (NDA). In the routing area (RA), multiple dam patterns (DAMs) play a role in blocking the flow of the organic layer (PCL) of the sealing section (ENC). For example, multiple dam patterns (DAMs) can be arranged to surround the periphery of the display area (DA) and block the flow of the organic layer (PCL) of the sealing section (ENC). Therefore, the organic layer (PCL) of the sealing section (ENC) may be arranged from the display area (DA) to the non-display area (NDA) where the multiple dam patterns (DAMs) are arranged. For example, the organic layer (PCL) may be arranged up to a part of the routing area (RA), and the first and second inorganic layers (EPAS1 and EPAS2) may be arranged to extend to the end of the routing area (RA). For example, the organic layer (PCL) and the first inorganic layer (EPAS1) may be arranged up to a part of the routing area (RA), and only the second inorganic layer (EPAS2) may be arranged to extend to the end of the routing area (RA), but the embodiments of this specification are not limited thereto.

[0102] Multiple dam patterns (DAMs) may be arranged to overlap with power supply voltage shorting lines DVSL, RVSL, CVSL and display drive link lines SLL1, SLL2. For example, at least some of the multiple dam patterns (DAMs) may be placed on the power supply voltage shorting lines DVSL, RVSL, CVSL. Multiple dam patterns (DAMs) and power supply voltage shorting lines DVSL, RVSL, CVSL may be arranged to intersect each other.

[0103] The multiple dam patterns DAM may include a first dam pattern DM1 adjacent to the display area DA and a second dam pattern DM2 adjacent to the pad area PA. Furthermore, the multiple dam patterns DAM may include at least one sub-dam pattern SDM1, SDM2 positioned between the first and second dam patterns DM1, DM2. Meanwhile, the non-display area NDA may further include at least one stopper STP positioned between the display area DA and the first dam pattern DM1. The at least one stopper STP may serve to restrict the flow of the organic layer PCL of the sealing area ENC; the embodiments herein are not limited thereto.

[0104] The first dam pattern DM1 is in contact with the first inorganic layer EPAS1, the organic layer PCL, and the second inorganic layer EPAS2 of the sealing portion ENC, and the second dam pattern DM2 and at least one sub-dam pattern SDM1, SDM2 may be in contact with at least one of the first and second inorganic layers EPAS1, EPAS2 of the sealing portion ENC. For example, the second dam pattern DM2 and at least one sub-dam pattern SDM1, SDM2 may be in contact with the first inorganic layer EPAS1 or the second inorganic layer EPAS2, but the embodiments herein are not limited thereto.

[0105] Multiple dam patterns (DAMs) may consist of at least some of the flattening layer (PLN), bank layer (BA), and spacer (SPC). For example, the first dam pattern (DM1) may consist of the flattening layer (PLN) and spacer (SPC), and the second dam pattern (DM2) may consist of the flattening layer (PLN) and bank layer (BA). In addition, at least one sub-dam pattern (SDM1, SDM2) may consist of the bank layer (BA), but the embodiments described herein are not limited to this.

[0106] A touch sealing layer (or inorganic insulating layer) S-BF, S-ILD may be placed on the sealing portion ENC. For example, the touch sealing layer S-BF, S-ILD may include a touch buffer layer S-BF and a touch insulating layer S-ILD, and the touch buffer layer S-BF may be placed on the sealing portion ENC. The touch buffer layer S-BF may be placed between the touch sensor array (or touch electrode array) TE, TL and the sealing portion ENC. For example, the touch buffer layer S-BF may be omitted, and the touch sensor array TE, TL may be placed directly on the sealing portion ENC, but the embodiments herein are not limited thereto.

[0107] Touch lines TL of the touch sensor array TE,TL may be arranged on the touch buffer layer S-BF. For example, the touch lines TL may have a single-layer or multi-layer structure made of a metal with strong corrosion and acid resistance such as aluminum (Al), titanium (Ti), copper (Cu), or molybdenum (Mo), but the embodiments herein are not limited thereto. The touch lines TL may be configured integrally with touch drive link lines TLL located in the non-display area NDA.

[0108] In the non-display area (NDA), a touch drive link line (TLL) is located on the touch buffer layer (S-BF), and the touch drive link line (TLL) may extend toward the pad area (PA). For example, the touch drive link line (TLL) may coincide with one end of the touch buffer layer (S-BF). For example, the touch buffer layer (S-BF) may coincide with the end of the touch drive link line (TLL) or extend beyond the end of the touch drive link line (TLL).

[0109] The touch line TL and the touch drive link line TLL may be formed together in the ToE (Touch on Encapsulation) process and may be composed of the same material in the same layer.

[0110] A touch insulating layer S-ILD may be placed on the touch line TL and the touch drive link line TLL. For example, an organic or inorganic film that can be formed in a low-temperature process can be used for the touch insulating layer S-ILD. When an organic film is used for the touch insulating layer S-ILD, the touch insulating layer S-ILD can be formed by coating it on the substrate 111 and then curing it at a temperature of 100 degrees Celsius or lower to prevent damage to the light-emitting element ED, which is sensitive to high temperatures. The touch insulating layer S-ILD according to the examples of this specification can be formed using an inorganic film. To prevent damage to the light-emitting element ED, which is sensitive to high temperatures, a multilayer touch insulating layer S-ILD can be formed by repeating the low-temperature chemical vapor deposition (CVD) deposition process and the cleaning process at least twice.

[0111] In the display area DA, a portion of the touch insulating layer S-ILD can be selectively removed to form a contact hole connected to the touch electrode TE, and the touch electrode TE can be placed on the touch insulating layer S-ILD. The touch electrode TE may be electrically connected to the touch line TL via the contact hole formed in the touch insulating layer S-ILD.

[0112] Touch protective films S-PAS and S-PAC may be further arranged on the touch insulating layer S-ILD, which includes the touch electrode TE. For example, the touch protective films S-PAS and S-PAC may include a first touch protective film S-PAS composed of inorganic material and a second touch protective film S-PAC composed of organic material, but the embodiments herein are not limited thereto. For example, the touch protective films S-PAS and S-PAC may be arranged in at least a portion of the area of ​​the non-display area NDA excluding the pad area PA. For example, the touch protective films S-PAS and S-PAC may be arranged in the routing area RA of the non-display area NDA.

[0113] Figure 6 is a diagram showing area B shown in Figure 4 according to one embodiment of this specification. Figure 7 is a cross-sectional view along the line II-II' shown in Figure 6 according to one embodiment of this specification. Figure 8 is a cross-sectional view along the line III-III' shown in Figure 6 according to one embodiment of this specification.

[0114] Referring to Figures 6 to 8, the pad area PA in one embodiment of this specification may include a display drive link line SLL and a display pad DPD.

[0115] The display drive link line SLL may be connected to a data line DL or a scan drive unit 120 located in the display area DA. For example, the display drive link line SLL may be made of the same material and in the same layer as the scan line SL or data line DL, and can extend continuously and integrally from the display area DA to the pad area PA.

[0116] The display drive link line SLL may be configured as a stacked structure of two or more layers, with a layered structure such as data lines DL, scan lines SL, or power supply voltage lines located in the display area DA, or it may be configured to be located in different layers for each area. For example, each display drive link line SLL may be made of the same material in the same layer as the gate electrode GE, or made of the same material in the same layer as the intermediate metal layer TM. For example, as shown in Figure 8, the display drive link line SLL may be made of the same material as the intermediate metal layer TM on the first interlayer insulating layer ILD1. Alternatively, the display drive link line SLL may be made of the same material as the gate electrode GE on the gate insulating layer GI, but the embodiments herein are not limited to this.

[0117] The indicator drive link line SLL may consist of a first indicator drive link line made of the same material as the gate electrode GE and a second indicator drive link line made of the same material as the intermediate metal layer TM, arranged alternately. For example, as shown in Figure 8, each indicator drive link line SLL may include a first indicator drive link line made of the same material as the gate electrode GE on the gate insulating layer GI and a second indicator drive link line made of the same material as the intermediate metal layer TM on the first interlayer insulating layer ILD1, and the first and second indicator drive link lines may superimpose to form a single signal line, but the embodiments herein are not limited thereto.

[0118] The display pad DPD may include a plurality of display pad electrodes DPE electrically connected to each display drive link line SLL, a pad cover portion PDCP covering at least a portion of the plurality of display pad electrodes DPE, an opening pattern DPE_OP formed on the pad cover portion PDCP to expose the other portion of each display pad electrode DPE, and a display connecting pad electrode DPE_CP disposed on the pad cover portion PDCP, superimposed on at least a portion of the display pad electrodes DPE, and electrically connected to the display pad electrodes DPE via the opening pattern DPE_OP.

[0119] Multiple display pad electrodes (DPEs) are configured to correspond to each display drive link line (SLL) and may be formed together in an array process that forms the data lines (DL), scan lines (SL), or pixel circuits of the display area (DA).

[0120] Multiple display pad electrodes (DPEs) may be arranged on a second interlayer insulating layer (ILD2). Each display pad electrode (DPE) may be made of the same material as the source-drain electrode (SD) on the second interlayer insulating layer (ILD2). For example, multiple display pad electrodes (DPEs) may be superimposed on a display drive link line (SLL) with the second interlayer insulating layer (ILD2) in between. Each display pad electrode (DPE) may be electrically connected to the display drive link line (SLL) via a contact hole (CH) that penetrates the second interlayer insulating layer (ILD2).

[0121] The pad cover portion PDCP may be configured to cover at least a portion of the multiple display pad electrodes DPE. The pad cover portion PDCP may be made of an organic insulating material. For example, the pad cover portion PDCP may be made of the same material in the same layer as the planarization layer PLN located in the display area DA. The height of the pad cover portion PDCP may be the same as the height of the planarization layer PLN, or the pad cover portion PDCP may be configured to be lower than the planarization layer PLN. For example, the height of the pad cover portion PDCP may be less than the height of the planarization layer PLN.

[0122] The pad cover portion PDCP may be configured to cover multiple display pad electrodes DPE. For example, the pad cover portion PDCP may extend in a first direction (or the X-axis direction) to cover multiple display pad electrodes DPE.

[0123] The pad cover portion PDCP may include an opening pattern DPE_OP that exposes a portion of each display pad electrode DPE. A portion of the upper surface of each display pad electrode DPE may be exposed through the opening pattern DPE_OP of the pad cover portion PDCP.

[0124] The display linking pad electrode DPE_CP may be placed on the pad cover portion PDCP. The display linking pad electrode DPE_CP may be placed superimposed on each display pad electrode DPE. The display linking pad electrode DPE_CP may be electrically connected to each display pad electrode DPE via the opening pattern DPE_OP of the pad cover portion PDCP.

[0125] According to one embodiment of this specification, touch sealing layers (or inorganic insulating layers) S-BF and S-ILD may be placed on the display drive link line SLL. For example, the touch sealing layers S-BF and S-ILD may be placed on a second interlayer insulating layer ILD2 that covers the display drive link line SLL in the pad area PA. For example, the touch sealing layers S-BF and S-ILD may be placed on the sealing portion ENC in the display area DA and on the second interlayer insulating layer ILD2 in the pad area PA. For example, the sealing portion ENC may extend to the end of the routing area RA in the non-display area NDA, and the touch sealing layers S-BF and S-ILD may be placed on the second interlayer insulating layer ILD2 from the pad area PA where the sealing portion ENC is not placed. At least a portion of the touch sealing layers S-BF and S-ILD may be removed in the pad area PA.

[0126] The touch sealing layers S-BF and S-ILD according to one embodiment of this specification may include an extended pattern portion S-EP configured to overlap at least a portion of the pad cover portion PDCP located on the display pad DPD. For example, the extended pattern portion S-EP may be configured to overlap with the edge of the pad cover portion PDCP.

[0127] The extension pattern section S-EP may be configured to overlap each display drive link line SLL from one side of the touch sealing layer S-BF, S-ILD. For example, the extension pattern section S-EP can extend from one side of the touch sealing layer S-BF, S-ILD to the end of the pad cover section PDCP while overlapping each display drive link line SLL. For example, each extension pattern section S-EP may consist of a finger pattern that overlaps each display drive link line SLL.

[0128] Referring to Figure 8, the extension pattern section S-EP may include a slit pattern SLP formed between adjacent display drive link lines SLL. The slit pattern SLP may be formed by removing the touch sealing layers S-BF and S-ILD between adjacent display drive link lines SLL. For example, the slit pattern SLP may be formed by removing at least a portion of the touch sealing layers S-BF and S-ILD and the second interlayer insulating layer ILD2.

[0129] The extension pattern section S-EP may be positioned on the pad cover section PDCP at a predetermined distance from the display connecting pad electrode DPE_CP. For example, one end of the display connecting pad electrode DPE_CP may be separated from the extension pattern section S-EP on the pad cover section PDCP, and the other end of the display connecting pad electrode DPE_CP may extend toward the pad area PA and be electrically connected to the display pad electrode DPE exposed through the opening pattern DPE_OP of the pad cover section PDCP.

[0130] According to one embodiment of this specification, the extension pattern portion S-EP of the touch sealing layers S-BF and S-ILD has a slit pattern SLP and is configured to extend so as to overlap each display drive link line SLL and overlap with the end of the pad cover portion PDCP. This prevents damage to the inorganic layer covering the display drive link line SLL or the occurrence of crack defects in the ToE (Touch on Encapsulation) process that follows the array process for forming the data line DL, scan line SL, or pixel circuit of the display area DA, and minimizes film lifting of the extension pattern portion S-EP and the pad cover portion PDCP having the slit pattern SLP. Therefore, by improving the moisture permeability reliability of the pad area PA, electrolytic corrosion defects of the display drive link line SLL can be effectively prevented, and the reliability of the light-emitting display device in high temperature / high humidity environments can be improved.

[0131] Figure 9 shows region C shown in Figure 4 according to another embodiment of this specification. Figure 10 is a cross-sectional view of the line IV-IV' shown in Figure 9 according to another embodiment of this specification.

[0132] Referring to Figures 9 and 10, the pad area PA in other embodiments of this specification may include a touch drive link line TLL and a touch pad TPD.

[0133] The touch drive link line TLL may be connected to the touch line TL located in the display area DA. For example, the touch drive link line TLL may be made of the same material and in the same layer as the touch line TL and may extend continuously and integrally from the display area DA to the pad area PA. The touch drive link line TLL may extend from the display area DA to the pad area PA and be connected to the touch pad TPD.

[0134] The touchpad TPD may include a plurality of touchpad electrodes TPE electrically connected to each touch drive link line TLL, a pad cover portion PDCP covering at least a portion of the plurality of touchpad electrodes TPE, an opening pattern TPE_OP formed on the pad cover portion PDCP to expose the other portion of each touchpad electrode TPE, and a touch connecting pad electrode TPE_CP disposed on the pad cover portion PDCP, superimposed on at least a portion of the touchpad electrodes TPE, and electrically connected to the touchpad electrodes TPE via the opening pattern TPE_OP.

[0135] Multiple touchpad electrodes (TPEs) are configured to correspond to each touch drive link line (TLL) and can be formed together in an array process that forms the data lines (DL), scan lines (SL), or pixel circuits of the display area (DA).

[0136] The spacing between multiple touchpad electrodes TPEs may be greater than the spacing between multiple display pad electrodes DPEs. For example, in a display area DA, the number of data lines DL arranged in each subpixel SP may be greater than the number of touch lines TL, so that multiple display pad electrodes DPEs can be arranged relatively more densely than multiple touchpad electrodes TPEs. For example, each touchpad electrode TPE may be arranged at equal intervals, or in the center or periphery of a pad area PA, or locally concentrated, but the embodiments herein are not limited thereto.

[0137] Multiple touchpad electrode TPEs may be arranged on the second interlayer insulating layer ILD2. Each touchpad electrode TPE may be made of the same material as the source-drain electrode SD on the second interlayer insulating layer ILD2.

[0138] The pad cover portion PDCP may be configured to cover at least a portion of the multiple touchpad electrodes TPE. The pad cover portion PDCP may be made of an organic insulating material. For example, the pad cover portion PDCP may be made of the same material in the same layer as the flattening layer PLN located in the display area DA. The height of the pad cover portion PDCP may be the same as the height of the flattening layer PLN, or the pad cover portion PDCP may be configured to be lower than the flattening layer PLN. For example, the height of the pad cover portion PDCP may be less than the height of the flattening layer PLN.

[0139] The pad cover portion PDCP may be configured to cover multiple touchpad electrode TPEs. For example, the pad cover portion PDCP may be configured to extend in a first direction (or the X-axis direction) to cover multiple touchpad electrode TPEs.

[0140] The pad cover portion PDCP may include an opening pattern TPE_OP that exposes a portion of each touchpad electrode TPE. A portion of the upper surface of each touchpad electrode TPE may be exposed through the opening pattern TPE_OP of the pad cover portion PDCP.

[0141] The touch connecting pad electrode TPE_CP may be placed on the pad cover portion PDCP. The touch connecting pad electrode TPE_CP may be placed superimposed on each touch pad electrode TPE. The touch connecting pad electrode TPE_CP may be electrically connected to each touch pad electrode TPE via the opening pattern TPE_OP of the pad cover portion PDCP.

[0142] According to other embodiments of this specification, the touch drive link line TLL may be positioned between the touch buffer layer S-BF and the touch insulating layer S-ILD, which are included in the touch sealing layer S-BF, S-ILD. That is, as shown in Figure 10, the extension pattern section S-EP may include a touch insulating layer S-ILD positioned on the touch drive link line TLL and a touch buffer layer S-BF positioned below the touch drive link line TLL. For example, the touch buffer layer S-BF may be positioned on the second interlayer insulating layer ILD2 in the pad area PA. The touch buffer layer S-BF may be positioned on the sealing section ENC in the display area DA and on the second interlayer insulating layer ILD2 in the pad area PA. For example, the sealing section ENC may extend to the end of the routing area RA in the non-display area NDA, and the touch buffer layer S-BF may be positioned on the second interlayer insulating layer ILD2 from the pad area PA where the sealing section ENC is not positioned.

[0143] A touch insulating layer S-ILD may be placed on the touch drive link line TLL. For example, the touch insulating layer S-ILD may be configured to cover the touch drive link line TLL. For example, the touch insulating layer S-ILD can be an organic or inorganic film that can be formed in a low-temperature process. The touch insulating layer S-ILD is composed of an inorganic insulating material. To prevent damage to the light-emitting element ED, which is sensitive to high temperatures, a multilayer touch insulating layer S-ILD can be formed by repeating a low-temperature CVD deposition process and a cleaning process at least twice. For example, a contact hole can be formed that penetrates between the touch line TL and the touch electrode TE by selectively removing a portion of the touch insulating layer S-ILD in the display area DA.

[0144] The touch buffer layer S-BF, touch drive link line TLL, and touch insulation layer S-ILD according to other embodiments of this specification may extend to overlap at least a portion of the pad cover portion PDCP located on the touchpad TPD. For example, the touch buffer layer S-BF, touch drive link line TLL, and touch insulation layer S-ILD may be configured to overlap with the edge of the pad cover portion PDCP.

[0145] The touch buffer layer S-BF and touch insulating layer S-ILD located at the top and bottom of each touch drive link line TLL may include a slit pattern SLP formed between adjacent touch drive link line TLLs. The slit pattern SLP may be formed by removing the touch buffer layer S-BF and touch insulating layer S-ILD between adjacent touch drive link line TLLs. For example, the slit pattern SLP may be formed by removing at least a portion of the touch buffer layer S-BF, the touch insulating layer S-ILD, and the second interlayer insulating layer ILD2.

[0146] The touch buffer layer S-BF, the touch drive link line TLL, and the touch insulation layer S-ILD may be arranged overlapping the edges of the pad cover portion PDCP placed on the touch pad TPD. At least a portion of the touch insulation layer S-ILD overlapping the pad cover portion PDCP can be removed to form the contact hole TCH.

[0147] The touch linking pad electrode TPE_CP may be positioned on the pad cover portion PDCP. One end of the touch linking pad electrode TPE_CP extends toward the display area DA and is electrically connected to the touch drive link line TLL via a contact hole TCH that penetrates the touch insulating layer S-ILD, and the other end of the touch linking pad electrode TPE_CP may extend toward the pad area PA and be electrically connected to the touch pad electrode TPE exposed through the opening pattern TPE_OP of the pad cover portion PDCP.

[0148] According to other embodiments of this specification, the touch drive link line TLL is configured to be electrically connected to the touch pad electrode TPE via the touch connecting pad electrode TPE_CP on the pad cover portion PDCP, thereby preventing damage or cracking of the inorganic layer placed on the pad area PA during the subsequent ToE (Touch on Encapsulation) process after the array process that forms the data line DL, scan line SL, or pixel circuit of the display area DA, and minimizing film lifting of the pad cover portion PDCP. Therefore, by improving the moisture permeability reliability of the pad area PA, electrolytic corrosion failure of the touch drive link line TLL can be effectively prevented, and the reliability of the light-emitting display device in high temperature / high humidity environments can be improved.

[0149] A display device including a light-emitting display device according to one or more embodiments of this specification can be described as follows.

[0150] A light-emitting display device according to one or more embodiments of this specification includes a substrate including a display area and a pad area; a sealing portion on the substrate extending from the display area toward the pad area; at least one inorganic insulating layer disposed on the sealing portion; pad electrodes disposed in the pad area on the substrate and electrically connected to each of the signal link lines; and a pad cover portion configured to cover at least a portion of the pad electrodes in the pad area, wherein the at least one inorganic insulating layer may include an extended pattern portion configured to overlap the edge of the pad cover portion.

[0151] According to one or more embodiments of this specification, the extended pattern portion can extend from one side of at least one inorganic insulating layer so as to overlap each of the signal link lines.

[0152] According to one or more embodiments of this specification, the extension pattern portion may include a plurality of finger patterns that overlap each of the signal link lines.

[0153] According to one or more embodiments of this specification, the extended pattern portion may have a slit shape between adjacent signal link lines.

[0154] According to one or more embodiments of this specification, the pad electrode includes a plurality of pad electrodes arranged in a first direction on a substrate, and the pad cover portion is configured to extend in the first direction and cover the plurality of pad electrodes, and the pad cover portion may be made of an organic material.

[0155] According to one or more embodiments of this specification, the display further includes a pixel circuit layer having a pixel circuit arranged in a display area on a substrate, a planar layer configured to cover the pixel circuit layer in the display area, and a light-emitting element arranged on the planar layer in the display area and connected to the pixel circuit, wherein the sealing portion may be arranged on the planar layer to cover the light-emitting element.

[0156] According to one or more embodiments of this specification, the pad cover portion may be made of the same material as the planarization layer, and the height of the pad cover portion may be the same as the height of the planarization layer, or the pad cover portion may be configured to be lower than the planarization layer.

[0157] According to one or more embodiments of this specification, the signal link line includes a display drive link line located in the same layer as the gate electrode and gate line of a thin-film transistor included in the pixel circuit, the display drive link line may be connected to a pad electrode and extend into a display area and be electrically connected to data lines located in the display area.

[0158] According to one or more embodiments of this specification, the pixel circuit layer includes an interlayer insulating layer disposed on the gate electrode, the interlayer insulating layer may extend to the pad area of ​​the substrate.

[0159] According to one or more embodiments of this specification, the pad electrode may include a display pad electrode electrically connected to a display drive link line via a contact hole penetrating the interlayer insulating layer.

[0160] According to one or more embodiments of this specification, the pad cover portion may include an opening pattern that covers at least a portion of the display pad electrode and exposes another portion of the display pad electrode.

[0161] According to one or more embodiments of this specification, the present invention further includes a display connecting pad electrode disposed on a pad cover portion, one end of which is separated from the extension pattern portion on the pad cover portion, and the other end of which extends toward the pad area and is electrically connected to a display pad electrode exposed through the opening pattern of the pad cover portion.

[0162] According to one or more embodiments of this specification, at least one inorganic insulating layer includes a touch buffer layer disposed on the sealing portion and a touch insulating layer disposed on the touch buffer layer, and the touch buffer layer and the touch insulating layer may extend so as to overlap the ends of the display drive link line and the pad cover portion.

[0163] According to one or more embodiments of this specification, the indicator drive link line includes a first indicator drive link line and a second indicator drive link line superimposed to form a single signal line, wherein the first indicator drive link line is made of the same material in the same layer as the gate electrode, and the second indicator drive link line is made of the same material in the same layer as the intermediate metal layer located in the interlayer insulating layer.

[0164] According to one or more embodiments of this specification, the display area further includes a touch electrode array disposed on a sealing portion, and the signal link line may include a touch drive link line electrically connected to the touch electrode array.

[0165] According to one or more embodiments of this specification, at least one inorganic insulating layer includes a touch buffer layer disposed on the sealing portion and a touch insulating layer disposed on the touch buffer layer, and the touch electrode array and touch drive link line are disposed between the touch buffer layer and the touch insulating layer, and the touch drive link line may be disposed between the touch buffer layer and the touch insulating layer overlapping with the edge of the pad cover portion.

[0166] According to one or more embodiments of this specification, the extended pattern portion may include a touch insulating layer disposed on the touch drive link line and a touch buffer layer disposed below the touch drive link line.

[0167] According to one or more embodiments of this specification, the pad electrode may include a touchpad electrode electrically connected to a touch drive link line via an opening pattern that penetrates the pad cover portion.

[0168] According to one or more embodiments of this specification, the present invention further includes a touch-connecting pad electrode disposed on a pad cover, one end of which extends toward the display area and is electrically connected to a touch-driving link line via a contact hole penetrating the touch-insulating layer, and the other end of which extends toward the pad area and is electrically connected to a touch-pad electrode exposed through an opening pattern in the pad cover.

[0169] According to one or more embodiments of this specification, the sealing portion can cover the entire display area and extend to the non-display area excluding the pad area.

[0170] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to such embodiments, and can be modified and implemented in various ways without departing from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and not limiting in all respects. The scope of protection of this specification should be interpreted by the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification. [Explanation of Symbols]

[0171] 110 Display Panel 120 Scan drive unit 130 Data Drive Unit 160 Timing Control Unit 170 Power supply circuit 200 Touch Sensing Circuits 210 Touch drive circuit 220 Touch Control Unit

Claims

1. A substrate including a display area and a pad area, A sealing portion extending from the display area toward the pad area on the substrate, At least one inorganic insulating layer disposed on the sealing portion, A pad electrode is arranged in the pad area on the substrate and electrically connected to each of the signal link lines, A pad cover portion configured to cover at least a portion of the pad electrode in the pad region, Includes, The at least one inorganic insulating layer includes an extended pattern portion configured to overlap with the edge of the pad cover portion, Light-emitting display device.

2. The light-emitting display device according to claim 1, wherein the extended pattern portion extends from one side of the at least one inorganic insulating layer so as to overlap with each of the signal link lines.

3. The light-emitting display device according to claim 2, wherein the extended pattern portion includes a plurality of finger patterns that overlap each of the signal link lines.

4. The light-emitting display device according to claim 3, wherein the extended pattern portion has a slit shape between adjacent signal link lines.

5. The pad electrode includes a plurality of pad electrodes arranged in a first direction on the substrate, The pad cover portion is configured to extend in the first direction and cover the plurality of pad electrodes, The aforementioned pad cover portion is made of an organic material. The light-emitting display device according to claim 1.

6. A pixel circuit layer having a pixel circuit is arranged in the display area on the substrate, A planarization layer configured to cover the pixel circuit layer in the display area, A light-emitting element is arranged on the planarization layer in the display area and connected to the pixel circuit, It further includes, The sealing portion is arranged on the planarization layer so as to cover the light-emitting element. The light-emitting display device according to claim 1.

7. The pad cover portion is made of the same material as the planarization layer. The height of the pad cover portion is the same as the height of the flattening layer, or the pad cover portion is lower than the flattening layer. The light-emitting display device according to claim 6.

8. The signal link line includes a display drive link line arranged in the same layer as the gate electrode and gate line of the thin-film transistor included in the pixel circuit. The display drive link line is connected to the pad electrode and extends to the display area and is electrically connected to the data line located in the display area. The light-emitting display device according to claim 6.

9. The pixel circuit layer includes an interlayer insulating layer disposed on the gate electrode, The interlayer insulating layer is arranged to extend to the pad region of the substrate. The light-emitting display device according to claim 8.

10. The light-emitting display device according to claim 9, wherein the pad electrode includes a display pad electrode electrically connected to the display drive link line via a contact hole penetrating the interlayer insulating layer.

11. The pad cover portion covers at least a part of the display pad electrode, The pad cover portion includes an opening pattern that exposes another part of the display pad electrode. The light-emitting display device according to claim 10.

12. The present invention further includes a display connecting pad electrode disposed on the pad cover portion, One end of the display connecting pad electrode is separated from the extension pattern portion on the pad cover portion, The other end of the display connecting pad electrode extends toward the pad area and is electrically connected to the display pad electrode exposed through the opening pattern of the pad cover portion. The light-emitting display device according to claim 11.

13. The at least one inorganic insulating layer is A touch buffer layer disposed on the sealing portion, A touch insulating layer disposed on the touch buffer layer, Includes, The touch buffer layer and the touch insulating layer extend so as to overlap the display drive link line and the end of the pad cover portion. The light-emitting display device according to claim 8.

14. The display drive link line includes a first display drive link line and a second display drive link line superimposed to form a single signal line. The first display drive link line is made of the same material in the same layer as the gate electrode. The second display drive link line is made of the same material in the same layer as the intermediate metal layer arranged in the interlayer insulating layer. The light-emitting display device according to claim 9.

15. The display area further includes a touch electrode array disposed on the sealing portion, The signal link line includes a touch drive link line electrically connected to the touch electrode array. The light-emitting display device according to claim 1.

16. The at least one inorganic insulating layer is A touch buffer layer disposed on the sealing portion, A touch insulating layer disposed on the touch buffer layer, Includes, The touch electrode array and the touch drive link line are arranged between the touch buffer layer and the touch insulating layer. The touch drive link line is positioned between the touch buffer layer and the touch insulating layer, overlapping with the end of the pad cover portion. The light-emitting display device according to claim 15.

17. The light-emitting display device according to claim 16, wherein the extended pattern portion includes the touch insulating layer disposed on the touch drive link line and the touch buffer layer disposed below the touch drive link line.

18. The light-emitting display device according to claim 16, wherein the pad electrode includes a touch pad electrode electrically connected to the touch drive link line via an opening pattern that penetrates the pad cover portion.

19. The aforementioned pad cover portion further includes a touch connecting pad electrode, One end of the touch connecting pad electrode extends toward the display area and is electrically connected to the touch drive link line via a contact hole that penetrates the touch insulating layer. The other end of the touch connecting pad electrode extends toward the pad area and is electrically connected to the touch pad electrode exposed through the opening pattern of the pad cover portion. The light-emitting display device according to claim 18.

20. The light-emitting display device according to claim 1, wherein the sealing portion covers the entire display area and extends to the non-display area excluding the pad area.

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