Light-emitting display device

Abstract

This prevents moisture from penetrating the interior through the bezel area of ​​the display panel. [Solution] A light-emitting display device according to one or more embodiments of this specification includes a substrate including a display area and a non-display area surrounding the display area; at least one insulating layer disposed on the substrate; a power supply voltage shorting line disposed on the at least one insulating layer in the non-display area and supplying a power supply voltage; a plurality of dam patterns disposed in the non-display area, each composed of one or more organic materials, and superimposed on the power supply voltage shorting line; and a cover pattern disposed between the plurality of dam patterns in the non-display area and covering the edge of the power supply voltage shorting line.

Description

Technical Field

[0001] This specification relates to a light-emitting display device.

Background Art

[0002] As the information society develops, the requirements for display devices for displaying images have increased in various forms, and light-emitting display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), micro LED displays (Micro Light Emitting Diode: Micro LED Display), and quantum dot displays (Quantum Dot Display: QD) are being utilized.

[0003] A sealing film is formed on the light-emitting display device to prevent the penetration of moisture and oxygen from the outside. Such a sealing film is composed of at least one inorganic film and at least one organic film, and prevents the penetration of moisture and oxygen into the interior.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the process of forming the sealing film of the light-emitting display device, there is a possibility that the organic film having fluidity may overflow into the bezel region of the display panel. To prevent this, a dam structure for blocking the flow of the organic film is provided in the bezel region of the display panel. However, in the dam structure, the adhesion characteristics of the organic substance may decrease in a high-temperature / high-humidity environment, and a film lifting phenomenon may occur. Therefore, cracks are formed in the sealing film, and moisture penetrates into the interior through this, and the signal voltage line crossing the dam structure is corroded, resulting in an electrolytic corrosion defect problem.

[0005] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting display device capable of preventing moisture from penetrating into the interior through the bezel region of the display panel.

[0006] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting device that can prevent film lifting and cracking defects of the sealing film in the bezel region.

[0007] The problem to be solved by one or more embodiments of this specification is to provide a light-emitting display device that can prevent electrolytic corrosion failure of signal voltage lines located in the bezel region.

[0008] The problem addressed by one or more embodiments of this specification is to provide a light-emitting device with improved reliability in high-temperature / high-humidity environments.

[0009] The problems addressed by one or more embodiments of this specification are not limited to those mentioned above, and other problems not mentioned will be readily apparent to those skilled in the art from the following description. [Means for solving the problem]

[0010] A light-emitting display device according to one or more embodiments of this specification may include a substrate including a display area and a non-display area surrounding the display area; at least one insulating layer disposed on the substrate; a power supply voltage shorting line disposed on at least one insulating layer in the non-display area and supplying a power supply voltage; a plurality of dam patterns disposed in the non-display area, each composed of one or more organic materials and superimposed on the power supply voltage shorting line; and a cover pattern disposed between the plurality of dam patterns in the non-display area and covering the edges of the power supply voltage shorting line.

[0011] Specific details, other than the solutions to the problems mentioned above, are included in the following descriptions and drawings. [Effects of the Invention]

[0012] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device that can prevent moisture from penetrating into the interior through the bezel area of ​​the display panel.

[0013] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device that can prevent film lifting and cracking defects of the sealing film in the bezel region.

[0014] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device that can prevent electrolytic corrosion failure of signal voltage lines arranged in the bezel region.

[0015] According to one or more embodiments of this specification, it is possible to provide a light-emitting display device with improved reliability in high-temperature / high-humidity environments.

[0016] The light-emitting display devices according to one or more embodiments of this specification can prevent film lifting and cracking defects of the sealing film in the bezel area of ​​the display panel, and can prevent moisture from penetrating into the interior through the bezel area. Therefore, it is possible to prevent electrolytic corrosion defects of the signal voltage lines located in the bezel area, improve reliability in high temperature / high humidity environments, optimize the manufacturing process of the light-emitting display device, reduce power consumption and enable low-power operation, extend lifespan, and reduce production energy, thereby contributing to ESG (Environment / Social / Governance).

[0017] The effects described herein are not limited to those mentioned above, and any other effects not mentioned will be readily apparent to those skilled in the art from the following description.

[0018] Since the content of the invention described in the problem to be solved, the means of solving the problem, and the effects does not specify the essential features of the claims, the scope of rights in the claims is not limited to the matters described above. [Brief explanation of the drawing]

[0019] [Figure 1] This figure shows a schematic configuration of a light-emitting display device according to the embodiments described herein. [Figure 2]This is a diagram showing a light-emitting display device according to an embodiment of the present specification. [Figure 3] This is a diagram showing the A region shown in FIG. 2 according to an embodiment of the present specification. [Figure 4] This is a cross-sectional view of the line I-I' shown in FIG. 3 according to an embodiment of the present specification. [Figure 5] This is a diagram showing the B region shown in FIG. 3 according to an embodiment of the present specification. [Figure 6] This is a cross-sectional view of the line II-II' shown in FIG. 5 according to an embodiment of the present specification. [Figure 7] This is a diagram showing the B region shown in FIG. 3 according to an embodiment of the present specification. [Figure 8] This is a cross-sectional view of the line III-III' shown in FIG. 7 according to an embodiment of the present specification. [Figure 9] This is a diagram showing the B region shown in FIG. 3 according to another embodiment of the present specification. [Figure 10] This is a cross-sectional view of the line IV-IV' shown in FIG. 9 according to another embodiment of the present specification. [Figure 11] This is a diagram showing the B region shown in FIG. 3 according to another embodiment of the present specification.

Mode for Carrying Out the Invention

[0020] The advantages, features, and methods for achieving them of the present specification will become apparent by referring to various examples described in detail hereinafter based on the accompanying drawings. However, the present specification is not limited to an example disclosed below, can be embodied in various different forms, the embodiments of the present specification complete the disclosure of the present specification, and are provided to fully inform those having ordinary knowledge in the technical field to which the technical idea of the present specification belongs of the scope of the technical idea. The present specification is only defined by the scope of the claims.

[0021] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings illustrating the embodiments herein are illustrative only, and this specification is not limited to those depicted. The same reference numerals throughout the specification indicate the same components. Furthermore, in the description herein, if it is determined that a specific description of related known technology would unnecessarily obscure the gist of this specification, such detailed description will be omitted.

[0022] When using words such as "includes," "possesses," and "becomes" as used herein, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0023] In interpreting the constituent elements, even if there is no separate explicit mention of the margin of error, it shall be interpreted as including the margin of error.

[0024] When describing the relative positions of two parts, for example, using phrases like "on top of," "above," "below," or "next to," one or more other parts can be located between the two parts, unless "immediately" or "directly" is used.

[0025] When describing temporal relationships, for example, when describing sequential relationships using phrases like "after," "following," "next," or "before," it can include non-continuous events unless "immediately" or "directly" is used.

[0026] The terms "first," "second," etc., are used to describe various components, but these components are not limited to these terms. These terms are used simply to distinguish one component from others. Therefore, the first component mentioned below may also be the second component within the technical concepts of this specification.

[0027] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component.

[0028] Where it is stated that one component is “connected,” “joined,” “attached,” or “attached” to another component, that component may be directly connected, joined, attached, or attached to the other component, but unless otherwise explicitly stated, it should be understood that other components may be interposed between each component that may be indirectly connected, joined, attached, or attached.

[0029] Where it is stated that a component or layer "contacts" or "overlaps" with another component or layer, the component or layer may directly contact or overlap with another component or layer, but unless otherwise explicitly stated, it can be understood that other components may be interposed between each component that may indirectly contact or overlap with it.

[0030] "At least one" should be understood to include all combinations of one or more related components. For example, "at least one of the first, second, and third components" can be said to include not only the first, second, or third component, but also all combinations of two or more components from the first, second, and third components.

[0031] Many of the features of the embodiments described herein can be combined or combined in part or in whole, enabling a variety of technical interdependencies and drives, and each embodiment can be implemented independently of the others or together in a related manner.

[0032] The embodiments of this specification will now be described based on the attached drawings and examples. The scale of the components shown in the drawings is different from the actual scale for the sake of explanation and is not limited to the scale shown in the drawings.

[0033] Figure 1 shows a schematic configuration of a light-emitting display device according to an embodiment of this specification. Figure 2 shows a light-emitting display device according to an embodiment of this specification.

[0034] In the following, the X-axis indicates the direction parallel to the scan line (or gate line), the Y-axis indicates the direction parallel to the data line, and the Z-axis indicates the height direction of the light-emitting display device.

[0035] The light-emitting display devices described herein will primarily be those embodied by organic light-emitting displays, but may also be embodied by liquid crystal displays, quantum dot light-emitting diodes, or electrophoresis displays.

[0036] Referring to Figures 1 and 2, the light-emitting display device according to the embodiment of this specification may include a display panel 110, a scan drive unit 120 (or gate drive unit) built into the display panel 110, a data drive unit 130 connected to the display panel 110, a timing control unit 160 that controls the scan drive unit 120 and the data drive unit 130, and a power supply circuit 170.

[0037] The display panel 110 may include a substrate 111 and a counter substrate 112. The counter substrate 112 may be a sealing substrate. The substrate 111 may include a plastic film or a glass substrate, but the embodiments herein are not limited thereto. For example, the substrate 111 may be made of a semiconductor material such as a silicon wafer. The counter substrate 112 may be a plastic film, a glass substrate, or a sealing film (or protective film).

[0038] The display panel 110 may include a display area DA and a non-display area NDA that surrounds the display area DA and is located in the outer casing. The display panel 110 can display an image by providing pixels P in the display area DA. Each pixel P may include multiple sub-pixels SP. The structure of the sub-pixels SP can be varied in various ways depending on the type of light-emitting device. For example, depending on the structure, the sub-pixels SP may be configured in a top emission, bottom emission, or dual emission manner. A sub-pixel SP means a unit that can emit its own hue, or one in which a specific type of color filter is formed. Depending on the light-emitting characteristics, the sub-pixels SP may have one or more different light-emitting areas. For example, multiple sub-pixels SP may be arranged in a stripe type or a quad type, but the embodiments herein are not limited thereto, and the color type, arrangement type, arrangement order, etc. of the sub-pixels SP can be configured in various forms depending on the light-emitting characteristics, element lifespan, device specifications, etc.

[0039] The display panel 110 may have data lines DL and scan lines SL (or gate lines) connected to the sub-pixels SP. The data lines DL may be positioned to intersect with the scan lines SL. Each sub-pixel SP of the display panel 110 may be connected to one of the data lines DL and one of the scan lines SL. The data lines DL can supply data voltage supplied from the data drive unit 130 to each sub-pixel SP. The scan lines SL can supply scan signals supplied from the scan drive unit 120 to each sub-pixel SP.

[0040] Each sub-pixel SP is turned on (turns to an ON state) in response to a scan signal. When the data voltage of data line DL is supplied to the gate electrode of the drive transistor while in the ON state, the current between the drain and source of the drive transistor causes the light-emitting elements contained in the sub-pixel SP to emit light. The scan drive unit 120 can receive a scan control signal GCS from the timing control unit 160. The scan drive unit 120 can use the scan control signal GCS to supply a scan signal or a light emission control signal to the scan line SL.

[0041] The scan drive unit 120 may be configured in a GIP (gate driver in panel) manner on the non-display area NDA outside one or both sides of the display area DA. Alternatively, the scan drive unit 120 may be manufactured as a drive chip, mounted on a flexible film, and attached to the non-display area NDA outside one or both sides of the display area DA using a TAB (tape automated bonding) method.

[0042] The data drive unit 130 can receive digital video data DATA and data control signal DCS from the timing control unit 160. Using the data control signal DCS, the data drive unit 130 can convert the digital video data DATA into analog positive / negative polarity data voltages and supply them to the data line DL.

[0043] The data drive unit 130 may include a plurality of source drive integrated circuits (source drive ICs). Each source drive IC may be mounted on the source film 140 using a COF (Chip On Film), COP (chip on plastic), FPC (Flexible Printed Circuit), or FFC (Flexible Flat Cable) method. One side of the source film 140 is electrically connected to the display panel 110, and COF wiring for electrically connecting each source drive IC to the display panel 110 may be arranged on the top of the source film 140. The source film 140 is attached to pads provided in the non-display area (NDA) of the display panel 110 using an anisotropic conducting film, so that each source drive IC can be connected to the pads.

[0044] The display panel 110 may include a circuit board 150 for circuit connection between the data drive unit 130 and other devices. The circuit board 150 may consist of at least one, but the embodiments herein are not limited thereto.

[0045] A source film 140 may be attached to the circuit board 150. Multiple circuits embodied by the drive chip may be mounted on the circuit board 150. For example, a timing control unit 160 may be mounted on the circuit board 150. The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

[0046] The timing control unit 160 can receive digital video data DATA and timing signals from the host system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The vertical synchronization signal is a signal that defines one frame period. The horizontal synchronization signal is a signal that defines one horizontal period required to supply data voltage to a pixel of one horizontal line on the display panel 110. The data enable signal is a signal that defines the period during which valid data is input. The dot clock is a signal that repeats at a predetermined short period.

[0047] The timing control unit 160 can generate a data control signal DCS to control the operating timing of the data drive unit 130 and a scan control signal GCS to control the operating timing of the scan drive unit 120, based on the timing signal. The timing control unit 160 can output the scan control signal GCS to the scan drive unit 120 and output digital video data DATA and the data control signal DCS to the data drive unit 130.

[0048] The power supply circuit 170 can use the input voltage to generate and supply multiple drive voltages necessary for the operation of all circuit configurations of the light-emitting display device. The power supply circuit 170 can generate and supply a first power supply voltage EVDD (or drive power supply voltage), a second power supply voltage EVSS (or common power supply voltage), and a reference power supply voltage Vref (or reference voltage) to the display panel 110. The power supply circuit 170 can generate and supply various drive voltages necessary for the operation of the scan drive unit 120, the data drive unit 130, and the timing control unit 160.

[0049] Figure 3 is a diagram showing area A shown in Figure 2 according to an embodiment of this specification. Figure 4 is a cross-sectional view of the line I-I' shown in Figure 3 according to an embodiment of this specification.

[0050] Referring to Figures 3 and 4, the display panel 110 according to the embodiment of this specification may include a display area DA for displaying images and a non-display area NDA surrounding the display area DA. Multiple dam patterns DAM may be arranged in the non-display area NDA. The non-display area NDA may include a pad area PA and a routing area RA.

[0051] The pad area PA is located at one end of the display panel 110 and may include a plurality of pads PD to which external signals are applied. The plurality of pads PD may not be covered by an insulating layer and may be exposed to the outside and connected to the source film 140. For example, the source drive IC of the data drive unit 130 may be mounted on the source film 140, and COF wiring that electrically connects the source drive IC to the plurality of pads PD may be arranged thereon. In addition, COF wiring that transmits drive control signals and drive power supply voltage supplied from the circuit board 150 may be arranged on the source film 140. The source film 140 is attached to the plurality of pads PD located in the pad area PA using an anisotropic conducting film, and can electrically connect each pad PD to the COF wiring.

[0052] Multiple pads PD may include power pads to which various drive power supply voltages are applied, and signal pads to which various control voltage signals are applied. The power pads may be supplied with a first power supply voltage EVDD (or drive power supply voltage), a second power supply voltage EVSS (or common power supply voltage), and a reference power supply voltage Vref (or reference voltage) supplied from the power supply circuit 170. For example, the power pads may include a first power supply pad to which the first power supply voltage EVDD is applied, a second power supply pad to which the second power supply voltage EVSS is applied, and a reference power supply pad to which the reference power supply voltage Vref is applied, but the embodiments herein are not limited thereto. For example, the signal pads may include a data signal pad to which a data signal is applied, and a gate drive pad to which a scan control signal for controlling the scan drive unit 120 is applied. The signal pads may further include a touch drive pad to which touch-related signals for driving a touch sensor are input and output, but the embodiments herein are not limited thereto.

[0053] The routing area RA is located between the pad area PA and the display area DA and may include power supply voltage shorting lines DVSL, RVSL, CVSL and various signal link lines SLL1, SLL2, TLL.

[0054] The power supply voltage shorting lines DVSL, RVSL, and CVSL are connected to power supply pads located in pad area PA and can extend to display area DA. The power supply voltage shorting lines DVSL, RVSL, and CVSL can extend in a first direction (or X-axis direction) and a second direction (or Y-axis direction), or can extend only in the second direction. For example, the power supply voltage shorting lines DVSL, RVSL, and CVSL may include a first power supply voltage shorting line DVSL, a second power supply voltage shorting line CVSL, and a reference voltage shorting line RVSL. For example, the first power supply voltage shorting line DVSL and the reference voltage shorting line RVSL can extend in the second direction, and the second power supply voltage shorting line CVSL can extend in the second direction and then bend and extend in the first direction, but the embodiments herein are not limited thereto.

[0055] The signal link lines SLL1, SLL2, and TLL are connected to signal pads located in the pad area PA and may extend to the display area DA. The signal link lines SLL1, SLL2, and TLL may extend in a first direction, a second direction, or a third direction (or diagonal direction) between the first and second directions. Depending on their position connected to the pad area PA, the signal link lines SLL1, SLL2, and TLL may extend in the third direction toward the right or left. For example, the signal link lines SLL1, SLL2, and TLL may include a gate control signal link line SLL1 and a data signal link line SLL2. The signal link lines SLL1, SLL2, and TLL may further include a touch signal link line TLL, but the embodiments herein are not limited thereto.

[0056] The gate control signal link line SLL1 and the data signal link line SLL2 may extend to different parts of the display area DA and do not necessarily overlap with each other in the routing area RA. For example, the gate control signal link line SLL1 may be connected to a scan drive unit 120 located on the left or right edge of the display area DA, and the data signal link line SLL2 may be connected to a data line DL located in the display area DA, but the embodiments herein are not limited thereto. The touch signal link line TLL may also extend to be connected to a touch sensor located in the display area DA and may overlap with the gate control signal link line SLL1 and the data signal link line SLL2 in the routing area RA, but the embodiments herein are not limited thereto.

[0057] The signal link lines SLL1, SLL2, and TLL may be arranged in the routing area RA so as to overlap the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the signal link lines SLL1, SLL2, and TLL may be arranged to cross below or above the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the gate control signal link line SLL1 and the data signal link line SLL2 can cross below the power supply voltage shorting lines DVSL, RVSL, and CVSL, and the touch signal link line TLL can cross above the power supply voltage shorting lines DVSL, RVSL, and CVSL, but the embodiments herein are not limited thereto. Thus, the gate control signal link line SLL1 and the data signal link line SLL2 may be arranged between the substrate 111 and the power supply voltage shorting lines DVSL, RVSL, and CVSL.

[0058] Multiple dam patterns (DAM) may be arranged to surround the display area (DA). Multiple dam patterns (DAM) may be placed in the routing area (RA) between the pad area (PA) and the display area (DA). Multiple dam patterns (DAM) may be superimposed on the power supply voltage shorting lines (DVSL, RVSL, CVSL) and the signal link lines (SLL1, SLL2, TLL). Multiple dam patterns (DAM) can serve to block the flow of the organic layer PCL that constitutes the sealing sections (EPAS1, PCL, EPAS2).

[0059] Multiple dam patterns (DAMs) may be arranged to intersect the power supply voltage shorting lines (DVSL, RVSL, CVSL) on a plane, as shown in Figure 3. For example, the multiple dam patterns (DAMs) may extend in a first direction (or along the X-axis), while the power supply voltage shorting lines (DVSL, RVSL, CVSL) may extend in a second direction (or along the Y-axis).

[0060] Multiple dam patterns (DAM) may be composed of one or more organic materials. Multiple dam patterns (DAM) may include a first dam pattern (DM1) adjacent to the display area (DA) and composed of multiple organic materials, and a second dam pattern (DM2) adjacent to the pad area (PA) and composed of multiple organic materials. Furthermore, multiple dam patterns (DAM) may include sub-dam patterns (SDM1, SDM2) positioned between the first dam pattern (DM1) and the second dam pattern (DM2) and composed of at least one organic material.

[0061] Referring to Figure 4, the display panel 110 according to the embodiment of this specification may include a substrate 111 having a display area DA and a non-display area NDA, at least one insulating layer disposed on the substrate 111, power supply voltage shorting lines DVSL, RVSL, CVSL, at least one thin-film transistor TFT, a light-emitting element ED, and sealing portions EPAS1, PCL, EPAS2.

[0062] The substrate 111 may include a transparent or opaque plastic film or a glass substrate. For example, the substrate 111 may include at least one thin-film transistor TFT and a light-emitting element ED, and may be an array substrate or a first substrate, but the embodiments herein are not limited thereto.

[0063] At least one insulating layer BF, GI, ILD1, and ILD2 may be placed on the substrate 111. For example, a buffer layer BF may be placed on the substrate 111. The buffer layer BF is placed over the entire substrate 111 and is configured to cover the light-blocking layer LS placed on the substrate 111, and can block foreign matter or moisture from penetrating through the substrate 111. Part of at least one insulating layer BF, GI, ILD1, and ILD2 may be placed on a part of the thin-film transistor TFT.

[0064] A gate insulating layer GI, first and second interlayer insulating layers ILD1 and ILD2, and at least one thin-film transistor TFT may be arranged on the buffer layer BF. For example, at least one insulating layer BF, GI, ILD1, and ILD2 may be silicon oxide (SiO2). X ), silicon nitride (SiN X The examples herein may consist of a single or multilayer structure comprising a material and an inorganic insulating material such as aluminum oxide (Al2O3), but the examples herein are not limited thereto.

[0065] In the display area DA, a thin-film transistor TFT may be placed on the buffer layer BF. The thin-film transistor TFT may include an active layer ACT, a gate electrode GE, and source and drain electrodes SD1 and SD2.

[0066] The active layer ACT is located on the buffer layer BF and may contain an oxide semiconductor-based semiconductor material such as IGZO (indium-gallium-zinc-oxide) or a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon, but the examples herein are not limited thereto. The active layer ACT may include a source region, a drain region, and a channel region between the source region and the drain region.

[0067] The gate isolation layer GI may be patterned and formed only on the channel region of the active layer ACT, or it may be placed over the entire buffer layer BF containing the active layer ACT.

[0068] The gate electrode GE is positioned on the gate insulating layer GI so as to overlap the channel region of the active layer ACT, and may be patterned together with the gate insulating layer GI. The gate electrode GE may be made of the same material on the same layer as the scanline SL located in the display region DA. For example, the gate electrode GE may be made of the same material on the same layer as the signal link line SLL located in the non-display region NDA, but the embodiments herein are not limited thereto.

[0069] A first interlayer insulating layer ILD1 is disposed on the gate insulating layer GI, which includes the gate electrode GE, and an intermediate metal layer TM may be disposed on the first interlayer insulating layer ILD. The intermediate metal layer TM may consist of a connecting pattern (or jumper pattern) that links the gate electrode GE pattern and the source drain electrode SD pattern between the gate electrode GE and the source drain electrode SD, or a part of the electrodes included in the storage capacitor. For example, the intermediate metal layer TM may consist of the same material and layer as the signal link line SLL located in the non-display region NDA, but the embodiments herein are not limited thereto.

[0070] Multiple signal link lines SLL may be arranged on the gate insulating layer GI and the first interlayer insulating layer ILD1 in the non-display area NDA. For example, the multiple signal link lines SLL may be arranged in the routing area RA between the display area DA and the pad area PA. The multiple signal link lines SLL may include a first signal link line on the gate insulating layer GI made of the same material as the gate electrode GE, and a second signal link line on the first interlayer insulating layer ILD1 made of the same material as the intermediate metal layer TM. The first and second signal link lines may be arranged alternately or overlapping each other, but the embodiments herein are not limited thereto.

[0071] A second interlayer insulating layer ILD2 is disposed on the first interlayer insulating layer ILD1, which includes an intermediate metal layer TM, and source-drain electrodes SD1 and SD2 may be disposed on the second interlayer insulating layer ILD2. The source-drain electrodes SD1 and SD2 may include a first source-drain electrode SD1 and a second source-drain electrode SD2. For example, the first source-drain electrode SD1 may be electrically connected to a first region (source or drain region) of the active layer ACT. The first source-drain electrode SD1 may also be electrically connected to a light-blocking layer LS on the substrate 111. The second source-drain electrode SD2 may be electrically connected to a second region (source or drain region) of the active layer ACT. For example, the source-drain electrodes SD1 and SD2 may be made of the same material on the same layer as the power supply voltage shorting lines DVSL, RVSL, and CVSL located in the non-display region NDA, but the embodiments herein are not limited thereto.

[0072] In the non-display area NDA, power supply voltage shorting lines DVSL, RVSL, and CVSL may be located on the second interlayer insulating layer ILD2. For example, the power supply voltage shorting lines DVSL, RVSL, and CVSL may be located in the routing area RA between the display area DA and the pad area PA. The power supply voltage shorting lines DVSL, RVSL, and CVSL may be made of the same material as the source drain electrodes SD1 and SD2 on the second interlayer insulating layer ILD2, but the embodiments herein are not limited thereto.

[0073] In the display area DA, a planarization layer PLN may be placed on the second interlayer insulating layer ILD2. The planarization layer PLN flattens steps caused by thin-film transistors TFT, scan lines SL and data lines DL, etc., placed on the substrate 111. The planarization layer PLN may be composed of an organic insulating material. For example, the planarization layer PLN may be composed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but the examples in this specification are not limited to these.

[0074] A light-emitting element ED, composed of a pixel electrode AE, an emissive layer EL, and a common electrode CE, may be arranged on the planarization layer PLN from the display area DA. Furthermore, a bank layer BA configured to define the aperture region (or emissive region) of the pixel electrode AE ​​may be further arranged on the planarization layer PLN. For example, the bank layer BA may be configured to cover the edge of the pixel electrode AE. The bank layer BA may be placed between the pixel electrode AE ​​and the emissive layer EL. On the other hand, a spacer SPC may be further arranged on the bank layer BA. The spacer SPC can maintain a gap between the light-emitting element ED and the sealing portions EPAS1, PCL, and EPAS2 in the display area DA and support the sealing portions EPAS1, PCL, and EPAS2, but the embodiments herein are not limited thereto.

[0075] Sealing portions EPAS1, PCL, and EPAS2 may be arranged on the light-emitting element ED and the bank layer BA to protect the light-emitting element ED. The sealing portions EPAS1, PCL, and EPAS2 may include a first inorganic layer EPAS1, an organic layer PCL, and a second inorganic layer EPAS2. The first inorganic layer EPAS1 may be arranged on the common electrode CE of the light-emitting element ED, the organic layer PCL may be arranged on the first inorganic layer EPAS1, and the second inorganic layer EPAS2 may be arranged on the organic layer PCL or the first inorganic layer EPAS1 so as to cover the organic layer PCL.

[0076] The sealing sections EPAS1, PCL, and EPAS2 are arranged across the entire display area DA so as to fully cover the light-emitting element ED, and may extend to at least a portion of the non-display area NDA. For example, the sealing sections EPAS1, PCL, and EPAS2 may extend to the non-display area NDA excluding the pad area PA, and may be arranged to overlap with the power supply voltage shorting lines DVSL, RVSL, and CVSL located in the routing area RA of the non-display area NDA. In the routing area RA, the sealing sections EPAS1, PCL, and EPAS2 may be configured to cover the power supply voltage shorting lines DVSL, RVSL, and CVSL.

[0077] Multiple dam patterns (DAMs) may be arranged in the non-display area (NDA) on the substrate 111. For example, multiple dam patterns (DAMs) may be arranged in the routing area (RA) of the non-display area (NDA). In the routing area (RA), multiple dam patterns (DAMs) can block the flow of the organic layer PCL of the sealing sections EPAS1, PCL, and EPAS2. For example, multiple dam patterns (DAMs) can be arranged to surround the periphery of the display area (DA) and block the flow of the organic layer PCL of the sealing sections EPAS1, PCL, and EPAS2. Therefore, the organic layer PCL of the sealing sections EPAS1, PCL, and EPAS2 may be arranged from the display area (DA) to the non-display area (NDA) where multiple dam patterns (DAMs) are arranged. For example, the organic layer PCL may be arranged up to a part of the routing area (RA), and the first and second inorganic layers EPAS1 and EPAS2 may be arranged to extend to the end of the routing area (RA). For example, the organic layer PCL and the first inorganic layer EPAS1 may be arranged to extend to a portion of the routing region RA, and only the second inorganic layer EPAS2 may extend to the end of the routing region RA, but the examples herein are not limited thereto.

[0078] Multiple dam patterns (DAMs) may be arranged to overlap with power supply voltage shorting lines (DVSL, RVSL, CVSL). For example, at least some of the multiple dam patterns (DAMs) may be placed on the power supply voltage shorting lines (DVSL, RVSL, CVSL). Multiple dam patterns (DAMs) and power supply voltage shorting lines (DVSL, RVSL, CVSL) may be arranged to intersect each other on a plane.

[0079] Multiple dam patterns (DAMs) may include a first dam pattern (DM1) adjacent to a display area (DA) and a second dam pattern (DM2) adjacent to a pad area (PA). For example, the first dam pattern (DM1) may be closer to the display area (DA) than the second dam pattern (DM2), and the second dam pattern (DM2) may be closer to the pad area (PA) than the first dam pattern (DM1). Furthermore, multiple dam patterns (DAMs) may include at least one sub-dam pattern (SDM1, SDM2) positioned between the first and second dam patterns (DM1, DM2). The at least one sub-dam pattern (SDM1, SDM2) may include a first sub-dam pattern (SDM1) adjacent to the first dam pattern (DM1) and a second sub-dam pattern (SDM2) adjacent to the second dam pattern (DM2), but the embodiments herein are not limited thereto. For example, the first sub-dam pattern (SDM1) may be positioned closer to the first dam pattern (DM1) than the second sub-dam pattern (SDM2), and the second sub-dam pattern (SDM2) may be positioned closer to the second dam pattern (DM2) than the first sub-dam pattern (SDM1). On the other hand, the non-display area NDA may further include at least one stopper STP positioned between the display area DA and the first dam pattern DM1. The at least one stopper STP can serve to block the flow of the organic layer PCL of the sealing portions EPAS1, PCL, and EPAS2, but the embodiments herein are not limited thereto.

[0080] The first dam pattern DM1 is in contact with the first inorganic layer EPAS1, the organic layer PCL, and the second inorganic layer EPAS2 of the sealing portion EPAS1, PCL, and EPAS2, and the second dam pattern DM2 and at least one sub-dam pattern SDM1, SDM2 can be in contact with at least one of the first and second inorganic layers EPAS1, EPAS2 of the sealing portion EPAS1, PCL, and EPAS2. For example, the second dam pattern DM2 and at least one sub-dam pattern SDM1, SDM2 can be in contact with the first inorganic layer EPAS1 or the second inorganic layer EPAS2, but the embodiments herein are not limited thereto.

[0081] Multiple dam patterns (DAMs) may consist of at least some of the flattening layer (PLN), bank layer (BA), and spacer (SPC). For example, the first dam pattern (DM1) may consist of the flattening layer (PLN) and spacer (SPC), and the second dam pattern (DM2) may consist of the flattening layer (PLN) and bank layer (BA). In addition, at least one sub-dam pattern (SDM1, SDM2) may consist of the bank layer (BA), but the embodiments described herein are not limited to this.

[0082] Figure 5 is a diagram showing area B shown in Figure 3 according to the embodiments of this specification. Figure 6 is a cross-sectional view along the line II-II' shown in Figure 5 according to the embodiments of this specification.

[0083] Referring to Figures 5 and 6, the non-display area (NDA) according to the embodiments herein may include multiple dam patterns (DAM) and power supply voltage shorting lines (DVSL, RVSL, CVSL).

[0084] The power supply voltage shorting lines DVSL, RVSL, and CVSL may be located on the second interlayer insulation layer ILD2 in the non-display area (NDA). The power supply voltage shorting lines DVSL, RVSL, and CVSL may extend in a second direction (or the Y-axis direction). The power supply voltage shorting lines DVSL, RVSL, and CVSL may include a first power supply voltage shorting line DVSL, a second power supply voltage shorting line CVSL, and a reference power supply voltage shorting line RVSL. For example, as shown in Figure 5, the first power supply voltage shorting line DVSL may be located adjacent to the reference power supply voltage shorting line RVSL. The first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL may be located at a predetermined distance from each other. The first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL may be located parallel to each other in a second direction.

[0085] Multiple signal link lines SLL extending from the pad area PA may be arranged to cross the power supply voltage shorting lines DVSL, RVSL, and CVSL. The multiple signal link lines SLL may include first signal link lines made of the same material as the gate electrode GE on the gate insulating layer GI, and second signal link lines made of the same material as the intermediate metal layer TM on the first interlayer insulating layer ILD1. The first and second signal link lines may be arranged alternately with each other or overlapping each other.

[0086] Each power supply voltage shorting line (DVSL, RVSL, CVSL) may include multiple fine protrusion patterns (HP) having a hammer shape to ensure excellent electrical characteristics. For example, each power supply voltage shorting line (DVSL, RVSL, CVSL) can increase the length and area of ​​its edge by having multiple fine protrusion patterns (HP) formed on its edge. Thus, each power supply voltage shorting line (DVSL, RVSL, CVSL) can reduce electrical resistance and improve heat dissipation efficiency. According to one embodiment, the hammer shape may include a handle portion and a head portion located at one end of the handle portion, the head portion may have a wider width than the handle portion.

[0087] Multiple dam patterns (DAMs) may be arranged to intersect with power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, as shown in Figure 5, multiple dam patterns (DAMs) may be arranged to intersect with the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL. Multiple dam patterns (DAMs) may be arranged on the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL. For example, multiple dam patterns (DAMs) may be arranged on at least a portion of the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL.

[0088] Multiple dam patterns (DAM) may include a first dam pattern (DM1) adjacent to a display area (DA) and a second dam pattern (DM2) adjacent to a pad area (PA), and may include at least one sub-dam pattern (SDM1, SDM2) positioned between the first and second dam patterns (DM1, DM2).

[0089] The at least one subdam pattern SDM1, SDM2 in the embodiments herein may be composed of a single organic material and placed directly on the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL. For example, the at least one subdam pattern SDM1, SDM2 may be composed of the same material as the bank layer BA.

[0090] The bank layer BA and at least one subdam pattern SDM1, SDM2 may experience a decrease in adhesive properties in high-temperature / high-humidity environments. Consequently, at least one subdam pattern SDM1, SDM2 in contact with the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL may separate from the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL, potentially causing film lifting.

[0091] Such film lifting phenomena can cause cracks (or seams) to form in the inorganic layers EPAS1 and EPAS2 of the sealing portion covering at least one subdam pattern SDM1 and SDM2. These cracks create moisture permeability pathways that allow moisture from the external environment to penetrate the interior, and the penetrating moisture can corrode the power supply voltage shorting lines DVSL, RVSL, and CVSL, causing electrolytic corrosion failures. For example, electrolytic corrosion failures mainly occur in the first power supply voltage shorting line DVSL, which supplies a high potential voltage, thus reducing the reliability of the light-emitting device.

[0092] Therefore, through various studies and experiments, the inventors of this specification have invented a light-emitting display device having a robust bezel structure that can prevent film lifting and cracking defects of the sealing film even in high-temperature / high-humidity environments.

[0093] In the following, with reference to Figures 7 to 11, one or more embodiments of this specification of light-emitting devices having a robust bezel structure will be described in more detail.

[0094] Figure 7 is a diagram showing area B shown in Figure 3 according to one embodiment of this specification. Figure 8 is a cross-sectional view along the line III-III' shown in Figure 7 according to one embodiment of this specification.

[0095] Referring to Figures 7 and 8, in one embodiment of this specification, the non-display area (NDA) may contain multiple dam patterns (DAM), power supply voltage shorting lines (DVSL, RVSL, CVSL), and cover patterns (CP).

[0096] A cover pattern CP according to one embodiment of this specification may be positioned between a plurality of dam patterns DAM. For example, the plurality of dam patterns DAM may include a first dam pattern DM1 and a second dam pattern DM2, and the cover pattern CP may be positioned between the first and second dam patterns DM1 and DM2. For example, the first dam pattern DM1 may be positioned away from the first side of the cover pattern CP, and the second dam pattern DM2 may be positioned away from the second side of the cover pattern CP, with the cover pattern CP positioned between the first dam pattern DM1 and the second dam pattern DM2. The plurality of dam patterns DAM may include at least one sub-dam pattern SDM1, SDM2 positioned between the first and second dam patterns DM1 and DM2. The at least one sub-dam pattern SDM1, SDM2 may include a first sub-dam pattern SDM1 adjacent to the first dam pattern DM1 and a second sub-dam pattern SDM2 adjacent to the second dam pattern DM2. The cover pattern CP may be positioned to overlap the first and second sub-dam patterns SDM1 and SDM2 between the first and second dam patterns DM1 and DM2. For example, the cover pattern CP may be positioned between the power supply voltage shorting lines DVSL, RVSL, CVSL and at least one of the first and second sub-dam patterns SDM1 and SDM2.

[0097] The cover pattern CP may be composed of a material that is at least partially different from that of the multiple dam patterns DAM. For example, the cover pattern CP may be composed of a different organic material from that of the first and second sub-dam patterns SDM1 and SDM2. The cover pattern CP may be composed of the same material as the planarization layer PLN. For example, the cover pattern CP may include a material that has better adhesion to the power supply voltage shorting lines DVSL, RVSL, and CVSL than that of the first and second sub-dam patterns SDM1 and SDM2.

[0098] The cover pattern CP may be positioned on the second interlayer insulating layer ILD2 so as to cover at least a portion of the first power supply voltage shorting line DVSL. The cover pattern CP may be configured to cover at least a portion of the fine protrusion pattern HP of the first power supply voltage shorting line DVSL. In one embodiment, the cover pattern CP can be in direct contact with at least a portion of the first power supply voltage shorting line DVSL. The first and second subdam patterns SDM1 and SDM2 are positioned on the cover pattern CP, and the cover pattern CP may be positioned between the first and second subdam patterns SDM1 and SDM2 and the first power supply voltage shorting line DVSL. At least a portion of the sealing layer may be superimposed on the cover pattern CP and at least a portion of the first and second subdam patterns SDM1 and SDM2.

[0099] The cover pattern CP may be an island-shaped pattern that covers one side edge of the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the cover pattern CP may be an island-shaped pattern that covers one side edge of the first power supply voltage shorting line DVSL. For example, the cover pattern CP may be positioned on the left side edge of the first power supply voltage shorting line DVSL in the first direction (or X-axis direction). Alternatively, the cover pattern CP may be positioned on the right side edge of the first power supply voltage shorting line DVSL in the first direction.

[0100] The island-like pattern of the cover pattern CP may be formed in a polygonal shape having a first width W1 and a second width W2. For example, the cover pattern CP may cover the fine protrusion pattern HP of the first power supply voltage shorting line DVSL and have a first width W1 extending in a first direction (or the X-axis direction), and a second width W2 extending in a second direction (or the Y-axis direction) between the first and second dam patterns DM1 and DM2. The first width W1 of the cover pattern CP may be the same as the second width W2, or it may be greater than the second width W2. For example, the first width W1 of the cover pattern CP may be configured to be greater than the second width W2.

[0101] The second width W2 of the cover pattern CP may be a width that is separated from the first and second dam patterns DM1 and DM2 by a first interval d1. For example, the first interval d1 may be the interval corresponding to two of the multiple micro-protrusion patterns HP. For example, the second width W2 of the cover pattern CP may be a width that has a first interval d1 from the first dam pattern DM1 and a first interval d1 from the second dam pattern DM2 between the first and second dam patterns DM1 and DM2.

[0102] According to one embodiment of this specification, the cover pattern CP covers the edge of the first power supply voltage shorting line DVSL and is composed of a planarization layer PLN which has relatively better adhesive properties than the first and second subdam patterns SDM1 and SDM2. This minimizes film lifting of the first and second subdam patterns SDM1 and SDM2 and crack defects in the inorganic layers EPAS1 and EPAS2, and reduces or minimizes the moisture permeability path at the edge of the first power supply voltage shorting line DVSL between the first and second dam patterns DM1 and DM2. Thus, the moisture permeability reliability of the multiple dam patterns DAM can be improved, electrolytic corrosion defects of the first power supply voltage shorting line DVSL can be effectively prevented, and a light-emitting display device with improved reliability in high temperature / high humidity environments can be realized.

[0103] Figure 9 shows area B shown in Figure 3 according to another embodiment of this specification. Figure 10 is a cross-sectional view of the line IV-IV' shown in Figure 9 according to another embodiment of this specification.

[0104] Referring to Figures 9 and 10, the non-display area (NDA) according to other embodiments of this specification may include multiple dam patterns (DAM), power supply voltage shorting lines (DVSL, RVSL, CVSL), and cover patterns (CP).

[0105] Cover patterns CP in other embodiments of this specification may be positioned between multiple dam patterns DAM. For example, cover pattern CP may be positioned between first and second dam patterns DM1 and DM2. Multiple dam patterns DAM may include at least one sub-dam pattern SDM positioned between first and second dam patterns DM1 and DM2. Cover pattern CP does not have to overlap with at least one sub-dam pattern SDM.

[0106] In other embodiments of this specification, at least one sub-dam pattern SDM may be configured in a closed-loop shape between the first and second dam patterns DM1 and DM2. For example, at least one sub-dam pattern SDM may be located in the portion excluding the first power supply voltage shorting line DVSL.

[0107] At least one subdam pattern SDM may be positioned at a second spacing d2 from the edge of the reference power supply voltage shorting line RVSL adjacent to the first power supply voltage shorting line DVSL. For example, at least one subdam pattern SDM may be made of the same material as the bank layer BA.

[0108] According to other embodiments of this specification, the cover pattern CP covers the edge of the first power supply voltage shorting line DVSL and is composed of a planarization layer PLN which has relatively better adhesive properties than the first and second subdam patterns SDM1 and SDM2, thereby minimizing film lifting of the cover pattern CP and crack defects in the inorganic layers EPAS1 and EPAS2. Furthermore, since at least one subdam pattern SDM, which has relatively lower adhesive properties than the cover pattern CP, is not placed on the edge of the moisture-sensitive reference power supply voltage shorting line RVSL, film lifting of at least one subdam pattern SDM and crack defects in the inorganic layers EPAS1 and EPAS2 can be minimized, and the moisture permeability path at the edge of the reference power supply voltage shorting line RVSL can be reduced or minimized. Thus, the moisture permeability reliability of the multiple dam patterns DAM can be improved, and electrolytic corrosion defects of the first power supply voltage shorting line DVSL and the reference power supply voltage shorting line RVSL can be effectively prevented, thereby realizing a light-emitting display device with improved reliability in high-temperature / high-humidity environments.

[0109] Figure 11 shows area B shown in Figure 3 according to another embodiment of this specification.

[0110] Referring to Figure 11, the non-display area (NDA) in other embodiments of this specification may include multiple dam patterns (DAM), power supply voltage shorting lines (DVSL, RVSL, CVSL), and cover patterns (CP).

[0111] Cover patterns CP according to other embodiments of this specification may be positioned between multiple dam patterns DAM. For example, cover pattern CP may be positioned between first and second dam patterns DM1 and DM2.

[0112] The cover pattern CP may be configured to cover one and the other edge of the power supply voltage shorting lines DVSL, RVSL, and CVSL in a first direction (or the X-axis direction). For example, the cover pattern CP may be configured in a closed-loop shape. The cover pattern CP may include a first cover pattern CP1 superimposed on a first subdam pattern SDM1, a second cover pattern CP2 superimposed on a second subdam pattern SDM2, and a third cover pattern CP3 superimposed on one and the other edge of the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the first to third cover patterns CP1, CP2, and CP3 may be configured to cover one and the other edge of the power supply voltage shorting lines DVSL, RVSL, and CVSL.

[0113] The first cover pattern CP1 extends in a first direction so as to overlap with the first subdam pattern SDM1, the second cover pattern CP2 extends in a first direction so as to overlap with the second subdam pattern SDM2, and the third cover pattern CP3 may extend in a second direction so as to overlap with the edges of the power supply voltage shorting lines DVSL, RVSL, and CVSL, and be connected to the first and second cover patterns CP1 and CP2.

[0114] Cover patterns CP in other embodiments of this specification may further include sub-cover patterns SCP protruding from the first and second dam patterns DM1 and DM2, respectively.

[0115] The sub-cover pattern SCP may be formed to project in a second direction from a portion of the first dam pattern DM1 that intersects with the edges of the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the sub-cover pattern SCP may be configured to be spaced apart from the first cover pattern CP1 at a predetermined distance. For example, the sub-cover pattern SCP connected to the first dam pattern DM1 may be configured to project downward in a second direction.

[0116] The sub-cover pattern SCP may be formed to project in a second direction from a portion of the second dam pattern DM2 that intersects with the edges of the power supply voltage shorting lines DVSL, RVSL, and CVSL. For example, the sub-cover pattern SCP may be configured to be spaced apart from the second cover pattern CP2 at a predetermined distance. For example, the sub-cover pattern SCP connected to the second dam pattern DM2 may be configured to project upward and downward in the second direction, respectively.

[0117] According to other embodiments of this specification, the cover pattern CP covers the edges of the power supply voltage shorting lines DVSL, RVSL, and CVSL and is composed of a planarization layer PLN which has relatively better adhesive properties than the first and second subdam patterns SDM1 and SDM2. This minimizes film lifting of the first and second subdam patterns SDM1 and SDM2 and the cover pattern CP, as well as crack defects in the inorganic layers EPAS1 and EPAS2. Furthermore, it is possible to reduce or minimize the moisture permeability paths at the edges of the power supply voltage shorting lines DVSL, RVSL, and CVSL between the first and second dam patterns DM1 and DM2. Thus, the moisture permeability reliability of multiple dam patterns DAM can be improved, and electrolytic corrosion defects of the power supply voltage shorting lines DVSL, RVSL, and CVSL can be effectively prevented, thereby realizing a light-emitting display device with improved reliability in high-temperature / high-humidity environments.

[0118] A display device including a light-emitting display device according to one or more embodiments of this specification can be described as follows.

[0119] A light-emitting display device according to one or more embodiments of this specification may include a substrate including a display area and a non-display area surrounding the display area; at least one insulating layer disposed on the substrate; a power supply voltage shorting line disposed on at least one insulating layer in the non-display area and supplying a power supply voltage; a plurality of dam patterns disposed in the non-display area, each composed of one or more organic materials and superimposed on the power supply voltage shorting line; and a cover pattern disposed between the plurality of dam patterns in the non-display area and covering the edges of the power supply voltage shorting line.

[0120] According to one or more embodiments of this specification, power supply voltage shorting lines and multiple dam patterns may intersect each other in a plane.

[0121] According to one or more embodiments of this specification, the dam patterns may extend in a first direction, and the power supply voltage shorting lines may extend in a second direction different from the first direction.

[0122] According to one or more embodiments of this specification, the power supply voltage shorting line may include a micro-protrusion pattern on the edge covered by the cover pattern.

[0123] According to one or more embodiments of this specification, the micro-protrusion pattern has a hammer shape including a handle portion and a head portion located at one end of the handle portion, the head portion may have a wider width than the handle portion.

[0124] According to one or more embodiments of this specification, the cover pattern may be composed of one or more organic materials different from a plurality of dam patterns.

[0125] According to one or more embodiments of this specification, the cover pattern may be an island-like pattern that covers the edges of the power supply voltage shorting lines but does not cover other edges of the power supply voltage shorting lines that are separated from the edges.

[0126] According to one or more embodiments of this specification, the cover pattern may include a first cover pattern and a second cover pattern, the first cover pattern covering the edge of the power supply voltage shorting line and the second cover pattern covering the other edge of the power supply voltage shorting line.

[0127] According to one or more embodiments of this specification, the dam patterns include a first dam pattern adjacent to a display area and composed of a plurality of organic materials, and a second dam pattern adjacent to the edge of the substrate and composed of a plurality of organic materials, wherein the first dam pattern is closer to the display area than the second dam pattern, and the second dam pattern is closer to the edge of the substrate than the first dam pattern, and the cover pattern is positioned between the first and second dam patterns and may be composed of organic materials different from the plurality of organic materials of the first dam pattern and the plurality of organic materials of the second dam pattern.

[0128] According to one or more embodiments of this specification, the dam pattern further includes at least one sub-dam pattern positioned between the first dam pattern and the second dam pattern, the at least one sub-dam pattern may be composed of an organic material different from the organic material of the cover pattern.

[0129] According to one or more embodiments of this specification, the cover pattern overlaps with at least a portion of at least one subdam pattern, the at least one subdam pattern is positioned on the cover pattern, and the cover pattern may include a material that has better adhesion to power supply voltage shorting lines than the material of the at least one subdam pattern.

[0130] According to one or more embodiments of this specification, the cover pattern does not overlap with at least one sub-dam pattern, and at least one sub-dam pattern may have a closed loop shape between the first dam pattern and the second dam pattern.

[0131] According to one or more embodiments of this specification, a power supply voltage shorting line includes a first power supply voltage shorting line that supplies a high potential power supply voltage and a second power supply voltage shorting line that supplies a low potential power supply voltage lower than the high potential power supply voltage, wherein at least one sub-dam pattern may not overlap with the first power supply voltage shorting line but may overlap with the second power supply voltage shorting line.

[0132] According to one or more embodiments of this specification, at least one subdam pattern includes a first subdam pattern and a second subdam pattern arranged parallel to and spaced apart from each other, and a cover pattern may overlap the first subdam pattern and the second subdam pattern.

[0133] According to one or more embodiments of this specification, the cover pattern may have a closed-loop shape and cover the first side edge and the second side edge of the power supply voltage shorting line.

[0134] According to one or more embodiments of this specification, each of the first dam pattern and the second dam pattern extends in a first direction, and the cover pattern may further include sub-cover patterns projecting from each of the first dam pattern and the second dam pattern in a second direction different from the first direction.

[0135] According to one or more embodiments of this specification, the display area further includes a planarization layer disposed on at least one insulating layer, a light-emitting element disposed on the planarization layer and comprising a pixel electrode, a light-emitting layer, and a common electrode, a pixel circuit disposed between the substrate and the planarization layer and connected to the light-emitting element, a bank layer disposed between the pixel electrode and the light-emitting layer so as to define the aperture region of the pixel electrode of the light-emitting element, and a sealing portion covering the light-emitting element and the bank layer, wherein a power supply voltage shorting line can supply a power supply voltage to a first power supply voltage shorting line connected to the pixel circuit.

[0136] According to one or more embodiments of this specification, the multiple dam patterns may be composed of the same material as at least a portion of the flattening layer and the bank layer, and the cover pattern may be composed of the same material as the flattening layer.

[0137] According to one or more embodiments of this specification, a plurality of dam patterns may include at least one sub-dam pattern made of the same material as the bank layer, and a cover pattern may be superimposed on the at least one sub-dam pattern.

[0138] According to one or more embodiments of this specification, the non-display area further includes a pad area, and further includes a plurality of voltage signal lines extending from the pad area and arranged between a power supply voltage shorting line and the substrate, and a plurality of dam patterns and a power supply voltage shorting line may be arranged between the display area and the pad area.

[0139] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to such embodiments, and can be modified and implemented in various ways without departing from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and not limiting in all respects. The scope of protection of this specification should be interpreted by the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification. [Explanation of Symbols]

[0140] 110 Display Panel 120 Scan drive unit 130 Data Drive Unit 160 Timing Control Unit 170 Power supply circuit

Claims

1. A substrate including a display area and a non-display area surrounding the display area, At least one insulating layer disposed on the substrate, A power supply voltage shorting line is disposed on the at least one insulating layer in the non-display area and supplies the power supply voltage, Arranged in the aforementioned non-display area, each composed of one or more organic materials, a plurality of dam patterns superimposed on the power supply voltage shorting line, A cover pattern is positioned between the plurality of dam patterns in the non-display area and covers the edge of the power supply voltage shorting line, A light-emitting display device, including a light-emitting display device.

2. The light-emitting display device according to claim 1, wherein the power supply voltage shorting line and the plurality of dam patterns intersect each other on a plane.

3. The aforementioned multiple dam patterns extend in the first direction, The power supply voltage shorting line extends in a second direction different from the first direction. The light-emitting display device according to claim 2.

4. The light-emitting display device according to claim 1, wherein the power supply voltage shorting line includes a fine protrusion pattern on the edge covered by the cover pattern.

5. The light-emitting display device according to claim 4, wherein the fine projection pattern has a hammer shape including a handle portion and a head portion disposed at one end of the handle portion, and the head portion has a wider width than the handle portion.

6. The light-emitting device according to claim 1, wherein the cover pattern is composed of an organic material different from one or more organic materials of the plurality of dam patterns.

7. The light-emitting display device according to claim 1, wherein the cover pattern is an island-shaped pattern that covers the edge of the power supply voltage shorting line but does not cover other edges of the power supply voltage shorting line that are separated from the edge.

8. The cover pattern includes a first cover pattern and a second cover pattern. The first cover pattern covers the edge of the power supply voltage shorting line, The second cover pattern covers the other edge of the power supply voltage shorting line. The light-emitting display device according to claim 7.

9. The aforementioned multiple dam patterns are Adjacent to the aforementioned display area is a first dam pattern composed of multiple organic materials, A second dam pattern, composed of multiple organic materials, is adjacent to the edge of the aforementioned substrate, Includes, The first dam pattern is closer to the display area than the second dam pattern, and the second dam pattern is closer to the edge of the substrate than the first dam pattern. The cover pattern is positioned between the first dam pattern and the second dam pattern and is composed of an organic material different from the plurality of organic materials of the first dam pattern and the plurality of organic materials of the second dam pattern. The light-emitting display device according to claim 1.

10. The plurality of dam patterns further include at least one sub-dam pattern positioned between the first dam pattern and the second dam pattern, The at least one subdam pattern is composed of an organic material different from the organic material of the cover pattern. The light-emitting display device according to claim 9.

11. The cover pattern overlaps with at least a portion of the at least one subdam pattern, The at least one subdam pattern is arranged on the cover pattern. The cover pattern includes a material that has better adhesion to the power supply voltage shorting line than the material of the at least one sub-dam pattern. The light-emitting display device according to claim 10.

12. The cover pattern does not overlap with the at least one sub-dam pattern. The at least one sub-dam pattern has a closed loop shape between the first dam pattern and the second dam pattern. The light-emitting display device according to claim 10.

13. The aforementioned power supply voltage shorting line is A first power supply voltage shorting line that supplies a high potential power supply voltage, A second power supply voltage shorting line that supplies a low-potential power supply voltage lower than the aforementioned high-potential power supply voltage, Includes, The at least one sub-dam pattern does not overlap with the first power supply voltage shorting line, but overlaps with the second power supply voltage shorting line. The light-emitting display device according to claim 12.

14. The at least one subdam pattern includes a first subdam pattern and a second subdam pattern arranged parallel to and separated from each other. The cover pattern overlaps with the first subdam pattern and the second subdam pattern. The light-emitting display device according to claim 11.

15. The light-emitting display device according to claim 14, wherein the cover pattern has a closed-loop shape and covers the first side edge and the second side edge of the power supply voltage shorting line.

16. Each of the first dam pattern and the second dam pattern extends in the first direction, The cover pattern further includes sub-cover patterns that protrude from each of the first dam pattern and the second dam pattern in a second direction different from the first direction. The light-emitting display device according to claim 15.

17. In the display area, a planarizing layer disposed on at least one insulating layer, A light-emitting element, which is disposed on the planarization layer and consists of a pixel electrode, a light-emitting layer, and a common electrode, A pixel circuit is disposed between the substrate and the planarization layer and connected to the light-emitting element, A bank layer is disposed between the pixel electrode and the light-emitting layer so as to define the aperture region of the pixel electrode of the light-emitting element, A sealing portion covering the light-emitting element and the bank layer, It further includes, The aforementioned power supply voltage shorting line supplies power supply voltage to the first power supply voltage shorting line connected to the pixel circuit. The light-emitting display device according to claim 1.

18. The plurality of dam patterns are composed of the same material as at least a portion of the flattening layer and the bank layer. The cover pattern is made of the same material as the planarization layer. The light-emitting display device according to claim 17.

19. The plurality of dam patterns include at least one sub-dam pattern composed of the same material as the bank layer, The cover pattern overlaps with the at least one sub-dam pattern. The light-emitting display device according to claim 18.

20. The aforementioned non-display area further includes the pad area, The system further includes a plurality of voltage signal lines extending from the pad region and positioned between the power supply voltage shorting line and the substrate, The plurality of dam patterns and the power supply voltage shorting line are arranged between the display area and the pad area. The light-emitting display device according to claim 1.

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